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jlechner |
-----------------------------------------------------------------------
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-- This file is part of SCARTS.
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--
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-- SCARTS is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- SCARTS is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with SCARTS. If not, see <http://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.scarts_core_pkg.all;
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use work.scarts_pkg.all;
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entity scarts_sysc is
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generic (
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CONF : scarts_conf_type);
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port (
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clk : in std_ulogic;
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extrst : in std_ulogic;
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sysrst : out std_ulogic;
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hold : in std_ulogic;
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cpu_halt : out std_ulogic;
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extsel : in std_ulogic;
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exti : in module_in_type;
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exto : out module_out_type;
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staen : in std_ulogic;
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stactrl : in STACTRL;
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staflag : in std_logic_vector(ALUFLAG_W-1 downto 0);
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interruptin : in std_logic_vector(15 downto 0);
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fptrwnew : in std_logic_vector(CONF.word_size-1 downto 0);
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fptrxnew : in std_logic_vector(CONF.word_size-1 downto 0);
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fptrynew : in std_logic_vector(CONF.word_size-1 downto 0);
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fptrznew : in std_logic_vector(CONF.word_size-1 downto 0);
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condflag : out std_ulogic;
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carryflag : out std_ulogic;
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interruptnr : out std_logic_vector(EXCADDR_W-2 downto 0);
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intcmd : out std_ulogic;
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fptrw : out std_logic_vector(CONF.word_size-1 downto 0);
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fptrx : out std_logic_vector(CONF.word_size-1 downto 0);
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fptry : out std_logic_vector(CONF.word_size-1 downto 0);
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fptrz : out std_logic_vector(CONF.word_size-1 downto 0));
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end scarts_sysc;
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architecture behaviour of scarts_sysc is
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constant WORD_W : natural := CONF.word_size;
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subtype WORD is std_logic_vector(WORD_W-1 downto 0);
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subtype BYTE is std_logic_vector(7 downto 0);
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type register_set is array (0 to 24) of BYTE;
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constant STATUSREG_CUST : integer := 1;
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constant CONFIGREG_CUST : integer := 3;
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constant INT_PROT_LOW : integer := 4;
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constant INT_PROT_HIGH : integer := 5;
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constant INT_MASK_LOW : integer := 6;
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constant INT_MASK_HIGH : integer := 7;
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constant FPTRW_0 : integer := 8;
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constant FPTRW_1 : integer := 9;
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constant FPTRW_2 : integer := 10;
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constant FPTRW_3 : integer := 11;
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constant FPTRX_0 : integer := 12;
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constant FPTRX_1 : integer := 13;
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constant FPTRX_2 : integer := 14;
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constant FPTRX_3 : integer := 15;
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constant FPTRY_0 : integer := 16;
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constant FPTRY_1 : integer := 17;
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constant FPTRY_2 : integer := 18;
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constant FPTRY_3 : integer := 19;
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constant FPTRZ_0 : integer := 20;
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constant FPTRZ_1 : integer := 21;
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constant FPTRZ_2 : integer := 22;
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constant FPTRZ_3 : integer := 23;
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constant STATUSREG_CUST_SAVE : integer := 24;
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type reg_type is record
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ifacereg : register_set;
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tmp_int_prot : std_logic_vector(15 downto 0);
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savedsr : std_ulogic;
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gie_backup : std_logic;
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nmiact : std_ulogic;
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end record;
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signal r_next : reg_type;
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signal r : reg_type := (
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ifacereg => (INT_MASK_LOW => (others => '1'), INT_MASK_HIGH => (others => '1'), others => (others => '0')),
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tmp_int_prot => (others => '0'),
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savedsr => '0',
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gie_backup => '0',
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nmiact => '0');
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signal rstint : std_ulogic;
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signal int_hold : std_ulogic;
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begin
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comb : process(r, staen, stactrl, staflag, interruptin, fptrwnew, fptrxnew, fptrynew, fptrznew,
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exti, extsel, rstint, extrst, hold, int_hold)
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variable v : reg_type;
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variable v_interruptnr : std_logic_vector(EXCADDR_W-2 downto 0);
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variable v_intcmd : std_ulogic;
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begin
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v := r;
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v.ifacereg(FPTRW_0) := fptrwnew(7 downto 0);
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v.ifacereg(FPTRX_0) := fptrxnew(7 downto 0);
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v.ifacereg(FPTRY_0) := fptrynew(7 downto 0);
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v.ifacereg(FPTRZ_0) := fptrznew(7 downto 0);
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v.ifacereg(FPTRW_1) := fptrwnew(15 downto 8);
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v.ifacereg(FPTRX_1) := fptrxnew(15 downto 8);
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v.ifacereg(FPTRY_1) := fptrynew(15 downto 8);
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v.ifacereg(FPTRZ_1) := fptrznew(15 downto 8);
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if CONF.word_size = 32 then
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v.ifacereg(FPTRW_2) := fptrwnew(WORD_W-9 downto WORD_W-16);
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v.ifacereg(FPTRX_2) := fptrxnew(WORD_W-9 downto WORD_W-16);
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v.ifacereg(FPTRY_2) := fptrynew(WORD_W-9 downto WORD_W-16);
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v.ifacereg(FPTRZ_2) := fptrznew(WORD_W-9 downto WORD_W-16);
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v.ifacereg(FPTRW_3) := fptrwnew(WORD_W-1 downto WORD_W-8);
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v.ifacereg(FPTRX_3) := fptrxnew(WORD_W-1 downto WORD_W-8);
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v.ifacereg(FPTRY_3) := fptrynew(WORD_W-1 downto WORD_W-8);
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v.ifacereg(FPTRZ_3) := fptrznew(WORD_W-1 downto WORD_W-8);
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end if;
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--interrupts protokollieren
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-- v.tmp_int_prot := interruptin;
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-- v.ifacereg(INT_PROT_LOW) := r.ifacereg(INT_PROT_LOW) or interruptin(7 downto 0) or r.tmp_int_prot(7 downto 0);
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-- v.ifacereg(INT_PROT_HIGH) := r.ifacereg(INT_PROT_HIGH) or interruptin(15 downto 8) or r.tmp_int_prot(15 downto 8);
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-- detect positve edge on interrupt lines and set flag in protocol register
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v.tmp_int_prot := interruptin;
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v.ifacereg(INT_PROT_LOW) := r.ifacereg(INT_PROT_LOW) or ((not r.tmp_int_prot(7 downto 0)) and interruptin(7 downto 0));
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v.ifacereg(INT_PROT_HIGH) := r.ifacereg(INT_PROT_HIGH) or ((not r.tmp_int_prot(15 downto 8)) and interruptin(15 downto 8));
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--schreiben
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if ((extsel = '1') and (exti.write_en = '1')) then
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case exti.addr(4 downto 2) is
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when "000" =>
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if ((exti.byte_en(0) = '1') or (exti.byte_en(1) = '1')) then
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v.ifacereg(STATUSREG)(STA_INT) := '1';
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v.ifacereg(CONFIGREG)(CONF_INTA) :='0';
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else
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if ((exti.byte_en(2) = '1')) then
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v.ifacereg(2) := exti.data(23 downto 16);
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end if;
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if ((exti.byte_en(3) = '1')) then
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v.ifacereg(3) := exti.data(31 downto 24);
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end if;
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end if;
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when "001" =>
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if ((exti.byte_en(0) = '1')) then
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v.ifacereg(4) := v.ifacereg(4) xor exti.data(7 downto 0);
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end if;
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if ((exti.byte_en(1) = '1')) then
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v.ifacereg(5) := v.ifacereg(5) xor exti.data(15 downto 8);
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end if;
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if ((exti.byte_en(2) = '1')) then
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v.ifacereg(6) := exti.data(23 downto 16);
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end if;
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if ((exti.byte_en(3) = '1')) then
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v.ifacereg(7) := exti.data(31 downto 24);
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end if;
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when "010" =>
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if ((exti.byte_en(0) = '1')) then
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v.ifacereg(8) := exti.data(7 downto 0);
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end if;
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if ((exti.byte_en(1) = '1')) then
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v.ifacereg(9) := exti.data(15 downto 8);
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end if;
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if CONF.word_size = 32 then
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if ((exti.byte_en(2) = '1')) then
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v.ifacereg(10) := exti.data(23 downto 16);
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end if;
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if ((exti.byte_en(3) = '1')) then
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v.ifacereg(11) := exti.data(31 downto 24);
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end if;
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end if;
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when "011" =>
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if ((exti.byte_en(0) = '1')) then
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v.ifacereg(12) := exti.data(7 downto 0);
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end if;
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if ((exti.byte_en(1) = '1')) then
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v.ifacereg(13) := exti.data(15 downto 8);
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end if;
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if CONF.word_size = 32 then
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if ((exti.byte_en(2) = '1')) then
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v.ifacereg(14) := exti.data(23 downto 16);
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end if;
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if ((exti.byte_en(3) = '1')) then
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v.ifacereg(15) := exti.data(31 downto 24);
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end if;
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end if;
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when "100" =>
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if ((exti.byte_en(0) = '1')) then
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v.ifacereg(16) := exti.data(7 downto 0);
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end if;
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if ((exti.byte_en(1) = '1')) then
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v.ifacereg(17) := exti.data(15 downto 8);
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end if;
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if CONF.word_size = 32 then
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if ((exti.byte_en(2) = '1')) then
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v.ifacereg(18) := exti.data(23 downto 16);
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end if;
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if ((exti.byte_en(3) = '1')) then
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v.ifacereg(19) := exti.data(31 downto 24);
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end if;
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end if;
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when "101" =>
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if ((exti.byte_en(0) = '1')) then
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v.ifacereg(20) := exti.data(7 downto 0);
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end if;
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if ((exti.byte_en(1) = '1')) then
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v.ifacereg(21) := exti.data(15 downto 8);
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end if;
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if CONF.word_size = 32 then
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if ((exti.byte_en(2) = '1')) then
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v.ifacereg(22) := exti.data(23 downto 16);
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end if;
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if ((exti.byte_en(3) = '1')) then
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v.ifacereg(23) := exti.data(31 downto 24);
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end if;
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end if;
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when "110" =>
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if ((exti.byte_en(0) = '1')) then
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v.ifacereg(24) := exti.data(7 downto 0);
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end if;
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when others =>
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null;
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end case;
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end if;
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-- Löschen des Interrupt Signals
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if r.ifacereg(STATUSREG)(STA_INT) = '1' and r.ifacereg(CONFIGREG)(CONF_INTA) ='1' then
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v.ifacereg(STATUSREG)(STA_INT) := '0';
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end if;
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exto.intreq <= r.ifacereg(STATUSREG)(STA_INT);
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--auslesen
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exto.data <= (others => '0');
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| 264 |
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if ((extsel = '1') and (exti.write_en = '0')) then
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case exti.addr(4 downto 2) is
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| 266 |
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when "000" =>
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| 267 |
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exto.data <= r.ifacereg(3) & r.ifacereg(2) & r.ifacereg(1) & r.ifacereg(0);
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| 268 |
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when "001" =>
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| 269 |
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if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
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| 270 |
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exto.data <= MODULE_VER & MODULE_ID;
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| 271 |
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else
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| 272 |
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exto.data <= r.ifacereg(7) & r.ifacereg(6) & r.ifacereg(5) & r.ifacereg(4);
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| 273 |
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end if;
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| 274 |
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when "010" =>
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| 275 |
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if CONF.word_size = 32 then
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| 276 |
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exto.data <= r.ifacereg(11) & r.ifacereg(10) & r.ifacereg(9) & r.ifacereg(8);
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| 277 |
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else
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| 278 |
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exto.data <= "00000000" & "00000000" & r.ifacereg(9) & r.ifacereg(8);
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| 279 |
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end if;
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| 280 |
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when "011" =>
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| 281 |
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if CONF.word_size = 32 then
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| 282 |
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exto.data <= r.ifacereg(15) & r.ifacereg(14) & r.ifacereg(13) & r.ifacereg(12);
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| 283 |
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else
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| 284 |
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exto.data <= "00000000" & "00000000" & r.ifacereg(13) & r.ifacereg(12);
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| 285 |
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end if;
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| 286 |
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when "100" =>
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| 287 |
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if CONF.word_size = 32 then
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| 288 |
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exto.data <= r.ifacereg(19) & r.ifacereg(18) & r.ifacereg(17) & r.ifacereg(16);
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| 289 |
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else
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| 290 |
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exto.data <= "00000000" & "00000000" & r.ifacereg(17) & r.ifacereg(16);
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| 291 |
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end if;
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| 292 |
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when "101" =>
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| 293 |
|
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if CONF.word_size = 32 then
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| 294 |
|
|
exto.data <= r.ifacereg(23) & r.ifacereg(22) & r.ifacereg(21) & r.ifacereg(20);
|
| 295 |
|
|
else
|
| 296 |
|
|
exto.data <= "00000000" & "00000000" & r.ifacereg(21) & r.ifacereg(20);
|
| 297 |
|
|
end if;
|
| 298 |
|
|
when "110" =>
|
| 299 |
|
|
exto.data <= "00000000" & "00000000" & "00000000" & r.ifacereg(24);
|
| 300 |
|
|
when others =>
|
| 301 |
|
|
null;
|
| 302 |
|
|
end case;
|
| 303 |
|
|
end if;
|
| 304 |
|
|
|
| 305 |
|
|
--berechnen der neuen status flags
|
| 306 |
|
|
v.ifacereg(STATUSREG)(STA_LOOR) := r.ifacereg(CONFIGREG)(CONF_LOOW);
|
| 307 |
|
|
v.ifacereg(STATUSREG)(STA_FSS) := '0';
|
| 308 |
|
|
v.ifacereg(STATUSREG)(STA_RESH) := '0';
|
| 309 |
|
|
v.ifacereg(STATUSREG)(STA_RESL) := '0';
|
| 310 |
|
|
v.ifacereg(STATUSREG)(STA_BUSY) := '0';
|
| 311 |
|
|
v.ifacereg(STATUSREG)(STA_ERR) := '0';
|
| 312 |
|
|
v.ifacereg(STATUSREG)(STA_RDY) := '1';
|
| 313 |
|
|
-- if exti.extaddr(2 downto 1) = "11" then
|
| 314 |
|
|
-- v.ifacereg(STATUSREG)(STA_ERR) := '1';
|
| 315 |
|
|
-- end if;
|
| 316 |
|
|
|
| 317 |
|
|
--module specific part
|
| 318 |
|
|
--interupt handler
|
| 319 |
|
|
v_interruptnr := (others => '0');
|
| 320 |
|
|
v_intcmd := not EXC_ACT;
|
| 321 |
|
|
v.ifacereg(INT_MASK_LOW)(0) := '0';
|
| 322 |
|
|
if r.ifacereg(INT_PROT_LOW)(0) = '1' and r.nmiact = not EXC_ACT then
|
| 323 |
|
|
--v_intcmd := EXC_ACT;
|
| 324 |
|
|
v.nmiact := EXC_ACT;
|
| 325 |
|
|
v_interruptnr := std_logic_vector(to_unsigned(0,EXCADDR_W-1));
|
| 326 |
|
|
v.ifacereg(INT_MASK_LOW)(0) := '1';
|
| 327 |
|
|
v.ifacereg(INT_PROT_LOW)(0) := '0';
|
| 328 |
|
|
else
|
| 329 |
|
|
for i in 1 to 7 loop
|
| 330 |
|
|
if (r.ifacereg(INT_PROT_LOW)(i) = '1') and (r.ifacereg(INT_MASK_LOW)(i) = '0')
|
| 331 |
|
|
and (r.ifacereg(INT_MASK_LOW)(0) = '0') and (r.ifacereg(CONFIGREG_CUST)(GIE) = '1') then
|
| 332 |
|
|
v_intcmd := EXC_ACT;
|
| 333 |
|
|
v_interruptnr := std_logic_vector(to_unsigned(i,EXCADDR_W-1));
|
| 334 |
|
|
v.ifacereg(INT_MASK_LOW)(0) := '1';
|
| 335 |
|
|
v.ifacereg(INT_PROT_LOW)(i) := '0';
|
| 336 |
|
|
end if;
|
| 337 |
|
|
end loop;
|
| 338 |
|
|
for i in 0 to 7 loop
|
| 339 |
|
|
if (r.ifacereg(INT_PROT_HIGH)(i) = '1') and (r.ifacereg(INT_MASK_HIGH)(i) = '0')
|
| 340 |
|
|
and (r.ifacereg(INT_MASK_LOW)(0) = '0') and (r.ifacereg(CONFIGREG_CUST)(GIE) = '1') then
|
| 341 |
|
|
v_intcmd := EXC_ACT;
|
| 342 |
|
|
v_interruptnr := std_logic_vector(to_unsigned(i+8,EXCADDR_W-1));
|
| 343 |
|
|
v.ifacereg(INT_MASK_LOW)(0) := '1';
|
| 344 |
|
|
v.ifacereg(INT_PROT_HIGH)(i) := '0';
|
| 345 |
|
|
end if;
|
| 346 |
|
|
end loop;
|
| 347 |
|
|
end if;
|
| 348 |
|
|
|
| 349 |
|
|
--update der status flags
|
| 350 |
|
|
if staen = STA_EN then
|
| 351 |
|
|
case stactrl is
|
| 352 |
|
|
when SET_FLAG =>
|
| 353 |
|
|
v.ifacereg(STATUSREG_CUST)(ZERO) := staflag(ZERO);
|
| 354 |
|
|
v.ifacereg(STATUSREG_CUST)(NEG) := staflag(NEG);
|
| 355 |
|
|
v.ifacereg(STATUSREG_CUST)(CARRY) := staflag(CARRY);
|
| 356 |
|
|
v.ifacereg(STATUSREG_CUST)(OVER) := staflag(OVER);
|
| 357 |
|
|
when SET_COND =>
|
| 358 |
|
|
v.ifacereg(STATUSREG_CUST)(COND) := staflag(COND);
|
| 359 |
|
|
v.ifacereg(STATUSREG_CUST)(ZERO) := staflag(ZERO);
|
| 360 |
|
|
v.ifacereg(STATUSREG_CUST)(NEG) := staflag(NEG);
|
| 361 |
|
|
v.ifacereg(STATUSREG_CUST)(CARRY) := staflag(CARRY);
|
| 362 |
|
|
v.ifacereg(STATUSREG_CUST)(OVER) := staflag(OVER);
|
| 363 |
|
|
when SAVE_SR =>
|
| 364 |
|
|
v.ifacereg(STATUSREG_CUST_SAVE) := r.ifacereg(STATUSREG_CUST);
|
| 365 |
|
|
v.gie_backup := r.ifacereg(CONFIGREG_CUST)(GIE);
|
| 366 |
|
|
v.ifacereg(STATUSREG_CUST) := (others => '0');
|
| 367 |
|
|
v.ifacereg(CONFIGREG_CUST)(GIE) := '0';
|
| 368 |
|
|
if v_intcmd = EXC_ACT then
|
| 369 |
|
|
v.savedsr := '1';
|
| 370 |
|
|
end if;
|
| 371 |
|
|
when REST_SR =>
|
| 372 |
|
|
v.nmiact := not EXC_ACT;
|
| 373 |
|
|
if r.savedsr = '1' then
|
| 374 |
|
|
v.savedsr := '0';
|
| 375 |
|
|
else
|
| 376 |
|
|
v.ifacereg(STATUSREG_CUST) := r.ifacereg(STATUSREG_CUST_SAVE);
|
| 377 |
|
|
v.ifacereg(CONFIGREG_CUST)(GIE) := r.gie_backup;
|
| 378 |
|
|
end if;
|
| 379 |
|
|
when others => null;
|
| 380 |
|
|
end case;
|
| 381 |
|
|
end if;
|
| 382 |
|
|
|
| 383 |
|
|
--soft- und hard-reset vereinen
|
| 384 |
|
|
rstint <= not RST_ACT;
|
| 385 |
|
|
if extrst = RST_ACT or r.ifacereg(CONFIGREG)(CONF_SRES) = '1' then
|
| 386 |
|
|
rstint <= RST_ACT;
|
| 387 |
|
|
end if;
|
| 388 |
|
|
|
| 389 |
|
|
-- output
|
| 390 |
|
|
condflag <= r.ifacereg(STATUSREG_CUST)(COND);
|
| 391 |
|
|
carryflag <= r.ifacereg(STATUSREG_CUST)(CARRY);
|
| 392 |
|
|
interruptnr <= v_interruptnr;
|
| 393 |
|
|
intcmd <= v_intcmd;
|
| 394 |
|
|
sysrst <= rstint;
|
| 395 |
|
|
|
| 396 |
|
|
|
| 397 |
|
|
fptrw(7 downto 0) <= r.ifacereg(FPTRW_0) ;
|
| 398 |
|
|
fptrx(7 downto 0) <= r.ifacereg(FPTRX_0) ;
|
| 399 |
|
|
fptry(7 downto 0) <= r.ifacereg(FPTRY_0) ;
|
| 400 |
|
|
fptrz(7 downto 0) <= r.ifacereg(FPTRZ_0) ;
|
| 401 |
|
|
|
| 402 |
|
|
fptrw(15 downto 8) <= r.ifacereg(FPTRW_1) ;
|
| 403 |
|
|
fptrx(15 downto 8) <= r.ifacereg(FPTRX_1) ;
|
| 404 |
|
|
fptry(15 downto 8) <= r.ifacereg(FPTRY_1) ;
|
| 405 |
|
|
fptrz(15 downto 8) <= r.ifacereg(FPTRZ_1) ;
|
| 406 |
|
|
|
| 407 |
|
|
if CONF.word_size = 32 then
|
| 408 |
|
|
fptrw(WORD_W-9 downto WORD_W-16) <= r.ifacereg(FPTRW_2) ;
|
| 409 |
|
|
fptrx(WORD_W-9 downto WORD_W-16) <= r.ifacereg(FPTRX_2) ;
|
| 410 |
|
|
fptry(WORD_W-9 downto WORD_W-16) <= r.ifacereg(FPTRY_2) ;
|
| 411 |
|
|
fptrz(WORD_W-9 downto WORD_W-16) <= r.ifacereg(FPTRZ_2) ;
|
| 412 |
|
|
|
| 413 |
|
|
fptrw(WORD_W-1 downto WORD_W-8) <= r.ifacereg(FPTRW_3) ;
|
| 414 |
|
|
fptrx(WORD_W-1 downto WORD_W-8) <= r.ifacereg(FPTRX_3) ;
|
| 415 |
|
|
fptry(WORD_W-1 downto WORD_W-8) <= r.ifacereg(FPTRY_3) ;
|
| 416 |
|
|
fptrz(WORD_W-1 downto WORD_W-8) <= r.ifacereg(FPTRZ_3) ;
|
| 417 |
|
|
end if;
|
| 418 |
|
|
|
| 419 |
|
|
if (v_intcmd = EXC_ACT) then
|
| 420 |
|
|
v.ifacereg(CONFIGREG_CUST)(SLEEP) := '0';
|
| 421 |
|
|
end if;
|
| 422 |
|
|
int_hold <= hold or r.ifacereg(CONFIGREG_CUST)(SLEEP);
|
| 423 |
|
|
cpu_halt <= int_hold;
|
| 424 |
|
|
|
| 425 |
|
|
r_next <= v;
|
| 426 |
|
|
end process;
|
| 427 |
|
|
|
| 428 |
|
|
reg : process(clk)--, rstint)
|
| 429 |
|
|
begin
|
| 430 |
|
|
if rising_edge(clk) then
|
| 431 |
|
|
if rstint = RST_ACT then
|
| 432 |
|
|
r.ifacereg <= (INT_MASK_LOW => (others => '1'), INT_MASK_HIGH => (others => '1'), others => (others => '0'));
|
| 433 |
|
|
r.tmp_int_prot <= (others => '0');
|
| 434 |
|
|
r.savedsr <= '0';
|
| 435 |
|
|
r.gie_backup <= '0';
|
| 436 |
|
|
r.nmiact <= not EXC_ACT;
|
| 437 |
|
|
else
|
| 438 |
|
|
if (int_hold = not HOLD_ACT) then
|
| 439 |
|
|
r <= r_next;
|
| 440 |
|
|
end if;
|
| 441 |
|
|
r.tmp_int_prot <= r_next.tmp_int_prot;
|
| 442 |
|
|
r.ifacereg(CONFIGREG_CUST)(SLEEP) <= r_next.ifacereg(CONFIGREG_CUST)(SLEEP);
|
| 443 |
|
|
end if;
|
| 444 |
|
|
end if;
|
| 445 |
|
|
end process;
|
| 446 |
|
|
|
| 447 |
|
|
end behaviour;
|
