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[/] [scarts/] [trunk/] [processor/] [workspace/] [terasic_de2-115/] [modelsim/] [compile_all.do] - Blame information for rev 3

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Line No. Rev Author Line
1 3 jlechner
vlib work
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vmap work work
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vlib altera
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vmap altera work
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vlib stratixii
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vmap stratixii work
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vlib altera_mf
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vmap altera_mf work
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set ALTERA_LIB_PATH /opt/altera/10.0/quartus/eda/sim_lib
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vcom  -work altera_mf $ALTERA_LIB_PATH/altera_mf_components.vhd
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vcom  -work altera_mf $ALTERA_LIB_PATH/altera_mf.vhd
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vcom  -work stratixii $ALTERA_LIB_PATH/stratixii_atoms.vhd
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vcom  -work stratixii $ALTERA_LIB_PATH/stratixii_components.vhd
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do compile.do

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