URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [processor/] [workspace/] [terasic_de2-115/] [modelsim/] [sim.do] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	jlechner	`vcom -work work ../VHDL/top_tb.vhd`
2			`vsim -t ps work.top_tb`
3			`do wave.do`
4