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[/] [scarts/] [trunk/] [processor/] [workspace/] [terasic_de2-115/] [quartus/] [top.qsf] - Blame information for rev 3

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Line No. Rev Author Line
1 3 jlechner
# Copyright (C) 1991-2007 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors.  Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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#               top_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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#               assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE115F29C7
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set_global_assignment -name TOP_LEVEL_ENTITY top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:52:19  APRIL 04, 2008"
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set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
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set_global_assignment -name USER_LIBRARIES db
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set_location_assignment PIN_G9 -to D_TxD
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set_location_assignment PIN_G12 -to D_RxD
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set_location_assignment PIN_Y2 -to db_clk
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set_location_assignment PIN_M23 -to rst
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#set_location_assignment PIN_D14 -to miso
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#set_location_assignment PIN_A15 -to mosi
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#set_location_assignment PIN_F14 -to sck
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rst
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
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set_global_assignment -name MUX_RESTRUCTURE AUTO
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name MISC_FILE top.dpf
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set_location_assignment PIN_G18 -to digits[0].SegA
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set_location_assignment PIN_F22 -to digits[0].SegB
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set_location_assignment PIN_E17 -to digits[0].SegC
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set_location_assignment PIN_L26 -to digits[0].SegD
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set_location_assignment PIN_L25 -to digits[0].SegE
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set_location_assignment PIN_J22 -to digits[0].SegF
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set_location_assignment PIN_H22 -to digits[0].SegG
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set_location_assignment PIN_M24 -to digits[1].SegA
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set_location_assignment PIN_Y22 -to digits[1].SegB
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set_location_assignment PIN_W21 -to digits[1].SegC
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set_location_assignment PIN_W22 -to digits[1].SegD
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set_location_assignment PIN_W25 -to digits[1].SegE
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set_location_assignment PIN_U23 -to digits[1].SegF
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set_location_assignment PIN_U24 -to digits[1].SegG
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set_location_assignment PIN_AA25 -to digits[2].SegA
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set_location_assignment PIN_AA26 -to digits[2].SegB
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set_location_assignment PIN_Y25 -to digits[2].SegC
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set_location_assignment PIN_W26 -to digits[2].SegD
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set_location_assignment PIN_Y26 -to digits[2].SegE
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set_location_assignment PIN_W27 -to digits[2].SegF
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set_location_assignment PIN_W28 -to digits[2].SegG
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set_location_assignment PIN_V21 -to digits[3].SegA
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set_location_assignment PIN_U21 -to digits[3].SegB
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set_location_assignment PIN_AB20 -to digits[3].SegC
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set_location_assignment PIN_AA21 -to digits[3].SegD
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set_location_assignment PIN_AD24 -to digits[3].SegE
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set_location_assignment PIN_AF23 -to digits[3].SegF
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set_location_assignment PIN_Y19 -to digits[3].SegG
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set_location_assignment PIN_AB19 -to digits[4].SegA
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set_location_assignment PIN_AA19 -to digits[4].SegB
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set_location_assignment PIN_AG21 -to digits[4].SegC
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set_location_assignment PIN_AH21 -to digits[4].SegD
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set_location_assignment PIN_AE19 -to digits[4].SegE
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set_location_assignment PIN_AF19 -to digits[4].SegF
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set_location_assignment PIN_AE18 -to digits[4].SegG
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set_location_assignment PIN_AD18 -to digits[5].SegA
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set_location_assignment PIN_AC18 -to digits[5].SegB
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set_location_assignment PIN_AB18 -to digits[5].SegC
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set_location_assignment PIN_AH19 -to digits[5].SegD
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set_location_assignment PIN_AG19 -to digits[5].SegE
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set_location_assignment PIN_AF18 -to digits[5].SegF
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set_location_assignment PIN_AH18 -to digits[5].SegG
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set_location_assignment PIN_AA17 -to digits[6].SegA
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set_location_assignment PIN_AB16 -to digits[6].SegB
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set_location_assignment PIN_AA16 -to digits[6].SegC
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set_location_assignment PIN_AB17 -to digits[6].SegD
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set_location_assignment PIN_AB15 -to digits[6].SegE
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set_location_assignment PIN_AA15 -to digits[6].SegF
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set_location_assignment PIN_AC17 -to digits[6].SegG
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set_location_assignment PIN_AD17 -to digits[7].SegA
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set_location_assignment PIN_AE17 -to digits[7].SegB
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set_location_assignment PIN_AG17 -to digits[7].SegC
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set_location_assignment PIN_AH17 -to digits[7].SegD
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set_location_assignment PIN_AF17 -to digits[7].SegE
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set_location_assignment PIN_AG18 -to digits[7].SegF
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set_location_assignment PIN_AA14 -to digits[7].SegG
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set_global_assignment -name RAPID_RECOMPILE_MODE ON
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set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "NEAR END"
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set_instance_assignment -name IO_STANDARD "2.5 V" -to digits[0].SegA
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set_instance_assignment -name IO_STANDARD "2.5 V" -to digits[0].SegB
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set_instance_assignment -name IO_STANDARD "2.5 V" -to digits[0].SegC
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set_global_assignment -name VHDL_FILE ../../../VHDL/common/scarts_amba_pkg.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/common/scarts_pkg.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/scarts_core_pkg.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/altera/boot_rom.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/vectab.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/byteram.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/core.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/dram.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/iram.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/prog.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/regf.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/regfram.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/scarts.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/sysc.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/brom.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/rs232.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/bpt.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/scarts_core/wpt.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/ext_modules/ext_Dis7Seg/ext_Dis7Seg.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/ext_modules/ext_Dis7Seg/ext_Dis7Seg_ent.vhd
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set_global_assignment -name VHDL_FILE ../../../VHDL/ext_modules/ext_Dis7Seg/pkg_Dis7Seg.vhd
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set_global_assignment -name VHDL_FILE ../VHDL/altera_pll.vhd
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set_global_assignment -name VHDL_FILE ../VHDL/top_pkg.vhd
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set_global_assignment -name VHDL_FILE ../VHDL/top.vhd
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set_global_assignment -name SDC_FILE top.sdc
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set_global_assignment -name QIP_FILE ../VHDL/altera_pll.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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