URL https://opencores.org/ocsvn/scarts/scarts/trunk
Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-binutils/] [binutils-2.19.1/] [cgen/] [ChangeLog] - Blame information for rev 6

Details | Compare with Previous | View Log

2009-08-29  Doug Evans  
 
        * hardware.scm (-keyword-parse): Fix `enum-prefix' default for
        rtl version 0.7.
        * doc/rtl.texi: Improve docs on rtl 0.7 vs 0.8 differences.
 
2009-08-27  Doug Evans  
 
        Add do-count rtl function.
        * rtl-c.scm (s-do-count): New function.
        (do-count): New rtl handler.
        * rtl-traverse.scm (-rtx-traverse-iteration): New function.
        (-rtx-make-traverser-table): Add ITERATION.
        * rtl.scm (rtx-make-iteration-limit-var): New function.
        (rtx-env-make-iteration-locals): New function.
        * rtx-funcs.scm (do-count): New rtl function.
        * cpu/play.cpu: Add do-count-test insn.
        * doc/rtl.texi: Add docs on do-count.
 
2009-08-26  Doug Evans  
 
        * read.scm (parse-error): Change error message output format
        to match context-owner-error.
        * rtl-c.scm (-rtl-c-get): Call estate-error instead of error.
        (rtl-c-set-quiet, rtl-c-set-trace): Ditto.
        (s-if, s-cond, -gen-non-vm-case-test): Ditto.
        (operand): Call estate-error instead of context-error.
        (local, delay): Ditto.
        (ref, attr): Call estate-error instead of error.
        * rtl-traverse.scm (tstate-error): New function.
        (-rtx-traverse-error): Call tstate-error instead of context-error.
        (-rtx-traverse-operands, -rtx-traverse): Ditto.
        (estate-error): New function.
        * rtl.scm (rtx-lvalue-mode-name): Handle locals.  Call estate-error
        instead of error.
        (e-if): Call estate-error instead of error.
        * rtx-funcs.scm (error): Call estate-error instead of context-error.
        (member): Ditto.
        * utils-cgen.scm (context-error): New arg `intro', all callers updated.
        Rewrite to call context-owner-error.
        (context-owner-error): New function.
 
        * ifield.scm ( constructor): New arg `location',
        all callers updated.
        * insn.scm ( constructor): Ditto.
        ( constructor): Ditto.
        * minsn.scm ( constructor): Ditto.
        * operand.scm ( constructor): Ditto.
        * utils-cgen.scm (builtin-location): New function.
        (): Fix default value of member `location'.
        (source-ident?): New function.
 
        * rtl-traverse.scm (estate-new-env): Rename arg state -> estate.
        (estate-push-env, estate-with-modifiers): Ditto.
        (estate-deepen): New function.
 
2009-08-25  Dave Korn  
 
        * sim-model.scm (-gen-mach-defns): Use @PREFIX@_INSN__MAX instead of
        @CPU@_INSN__MAX.  Use @prefix@ instead of @cpu@ for engine_run
        routines.
 
2009-08-25  Doug Evans  
 
        * doc/pmacros.texi (pmacro default argument values): Add text.
 
2009-08-23  Doug Evans  
 
        * hardware.scm (): Rename member print-name -> enum-prefix.
        Rename member prefix -> name-prefix.
        ( getters): Update.
        (-keyword-parse): Update.  Default enum-prefix to NAME-.
        (-keyword-read): Update.  Don't compute default value for
        enum-prefix here.
        (define-keyword): Update.
        (-hw-parse-keyword): Pass "UNUSED" for enum-prefix to -keyword-parse.
        * read.scm (cgen-rtl-version): New function.
        (-supported-rtl-versions): Add (0 8).
        * desc-cpu.scm (-gen-hw-decl): Remove cruft.
        * desc.scm ( gen-defn): prefix -> name-prefix.
        * gas-test.scm ( test-data): prefix -> name-prefix.
        * cpu/arm.cpu (gr-names, shift-type): Call define-rtl-version.
        Update, print-name -> enum-prefix, make uppercase.
        Remove unnecessary name-prefix spec.
        * cpu/fr30.cpu (gr-names, cr-names, dr-names): Ditto.
        * cpu/ip2k.cpu (register-names): Ditto.
        * cpu/m68k.cpu (dr-names, ar-names): Ditto.
        * cpu/sparc.cpu (gr-names): Ditto.
        * cpu/xc16x.cpu (gr-names, ext-names,psw-names): Ditto.
        (grb-names, conditioncode-names, extconditioncode-names): Ditto.
        (grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
        (reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
        * cpu/ia32.cpu (gr8-names, gr16-names, gr-names): Call
        define-rtl-version.  Update, print-name -> enum-prefix, make uppercase,
        prefix -> name-prefix.
        * cpu/sh64-compact.cpu (frc-names): Call define-rtl-version.
        Update, print-name -> enum-prefix, make uppercase.
        (drc-names, xf-names): Ditto.
        * cpu/xstormy16.cpu (gr-names, gr-Rb-names): Ditto.
        * doc/rtl.texi (Keywords): New section.
        (hardware indices): Update text.
        (rtl versions): Add 0.8.
 
        Add define-rtl-version.
        * read.scm (-CGEN-RTL-VERSION): Renamed from -CGEN-LANG-VERSION.
        (cgen-rtl-major, cgen-rtl-minor): Similarly renamed.
        (cgen-lang-fixlevel): Delete.
        (-supported-rtl-versions): New variable.
        (-cmd-define-rtl-version): New function.
        (init-reader!): New command define-rtl-version.
        (-cgen): Add rtl version to --version output.
        * doc/rtl.texi: Document rtl version support.
        * cpu/play.cpu: Add define-rtl-version.
 
2009-08-22  Doug Evans  
 
        * Makefile.am (OPTIONS): Define.
        (desc): Just generate -desc.[ch] files.
        * Makefile.in: Regenerate.
        * desc-cpu.scm (cgen-desc.h): Skip call to gen-extra-cpu.h if there's
        no .opc file.
        (cgen-desc.c): Similarly.
        * gen-all-desc: New file.
        * opcodes.scm (opc-file-provided?): New function.
 
        * mach.scm (current-*-add!): Update calls to parse-error.
        * operand.scm (op:new-mode): Update call to parse-error.
        * utils-cgen.scm (make-obj-context): New function.
 
        * NEWS: Copy over entries from 1.1 branch.
 
2009-08-20  Doug Evans  
 
        * gas-test.scm ( test-data): Catch invalid requests,
        flag a warning and compensate.
        (
        (
        (cgen-build.sh): Convert symbols to strings before passing to
        string-append.
        (cgen-allinsn.exp): Ditto.
 
        * doc/pmacros.texi (.splice): Add more text.
 
2009-08-19  Doug Evans  
 
        * configure.in (AM_INIT_AUTOMAKE): Change version to 1.1.50 to
        distinguish from 1.1.
        * configure: Regenerate.
        * read.scm (-CGEN-VERSION): Update.
        * doc/version.texi: Update.
 
        New builtin .pmacro?.
        * pmacros.scm (-pmacro-builtin-pmacro?): New function.
        (pmacros-init!): Add .pmacro?.
        * doc/pmacros.text: Document .pmacro?.
        * testsuite/pmacros-1.test: Test .pmacro?.
 
        * pmacros.scm (scan-list1): Reorganize tracing so that the tracing
        of a pmacro begins before its arguments are evaluated, improves
        readability.
 
        * pmacros.scm (.sll, .srl, .sra): Fix thinko.
        * testsuite/pmacros-1.test: Ditto.  Add better tests.
 
        * doc/rtl.texi (Instructions): Improve docs of when ${...} is needed
        in assembler syntax.
        (Operands): Similarly.
 
2009-08-18  Doug Evans  
 
        * ifield.scm (ifld-encode-mode): Add FIXME.
        * opcodes.scm ( gen-insert): Handle encode parameters with
        modes.
        ( gen-extract): Similarly.
 
        * read.scm (parse-error): Handle #f for context-location.
        * utils-cgen.scm (unspecified-location): Fix building of
        single-location.
 
        * doc/rtl.texi: Document how to write hex and boolean values.
 
        * gas-test.scm ( test-data): Handle () values.
        ( test-data): Convert symbols to strings before passing
        to string-append.
        ( test-data): Enumerate all cases.  Emit correctly sized
        result for scalars.
 
        * operand.scm (hw-index-scalar): Set `name'.
        (hw-index-anyof, hw-index-derived): Ditto.
 
2009-08-17  Doug Evans  
 
        * pmacros.scm (-pmacro-builtin-internal-test): New function.
        (pmacros-init!): Add .internal-test.
        * testsuite/test-utils.sh.in (post_process): Tweak FAIL output.
        * testsuite/testsuite.cpu (internal-verify): New pmacro.
        * doc/pmacros.text: Document .internal-test.
 
        * utils-cgen.scm (parse-name): Handle (add 3) -> add3.
        (parse-comment): Allow numbers.
        * doc/porting.texi: Document that names and comments may be lists.
 
        * insn.scm (-insn-parse): Fix typo.
 
        Rename .eval -> .exec.  Add new .eval.
        * pmacros.scm (-pmacro-built-exec): Renamed from -pmacro-builtin-eval.
        (-pmacro-builtin-eval): New function.
        (pmacros-init!): Add .exec.
        * doc/pmacros.texi: Update, .exec -> .eval.  Document new .eval.
        * testsuite/location-1.test: Update.
        * testsuite/pmacros-1.test: Add test for .eval.
 
2009-08-16  Doug Evans  
 
        * doc/porting.texi: Remove support for Guile 1.4.
 
        * read.scm (current-reader-location): Return unspecified location
        if reader hasn't been initialized yet.
 
2009-08-13  Doug Evans  
 
        * dev.scm: Document tracing options.
 
        * pmacros.scm (pmacro-dump): New function.
        (check-pmacro): Tweak debugging output.
        * doc/cgenint.texi: Mention pmacro-dump, pmacro-debug.
        * doc/pmacros.texi (.splice): Use pmacro-dump instead of pmacro-expand.
 
        Add .let* pmacro builtin.
        * pmacros.scm (-pmacro-builtin-let*): New function.
        (pmacros-init!): Add .let*.
        * doc/pmacros.texi: Document .let*.
        * testsuite/pmacros-1.test: Test .let*.
 
2009-08-12  Doug Evans  
 
        Clean up cpu file parsing, pass context consistently instead of the
        old "errtxt" argument.
        NOTE: ACU == "All Callers Updated".
        * attr.scm (-parse-simple-attribute): Renamed from
        parse-simple-attribute, ACU.
        (-attr-parse): Change errtxt argument to context, ACU.
        (-attr-read): Ditto.
        (atlist-parse): Ditto.  Put context arg first.
        (attr-parse): Use parse-error instead of context-error.
        * enum.scm (parse-enum-vals): Change errtxt argument to context, ACU.
        (-enum-parse-prefix, -enum-parse, -enum-read): Ditto.
        * hardware.scm (-keyword-parse): Renamed from keyword-parse.
        `context' arg is now a  object.  ACU.
        (-keyword-read): `context' arg is now a  object.  ACU.
        (-hw-parse-indices): Change errtxt argument to context, ACU.
        (-hw-parse-values, -hw-parse-handlers): Ditto.
        (-hw-parse-getter, -hw-parse-setter, -hw-parse, -hw-read): Ditto.
        (-hw-validate-layout, -hw-create-getter-from-layout,
        -hw-create-setter-from-layout): Ditto.
        (:parse!, :parse!): Ditto.
        (:parse!, :parse!): Ditto.
        (:parse!): Ditto.
        * ifield.scm (-ifield-parse, ifield-read): Ditto.
        (-ifld-parse-follows, -ifld-parse-encode-decode): Ditto.
        (-ifld-parse-encode, -ifld-parse-decode): Ditto.
        (-multi-ifield-parse, -multi-ifield-read): Ditto.
        * insn.scm (-insn-parse, -insn-read): Ditto.
        (parse-syntax): Ditto.  Put context arg first.
        (-parse-insn-format-symbol): Change errtxt argument to context, ACU.
        (-parse-insn-format-ifield-spec, -parse-insn-format-list): Ditto.
        (-parse-insn-format): Ditto.
        * mach.scm (-arch-parse-alignment, -arch-parse-machs): Ditto.
        (-arch-parse-isas): Ditto.
        (-isa-read): Add context arg, ACU.
        (-cpu-parse, -cpu-read, -mach-read): Ditto.
        * minsn.scm (-minsn-parse-expansion): Change errtxt argument to
        context, ACU.
        (-minsn-parse, -minsn-read, -minsn-compute-iflds): Ditto.
        (minsn-make-alias): Ditto.
        * mode.scm (-mode-parse): Ditto.
        (parse-mode-name): Ditto.  Put context arg first.
        * model.scm (-prefetch-parse, -retire-parse, -pipeline-parse): Change
        errtxt argument to context, ACU.
        (-unit-parse, -model-parse, -model-read): Ditto.
        * operand.scm (-operand-parse-getter): Use parse-error instead of
        context-error.
        (-operand-parse-setter): Ditto.
        (-operand-parse): Change errtxt argument to context, ACU.
        (-operand-read, -derived-operand-parse, -derived-operand-read): Ditto.
        (-anyof-operand-parse, -anyof-operand-read): Ditto.
        * read.scm (reader-error): Delete.  Use parse-error instead.
        (parse-error): Change errtxt argument to context, ACU.  Split args
        argument into expr and maybe-help-text.
        (-reader-process-expanded-1!): Reorganize.
        * rtl.scm (-subr-read): Change errtxt argument to context, ACU.
        * types.scm (parse-type): Ditto.
        * utils-cgen.scm (single-location->simple-string): New function.
        (): Replace members file,lineno with location.
        (make-prefix-context): Renamed from context-make-prefix, ACU.
        (make-current-context): New function.
        (context-append, context-append-name): New functions.
        (context-make-reader): Delete.
        (parse-name): Change errtxt argument to context, ACU.
        Put context arg first.
        (parse-comment): Ditto.
        (parse-number): Change errtxt argument to context, ACU.
        (arg-list-validate-name, arg-list-check-no-args,
        arg-list-symbol-arg): Ditto.
 
        * read.scm (-cmd-if): Don't assume test is a list.
 
        * html.scm (get-insn-properties): Delete errtxt, unused.
 
2009-08-11  Doug Evans  
 
        * doc/rtl.texi (hardware types): Add pc.
 
2009-08-07  Doug Evans  
 
        Add -t option for tracing things like commands, pmacro expansion.
        * dev.scm (cload): New arg #:trace.
        * pmacros.scm (-pmacro-expand): Rewrite pmacro tracing.
        (pmacro-trace): New arg `loc'.  Rewrite pmacro tracing.
        (pmacro-debug): Call pmacro-trace instead of -pmacro-expand.
        * read.scm (): New members trace-commands?, trace-pmacros?.
        (-reader-process-expanded-1!): Trace commands if requested.
        (-reader-process!): Call pmacro-trace of pmacro tracing requested.
        (-set-trace-options!): New function.
        (-init-reader!): New function.
        (cpu-load): New arg trace-options, all callers updated.
        Call -init-reader! and -set-trace-options!.
        (cgen-usage): Improve output formatting.
        (common-arguments): New option -t.
        (-cgen): Process -t.
        * utils-cgen.scm (single-location->string): Renamed from
        pretty-print-single-location.  All callers updated.
        (location->string): Renamed from pretty-print-location.
        All callers updated.
        (source-properties-location->string): New function.
        * doc/running.texi: Document -t.
 
2009-08-06  Doug Evans  
 
        * read.scm (debug-env, debug-var-names, debug-var, debug-tty,
        debug-tty-port, debug-repl, debug-quit, debug-repl-env): Move to ...
        * utils.scm: ... here.
 
2009-08-05  Doug Evans  
 
        Track source location better, for better error messages.
        * pmacros.scm (-pmacro-eval): Delete, unused.
        (pmacro-expand, -pmacro-expand): New arg `loc', all callers updated.
        (-pmacro-expand-expr-list, -smacro-apply): Ditto.
        (scan-list, scan): Ditto.
        (-pmacro-builtin-pmacro, -pmacro-builtin-let, -pmacro-builtin-if,
        -pmacro-builtin-case, -pmacro-builtin-cond, -pmacro-builtin-begin,
        -pmacro-builtin-andif, -pmacro-builtin-orif): Ditto.
        (scan-list1): New function.
        (-pmacro-build-lambda): New arg `loc', all callers updated.  Rewrite.
        * read.scm (): New member `location'.
        (-reader-lookup-command): Renamed from reader-lookup-command,
        all callers updated.
        (reader-error): Rewrite to produce better source location info.
        (current-reader-location): New function.
        (-reader-process-expanded-1!): Renamed from -reader-process-expanded-1.
        All callers updated.  Record source location of expression.
        (reader-process-expanded!): Renamed from reader-process-expanded.
        All callers updated.
        (-reader-process!): Renamed from reader-process.  New arg `loc'.
        All callers updated.  Record source location of define-pmacro.
        * utils-cgen.scm (): New class.
        (single-location): New (pseudo) class.
        (pretty-print-single-location, pretty-print-location): New functions.
        (location-top, location-push-single, location-push): New functions.
        (unspecified-location, current-input-location): New functions.
        (location-property): New object property.
        (location-property-set!): New function.
        (): Renamed from .  New member `location'.
        All uses updated.
        * testsuite/location-1.test: New testcase.
        * testsuite/run-tests.sh: Fix fail count handling.
        * testsuite/test-utils.sh.in (run_cgen): New option `-f'.  Allow tests
        to expect cgen to fail.
 
        * pmacros.scm (*): Use "pmacro" instead of "macro" more consistently.
 
        * read.scm (-cmd-include): Renamed from include.  All callers updated.
        (-cmd-if): Renamed from cmd-if.  All callers updated.
        Use reader-process-expanded! on then/else clauses instead of eval1.
 
2009-07-22  Doug Evans  
 
        * modes.scm (TI,OI): New modes.
        * types.scm (parse-type): Improve error checking.  Don't hardwire
        mode names here.
        * utils.scm (non-negative-integer?): New function.
 
        * pmacros.scm (-pmacro-builtin-find): New predicate.
        (pmacros-init!): Add .find.
        * doc/pmacros.tex: Document .find.
        * testsuite/pmacros-1.test: Test .find.
 
2009-07-20  Doug Evans  
 
        * insn.scm (multi-insn-instantiate!): Use logging messages instead of
        commented out printfs.
        * rtl.scm (rtl-finish!): Whitespace tweaks.
        * model.scm (parse-insn-timing): Tweak logging message.
        * operand.scm: Comment and whitespace tweaks.
        (op:type): Tweak error message.
        (op-ifield): Tweak logging message.
        (-derived-operand-parse, anyof-merge-semantics): Ditto.
        * read.scm: Whitespace cleanup.
        * utils.scm: Whitespace cleanup.
 
2009-07-19  Doug Evans  
 
        Fix binding of nested pmacro parameters.
        * pmacros.scm (-pmacro-env-make): New arg prev-env.
        All callers updated.
        (-pmacro-bulid-lambda): Ditto.
        * doc/pmacros.texi: Update.
        * testsuite/pmacros-1.test: Add testcase.
 
        * ifield.scm (-multi-ifield-make-default-insert): Fix shifts
        calculation.
        (-multi-ifield-make-default-extract): Ditto.
 
        * rtl-c.scm (addc-cflag, addc-oflag, subc-cflag, subc-oflag): Define.
        (add-cflag, add-oflag, sub-cflag, sub-oflag): Deprecate.
        * rtx-funcs.scm (addc-cflag, addc-oflag, subc-cflag, subc-oflag):
        Define.
        (add-cflag, add-oflag, sub-cflag, sub-oflag): Deprecate.
        * doc/rtl.texi: Update.
 
        * doc/pmacros.texi (.not): Emphasize (.not 0) is not 1.
 
        Rename builtin boolean pmacros, for consistency with rtl.
        * pmacros.scm: .and -> .andif, .or -> .orif, .bitand -> .and,
        .bitor -> .or, .bitxor -> .xor, .bitinv -> .inv.
        * doc/pmacros.texi: Update.
        * testsuite/pmacros-1.test: Update.
 
2009-07-17  Doug Evans  
 
        Use hash tables to record ifields, operands, insns, macro-insns.
        * attr.scm (attr-builtin!): Tweak some comments.
        * hardware.scm (hardware-builtin!): Call all-isas-attr-value.
        * ifield.scm (): Subclass from  instead of
        .
        (): New constructor.
        (ifield-builtin!): Add isa attr to f-nil, f-anyof.
        * insn.scm (): Subclass from  instead of
        .
        (-sub-insn-make!): Add hack to avoid differences in generated code.
        (multi-insn-instantiate!): Add total number of multi-insns to
        logging message.
        * mach.scm (): Rename members ifld-list, op-list, insn-list,
        minsn-list to foo-table.  New member next-ordinal.
        Update getters/setters.
        (arch-ifld-list, arch-op-list, arch-insn-list, arch-minsn-list):
        New functions.
        (-get-next-ordinal!, -get-lowest-ordinal): New function.
        (-make-ident-object-table, -ident-object-table->list,
        -ident-object-table-add!, -ident-object-table-lookup): New functions.
        (current-ifld-list, current-ifld-add! current-ifld-lookup,
        -ifld-already-defined?): Rewrite.
        (current-op-list, current-op-add! current-op-lookup,
        -op-already-defined?): Rewrite.
        (current-raw-insn-list, insn-list-car, insn-list-splice!): Delete.
        (current-insn-list, current-insn-add! current-insn-lookup,
        -insn-already-defined?): Rewrite.
        (current-minsn-list, current-minsn-add! current-minsn-lookup,
        -minsn-already-defined?): Rewrite.
        (all-isas-attr-value, all-isas-attr, attr-isa-list): New functions.
        (MAX-VIRTUAL-INSNS): Define.
        (arch-analyze-insns!): Add hack to avoid differences in generated code.
        Update use of arch-insn-list.
        (mach-init!): Initialize ifld-table, op-table, insn-table, minsn-table.
        (arch-finish!): Delete references to ifld-list, op-list, insn-list,
        minsn-list.
        * minsn.scm (): Subclass from  instead of
        .  New constructor.
        * operand.scm (): Subclass from  instead of
        .
        * sid.scm (-virtual-insn-add!): New function.
        (-create-virtual-insns!): Call it.
        (-fill-sim-insn-list!): Rewrite.
        * sim.scm (-virtual-insn-add!, -create-virtual-insns!): New functions.
        (sim-finish!): Move contents to -create-virtual-insns!, and call it.
        * utils-cgen.scm (): New class.
        (obj-ordinal, obj-set-ordinal!): New functions.
        (add-ident-methods!): Delete.
 
        * model.scm (parse-insn-timing): Change logging message to level 3.
 
2009-07-16  Doug Evans  
 
        * doc/rtl.texi (Enumerated constants): Add example, fix a typo,
        add a link to define-normal-insn-enum.
 
        * doc/porting.texi (Conventions): Add docs on writing integers.
 
        * cpu/simplify.inc (*): One line doc strings don't need \n.
        (df): Invoke define-full-ifield instead of claiming it's an alias.
        (dno): Define.
        (dnop): Mark as deprecated.
 
        * cpu/play.cpu: Add example of hardware `layout'.
        * doc/porting.tex: Add docs on simplify.inc.
        * doc/rtl.texi: Cleanup pass over "Simplification macros",
        and other things.
 
        * ifield.scm: Whitespace/formatting cleanup.
 
        * ifield.scm (-multi-ifield-parse): Watch for missing subfields.
 
        * read.scm (parse-error): Don't print single entry args as a list.
        (-reader-process-expanded-1): Convert symbol to string for
        string-append.
 
        * insn.scm (multi-insn-instantiate!): Tweak logging message.
 
2009-07-15  Doug Evans  
 
        * cpu/simplify.inc (dno): New pmacro.
        * doc/porting.texi: Add section on simplify.inc.
        * doc/rtl.texi (Instruction operands): Mention dno, dnop.
 
2009-07-15  Doug Evans  
 
        * gen-all-doc: Generate index.html.
 
2009-07-13  Doug Evans  
 
        Extend pmacro language, add testsuite.
        * Makefile.am (SUBDIRS): Add testsuite.
        * Makefile.in: Regenerate.
        * configure.in (AC_OUTPUT): Create testsuite/Makefile,
        testsuite/test-utils.sh.
        * configure: Regenerate.
        * dev.scm (cload): Handle testsuite app.
        (load-testsuite): New function.
        * pmacros.scm: (-pmacro-debug?): New global.
        (-smacro-table): New global.
        (-smacro-lookup, -smacro-set!): New functions.
        (-pmacro-make): New argument `syntactic-form?', all callers updated.
        (-pmacro-syntactic-form?): New function.
        (-pmacro-expected-number, -pmacro-verify-number): New functions.
        (-pmacro-expected-integer, -pmacro-verify-integer): New functions.
        (-pmacro-expected-non-negative-integer): New function.
        (-pmacro-verify-non-negative-integer): New function.
        (-pmacro-expand-expr-list): New function.
        (-pmacro-process-args-1): Renamed from -pmacro-process-args.
        (-pmacro-process-args): Renamed from -pmacro-invoke.
        (-pmacro-apply, -smacro-apply): New functions.
        (-pmacro-expand): Rewrite syntactic form processing.
        (-pmacro-build-lambda): Reformat.
        (define-pmacro): Watch for more errors in definition.
        (pmacro-debug): New function.
        (pmacro-trace): Set/reset -pmacro-debug?.
        (all existing builtin pmacro helpers): Rename to -pmacro-builtin-foo.
        (-pmacro-builtin-substring): Fix.  Add support for `end' marker.
        (-pmacro-builtin-for-each, et.al.): New helpers for .for-each, .let,
        .if, .case, .cond, .begin, .print, .dump, .error, .list, .ref,
        .length, .replicate, .equals, .and, .or, .not, .eq, .ne, .lt, .gt,
        .le, .ge, .add, .sub, .mul, .div, .rem, .sll, .srl, .sra, .bitand,
        .bitor, .bitxor, bitinv, .car, .cdr, .caar, .cadr, .cdar, .cddr.
        (pmacros-init!): Initialize -smacro-table.
        Rewrite pmacro initialization.
        * read.scm (reader-process-expanded): Renamed from
        -reader-process-expanded.  All callers updated.
        Recognize () as a no-op.
        (cpu-load): Tweak logging messages.
        * utils.scm (message): Add comment.
        * cpu/play.cpu: Add some instructions to play with .let.
        * doc/cgenint.texi: Move some debugging related docs to here from
        cgen.texi.
        * doc/pmacros.texi: Reorganize.  Add docs for new builtin pmacros.
        * testsuite/Makefile.am: New file.
        * testsuite/Makefile.in: New file.
        * testsuite/test-utils.sh.in: New file.
        * testsuite/run-tests.sh: New file.
        * testsuite/testsuite.cpu: New file.
        * testsuite/pmacros-1.test: New file.
 
        * decode.scm: Comment and formatting tweaks.
        (-build-decode-table-guts): Add more data to logging message.
 
2009-07-12  Doug Evans  
 
        Delete files that now live in ../cpu.
        * cpu/iq10.cpu: Delete.
        * cpu/iq2000.cpu: Delete.
        * cpu/iq2000.opc: Delete.
        * cpu/iq2000m.cpu: Delete.
        * cpu/m32r.cpu: Delete.
        * cpu/m32r.opc: Delete.
 
2009-07-09  Doug Evans  
 
        * utils-sim.scm (-gen-decode-bits): New argument `entire-val'.
        All callers updated.  Work around -ve shifts by referencing the
        entire value.
 
        * utils.scm (message): Handle pairs.
 
2009-07-08  DJ Delorie  
 
        * cpu/mep-ivc2.cpu (cpmovtocsar0_C3, cpmovtocsar1_C3,
        cpmovtocc_C3, cpmovtocsar0_P0S_P1, cpmovtocsar1_P0S_P1,
        cpmovtocc_P0S_P1): Mark volatile.  Note which registers are
        written to.
 
2009-07-07  Doug Evans  
 
        * cpu/play.cpu (add): Use (ifield enum) for one format element.
        * cpu/play.opc: New file.
 
        Allow arbitrary enums in instruction formats, e.g. (f-op1 OP1_4).
        * insn.scm (-parse-insn-format-ifield-spec): Recognize (ifield enum).
        * doc/rtl.texi (Instructions): Update.
 
        * cgen-opc.scm (-opc-file-path,opc-file-path): Move to opcodes.scm
        (opc-arguments, -OPC): Call set-opc-file-path!.
        * opcodes.scm (-opc-file-path,opc-file-path): Moved here.
        (set-opc-file-path!): New function.
        * dev.scm: Mention set-opc-file-path!.  Mention doc options.
 
        * opc-ibld.scm (gen-insn-builder): Convert symbols to strings
        before passing to gen-c-args.
 
2009-07-06  DJ Delorie  
 
        * cpu/mep-core.cpu (fsft, ssarb): Mark as VOLATILE.
        * cpu/mep-ivc2.cpu (many): Add VOLATILE to more insns that make
        unspecified accesses to control registers.
 
2009-07-01  DJ Delorie  
 
        * cpu/mep-ivc2.cpu: Add VOLATILE to insns that make
        unspecified accesses to control registers.
 
        * cpu/mep-ivc2.cpu (cmov, cmovc, cmovh): Add intrinsic names to VLIW variants.
        (ivc2rm, ivc2crn): Make data type consistent with non-VLIW variants.
 
2009-06-27  Doug Evans  
 
        * gen-all-intrinsics: New file.
 
2009-06-24  Doug Evans  
 
        * All *.scm files: Update copyright year.
        * utils.scm (copyright-fsf, copyright-redhat): Ditto.
 
2009-06-23  DJ Delorie  
 
        * intrinsics.scm: Updates to support IVC2.
        (belongs-to-group?): Check IVC2 slots.
        (-slots-attribute): New.
        (targets::attributes): Add SLOTS.
        (target:add-well-known-intrinsics): Add CPMOV.
        (md-insn): Add CPTYPE and CRET?.
        (add-md-insn): Likewise.
        (add-intrinsic-for-isa): Disable the duplicate tests, as IVC2 has
        duplicate insns with different bit patterns.
        (write-cgen-insn?): Add cret? support.
        (intrinsics.h): Add vector types.
        (runtime-op): Add vector support.
        (intrinsic-protos.h): Let GCC define its types.  Add cret? support.
 
        * cpu/mep-core.cpu: Add CPTYPE and CRET attributes.
        * cpu/mep-ivc2.cpu: Update all insns to include type information.
        (h-cr-ivc2): Default to typeless.
        (h-ccr-ivc2): Fix register width.
        (SLOTS): Fix values and default.
        (ivc2_*): Add control register names.
        (crop, crqp, crpp, croc, crqc, crpc): Default to typeless.
 
        * cpu/mep.opc (mep_cgen_insn_supported_asm): New, skip the short
        version of BSR when assembling VLIW bundles.  Use it in mep-asm.c
 
2009-06-22  Doug Evans  
 
        * semantics.scm (insn-build-known-values): Fix typo in comment.
 
2009-06-21  Doug Evans  
 
        * rtl-xform.scm (rtx-simplify-insn): New function.
        * html.scm (gen-insn-docs): Call it.
        * sem-frags.scm (sem-find-common-frags, -frag-test-data): Ditto.
        * iformat.scm (ifmt-analyze): Minor simplification.
 
        * semantics.scm (semantic-compile): Change arg sem-code-list to
        sem-code.
        (semantic-attrs): Ditto.
        * iformat.scm (ifmt-analyze): Update.
        (ifmt-compute!): Update.
        * rtl-traverse.scm (-compile-expr-fn, rtx-compile): Move to
        rtl-xform.scm.
        (-rtx-trim-args, -rtx-trim-for-doc, rtx-trim-for-doc): Ditto.
        * rtl.scm (-rtx-canonicalize-expr, rtx-canonicalize): Ditto.
        * semantics.scm (rtx-simplify): Ditto.
        (rtx-const-equal, rtx-const-list-equal): Ditto, and make local.
        (rtx-simplify-eq-attr-mach, rtx-simplify-eq-attr-insn): Ditto.
        (-simplify-expr-fn): Move to rtl-xform.scm.
        (-solve-expr-fn, rtx-solve): Ditto.
        * rtl-xform.c: New file.
        * read.scm: Load it.
 
        * rtl-c.scm (delay): Add FIXME, tweak formatting.
        * rtl-traverse.scm (-rtx-traverse-expr): Tweak comments.
        (-rtx-traverse, rtx-traverse): Ditto.
 
2009-06-20  Doug Evans  
 
        * doc/rtl.texi (Expressions): Enhance docs of shift ops.
 
        * configure.in: Update version to 1.1.
        * configure: Regenerate.
        * read.scm (-CGEN-VERSION): Update to 1.1.0.
 
2009-06-20  Masaki Muranaka  
            Doug Evans  
 
        * desc-cpu.scm (cgen-desc.h): Tweak logit message for consistency.
        (cgen-desc.c): Ditto.
        * sid-cpu.scm (cgen-desc.h, cgen-cpu.h, cgen-defs.h): Ditto.
        (cgen-write.cxx, cgen-semantics.cxx, cgen-sem-switch.cxx): Ditto.
        * sid-decode.scm (cgen-decode.h, cgen-decode.cxx): Ditto.
        * sid-model.scm (cgen-model.cxx, cgen-model.h): Ditto.
        * sim-arch.scm (cgen-arch.h, cgen-arch.c): Ditto.
        (cgen-cpuall.h, cgen-ops.c): Ditto.
        * sim-cpu.scm (cgen-cpu.h, cgen-defs.h, cgen-cpu.c): Ditto.
        (cgen-read.c, cgen-write.c, cgen-semantics.c): Ditto.
        (cgen-sem-switch.c): Ditto.
        * sim-decode.scm (cgen-decode.h, cgen-decode.c): Ditto.
        * sim-model.c (cgen-model.c): Ditto.
 
2009-06-18  Doug Evans  
 
        * gen-all-doc: Add fr30, ip2k, iq2000, lm32, mep, mt.
 
        * html.scm (doc-analyze!): Provide default IDOC attribute if missing.
 
        * dev.scm (cload): Change #:arch argument to take the path to the
        .cpu file instead of just the name of the architecture.
        * read.scm (arch-path): Remove trailing '/'.
        (cpu-load): Set `arch-path' to directory of .cpu file.
        (-cgen): Don't set `arch-path' here.
        (include): Update.
        * doc/porting.texi: Update.
 
2009-06-14  Doug Evans  
 
        * gen-all-doc: Use files in ../cpu where possible.
 
        * Makefile.am (ARCHFILE): Fix path.
        * Makefile.in: Regenerate.
        * html.scm: Use "pre" instead of "plaintext".
 
        * doc/cgenint.texi: Renamed from internals.texi.  Several cleanups.
        * doc/app.texi: Cleanup pass.
        * doc/cgen.texi: Cleanup pass.
        * doc/glossary.texi: Add entries for ifield, iformat, sformat, insn.
        * doc/intro.texi: Cleanup pass.
        * doc/mdate-sh: New file.
        * doc/opcodes.texi: Cleanup pass.
        * doc/pmacros.texi: Cleanup pass.
        * doc/porting.texi: Cleanup pass.
        * doc/rtl.texi: Cleanup pass.
        * doc/running.texi: Cleanup pass.  Document more runtime options.
        * doc/stamp-vti: Update.
        * doc/version.texi: Update.
 
        * Makefile.am (AUTOMAKE_OPTIONS): Add 1.9
        (GUILE): Fix definition.
        * Makefile.in: Regenerate with automake 1.9.6.
        * aclocal.m4: Regenerate with aclocal 1.9.6.
        * configure.in (AC_PREREQ): Set to 2.59.
        (GENINSRC_NEVER): Define.
        * configure: Regenerate with autoconf 2.59.
        * doc/Makefile.am (info_TEXINFOS): Add cgenint.texi.
        (cgen.info,cgen.dvi): Delete.
        (cgen_TEXINFOS,cgenint_TEXINFOS): Define.
        (noinst_TEXINFOS): Add cgenint.texi.
        (DOCFILES): Add missing files.
        (MAINTAINERCLEANFILES,DISTCLEANFILES): Define.
        * doc/Makefile.in: Regenerate with automake 1.9.6.
 
        * guile.scm: Add "." to %load-path if >= guile version 1.8.
 
        * attr.scm: Removing trailing whitespace.
        * cgen-intrinsics.scm: Ditto.
        * cgen-sim.scm: Ditto.
        * cos.scm: Ditto.
        * enum.scm: Ditto.
        * guile.scm: Ditto.
        * sim.scm: Ditto.
 
2009-05-28  DJ Delorie  
 
        * cpu/mep.opc (parse_signed16_range): New.
        (parse_unsigned16_range): New.
        * cpu/mep-ivc2.cpu (imm16p0, simm16p0): Use them.
 
2009-05-26  DJ Delorie  
 
        * cpu/mep-ivc2.cpu (h-ccr-ivc2): Enable for C3 slots, fix
        accumulator names.
        (f-ivc2-ccrn-c3hi): New.
        (f-ivc2-ccrn-c3lo): New.
        (f-ivc2-ccrn-c3): New.
        (ivc2c3ccrn): Use it.
 
2009-05-22  DJ Delorie  
 
        * cpu/mep.opc (mep_examine_ivc2_insns): Fix bug in ivc2 decoder.
        (mep_config_map): Regenerate.
 
        * cpu/mep-ivc2.cpu (h-ccr-ivc2): Add generic names as well as
        ivc2-specific names.
        (simm8p20): New.
        (cmovc): move to after field definitions, use ivc2-specific
        register names.
        (cpmovi_b_P0S_P1): New.
 
2009-05-19  DJ Delorie  
 
        * cpu/mep.opc: Regenerate configuration.
        (parse_cdisp10): Only check CPU flags, not COP flags.
        (check_configured_mach): Likewise.
 
2009-05-13  DJ Delorie  
 
        * intrinsics.scm (insns.md): Add RTL predicates.
        (intrinsics.h): Remove old C intrinsics.
 
2009-04-29  DJ Delorie  
 
        * mep-ivc2.cpu: New.
        * mep-core.cpu: Regenerated.  Add support for deferred register
        writes.
        (SLOT): Add IVC2 slot types.
        (sim-syscall): Rename to something more appropriate.
        * mep-ext-cop.cpu: Regenerate.
        * mep.opc: Regenerate.  Add "coprocessor supported" define area.
        (print_slot_insn): New.
        (mep_examine_ivc2_insns): New.
        (mep_print_insn_set_ivc2_mode): New.
        (mep_print_insn): Support IVC2 slotting.
 
2009-04-20  DJ Delorie  
 
        * intrinsics.scm (intrinsics-analyze!): Include aliases.
        (guess-mode): Drop COP* syntax.
        (need-insn): Add "--syscall--" to the list.
        (enum-type): Drop COP* syntax.
        (intrinsics.h): Likewise.
        (intrinsic-protos.h): Change file header to allow it to be
        included.
 
2009-04-17  DJ Delorie  
 
        * cpu/mep-c5.cpu (f-12s20): Change to signed.
        (lhucpm1): Limit to C5 mach.
        (dsp0,dsp1): Rewrite as aliases so that intrinsics are generated.
        * cpu/mep-core.cpu (extend-cdisp10): New.
        (f-cdisp10): Change to signed, use extend-cdisp10 to sign extend.
 
2009-04-08  DJ Delorie  
 
        * cpu/mep-c5.cpu: New.
        * cpu/mep-core.cpu: Add C5 support.
        * cpu/mep.opc: Likewise.
 
2009-02-18  Pierre Muller  
 
        * opc-itab.scm (<>_cgen_init_opcode_table): Avoid compiler warning
        about calling memset with a zero length.
 
2009-02-03  DJ Delorie  
 
        * cpu/mep-core.cpu: Update to new MeP configuration.
        * cpu/mep-ext-cop.cpu: Likewise.
        * cpu/mep.opc: Likewise.
 
2008-12-23  Frank Ch. Eigler  
 
        * sim.scm (-op-gen-queued-write): Add needed symbol->string.
 
2008-06-17  Dave Brolley  
 
        * cpu/xstormy16.cpu (h-pc): Add a set handler.
        (h-gr): Likewise.
 
2007-11-13  Dave Brolley  
 
        * cgen-intrinsics.scm (load-files): Remove reference to fixup.scm.
 
2007-11-05  Dave Brolley  
 
        * intrinsics.scm,cgen-intrinsics.scm: New application which
        generates code to support intrinsic functions for insns in the
        mep architecture in gcc.
 
2007-09-21  Dave Brolley  
 
        * cpu/mep-core.cpu (rnc, rnuc, rns, rnus, rn3c, rn3uc, rn3s)
        (rn3us): CDATA attribute now LONG.
 
2007-08-21  Dave Brolley  
 
        * rtl-c.scm (const): Generate call to MAKEDI for integers larger
        than 32 bits.
 
2007-07-05  Nick Clifton  
 
        * utils.scm (copyright-fsf): Update copyright notice to refer to
        the GPL version 3.
 
2007-05-22  Nick Clifton  
 
        * doc/cgen.texi: Use @copying around the copyright notice.
        * doc/internals.texi: Likewise.
 
2007-02-05  Dave Brolley  
 
        * *mep*: New cpu description for Toshiba Media Processor (MeP).
 
2007-02-05  Dave Brolley  
 
        * opc-asmdis.scm (-gen-init-asm-fn): Include CGEN_ASM_INIT_HOOK
        in the generated code for @arch@_cgen_init_asm if it is defined.
 
        * Contribute the following changes:
        2005-04-05  Richard Sandiford  
 
        * attr.scm (): New attribute class.
        (attr-kind): Handle .
        (parse-simple-attribute): New function.
        ( 'parse-value): Use parse-simple-attribute.
        ( 'parse-value): Likewise.
        ( 'parse-value): Likewise.
        ( 'parse-value): Likewise.
        ( 'parse-value): New function.
        (-attr-parse): Handle .
        (-attr-read): Likewise.
        ( 'gen-value-for-defn-raw): New function.
        ( 'gen-value-for-defn): New function.
 
2006-11-07  Dave Brolley  
 
        * sid-model.scm (gen-model-unit-fn-decl): Use symbol->string where
        necessary.
 
2006-10-18  Dave Brolley  
 
        * Contribute the following changes:
 
        2006-07-11  Dave Brolley  
 
        * cpu/sh64-compact.cpu (movual, movual2): New insns.
        (movcol): New insn.
        * cpu/sh.cpu (sh4a-nofpu-models): New pmacro.
        * sid.scm (-op-gen-delayed-set-maybe-trace): If delay used, note the
        hardware or memory mode which was used.
        * sid-cpu.scm (hw-need-write-stack?): New function.
        (-gen-hw-stream-and-destream-fns): Compute stack-regs. Use it to
        identify hardware which uses write stacks.
        (useful-mode-names): Renamed to write-stack-memory-mode-names.
        Initialized to an empty list.
        (-gen-writestacks, -gen-reset-fn, -gen-unified-write-fn): Use
        hw-need-write-stack?.
        * hardware.scm (used-in-delay-rtl?): New member of .
        (define-getters ): Define used-in-delay-rtl?.
        (used-in-delay-rtl?): New method of .
        (hw-used-in-delay-rtl?): New function.
 
        2006-06-20  Dave Brolley  
 
        * sid.scm (gen-attr-type): Removed.
        * cpu/sh.cpu (SH2a-nofpu-MACH): Add sh5.
        (SH2a-MACH): Add sh5.
        (sh2a-nofpu-models): Add units for sh5.
        (sh2a-fpu-models): Likewise.
 
        2006-06-15  Dave Brolley  
 
        * cpu/sh-sim.cpu: New file.
        * cpu/sh-sid.cpu: New file.
        * cpu/sh64-media.cpu (dshci): Add xtiming argument and splice it in.
        (All fields): Remap for (insn-lsb0? #f)
        (All insns): Add timing specs.
        * cpu/sh64-compact.cpu (dshcf,dshcop): Replace 'ignored' argument with
        'xattrs' and .splice it in.
        (32-BIT-INSN,SH4-GROUP,SH4A-GROUP): New insn attributes.
        (h-frc,h-drc): Add PROFILE attribute.
        (h-fpccr): Removed.
        (h-vbr): New hardware.
        (All fields): Remap for (insn-lsb0? #f)
        (f-imm20-hi,f-imm20-lo,f-imm20): New fields.
        (fr0,fmovm,fmovn,imm20,imm12x4,imm12x8,vbr): New operands.
        (fpscr): Use h-fpscr.
        (fsdm,fsdn): Use h-fsd.
        (dshci): Add xtiming argument and splice it in.
        (dr,xd): pmacros removed.
        (All insns): Add timing specs, *-MACH attribibutes,
        SH4{A}-GROUP attributes.
        (divu,mulr,ldc-vbr,ldc-sr,ldcl-vbr,movl12,movl13,stcl-vbr): New insns.
        * cpu/sh.cpu): Include sh-sid.cpu or sh-sim.cpu depending on whether
        we're being processed for sim or sid.
        (define-arch): Change insn-lsb0? for #f. Add machs sh2e, sh2a-fpu,
        sh2a-nofpu, sh4-nofpu, sh4a-nofpu, sh4a, sh4al.
        (define-isa compact): Add (isa-parallel-insns 2).
        (define-isa media): Add (isa-parallel-insns 2). Add
        (default-insn-word-bitsize 32). Change base-insn-bitsize to 32.
        (define-mach): Add sh2e, sh2a-fpu, sh2a-nofpu, sh4-nofpu, sh4a-nofpu,
        sh4a, sh4al
        (SH2-MACH, SH2e-MACH, SH2a-nofpu-MACH, SH2a-MACH, SH3-MACH)
        (SH3e-MACH, SH4-nofpu-MACH, SH4-MACH, SH4a-nofpu-MACH, SH4a-MACH)
        (SH4al-MACH, SH5-MACH): New pmacros.
        (common-units, common-fp-units, sh2a-nofpu-units, sh2a-fpu-units)
        (sh4-nofpu-units, sh4-common-fp-units, sh5-media-units)
        (sh5-media-fp-units, common-model, common-model-with-fp)
        (sh3-model, sh3e-model): New pmacros.
        (define-model sh2): New model.
        (define-model sh2e): New model.
        (define-model sh3): New model.
        (define-model sh3e): New model.
        (define-model sh2a-nofpu): New model.
        (define-model sh2a-fpu): New model.
        (define-model sh4-nofpu): New model.
        (define-model sh4): New model.
        (define-model sh4a-nofpu): New model.
        (define-model sh4a): New model.
        (define-model sh4al): New model.
        (define-model sh5-media): New model.
        (define-model sh5): Add all units.
        (all-models, sh2e-models, sh2a-nofpu-models, sh2a-fpu-models)
        (sh3-models, sh3e-models, sh4-nofpu-models, sh4-models)
        (sh5-media-models, shad-models, fsqrt-models): New pmacros.
        (h-pc): Add PROFILE attribute.
        (h-fr): Likewise.
        (h-tr): Likewise.
        (h-gr,h-grc): Likewise.
        (h-cr): Set h-sr in setter.
        (h-frbit): Get/Set h-fpscr.
        (h-szbit,h-prbit): Likewise.
        (h-fp): Add PROFILE attribute. Now indexed by even indices 0-62.
        Add getter and setter.
        (h-fc): Add PROFILE attribute. Now indexed by quad indices 0-60.
        Adjust getter and setter.
        (h-fmtx): Add PROFILE attribute. Now indexed by 0, 16, 32 and 48.
        Adjust getter and setter.
        (h-dr): Add PROFILE attribute. Now indexed by even indices 0-62.
        (h-fsd,h-fmov): New hardware.
 
2006-07-24  Ralk Wildenhues  
 
        * doc/app.texi, doc/internals.texi, doc/intro.texi,
        doc/notes.texi, doc/porting.texi, doc/running.texi,
        doc/sim.texi: Fix some typos.
 
2006-07-14  Dave Brolley  
 
        * sid.scm (-op-gen-delayed-set-maybe-trace): If delay used, note the
        hardware or memory mode which was used.
        * sid-cpu.scm (hw-need-write-stack?): New function.
        (-gen-hw-stream-and-destream-fns): Compute stack-regs. Use it to
        identify hardware which uses write stacks.
        (useful-mode-names): Renamed to write-stack-memory-mode-names.
        Initialized to an empty list.
        (-gen-writestacks, -gen-reset-fn, -gen-unified-write-fn): Use
        hw-need-write-stack?.
        * hardware.scm (used-in-delay-rtl?): New member of .
        (define-getters ): Define used-in-delay-rtl?.
        (used-in-delay-rtl?): New method of .
        (hw-used-in-delay-rtl?): New function.
 
2006-06-20  Dave Brolley  
 
        * sid.scm (gen-attr-type): Removed.
 
2006-05-10  Dave Brolley  
 
        * read.scm (cmd-if): Provide the correct argument to reader-error. Add
        support for (if (application-is? ) (...) (...)).
        (-cgen): Add trailing "/" to arch-path.
        * utils.scm (dirname): Removed. dirname is a primitive function.
 
2006-05-09  Dave Brolley  
 
        * utils-sim.scm (-gen-decode-insn-entry): Generated code should shift
        'entire_insn' not 'base_insn'.
        * sid-model.scm (-gen-model-class-decls): Handle the case where insn-timing
        is null.
        * sim.scm (-gen-arch-model-decls): Likewise.
        * sid-cpu.scm (-gen-scache-semantic-fn): Generate code to set
        abuf->written if profiling.
        (-gen-hw-stream-and-destream-fns): Use symbol->string instead of
        object->string om the mode.
        (-hw-gen-write-stack-decl): Likewise.
        * read.scm (include): Use arch-path as file location.
        (arch-path): Define it with a default setting.
        (-cgen): Update arch-path when "-a" option is specified.
        * utils.scm (dirname): New function.
 
2006-05-05  Steve Ellcey  
 
        * configure.in: Remove AC_ARG_PROGRAM.
        * configure: Regenerate with autoconf 2.59.
 
2006-03-14  Hans-Peter Nilsson  
 
        * dev.scm (cload) : New case, duplicated from
        SIMULATOR.
 
2006-03-03 Shrirang Khisti 
 
        * cpu/xc16x.opc (parse_hash): Return NULL if the input was parsed
        or an error message otherwise.
        (parse_dot, parse_pof, parse_pag, parse_sof, parse_seg): Likewise.
        Fix up comments to correctly describe the functions.
 
2006-02-17  Shrirang Khisti  
            Anil Paranjape   
            Shilin Shakti    
 
        * cpu/xc16x.cpu: New file containing complete CGEN specific XC16X
        CPU description.
        * cpu/xc16x.opc: New file containing supporting XC16C routines.
 
2006-02-10  Nick Clifton  
 
        * cpu/iq2000.opc (parse_hi16): Truncate shifted value to 16 bits.
 
2005-12-28  Nathan Sidwell  
 
        * sid-cpu.scm (-gen-hw-stream-and-destream-fns): Stringize mode
        for concatenation.
        (-hw-gen-write-stack-decl): Likewise.
 
2005-12-05  Hans-Peter Nilsson  
 
        * utils-sim.scm (-gen-decode-insn-entry): Correct last change for
        non-(adata-integral-insn? CURRENT-ARCH) case.
 
2005-10-28  Dave Brolley  
 
        Contribute the following changes:
        2005-09-19  Dave Brolley  
 
        * attr.scm (gen-value-for-defn-raw): New methods.
        (gen-value-for-defn): Don't test for 'SID-SIMULATOR. Call
        gen-value-for-defn-raw.
        * sid.scm (gen-obj-attr-sid-defn): Call gen-value-for-defn-raw.
 
        2002-12-13  Dave Brolley  
 
        * utils-cgen.scm (gen-attr-type): Moved from sid.scm.
        (-gen-attr-accessors): New function.
        (gen-obj-attr-defn): Update terminating initializer.
        (gen-obj-attr-end-defn): New function.
        * sid.scm (gen-attr-type): Moved to utils-cgen.scm.
        * sid-cpu.scm (cgen-desc.h): Generate code to include
        "opcode/cgen-bitset.h"
        * intrinsics.scm (kept-insn-isas): Correct the extraction of the isa
        name.
        * desc.scm ('gen-defn): Update terminating initializer.
        * desc-cpu.scm (gen-ifld-decls): Call -gen-attr-accessors. Update
        terminatinig initializer.
        (gen-hw-decls): Ditto.
        (gen-operand-decls): Ditto.
        (gen-insn-decls): Ditto.
        (-gen-hash-defines): Generate code to include "opcde/cgen-bitset.h"
        (gen-insn-table): Update terminating initializer.
        (-gen-cpu-open): Update generation of @arch@_cgen_rebuild_tables,
        @arch@_cgen_cpu_open, @arch@_cgen_cpu_close.
        * attr.scm (charmask-bytes): New function.
        (bitset-attr->charmask): New function.
        (): Handle isa-attributes specially. Also handle
        differences for SID-SIMULATOR.
        (): Handle differences for SID-SIMULATOR.
        (): Ditto.
 
2005-10-26  Kazuhiro Inaoka 
 
        * cpu/m32r.opc (parse_hi16): Do not assume a 32-bit host word size.
 
2005-10-24  DJ Delorie  
 
        * operand.scm (-anyof-merge-syntax): Print a more useful error
        message.
 
2005-10-19  Nick Clifton  
 
        * cpu/m32r.opc (parse_slo16): Fix bad application of previous
        patch.
 
2005-10-18  Andreas Schwab  
 
        * cpu/m32r.opc (parse_slo16): Better version of previous patch.
 
2005-10-14  Kazuhiro Inaoka 
 
        * cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word
        size.
 
2005-08-02  Dave Brolley  
 
        * rtl-c.scm (s-unop): Don't dereference
        CGEN_CPU_FPU (current_cpu)->ops->xxxxx in the generated code.
        (s-binop, s-convop, s-cmpop): Likewise.
 
2005-07-29  Dave Brolley  
 
        * sid-cpu.scm (-gen-scache-semantic-fn): Generate a declation of 'written'
        if with-profile or with-parallel-write.
        (cgen-semantics.cxx): Make the @prefix@ namespace available if with-parallel.
        * operand.scm (op:new-mode): Convert (obj:name op) to a string for
        string-append.
 
2005-07-15  Alan Modra  
 
        * cpu/fr30.opc (print_register_list): Correct format strings.
        * cpu/ip2k.opc: Likewise.
 
2005-07-05  Nick Clifton  
 
        * cpu/iq2000.opc (parse_lo16, parse_mlo16): Make value parameter
        unsigned in order to avoid compile time warnings about sign
        conflicts.
 
2005-07-01  Nick Clifton  
 
        * desc-cpu.scm: Update to ISO C90 function declaration style.
        * opc-asmdis.scm: Likewise.
        * opc-ibld.scm: Likewise.
        * opc-itab.scm: Likewise.
        * cpu/fr30.opc: Likewise.
        * cpu/i960.opc: Likewise.
        * cpu/ip2k.opc: Likewise.
        * cpu/iq2000.opc: Likewise.
        * cpu/m32r.opc: Likewise.
        * cpu/openrisc.opc: Likewise.
        * cpu/sh.opc: Likewise.
        * cpu/sparc.opc: Likewise.
        * cpu/xstormy16.opc: Likewise.
 
2005-06-15  Dave Brolley  
 
        * sid-cpu.scm (-gen-hw-stream-and-destream-fns): New function.
        (cgen-cpu.h): Call it.
 
        Contributed on behalf of Graydon Hoare
        2001-06-05  graydon hoare  
 
        * utils.scm (foldl): Define.
        (foldr): Define.
        (filter): Define.
        (union): Define.
        (intersection): Simplify.
        * sid.scm : Set APPLICATION to SID-SIMULATOR.
        (-op-gen-delayed-set-maybe-trace): Define.
        ( 'gen-set-{quiet,trace}): Delegate to
        op-gen-delayed-set-quiet etc. Note: this is still a little tangled
        up and needs cleaning.
        (-with-parallel?): Hardwire with-parallel to #t.
        ( 'cxmake-get): Replace with lookahead-aware code
        * sid-decode.scm: Remove per-insn writeback fns.
        (-gen-idesc-decls): Redefine sem_fn type.
        * sid-cpu.scm (gen-write-stack-structure): Replace parexec stuff
        with write stack stuff.
        (cgen-write.cxx): Replace per-insn writebacks with single write
        stack writeback. Add write stack reset function.
        (-gen-scache-semantic-fn insn): Replace parexec stuff with write
        stack stuff.
        * rtl-c.scm (xop): Clone operand into delayed operand if #:delayed
        estate attribute set.
        (delay): Set #:delayed attribute to calculated delay, update
        maximum delay of cpu, check (delay ...) usage.
        * operand.scm (): Add delayed slot to .
        * mach.scm (): Add max-delay slot to .
        * dev.scm (load-sid): Set APPLICATION to SID-SIMULATOR.
        * doc/rtl.texi (Expressions): Add section on (delay ...).
 
2005-06-13  Jim Blandy  
 
        * pmacros.scm (-pmacro-upcase, -pmacro-downcase): Handle symbols
        as well as strings.
 
2005-06-07  Zack Weinberg  
 
        * doc/porting.texi: Change all mention of md_apply_fix3 and
        gas_cgen_md_apply_fix3 to md_apply_fix and gas_cgen_md_apply_fix
        respectively.
 
2005-05-18  Dave Brolley  
 
        * utils-sim.scm (-gen-decode-default-entry): New function.
        (-gen-decode-insn-entry): Now takes 'invalid-insn' argument. Generate
        code to check that all opcodes bits match.
        (-gen-decoder-switch): Use -gen-decode-default-entry.
 
2005-05-16  Jim Blandy  
 
        * sid.scm (gen-ifetch): Require BITSIZE to be exactly the size
        fetched by one of our GETIMEM* methods.
        * utils-gen.scm (-extract-chunk-specs): Always fetch full
        base-insn-sized chunks.
 
2005-05-10  Nick Clifton  
 
        * Update the address and phone number of the FSF organization in
        the GPL notices in the following files:
        COPYING.CGEN, utils.scm, cpu/iq2000m.cpu, cpu/openrisc.cpu,
        cpu/powerpc.cpu, slib/random.scm
 
2005-05-06  Jim Blandy  
 
        * pprint.scm, cos-pprint.scm: Add documentation.
 
        * pprint.scm (pprint): Don't wipe out elide-table after each call.
 
        * pprint.scm, cos-pprint.scm: New files.
 
2005-04-04  Nick Clifton  
 
        * opcodes.scm (-gen-parse-address): Initialise value to zero to
        avoid a compile time warning.
 
2005-03-18  Nick Clifton  
 
        * cpu/ip2k.opc (parse_lit8): Change wording of error message to
        "percent-operand" from "%operand" as the latter confuses xgettext
        into thinking that it is a C printf formating directive, which
        prevents proper translation.
 
2005-02-23  Nick Clifton  
 
        * opcodes.scm (gen-parse-number): Add a cast to the desired
        pointer signed'ness in order to prevent compile time warnings.
        * cpu/ip2k.opc: Fixed compile time warnings about differing
        signed'ness of pointers passed to functions.
        * cpu/iq2000.opc: Likewise.
        * cpu/m32r.opc: Likewise.
        * cpu/openrisc.opc: Likewise.
        * cpu/xstormy16.opc: Likewise.
 
2005-02-22  Alan Modra  
 
        * desc-cpu.scm (gen-ifld-decls): Move cgen_ifld_table from here..
        (cgen-desc.h): ..to here, after opcode/cgen.h include.
 
2005-02-16  Dave Brolley  
 
        * utils.scm: Update copyright years.
        * utils-gen.scm (gen-ifld-extract): Pass base-length to -gen-ifld-extract-base.
        * sid.scm (gen-ifetch): Handle the case where bitsize == 24.
        * operand.scm (-derived-operand-parse): Move logit message from level 1
        to level 2.
 
2005-02-15  Nick Clifton  
 
        * opc-itab.scm (-gen-ifmt-table-1): Add an ATTRIBUTE_UNUSED to
        prevent compile time warning messages.
        * opc-opinst.scm (-gen-operand-instance-table): Likewise.
        * utils-gen.scm (attr-int-gen-defn): Likewise.
        (attr-gen-defn): Likewise.
        * cpu/ip2k.opc (parse_addr16_p): Remove unused function.
        (print_dollarhex16): Remove unused function.
 
2005-02-15  Jim Blandy  
 
        * guile.scm (cgen-call-with-debugging): Doc fix.
 
        Make backtraces work more reliably.
        * guile.scm: Set up debugging parameters, and enable debugging and
        source positions while loading.
        (cgen-call-with-debugging, cgen-debugging-stack-start): New
        functions.
        * read.scm: Don't set debugging parameters here.
        (catch-with-backtrace): Function deleted.
        (-cgen): Simply note the presence or absence of the -b option.
        Pass the flag to cgen-call-with-debugging, so debugging is turned
        off here if the user didn't request it, for faster computation.
        (cgen): Call cgen-debugging-stack-start here, instead of
        catch-with-backtrace.
 
        * Makefile.am (GUILE): Explicitly load guile.scm here, and leave a
        trailing -s.
        (desc, html, opcodes, sim-arch, sim-cpu, gas-test, sim-test):
        Don't write out the trailing -s here.
        * Makefile.in: Regenerated.
        * cgen-doc.scm, cgen-gas.scm, cgen-stest.scm): Don't load
        fixup.scm here; let the caller decide which Scheme's customization
        file to preload.
        * dev.scm: Load guile.scm, not fixup.scm.
        * fixup.scm: Deleted; contents have all moved to guile.scm.
        * README: Doc fix.
 
        * guile.scm (debug-write): New function.
 
2005-02-14  Jim Blandy  
 
        * pmacros.scm (pmacros-init!): For .eval macros, use eval1 as the
        transformer procedure, not eval.  Transformer procedures take one
        argument.
 
2005-02-11  Nick Clifton  
 
        * cpu/iq2000.opc (parse_jtargq10): Change type of valuep argument
        to 'bfd_vma *' in order avoid compile time warning message.
 
2005-02-09  Jim Blandy  
 
        * cgen-sim.scm (load-files): Don't load fixup.scm.  (See
        corresponding change in the sim/common directory.)
 
2005-02-07  Jim Blandy  
 
        * cgen-opc.scm: Don't load fixup.scm here.  (See corresponding
        changes in the opcodes directory.)
 
        * guile.scm: New file, containing Guile-specific definitions and
        adaptations.  This is loaded by the app-specific shell scripts.
        Initially identical to fixup.scm.
        * cgen-sid.scm: Don't load fixup.scm here.
 
        * cos.scm: Profile elm-xset! when requested, not elm-set!; the
        latter is a macro.
 
2005-01-27  Jim Blandy  
 
        * utils.scm (string/symbol->append): Renamed from 'concat'.
        * opcodes.scm (gen-switch): Use new name.
        * insn.scm (-sub-insn-make!): Same.
        * rtl.scm (rtx-dump): Same.
        * semantics.scm (semantic-compile): Same.
 
2005-01-20  Jim Blandy  
 
        * opcodes.scm (gen-switch): Use concat instead of string-map.
 
        * utils.scm (concat): New function.
        * insn.scm (-sub-insn-make!): Use concat instead of string-map.
        * rtl.scm (rtx-dump): Same.
        * semantics.scm (semantic-compile): Same.
 
2004-12-16  Jim Blandy  
 
        * utils-cgen.scm (parse-name): Don't assume that string-map can be
        applied to symbols.  Process everything as strings, and then
        convert to a symbol at the end.
 
        * read.scm (debug-repl): Temporarily redirect input and output to
        /dev/tty while we debug, so we don't interfere with whatever CGEN
        is reading or writing.
        * utils.scm (setter-getter-fluid-let, with-input-and-output-to):
        New functions.
 
2004-11-15  Michael K. Lechner 
 
        * cpu/iq2000.cpu: Added quotes around macro arguments so that they
        will work with newer versions of guile.
 
2004-10-27  Nick Clifton  
 
        * cpu/iq2000m.cpu: Import latest version from cpu/ directory.
        * cpu/iq2000.cpu: Likewise.
 
2004-07-21  DJ Delorie  
 
        * cpu/xstormy16.cpu (movhmemgr): Use hmem8, not lmem8.
 
2003-03-14  Frank Ch. Eigler  
 
        * cpu/iq2000.opc (parse_jtargq10): Add ATTRIBUTE_UNUSED on unused args.
        (parse_jtargq10, iq2000_cgen_isa_register, parse_mlo16): Declare.
 
2004-03-30  Kazuhiro Inaoka  
 
        * cpu/m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug.
 
2004-03-22  Dave Brolley  
 
        * utils.scm (copyright-fsf): Update copyright years.
        (copyright-red-hat): Ditto.
        * sid.scm (-op-gen-set-trace): Generate trace code before semantic
        code.
        (-op-gen-set-trace-parallel): Ditto.
 
2004-02-10  Kazuhiro Inaoka  
 
        * cpu/m32r.opc (my_print_insn): Fixed incorrect output when
        disassembling codes for 0x*2 addresses.
 
2004-01-29  Dave Brolley  
 
        * decode.scm (-opcode-slots): For short insns, generate 'opcode' with
        zeroes in the extra bit positions and generate 'opcode-mask' with ones
        in the extra bit positions.
 
2003-12-15  Kazuhiro Inaoka  
 
        * cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
 
2003-12-04  Alan Modra  
 
        * cpu/openrisc.opc (openrisc_sign_extend_16bit): Don't rely on
        "short" being 16 bit.
        (parse_hi16): Likewise.  Fix type-punned pointer warnings too, and
        internationalize error message.
        (parse_lo16): Likewise.  Remove useless code.
 
2003-12-03  Kazuhiro Inaoka  
 
        * cpu/m32r.cpu : Add new model m32r2.
        Add new instructions.
        Replace occurrances of 'Mitsubishi' with 'Renesas'.
        Changed PIPE attr of push from O to OS.
        Care for Little-endian of M32R.
        * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
        Care for Little-endian of M32R.
        (parse_slo16): signed extension for value.
 
2003-10-26  Dave Brolley  
 
        * sid-decode.scm (-gen-record-profile-args): Test trace_counter_p
        and final_insn_count_p. Don't test WITH_PROFILE_MODEL_P.
        (-gen-extract-fn): Call -gen-record-profile-args.
 
2003-10-21  Dave Brolley  
 
        * sid-model.scm (-gen-model-class-decls): Generate MAX_UNITS as
        a static const int.
        * decode.scm (-opcode-slots): Correct typo in logit call.
 
2003-10-09  Jim Blandy  
 
        * desc-cpu.scm (gen-hw-table-decls): Emit an 'extern' declaration
        for @arch@_cgen_hw_table.  GDB needs to be able to find this.
 
        * mach.scm (def-isa-attr!): hardware can have ISA attributes, too.
 
2003-10-06  Dave Brolley  
 
        * gen-all-doc: Add fr550.
 
2003-09-11  Doug Evans  
 
        * Makefile.am (ARCHFILE): New var.
        (desc): Pass $(ARCHFILE) for -a parm, not $(ARCH).
        (html,opcodes,sim-arch,sim-cpu,gas-test,sim-test): Ditto.
        * Makefile.in: Regenerate.
 
2003-09-08  Dave Brolley  
 
        On behalf of Doug Evans 
        Pass in paths to input files, instead of assuming they live in
        $srcdir/cpu.  Plus misc. option processing cleanup.
        * cgen-doc.scm (doc-arguments): Make options strings not symbols.
        Add pre-process pass to all options.
        * cgen-gas.scm (gas-arguments): Ditto.
        * cgen-sid.scm (sim-arguments): Ditto.
        * cgen-sim.scm (sim-arguments): Ditto.
        * cgen-stest.scm (stest-arguments): Ditto.
        * cgen-opc.scm (opc-arguments): Ditto.  New argument -OPC.
        (-opc-file-path): New global.
        (opc-file-path): New fn.
        * opcodes.scm (read-cpu.opc): Replace srcdir,cpu args with opc-file.
        All callers updated.
        (gen-extra-cpu.h,gen-extra-cpu.c,gen-extra-opc.h,gen-extra-opc.c,
        gen-extra-asm.c,gen-extra-dis.c,gen-extra-ibld.h,gen-extra-ibld.c):
        Replace srcdir arg with opc-file.  All callers updated.
        * read.scm (-opt-spec-update): Delete.
        (opt-get-first-pass,opt-get-second-pass): New fns.
        (-cgen): Process application-specific arguments in two passes.
 
2003-08-29  Dave Brolley  
 
        * cpu/frv.cpu: Removed.
        * cpu/frv.opc: Removed.
 
2003-08-21  Nick Clifton  
 
        * cpu/frv.cpu (mbtoh): Replace input parameter to
        u-media-dual-expand and u-media-dual-btoh with output parameter.
        (cmbtoh): Add profiling hack.
 
2003-08-19  Michael Snyder  
 
        * cpu/frv.cpu: Fix typo, Frintkeven -> FRintkeven
 
2003-08-07  Michael Meissner  
 
        * opc-opinst.scm (-gen-operand-instance-table): Initialize all of
        the elements for the END record of CGEN_OPINST, silencing warnings.
 
2003-07-15  Doug Evans  
 
        Add guile 1.6.4 support.
        - empty list must be quoted
        - string functions have stricter type checking
        - eval now takes a second argument
        - symbol-bound? is deprecated
        * attr.scm (-attr-parse): Use stringsym-append to build errtxt.
        (bitset-attr->list): Ensure arg to string-cut is a string.
        (attr-parse): Ensure args to string-ref and string-drop1 are strings.
        (,gen-value-for-defn): Fetch string name of self.
        * cos.scm (-class-list): Must quote empty list.
        (-class-parent-classes,-class-compute-class-desc): Ditto.
        (class-make,make,object-reset!): Ditto.
        (method-make-make!): Call eval1 instead of eval.
        (method-make-forward!,method-make-virtual-forward!): Ditto.
        * decode.scm (subdtable-add): Use stringsym-append instead of
        string-append.
        (-gen-exprtable-name): Fetch string name of exprtable-entry-insn.
        (-build-decode-table-entry): Fetch string name of insn.
        * desc-cpu.scm (-gen-isa-table-defns): Fetch string name of isa.
        (-gen-mach-table-defns): Ditto for mach.
        (gen-ifld-defns): Ditto for ifld.
        (gen-hw-table-defns): Ditto for hw.
        (gen-operand-table): Ditto for op.
        (gen-insn-table-entry): Ditto for insn.
        * desc.scm (gen-attr-table-defn): Ditto for attr.
        (,gen-defn): Don't pass symbols to string-append.
        * enum.scm (parse-enum-vals): Use symbolstr-append instead of
        symbol-append.
        (enum-vals-upcase): Use symbol-upcase to build result.
        (-enum-parse): Use stringsym-append to build errtxt.
        * fixup.scm (*guile-major-version*,*guile-minor-version*): New globals.
        (eval1): New function.
        (symbol-bound?): Provide own version if >= guile 1.6.
        * hardware.scm (define-keyword): Use string-append instead of
        symbol-append.
        * html.scm (gen-html-header,gen-table-of-contents,gen-arch-intro,
        cgen.html,cgen-insn.html): Convert current-arch-name to a string
        before using.
        (gen-list-entry): Handle either symbol or string `name' arg.
        (gen-obj-doc-header): Fetch string name of `o' arg.
        (define-cpu-intro): Ditto for cpu.
        (gen-mach-intro): Ditto for mach.
        (gen-model-intro): Ditto for model.
        (gen-isa-intro): Ditto for isa.
        (gen-machine-doc-1): Ditto for isa.
        (gen-reg-doc-1): Convert mach to string first.
        (gen-insn-doc-1): Ditto.  Convert model/unit names to strings first.
        (gen-insn-doc-list): Fetch string name of mach.  Convert insn name
        to string first.
        (gen-insn-categories): Fetch string name of mach.  Convert
        enum-val-name to string first.
        (gen-insn-docs): Fetch string name of mach.
        * ifield.scm (ifld-ilk): Result is a string.
        * iformat.scm (-ifmt-search-key): Convert attr value to string first.
        Fetch string name of ifld.
        (-sfmt-search-key): Similarily for ifld and op.
        * insn.scm (syntax-make): Fetch string name of syntax element.
        * mach.scm (-cpu-parse): Use stringsym-append to build errtxt.
        * minsn.scm (minsn-make-alias): Fetch string name of minsn.
        * mode.scm (mode:c-type): Result is a string.
        (mode:enum): Fetch string name of mode.
        (-mode-parse): Use stringsym-append to build errtxt.
        * model.scm (model:enum): Fetch string name of model.
        (-model-parse): Use stringsym-append to build errtxt.
        (parse-insn-timing): Must quote empty list.
        * opc-itab.scm (-gen-minsn-table-entry): Fetch string name of minsn.
        (-gen-minsn-opcode-entry): Ditto.
        * opcodes.scm (,gen-function-name): `what' arg is a symbol,
        convert to string.
        (read-cpu.opc): Convert current-arch-name to a string before using.
        * operand.scm (,gen-pretty-name): Ensure `name' is a string.
        (): Must quote empty list.
        (op-sort): Simplify, call alpha-sort-obj-list to do sort.
        * pgmr-tools.scm (pgmr-pretty-print-insn-value): Fetch string name
        of ifld.
        * pmacros.scm (-pmacro-build-lambda): Use eval1 instead of eval.
        (-pmacro-sym): Must convert symbols to strings before passing to
        string-append.
        (-pmacro-str): Ditto.
        (pmacros-init!): Use eval1 instead of eval.
        * read.scm (keep-mach-atlist?): Simplify, use bitset-attr->list.
        (keep-isa-atlist?): Ditto.
        (cmd-if): Use eval1 instead of eval.
        * rtl-c.scm (,get-name): Fetch string name of self.
        (-rtl-c-get): Fetch string name of src.
        (s-unop): Ditto for mode.
        (s-binop,s-binop-with-bit,s-shop,s-convop,s-cmpop): Ditto.
        (-gen-par-temp-defns,subword): Ditto.
        (join): Use stringsym-append instead of string-append.
        * rtl-traverse.scm (rtx-option?): Convert option to string first.
        (rtx-traverse-debug): Fetch string name of rtx-obj.
        * rtl.scm (def-rtx-node): Use eval1 instead of eval.
        (def-rtx-syntax-node,def-rtx-operand-node,def-rtx-macro-node): Ditto.
        (rtx-pretty-name): Result is a string.
        (-rtx-hw-name): Use symbolstr-append instead of symbol-append.
        * semantics.scm (semantic-compile): Simplify, use alpha-sort-obj-list.
        * sid-cpu.scm (cgen-write.cxx): Convert current-arch-name to a string
        before using.
        (-gen-sfrag-case): Fetch string name of user.
        * sid-model.scm (unit:enum): Fetch string name of unit.
        * sid.scm (,cxmake-get): Fetch string name of mode.
        (,gen-set-quiet): Ditto.
        (gen-mode-defs): Ditto.
        (sim-finish!): Convert current-arch-name to a string before using.
        * sim-cpu.scm (-gen-scache-semantic-fn): Fetch string name of insn.
        (-gen-no-scache-semantic-fn): Ditto.
        (cgen-defs.h): Fetch string name of isa.
        (cgen-read.c): Convert current-arch-name to a string before using.
        (cgen-write.c): Ditto.
        * sim-model.scm (unit:enum): Fetch string name of unit.
        (gen-model-fn-decls): Use stringsym-append instead of string-append.
        (-gen-model-timing-table): Fetch string name of model.
        (-gen-mach-model-table): Ditto.
        (-gen-mach-defns): Fetch string name of mach.
        * sim.scm (gen-reg-access-defn): Fetch string name of hw.
        (,cxmake-get): Fetch string name of mode.
        (,gen-set-quiet): Ditto.
        (gen-mode-defs): Ditto.
        (sim-finish!): Must quote empty list.
        * utils-cgen.scm (): Must quote empty list.
        (obj:str-name): New fn.
        (parse-comment): Result is a string.
        (parse-symbol): Result is a symbol.
        (parse-string): Result is a string.
        (keyword-list?): Convert arg to string before calling string-ref.
        (keyword-list->arg-list): Ditto.
        (gen-attr-name): Convert attr-name to string first.
        (alpha-sort-obj-list): Use symbol
        * utils-gen.scm (attr-gen-decl): Fetch string name of attr.
        (gen-define-ifmt-ifields): Ditto for fld.
        * utils.scm (gen-c-symbol): Ensure str is a string before calling
        map-over-string.
        (gen-file-name): Ditto.
        (symbol-downcase,symbol-upcase,symbol
        (stringsym-append,symbolstr-append,->string,->symbol): New fns.
        (reduce): Call eval1 instead of eval.
        * cpu/m32r.cpu (addi): Don't use `#.'.
 
        * gen-all-sim: Fix some typos.
 
2003-07-08  Doug Evans  
 
        * gen-all-doc: Ensure run from cgen src dir.
        * gen-all-opcodes: Build in ./tmp-opcodes.  Don't delete dir when done.
        * gen-all-sid: Similarily, in ./tmp-sid.
        * gen-all-sim: Similarily, in ./tmp-sim.
 
2003-06-20  Doug Evans  
 
        * gen-all-sim: Add fr30,sh64 support.  Only generate m32r by default.
 
2003-06-19  Doug Evans  
 
        * mach.scm (-ifld-already-defined?): New proc.
        (current-ifld-add!): Use it.
        (-op-already-defined?): New proc.
        (current-op-add!): Use it.
        (-insn-already-defined?): New proc.
        (current-insn-add!): Use it.
        (-minsn-already-defined?): New proc.
        (current-minsn-add!): Use it.
        (obj-isa-list): New proc.
        (isa-supports?): Use it.
 
2003-06-10  Doug Evans  
 
        * insn.scm (insn-builtin!): RELAX renamed to RELAXABLE.
        * cpu/m32r.cpu (all insns): Ditto.
 
        * mach.scm (current-*-add!): Disallow redefinition.  Make result
        "unspecified".
 
        * gen-all-doc: Split arm and frv docs up a bit.
 
        * cpu/arm.cpu: Add IDOC attribute.
        * cpu/frv.cpu: Ditto.
        * cpu/i960.cpu: Ditto.
        * cpu/openrisc.cpu: Ditto.
        * cpu/xstormy16.cpu: Ditto.
        * cpu/m32r.cpu: Ditto.
        (all insns): Explicitly specify IDOC attribute.
 
        * Makefile.am (MACH,ISAS,INSN_FILE_NAME): New vars.
        (desc,opcodes,sim-arch,sim-cpu,gas-test,sim-test): Use MACH,ISAS.
        (html): Use MACH,ISAS,INSN_FILE_NAME.  Generate insn.html separately.
        * Makefile.in: Regenerate.
        * attr.scm (:parse-value-def): Implement.
        (-attr-read): Defer computing default value until we know the type.
        (attr-has-attr?): Delete, move contents to :has-attr?.
        (:attr-present?): New method.
        (atlist-attr-present?,obj-attr-present?): New fns.
        (obj-has-attr-value?,obj-has-attr-value-no-default?): New fns.
        (attr-builtin!): New insn attr IDOC.
        * cgen-doc.scm (doc-arguments): New args -I,-N.
        * enum.scm (parse-enum-vals): New arg errtxt, all callers updated.
        Support comment as fourth element of enum value.
        (enum-val-name,enum-val-value,enum-val-attrs,enum-val-comment): New fns.
        * html.scm (gen-html-header): New arg kind, all callers updated.
        (gen-table-of-contents): New arg insn-file, all callers updated.
        (gen-list-entry,gen-doc-header): New fn.
        (get-operands): Delete.
        (gen-iformat-table): Rewrite.
        (gen-insn-doc-1): Print constant-folded and trimmed semantics.
        (gen-insn-doc-list): New args name, comment, insns.  All callers updated.
        (get-insn-properties,guess-insn-idoc-attr!): New fn.
        (insn-sets-pc?,insn-refs-mem?,insn-uses-fpu?): New fns.
        (get-insns-for-category,gen-categories-insn-lists): New fns.
        (gen-insn-docs): Simplify each insn's semantics first.
        Print insn tables sorted by IDOC categories.
        (*insn-html-file-name*): New global.
        (cgen-insn.html): New fn.
        (cgen-all): Update.
        * insn.scm (): Create a setter for the `tmp' member.
        * semantics.scm (insn-build-known-values): Renamed from
        -build-known-values.  All callers updated.
 
        * rtl.scm: Move traveral/evaluation support to ...
        * rtl-traverse.scm: New file.
        * read.scm: Maybe-load rtl-traverse.scm.
 
        * rtl.scm (-rtx-valid-types): Add SETRTX.
 
        * rtx-funcs.scm (nop,parallel): Fix mode.
 
        * utils.scm (eqv-lookup-index): New fn.
        (assq-lookup-index): Renamed from lookup-index.  All callers updated.
 
        * dev.scm (load-doc): Set APPLICATION.
 
2003-06-10  Dave Brolley  
 
        * sid-cpu.scm: Generate #include of config.h into @prefix@-sem.cxx.
        * sid-decode.scm: Generate #include of config.h into
        @prefix@-decode.cxx.
        * sid-model.scm: Generate #include of config.h into @prefix@-model.cxx.
 
2003-06-07  Doug Evans  
 
        * gen-all-sid: New file.
        * gen-all-opcodes: New file.
 
2003-06-05  Nick Clifton  
 
        * cpu/frv.cpu (FRintieven): New operand.  An even-numbered only
        version of the FRinti operand.
        (FRintjeven): Likewise for FRintj.
        (FRintkeven): Likewise for FRintk.
        (mdcutssi, media-dual-word-rotate-r-r, mqsaths,
        media-quad-arith-sat-semantics, media-quad-arith-sat,
        conditional-media-quad-arith-sat, mdunpackh,
        media-quad-multiply-semantics, media-quad-multiply,
        conditional-media-quad-multiply, media-quad-complex-i,
        media-quad-multiply-acc-semantics, media-quad-multiply-acc,
        conditional-media-quad-multiply-acc, munpackh,
        media-quad-multiply-cross-acc-semantics, mdpackh,
        media-quad-multiply-cross-acc, mbtoh-semantics,
        media-quad-cross-multiply-cross-acc-semantics,
        media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics,
        media-quad-cross-multiply-acc-semantics, cmbtoh,
        media-quad-cross-multiply-acc, media-quad-complex, mhtob,
        media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd,
        cmhtob): Use new operands.
        * cpu/frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define.
        (parse_even_register): New function.
 
2003-06-04  Doug Evans  
 
        Better handling of 64 bit and mixed 32/64 bit architectures.
        * hardware.scm (hw-update-word-modes!): New fn.
        * mach.scm (define-cpu)): Call mode-set-word-modes!,
        hw-update-word-modes!.
        (state-word-bitsize): Replace FIXME with requested check.
        (arch-analyze-insns!): Call mode-ensure-word-sizes-defined.
        * mode.scm (mode-find): Ignore INT,UINT.
        (-mode-word-sizes-kind): New global.
        (mode-set-word-modes!,mode-set-identical-word-bitsizes!,
        mode-set-biggest-word-bitsizes!,mode-ensure-word-sizes-defined): New fns.
        (mode-init!): Initialize -mode-word-sizes-kind.  Move initialization
        of mode-list to ...
        (mode-builtin!): ... here.  Initialize WI/UWI/AI/IAI to something
        unusable, correct values set later.
        (mode-finish!): Remove cruft.
        * html.scm (doc-init!): Call mode-set-biggest-word-bitsizes!.
        * opcodes.scm (opcodes-init!): Ditto.
        * rtx-funcs.scm (annul): Fix mode of pc.
        * cpu/ia64.cpu: Remove cruft that sets word modes.
        * cpu/xstormy16.cpu (define-cpu): Set word-bitsize.
 
2003-06-03  Nick Clifton  
 
        * cpu/frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit
        immediate value not unsigned.
 
2003-05-21  J"orn Rennecke 
 
        * cpu/sh.cpu: Amend comments to refer to SuperH.
        * cpu/sh64-compact.cpu: Change comment to refer to SuperH.
        * cpu/sh64-media.cpu: Likewise.
        (Saturation): Update manual reference.
 
2003-05-15  Doug Evans  
 
        * Makefile.am (srcroot): New var.
        (html): New rule.
        * Makefile.in: Regenerate.
        * cgen-doc.scm: New file.
        * html.scm: New file.
        * gen-all-doc: New file.
        * dev.scm (cload): Handle DOC application.
        (load-doc): New fn.
        * machs.scm (machs-for-cpu): New fn.
        * model.scm (models-for-cpu): New fn.
        * utils.scm (gen-c-copyright): Renamed from gen-copyright.
        All uses updated.
        (iota): Rewrite to be identical to pmacro version.  All uses updated.
        * utils-cgen.scm (alpha-sort-obj-list): New fn.
 
        * utils-sim.scm (-gen-decoder-switch): Back out patch of 2003-01-09.
        (-gen-decode-bits): Instead put in better fix here.
 
        * cpu/i960.cpu (index): Rename to indx.  All uses updated.
 
2003-05-01  DJ Delorie  
 
        * cpu/xstormy16.cpu (alignfix-mem): Correct logic for unaligned
        word accesses.
        (set-alignfix-mem): Likewise.
 
2003-04-16  Dave Brolley  
 
        * doc/rtl.texi (Iiming): Correct example to use 'model-name'.
        * utils.scm (copyright-fsf): Update generate copyright years.
        (copyright-cygnus): Ditto.
        * sid.scm (-op-gen-set-trace): Generate code to fill in bitmask of modified
        operands.
        (-gen-arch-model-decls): Don't generate unit enum declaration or MAX_UNITS
        here.
        ('gen-profile-code): New parameter 'when'.
        ('gen-profile-code): Ditto.
        ('gen-profile-code): Ditto.
        ('gen-profile-code): Ditto. Only generate 'referenced' and
        'insn_reference' for the 'after' function.
        * model.scm (unit:enum): Moved to sim-model.scm.
        * sim-model.scm (unit:enum): Moved from model.scm.
        * sid-decode.scm (-gen-scache-decls): Generate the 'written' field.
        * cgen-sid.scm (sim-arguments): Document the generation of model.h.
        * sid-model.scm (unit:enum): New version for sid.
        (gen-model-class-name): New function.
        (gen-model-unit-fn-decl): New function.
        (gen-model-fn-decls): Call gen-model-unit-fn-decl.
        (gen-model-unit-fn-name): New parameter 'when'.
        (-gen-model-insn-fn-name): Ditto.
        (-gen-model-insn-qualified-fn-name): New function.
        (-gen-model-insn-fn-decl): New function.
        (-gen-model-insn-fn-decls): New function.
        (-gen-model-insn-fn): New parameter 'when'. Call
        -gen-model-insn-qualified-fn-name.
        (-gen-model-insn-fns): Generate the constructor for the model. Generate
        functions for modelling insn before and after execution.
        (-gen-model-class-decls): New function.
        (" (gen-model-class-name model) "): New function.
        (gen-model-classes): New function.
        (-gen-insn-timing): Generate functions for modelling insn before and after
        execution.
        (-gen-insn-unit-timing): Generate class-qualified names.
        (-gen-model-timing-table): Ditto.
        (cgen-model.cxx): Generate #include for @cpu@.h. Omit generation of code
        not needed (yet) by sid.
        (cgen-model.h): New function.
 
2003-04-15  Rohit Kumar Srivastava 
 
        * cpu/sh.cpu: Replace occurrances of 'Hitachi' with 'Renesas'.
        * cpu/sh64-compact.cpu: Likewise.
        * cpu/sh64-media.cpu: Likewise.
 
2003-03-21  DJ Delorie  
 
        * cpu/xstormy16.cpu (basic-psw): New argument ws (wordsize),
        which indicates if the sign flag is set from bit 15 or 7.
        Adjust all callers.
        (set-psw): New argument ws, propogate it.
        (set-psw-nowrite): Likewise.
        (set-mem-psw): Likewise.
        (set-psw-carry): Likewise.  Use temporaries to prevent
        prematurely overwriting needed inputs.
        (set-psw-rrotate17): Fix logic.
        (shrgrgr): Preserve carry for zero-bit shifts.
        (shrgrimm): Likewise.
        (shlgrgr): Likewise.
        (shlgrimm): Likewise.
        (asrgrgr): Likewise.
        (asrgrimm): Likewise.
        (reset): New.
 
2003-03-12  Frank Ch. Eigler  
 
        * sid.scm: Set APPLICATION to SID-SIMULATOR.
 
2002-03-05  DJ Delorie  
 
        * cpu/xstormy16.cpu (set-psw-add): Use temporaries to prevent
        prematurely overwriting needed inputs.
        (set-psw-sub): Likewise.
 
Fri Feb 21 19:48:19 2003  J"orn Rennecke 
 
        * cpu/sh64-media.cpu (make-mextr): Fix setting of count.
 
2003-02-18  DJ Delorie  
 
        * xstormy16.cpu (set-mem-alignfix-psw): Remove.
        (movlmemimm): Just mask the address.
        (movhmemimm): Likewise.
        (movlmemgr): Likewise.
        (movhmemgr): Likewise.
        (set-psw): Always set the psw last.
        (set-psw-carry): Likewise.
        (set-psw-add): Likewise.
        (set-psw-sub): Likewise.
 
        * xstormy16.cpu (set-psw-rrotate17): New.  Choose the correct set
        of 16 patterns from the set-psw-rotate17 function.
        (movgrigr, movgripostincgr, movgripredecgr, movgriigr,
        movgriipostincgr, movgriipredecgr): Set psw correctly.
        (movfgrigr, movfgripostincgr, movfgripredecgr, movfgriigr,
        movfgriipostincgr, movfgriipredecgr): Fix semantics.
        (rrcgrgr, rrcgrimm4): Use new set-psw-rrotate17 function.
 
2003-02-11  Dave Brolley  
 
        * desc-cpu.scm (gen-ifld-defns): Add all ifields to the
        @arch@_cgen-ifld_table.
        (gen-maybe-multi-ifld): Use the ifield enumerators to index the
        @arch@_cgen-ifld_table.
 
2003-02-03  Frank Ch. Eigler  
 
        * sid-cpu.scm (-gen-sfrag-engine-fn): Generate more hygienic C++.
 
2003-01-09  Graydon Hoare  
 
        * utils-sim.scm (-gen-decoder-switch): Fix edge condition for
        empty ISAs.
 
2003-01-07  Graydon Hoare  
 
        * utils-gen.scm (attr-int-gen-defn): Define.
 
2002-12-21  Doug Evans  
 
        * ifield.scm (-ifield-parse): Rewrite  computation.
        (-get-ifld-word-offset,-get-ifld-word-length): New fns.
 
        * dev.scm (cload): Update location of .cpu files.
 
2002-12-19  Doug Evans  
 
        * utils-sim.scm (gen-profile-sym): New fn.
        (,sbuf-profile-sym): New method.
        (,sbuf-profile-elm): Use it.
        * sim.scm (,gen-record-profile): Use sbuf-profile-sym instead
        of hardcoding symbol name.
        (,gen-profile-code): Ditto.
        (,gen-profile-code): Use gen-profile-sym instead of hardcoding
        symbol name.
 
        * mode.scm (mode-sem-mode): New fn.
        * operand.scm (op:new-mode): Update. mode-name.
        (op-natural-mode?) New fn.
        * rtl.scm (hw): Set hw-name,mode-name.
 
        Back out sim*.scm changes of 2001-04-02  Ben Elliston  
        Instead do:
        * sim-decode.scm (-gen-decode-insn-globals): Use @PREFIX@_INSN__MAX
        as size of IDESC-TABLE-VAR.
        (@prefix@_init_idesc_table): Ditto.
        * sim-model.scm (-gen-mach-defns): Ditto.
        * sim.scm (gen-cpu-insn-enum-decl): Rename last elm from max to -max.
 
        * utils-sim.scm (-gen-decode-insn-entry): Fix some spacing in output.
 
        * insn.scm (-parse-insn-format-symbol): Improve error message.
        (-parse-insn-format): Ditto.
 
        * gen-all-sim: New script.
 
2002-12-16  DJ Delorie  
 
        * cpu/xstormy16.opc (parse_immediate16): Add prototype.
 
2002-12-16  Andrew MacLeod  
 
        * cpu/xstormy16.cpu (imm16): Call handler immediate16.
        * cpu/xstormy16.opc (parse_small_immediate): Return on '@'.
        (parse_immediate16): Handle immediate16 values, which now include
        @hi(label) and @lo(label)
 
2002-12-03  Alan Modra  
 
        * desc-cpu.scm (gen-maybe-multi-ifld): Remove superfluous parens.
        Add braces and cast for union field.
        (gen-multi-ifield-nodes): Add braces and cast for union field.
        (cgen_operand_table): Similarly fix sentinel.
        (cgen_cpu_close): Constify "insns".  Formatting.
        (cgen-desc.c): Include xregex.h.
        * cpu/ip2k.opc (ip2k_cgen_insn_supported): Move to opc.c section.
        Prototype.
        : Include safe-ctype.h.
        (ip2k_asm_hash): Use ISSPACE and TOLOWER.
        (PARSE_FUNC_DECL): Declare.  Use to prototype parse_fr, parse_addr16,
        parse_addr16_p, parse_addr16_cjp, parse_lit8 and parse_bit3.
        (parse_fr): Constify "old_strp".  Correct type of "tempvalue".
        Don't test it for >= 0.  Use ISSPACE rather than isspace.  Formatting.
        (parse_addr16): Correct type of "value".  Formatting.
        (parse_addr16_p): Likewise.
        (parse_addr16_cjp): Likewise.
        (parse_lit8): Likewise.
        (parse_bit3): Formatting.
        (PRINT_FUNC_DECL): Define.  Use to prototype print_fr, print_dollarhex,
        print_dollarhex8, print_dollarhex16, print_dollarhex_addr16h,
        print_dollarhex_addr16l, print_dollarhex_p, print_dollarhex_cj and
        print_decimal.
        (print_fr): Add ATTRIBUTE_UNUSED on unused args.  Formatting.
        (print_dollarhex): Add ATTRIBUTE_UNUSED on unused args.
        (print_dollarhex8): Likewise.
        (print_dollarhex16): Likewise.
        (print_dollarhex_addr16h): Likewise.
        (print_dollarhex_addr16l): Likewise.
        (print_dollarhex_p): Likewise.
        (print_dollarhex_cj): Likewise.
        (print_decimal): Likewise.
        * cpu/xstormy16.opc (parse_mem8): Use ISALNUM rather than isalnum.
 
2002-11-30  Hans-Peter Nilsson  
 
        * doc/rtl.texi (Model variants): Mention current limitations for
        unit inputs and outputs.
        (Hardware elements) : Be slightly more
        verbose.
        (Instructions) : input/output overrides have a direction
        operand.
 
2002-11-25  DJ Delorie  
 
        * xstormy16.cpu (sdiv, divlh, sdivlh): Fix sdivlh/divlh encodings.
 
2002-11-21  Jeff Johnston  
 
        * cpu/iq10.cpu: New file.
        * cpu/iq2000.cpu: Likewise.
        * cpu/iq2000.opc: Likewise.
        * cpu/iq2000m.cpu: Likewise.
 
2002-11-19  DJ Delorie  
 
        * cpu/xstormy16.cpu (sdiv, divlh, sdivlh): New.
 
2002-11-05  Frank Ch. Eigler  
 
        * dev.scm: Call getenv with a string, not a symbol.
 
2002-10-08  Doug Evans  
            Hans-Peter Nilsson  
 
        * types.scm (bitrange-overlap?): Handle lsb0?.
 
2002-09-07  Frank Ch. Eigler  
 
        From Robert Cragie :
        * cpu/arm7.cpu (ldm*-sw*, stm*-sw*): New instructions.
 
2002-07-17  Frank Ch. Eigler  
            Ben Elliston  
            John Healy  
            Jeff Johnston  
            Alan Lehotsky  
            Ubicom Inc. 
 
        * cpu/ip2k.cpu: New file.
        * cpu/ip2k.opc: Likewise.
 
2002-07-01  Hans-Peter Nilsson  
 
        * utils-gen.scm (-gen-extract-word): Handle lsb0?.
 
2002-06-25  J"orn Rennecke 
 
        * cpu/sh64-compact.cpu (movw5): Use Correct operand field for reg.
        * cpu/sh64-media.cpu (-ldhi-byte, -ldhi-word, -ldhi-long): New macros.
        (-ldlo-byte, -ldlo-word, -ldlo-long): Likewise.
        (-sthi-word, -sthi-long -stlo-byte, -stlo-word, -stlo-long): Likewise.
        (ldhil, ldhiq, ldlol, ldloq, stlol, stloq): Implement.
        (mshfhib, mshfhil, mshfhiw, mshflob, mshflol, mshflow): Fix indices.
        (-sthi-byte): If there is a single byte to store, store it at
        proper address.
        (sthil, sthiq): Fix big-endian behaviour.
        (mcnvslw, mcnvswb, mcnvswub, mmacfxwl, mmacnfx.wl): Fix indices.
        (mmulfxl, mmulfxw, mmulfxrpw, mmulhiwl, mmullowl): Likewise.
        (saturate): Use Dimode to check if saturation operation is required.
        (usaturate): Likewise.
        (mpermw): Fix mask.
        (-maddsl, -maddsub): Compute to-be-saturated value in wider mode.
        (-maddsw, mmacfxwl, mmacnfx.wl, -mshaldsl, -mshaldsw): Likewise.
        (-mshardl, -mshardw, -msubsl, -msubsub, -msubsw): Likewise.
        (msadubq): Fix subword index in second operand of first subtraction.
 
2002-06-20  Hans-Peter Nilsson  
 
        * sim-cpu.scm (gen-semantic-code): Prepend with setup-semantics
        code.
 
2002-06-18  Dave Brolley  
 
        * cpu/frv.cpu: New cpu description.
        * cpu/frv.opc: New cpu support code.
 
2002-05-21  Dave Brolley  
 
        * decode.scm (-opcode-slots): Don't consider bits beyond the
        length of the insn.
 
2002-05-17  Johan Rydberg  
 
        * cpu/powerpc.cpu: New file.
 
2002-05-01  Graydon Hoare  
 
        * desc-cpu.scm (@arch@_cgen_cpu_close): Fix memory leaks.
 
2002-03-20  Hans-Peter Nilsson  
 
        * doc/pmacros.texi (Symbol concatenation): Mention that .sym
        results are expanded recursively.
 
2002-03-19  Hans-Peter Nilsson  
 
        * pmacros.scm (-pmacro-expand,scan): If result is a symbol,
        call scan-symbol on it, to enable recursive macro-expansion.
 
2002-01-25  Frank Ch. Eigler  
 
        * sid-cpu.scm (-gen-hardware-types): Generate single hardware union
        for multiple-isa configurations.
        * sid-decode.scm (-gen-decode-fn): Tolerate empty insn list.
 
2002-02-04  Ben Elliston  
 
        * cpu/sh.cpu, cpu/sh.opc: New files.
        * cpu/sh64-comact.cpu, cpu/sh64-media.cpu: Likewise.
 
2002-01-29  Hans-Peter Nilsson  
 
        * doc/rtl.texi: Fix typo: define-attr, not define-attribute.
        (Enumerated constants): Mention that an ifield must not specify a
        multi-ifield.
        (Instruction operands): Ditto for index.
        (Expressions) : Remove misplaced mention of local
        variables.
        : Mention that mode must be specified and non-VOID when the
        result is used.
 
2002-01-28  Hans-Peter Nilsson  
 
        * doc/porting.texi: When referring to *.opc, mention they are in
        the cpu subdir.  Call top-level directory toplevel, not devo.
        Close string in define-normal-insn example.
 
        * doc/pmacros.texi: Fix .substr typo to .substring.
        Mention that .sym expansions are not further expanded.
 
2002-01-22  Graydon Hoare  
 
        * desc-cpu.scm (ifld-number-cache): Add.
        (ifld-number): Add.
        (gen-maybe-multi-ifld-of-op): Add.
        (gen-maybe-multi-ifld): Add.
        (gen-multi-ifield-nodes): Add.
        (cgen-desc.c): Add call to gen-multi-ifield-nodes.
 
2002-01-10  matthew green  
 
        * cpu/xstormy16.cpu (gr-Rbj-names): Rename this ...
        (gr-Rb-names): ... to this.
        (h-Rb): New hardware piece.
        (h-Rbj): Use gr-Rb-names.
        (Rb): Use h-Rb.
        (holdx): New instruction.
 
2002-01-07  Ben Elliston  
 
        * utils.scm (package-cygnus-simulators): Rename from this ..
        (package-red-hat-simulators): .. to this.
        * opcodes.scm (option-set!): Use package-red-hat-simulators.
        * sid-cpu.scm (cgen-desc.h): Likewise.
        (cgen-cpu.h): Likewise.
        (cgen-defs.h): Likewise.
        (cgen-write.cxx): Likewise.
        (cgen-semantics.cxx): Likewise.
        (cgen-sem-switch.cxx): Likewise.
        * sid-decode.scm (cgen-decode.h): Likewise.
        (cgen-decode.cxx): Likewise.
        * sid-model.scm (cgen-model.cxx): Likewise.
        * sid.scm (option-set!): Likewise.
        * sim.scm (option-set!): Likewise.
 
2002-01-07  Ben Elliston  
 
        * utils.scm (copyright-fsf): Add 2002.
        (copyright-cygnus): Rename to copyright-red-hat.
        (copyright-red-hat): Add 2002.
        (CURRENT-COPYRIGHT): Update comment.
        * opcodes.scm (option-set!): Update callers.
        * sid-model.scm (cgen-model.cxx): Likewise.
        * sid-cpu.scm: Likewise.
        * sid-decode.scm: Likewise.
        * sid.scm (option-set!): Handle "redhat" as an option for
        "copyright"; use copyright-red-hat.
        * sim.scm (option-set!): Likewise.
 
2002-01-03  Dave Brolley  
 
        * decode.scm (-distinguishing-bit-population): Compute num-insns, the
        number of insns in the list.  Update the population count function to
        identify and prioritize 3 catgories of useful bits.
        (-population-top-few): Don't consider bits with a population count of
        zero.
        (-build-decode-table-entry): Don't call
        filter-harmlessly-ambiguous-insns.  Filter out non-specialized and
        identical insns at the next tree level.
        * insn.scm (filter-harmlessly-ambiguous-insns): Note in a comment that
        this function is no longer used.
        (filter-non-specialized-ambiguous-insns): New function.
        (filter-identical-ambiguous-insns): New function.
        (find-identical-insn): New function.
        (filter-harmlessly-ambiguous-insns): Removed.
 
2001-11-26  Geoffrey Keating  
            matthew green  
            Frank Ch. Eigler  
            Nick Clifton  
 
        * cpu/xstormy16.cpu: New file.
        * cpu/xstormy16.opc: New file.
 
2001-11-26  Frank Ch. Eigler  
 
        * doc/sim.texi, rtl.texi, porting.texi: Correct texinfo markup typos.
 
2001-11-14  Dave Brolley  
 
        * utils-gen.scm (-gen-extract-word): Correct computation of the length
        of the field being extracted.
 
2001-10-29  Johan Rydberg  
 
        * doc/rtl.texi (Expressions): Document the (error ..), (sqrt ..),
        (cos ...) and (sin ..) rtx.
 
2001-10-13  Nick Clifton  
 
        * desc-cpu.scm: Do not include ctype.h in generated desc
        files.  They will inherit safe-ctype.h instead.
 
2001-10-08  Nick Clifton  
 
        * desc-cpu.scm: Add missing function prototypes (for generated
        C files).  Fix compile time warning messages about unused
        parameters (for generated C files).
        * opc-asmdis.scm: The same.
        * opc-ibld.c: The same.
        * opc-itab.scm: The same.
        * cpu/fr30.opc: The same.
        * cpu/m32r.opc: The same.
        * cpu/openrisc.opc: The same.
 
2001-09-17  graydon hoare  
 
        * insn.scm (syntax-break-out): Correct logic in handling escaped
        syntax characters.
 
2001-07-12  Jeff Johnston  
 
        * opc-itab.scm (@arch@_cgen_init_opcode_table): Unconditionally
        call @arch@_cgen_build_insn_regex now that regex support is in
        libiberty.
 
2001-07-12  Frank Ch. Eigler  
 
        * insn.scm (filter-harmlessly-ambiguous-insns): Fix msg typo.
        (mask-superset?): Look for strict supersets to allow rejection of
        duplicate insns.
 
2001-07-11  Frank Ch. Eigler  
 
        * sid-cpu.scm (-gen-mach-params): New proc to emit ...CHUNK_BITSIZE...
        (cgen-desc.h): Call it.
        * sid-decode.scm (-gen-decode-fn): Use base-insn-bitsize as
        decode-size.
        * utils-sim.scm (-gen-decode-insn-entry): For SID only, prepare
        entire_insn for extraction, if it's shorter than base-insn-bitsize.
 
2001-07-11  Frank Ch. Eigler  
 
        * desc-cpu.scm (-gen-mach-table-defns): Emit fourth field: the
        mach->cpu insn-chunk-bitsize.
        (-gen-cpu-open): In @arch@_cgen_rebuild_tables, process above new
        field toward CGEN_CPU_TABLE->insn_chunk_bitsize.
        * mach.scm (): New field insn-chunk-bitsize.
        (-cpu-parse, -cpu-read): Parse/initialize it.
        * doc/rtl.texi (define-cpu): Document it.
 
2001-07-09  Geoffrey Keating  
 
        * ifield.scm ( 'field-start): Don't look at word-len.
 
2001-07-06  Ben Elliston  
 
        * opcodes.scm (read-cpu.opc): Read .opc files from subdir/cpu.
 
2001-07-05  Ben Elliston  
 
        * README: Update.
 
        * read.scm (include): Include files from srcdir/cpu.
        (-cgen): Likewise for loading .cpu files.
        * sid.scm (sim-finish!): Read .sim files from srcdir/cpu.
        * *.cpu: Move all cpu descriptions into cpu subdirectory.
        * *.opc: Likewise.
        * simplify.inc: Likewise.
 
2001-07-04  Ben Elliston  
 
        * read.scm (include): Log "Including file" message at level 1,
        rather than outputting it with (display).
        (cpu-load): Log "Loading cpu description" and "Processing cpu
        description" messages at levels 1 and 2, respectively, rather than
        using (display).
 
2001-06-14  Geoffrey Keating  
 
        * desc.scm ( 'gen-defn): Add extra zero into
        CGEN_KEYWORD_ENTRY initializers.
 
        * gas-test.scm (gen-gas-test): Create 8 testcases, not just 5.
        ( 'test-data): Involve both the index and the hardware
        in testcase generation.
        ( 'test-data): Generate test data from the underlying
        object.
        ( 'test-data): Generate test data by computing bit
        patterns for the field, then decoding them.
        ( 'test-data): Allow for new calling convention.
        ( 'test-data): Likewise.
        ( 'test-data): Convert index values into keywords.
        ( 'test-data): Convert index values into integer strings.
 
        * gas-test.scm (cgen-build.sh): Escape '.' as well.
 
2001-06-01  Frank Ch. Eigler  
 
        * rtl.scm (hw): Encode hw access mode into  name, since this
        is required for multi-mode hw types (memory).
 
2001-05-11  Ben Elliston  
 
        * gas-test.scm (cgen-build.sh, gentest): Escape $ with a backslash
        when generating allinsn.d from objdump output. Without it, the
        testsuite will treat $ as the regular expression for end of line.
 
2001-05-09  Ben Elliston  
 
        * doc/porting.texi (Doing a GAS port): Replace `cgen_opcode_open'
        with `cgen_cpu_open'; documentation had become out of date.
        * doc/rtl.texi (Instruction operands): Likewise.
 
2001-05-07  Frank Ch. Eigler  
 
        * iformat.scm (compute-insn-base-mask-length): Rewrite to tolerate
        various-base-length instruction sets.
 
2001-04-02  Ben Elliston  
 
        * sid-cpu.scm (-last-insn): New function.
        (-gen-sem-switch-engine): Loop through idesc while less than or
        equal to the last instruction enum, not less than the MAX enum.
        (-gen-sfrag-engine-fn): Clean up frag_label_table initialisation.
        * sid-decode.scm (-gen-decode-insn-globals): Define the idesc
        table's size to be the last instruction enum plus one, not
        @PREFIX@_INSN_MAX.
        * sid.scm (gen-cpu-insn-enum-decl): Do not append a dummy `max'
        instruction onto the instruction list.
 
        * sim-decode.scm (@prefix@_init_idesc_table): Compute tabsize
        using the size of the table and its elements.
        (-gen-decode-insn-globals): Define the idesc table's size to be
        the last instruction enum plus one, not @PREFIX@_INSN_MAX.
        * sim-model.scm (-gen-mach-defns): Define CPU_MAX_INSNS as the
        last instruction enum plus one, not @CPU@_INSN_MAX.
 
2001-03-28  Ben Elliston  
 
        * doc/version.texi (UPDATED, EDITION): Update.
        * doc/stamp-vti: Likewise.
 
2001-03-26  Ben Elliston  
 
        * doc/credits.texi (Credits): Update.
 
        * gas-test.scm (,test-data): Prefix keywords by their
        specified prefix and, if necessary, escape `$' in gas-build.sh to
        prevent unwanted shell variable expansion.
 
2001-03-24  Ben Elliston  
 
        * gas-test.scm (,test-data): Choose pseudo-random data.
        (,test-data): Likewise.
        (,test-data): Likewise.
        (,test-data): Likewise.
        (-collate-test-set): New function.
        (build-test-set): Use it.
        (gen-gas-test): Generate five test cases per instruction.
        (cgen-allinsn.exp): Include "-*- Tcl -*-" in DejaGNU test file.
 
        * read.scm: Load "slib/random" if random is not defined.
        * slib/random.scm: New file.
 
        * utils.scm: Remove comments about the Hobbit compiler.
        (copyright-cygnus): Add 2001.
        (package-cygnus-simulators): Replace "Cygnus" with "Red Hat".
        (package-gnu-simulators): Tidy.
 
2001-03-23  Ben Elliston  
 
        * cgen-gas.scm: Inline documentation improvements.
 
2001-03-21  Ben Elliston  
 
        * opc-itab.scm (compute-syntax): Emit a parse error if an operand
        given in a syntax string is undefined.
 
        * opc-itab.scm (compute-syntax): Emit a parse error if an operand
        name is empty or invalid -- eg. "$(rs)" instead of "($rs)".
 
2001-03-20  Patrick Macdonald  
 
        * desc-cpu.scm (@arch@_cgen_cpu_open): Correct machine calculation
        for arg_type CGEN_CPU_OPEN_BFDMACH.
 
2001-03-20  Ben Elliston  
 
        * opc-itab.scm (-gen-insn-enum): Do not append a dummy `max'
        instruction onto the instruction list. Define MAX_INSNS to be the
        value of the last instruction enum plus one.
 
2001-03-14  Nick Clifton  
 
        * utils.scm (copyright-fsf): Add 2001.  Remove (C).
 
2001-03-05  Dave Brolley  
 
        * sim-decode.scm (-gen-extract-case): Generate declaration of "insn"
        if the number of ifields is greater than zero.
 
2001-03-01  Frank Ch. Eigler  
 
        * sid.cpu (-op-gen-set-trace[-parallel], -create-virtual-insns!):
        Emit LIKELY/UNLIKELY branch probability hints.
        * sid-decode.cpu (-gen-record-args): Ditto.
 
2001-02-02  Patrick Macdonald  
 
        * desc-cpu.scm (-gen-hash-defines): Rename
        CGEN_ACTUAL_MAX_SYNTAX_BYTES to CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS.
 
2001-01-26  Frank Ch. Eigler  
 
        * sid-cpu.scm (gen-parallel-exec-type): Use unsigned long long for
        writeback tracking.
        (-gen-write-fn, -gen-sem-case, -gen-sfrag-case): Ditto.
        * sid-decode.scm (-gen-scache-decls): Exclude writeback tracking field
        if unnecessary.
        * sid.scm ( gen-write): Use unsigned long long expression
        for writeback.
        (-op-gen-set-trace, -op-gen-set-trace-parallel): Ditto.
        ( gen-profile-code): Ditto.
 
2001-01-23  Johan Rydberg  
 
        * doc/rtl.texi (Expressions): Document the (index-of ...) and
        (regno ...) rtx.
 
2001-01-08  Frank Ch. Eigler  
 
        * operand.scm ( pretty-sem-name): New field.
        ( make): Initialize it from hw-name.
        (op:set-pretty-sem-name!): New function.
        ( gen-pretty-name): Default to fetching new field.
        * rtl.scm (hw): Copy hw-name to pretty-sem-name instead.  Restore
        sem-name setting from -rtx-hw-name.
 
2001-01-08  Frank Ch. Eigler  
 
        * rtl.scm (hw): Copy hw-name to new operand's sem-name, to simplify
        its subsequent gen-pretty-name.
 
        * read.scm: Increase thread working stack limit and backtrace
        depth limits.
 
2001-01-08  Frank Ch. Eigler  
 
        * doc/rtl.texi: Deprecate and depreciate the decode-assist construct.
 
2001-01-06  Johan Rydberg  
 
        * openrisc.cpu (or32): Setup semantics for h-delay-insn to
        current insn plus 4.
        (h-delay-insn): New hardware register.
        (l-jal): Uses h-delay-insn instead of pc when setting link register.
        (l-jalr): Likewise.
        (l-bal): Likewise.
 
        * openrisc.opc (parse_hi16): Sign extend value.
        (parse_lo16): Likewise.
 
2001-01-06  Ben Elliston  
 
        * utils-gen.scm (gen-sfmt-enum-decl): Use @prefix@ and @PREFIX@
        instead of @cpu@ and @CPU@ to generically prefix symbol names.
        * sim-cpu.scm (-gen-sem-fn-table-entry): Likewise.
        (-gen-semantic-fn-table): Likewise.
        (-gen-scache-semantic-fn): Likewise.
        (-gen-no-scache-semantic-fn): Likewise.
        (cgen-read.c): Likewise.
        (cgen-sem-switch.c): Likewise.
        * desc-cpu.scm (cgen-desc.c): Use @arch@, not @prefix@, since this
        is a filename prefix.
        * sim-decode.scm (IDESC-TABLE-VAR): Use @prefix@, et al.
        (-gen-decode-insn-globals): Likewise.
        (-gen-idesc-decls): Likewise.
        (cgen-decode.h): Likewise.
        (cgen-decode.c): Likewise.
        * sim.scm (gen-cpu-insn-enum-decl): Likewise.
        (gen-cpu-insn-enum): Likewise.
        (sim-finish!): Likewise.
 
2001-01-05  Johan Rydberg  
 
        * openrisc.cpu: New file.
        * openrisc.opc: Likewise.
 
2000-12-12  Ben Elliston  
 
        * doc/rtl.texi (Expressions): Document the (delay ..) rtx.
 
2000-12-07  Ben Elliston  
 
        * sim-decode.scm (-gen-extract-case): Do not emit a definition for
        "insn" when there are zero ifields to extract.
 
2000-12-04  Frank Ch. Eigler  
 
        * utils-sim.scm (gen-define-argbuf-macro): Handle sfmt=#f case, to be
        used by simple/non-scache simulators.
        * sim-cpu.scm (-gen-read-case): Call gen-define/undef-field-macro
        regardless of with-scache?.
        (-gen-write-case, -gen-no-scache-semantic-fn, -gen-sem-case): Ditto.
 
2000-12-03  Ben Elliston  
 
        * desc-cpu.scm (cgen-desc.h): Clarify generated filenames.
        (cgen-desc.c): Likewise.
 
2000-12-01  Greg McGary  
 
        * desc.scm (,gen-defn): Prepend prefix to keyword names.
 
2000-12-01  Ben Elliston  
 
        * sim-cpu.scm (cgen-cpu.h): Only emit argbuf, scache and extract
        definitions if run without with-multipla-isa?.
        (cgen-defs.h): New function. Emit an ISA-specific defs file.
        * cgen-sim.scm (sim-arguments): Accept -G option to generate defs.
 
2000-11-24  Ben Elliston  
 
        * sim-cpu.scm (-gen-hardware-struct): New function.
        (-gen-hardware-types): If with-multiple-isa is specified, emit all
        hardware elements wich have share one or more ISAs with the ISAs
        being kept.
 
        * sim.scm (-with-multiple-isa?): New symbol.
        (with-multiple-isa?): New function.
        (option-init!): Initialise -with-multiple-isa?.
        (option-set!): Handle with-multiple-isa option.
 
2000-11-21  Ben Elliston  
 
        * utils.scm (copyright-fsf): Add the year 2000.
 
2000-11-20  Frank Ch. Eigler  
 
        * opc-itab.scm (-gen-ifmt-table, -gen-macro-insn-table: Remove
        unneeded "\n\n" from F() macro definition.
 
2000-11-15  Greg McGary  
 
        * utils-cgen.scm (gen-define-with-symcat): New function.
        * desc-cpu.scm (gen-ifld-defns): Use it.
        (gen-hw-table-defns): Use it.
        (-gen-hash-defines): Use it.
        (gen-operand-table): Use it.
        (gen-insn-table): Use it.  Remove spurious `#undef MNEM'.
        * opc-itab.scm (-gen-ifmt-table): Use it.
        (-gen-insn-opcode-table): Use it.
        (-gen-macro-insn-table): Use it.
        * opc-opinst.scm (-gen-operand-instance-tables): Use it.
        * sim-cpu.scm (cgen-semantics.c): Use it.
        (cgen-sem-switch.c): Use it.
 
2000-11-10  Frank Ch. Eigler  
 
        * utils-sim.scm (-gen-decode-insn-entry): Add fn? parameter to signal
        request to emit calls to insn extractors as functions rather than
        branches to inline blocks.
        (-gen-decode-expr-set-itype, -gen-decode-expr-entry): Ditto.
        (-gen-decode-table-entry, -gen-decoder-switch, gen-decoder): Ditto.
 
        * sim-decode.c (-gen-decode-fn): Tell (gen-decode) to emit branches
        to extractor clauses.
 
2000-11-10  Frank Ch. Eigler  
 
        * decode.scm (-distinguishing-bit-population): Significantly
        improve popularity heuristic.  Renamed from
        (-mask-bit-population): Gone.
        (-population-above-threshold): Sort new bit numbers in order of
        popularity.
        (-population-top-few): Allow up to three more bits to be selected
        than requested.  Correct selection order to prefer better bits.
        Correct bug in fewer-than-requested case.  Keep threshold as
        floating-point.
        (decode-best-get-bits): Pass also the insn-values.
 
        * utils-sim.scm (-gen-decoder-switch): Add comment suggesting a
        future optimization.
 
        * utils.scm (message): Format nested lists better.
 
2000-11-09  Doug Evans  
 
        * dev.scm: Add srcdir to %load-path.
 
        * rtx-funcs.scm (subword): Mode of argument can be different
        than mode of result, so don't use OP0 to specify argument's mode.
 
2000-11-02  Ben Elliston  
 
        * doc/porting.texi (Building a GAS test suite): Document my change
        to gas-build.sh.
 
2000-11-01  Ben Elliston  
 
        * sim-test.scm (cgen-build.sh): Include "-*- Asm -*-" in test cases.
 
2000-10-31  Ben Elliston  
 
        * gas-test.scm (cgen-build.sh): Allow the generated script to run
        with no command line arguments if the gas build directory can be
        determined.
 
2000-10-26  Doug Evans  
 
        * insn.scm (-parse-insn-format-symbol): Fix spelling error,
        op-ifld -> op-ifield.
 
2000-10-23  Frank Ch. Eigler  
 
        * thumb.scm (cc-tests): Add (ISA thumb) attribute.
 
2000-10-13  matthew green  
 
        * utils-cgen.scm (get-ifetch): Move from here ...
        * sim.scm (get-ifetch): ... to here.
        * sid.scm (get-ifetch): Copy and port to c++.
 
2000-10-06  Dave Brolley  
 
        * utils-gen.scm (-gen-ifld-extract-base): Compute start position as
        ifld-start + ifld-word-offset.
        (gen-ifld-extract): Check adata-integral-insn? before checking whether
        the field is beyond the base number of bits.
        (gen-define-ifields): Use a base-length of 32 if adata-integral-insn?.
        (gen-extract-ifields): Ditto.
        * gas-test.scm (gentest): Generate backslashes before '[' and ']'
        characters in the regular expression.
 
2000-10-02  Frank Ch. Eigler  
 
        * desc-cpu.scm: (gen-operand-decls): Emit MAX_OPERANDS as a
        preprocessor constant.
 
2000-09-21  Frank Ch. Eigler  
 
        * slib/logical.scm: New file from slib.  Provides robust bitwise
        logical operations for large integers.
        * read.scm: maybe-load it.
 
2000-09-15  Frank Ch. Eigler  
 
        * enum.scm (define-full-insn-enum): Filter with keep-isa predicate.
        * ifield.scm (-ifield-parse, -multi-ifield-parse): No longer assert
        single-isa predicate, but support keep-isa filtering.
 
2000-09-08  Frank Ch. Eigler  
 
        * rtl-c.scm (s-sequence): Handle nested c-calls in both
        statement-expression and comma-expression contexts.
        (s-c-call, s-c-raw-call): Add warning comment about bad assumption.
 
2000-09-08  Frank Ch. Eigler  
 
        * decode.scm (-population-top-few): Signal error gracefully if
        decoding is about to become ambiguous.
 
2000-09-06  Frank Ch. Eigler  
 
        * doc/rtl.texi (decode-assist): Describe this field as optional.
 
2000-09-06  Frank Ch. Eigler  
 
        * utils-gen.scm (gen-multi-ifld-extract): Handle case of multi-ifield
        with decode proc.
 
2000-09-05  Dave Brolley  
 
        * sim.scm (sim-finish!): Honour the definition of FAST_P when calling
        @cpu@_pbb_begin. Use 0 if FAST_P is not defined.
 
2000-08-29  Dave Brolley  
 
        * utils-gen.scm (gen-ifld-extract): Pass total-len if
        adata-integral-insn is true for this architecture.
 
2000-08-24  Frank Ch. Eigler  
 
        * hardware.scm ( get-index-mode): Define method.
        * operand.scm ( gen-pretty-name): Tolerate no op:sem-name.
        * rtl-c.scm (-c-rtl-get): Improve an error message.
        * sim.scm (-op-gen-set-trace): Support  lvalues.
 
2000-08-22  Frank Ch. Eigler  
 
        * Makefile.in (DIST_COMMON): Regenerated.
        * ifield.scm ( needed-iflds): New method.
        * iformat.scm (-ifmt-lookup-sfmt!): Use base ifields for
        sfmts built from s.
        * operand.scm (-derived-parse-encoding): Give  a fixed
        type symbol 'derived-ifield, not an unparseable string.
        * utils-sim.scm (op-needed-iflds) Handler 'derived-ifield case.
        (-sfmt-contents): Add tracing.
 
        From Doug Evans :
        * sim.scm ( cxmake-get): Result is a , not a string of
        C code.
 
2000-08-20  Doug Evans  
 
        * rtl-c.scm (rtl-c-expr-with-estate): New fn.
        (rtl-c-expr-parsed,rtl-c-expr): New fns.
        (-rtl-c-get): Rename from rtl-c-get.
        (rtl-c-get): New fn for getter logging.
 
2000-07-28  Ben Elliston  
 
        * NEWS: Update.
 
2000-07-25  Ben Elliston  
 
        * doc/credits.texi (Credits): Add Frank Eigler.
 
2000-07-24  Dave Brolley  
 
        * opc-itab.scm (gen-insn-opcode-table): Initialize the first element
        fully.
        * desc.scm (gen-attr-table-defn): Initialize all elements fully.
        (): Initialize all elements fully.
        * desc-cpu.scm (-gen-isa-table-defns): Initialize the last element
        fully.
        (-gen-mach-table-defns): Ditto.
        (-gen-ifld-defns): Ditto.
        (-gen-operand-table): Ditto.
        (-gen-insn-table): Ditto.
        (-gen-cpu-open): Nothing to do for the mach table.
 
2000-07-13  Ben Elliston  
 
        * doc/version.texi (UPDATED): Update.
 
2000-07-05  Ben Elliston  
 
        * configure.in (AC_PATH_PROG): Remove.
        * configure: Regenerate.
        * Makefile.am (GUILE): Locate guile dynamically.
        * Makefile.in: Regenerate.
        * doc/Makefile.in: Likewise.
 
2000-07-03  Ben Elliston  
 
        * desc-cpu.scm (cgen-desc.c): Include "libiberty.h".
        * opc-itab.scm (cgen-opc.c): Likewise.
 
2000-06-28  Frank Ch. Eigler  
 
        * rtl.scm (-rtx-traverse-locals): Correct call to `symbol?' for
        guile 1.4 compatibility.
        (rtx-env-dump): Comment out buggy display calls.
 
2000-06-15  matthew green  
 
        * opc-itab.scm (-gen-ifmt-table-1): Add extra braces to pacify GCC.
 
2000-06-14  Frank Ch. Eigler  
 
        * Makefile.in: Regenerated.
 
        * desc-cpu.scm (gen-ifld-decls): Exclude derived ifields.
        (gen-ifld-defns): Ditto.
        * pgmr-tools.scm (pgmr-pretty-print-insn-format): Ditto.
        * rtl.c (rtl-finish!): Ditto.
        * opc-itab.scm (-gen-ifield-decls): Ditto.
        * opcodes.scm (gen-switch): Exclude derived operands.
        * operand.scm (op-iflds-used): Expand derived operands.
        (hw-index-derived): New dummy function to create dummy object.
        (-derived-operand-parse): Fix mode arg passed to 
        constructor.  Set object's hw-name and index fields.
        (-anyof-merge-subchoices): Set instance object's index also.
        (-anyof-name): New helper function.
        (anyof-merge-semantics): Correct replacement of operand names in
        anyof instance.
        (op-ifield): Tolerate derived-operands and their funny indices better.
        * ifield.scm (ifld-known-values): Expand derived ifields.
        (non-multi-ifields, non-derived-ifields): New utility functions.
        (ifld-decode-mode): Tolerate objects with unbound decode field.
        * iformat.scm (compute-insn-length): Expand derived ifields.
        (compute-insn-base-mask): Ditto.
        * insn.scm (insn-base-ifields): Remove.
        (): Add iflds-values entry to cache ifld-base-ifields values.
        (insn-value): Call ifld-base-ifields and ifld-constant? instead.
        * mach.scm (arch-analyze-insns!): Exclude multi-insns.
        * sem-frags.scm (sim-sfrag-analyze-insns!): Ditto.
        (-frag-test-data): Ditto.
        * sid-cpu.scm (cgen-write.cxx,-gen-sem-switch): Ditto.
        (-gen-sem-switch-engine); Ditto.
        * sid-model.scm (-gen-model-insn-fns, -gen-model-timing-table): Ditto.
        * sid-decode.scm (cgen-decode.h, cgen-decode.cxx): Ditto.
        (-gen-record-args): Tolerate unbound op-ifield.
        * sid.scm ( cxmake-get): New sketch implementation.
        (-gen-arch-model-decls, scache-engine-insns, pbb-engine-insns):
        Exclude multi-insns.
        * sim-decode.scm (cgen-decode.h, cgen-decode.cxx): Ditto.
        * utils-sim.scm (op-extract?): Handle derived operands.
 
        * gas-test.scm (cgen-build.sh): Quote '*' chars printed by objdump.
        * semantics.scm (-build-operand!): Handle 'DFLT case during parsing.
        * hardware.scm (hardware-for-mode): New function.
 
        * insn.scm (filter-harmlessly-ambiguous-insns): New function for
        cleaning up decode tables.
        (mask-superset?): Little helper function for above.
        * decode.scm (-build-decode-table-entry): Call it.
        (-opcode-slots): Add some more tracing.
        * arm.cpu: Disable decode-splits construct due to implementation
        conflict with `filter-harmlessly-ambiguous-insns'
 
        * decode.scm (-population-top-few): New function for better decode
        bit generation.  Includes minor helper functions.
        (decode-get-best-bits): Call it instead.
        (OLDdecode-get-best-bits): Renamed previous version of above.
 
 
2000-06-13  Ben Elliston  
 
        * configure.in: Use AC_EXEEXT with Cygnus mode. Remove AC_ARG_WITH
        for the Guile library directory.
        * configure: Regenerate.
        * Makefile.in, doc/Makefile.in: Regenerate.
 
        * Makefile.in, doc/Makefile.in: Regenerate.
        * configure.in: Remove unnecessary tests. Move to version 1.0.
        * acconfig.h, config.in: Remove.
        * configure, aclocal.m4: Regenerate.
        * doc/stamp-vti, doc/version.texi: Likewise.
        * AUTHORS: New file.
 
2000-06-07 Ben Elliston  
 
        * fixup.scm (symbol-bound?): Reduce debugging output.
 
2000-06-02  matthew green  
 
        * insn.scm (insn-base-ifields): Returns all the instruction fields for
        a given instruction, replacing derived fields with their subfields.
        (insn-value): Use `insn-base-ifields' to find all constant values.
        (multi-insn-instantiate!): Comment some debug messages.
 
2000-06-01  Ben Elliston  
 
        * doc/rtl.texi (Expressions): Document a hazard with the choice of
        symbol names used in a (c-call ..) rtx.
 
        * sim-test.scm (build-test-set): Return (()) for an instruction
        with no operands, so it too is included in the generated test set.
 
2000-05-31  Ben Elliston  
 
        * Makefile.am (gas-test): Ensure $(ISA) is not empty.
        (sim-test): Likewise.
        * Makefile.in: Regenerate.
 
2000-05-30  Frank Ch. Eigler  
 
        * read.scm (-cgen): In debugging mode (-b), ask guile for untruncated
        stack traceback, in an order that resembles gdb's `bt'.
 
2000-05-24  Frank Ch. Eigler  
 
        * desc-cpu.scm (-gen-hash-defines): Use ifmt-ifields again.
        * opc-itab.scm (-gen-ifmt-table-1): Ditto.
        * gas-test.scm (gas-test-analyze!, cgen-build.sh): Filter out
        multi insns.
        * ifield.scm (multi-ifield): Define workable field-mask and field-value
        virtual functions.
        (ifld-base-ifields): New routine to replace ifmt-expanded-ifields.
        * iformat.scm (ifmt-expanded-ifields): Gone.
        (ifields-base-ifields): New function.  Call ifld-base-ifields for real
        work.
        (-ifmt-lookup-ifmt!): Use it to expand derived/multi combos in new
        ifmt entries.
 
        * opcodes.scm (multi-ifield gen-extract): Correct spacing in generated
        code.
 
2000-05-23  Frank Ch. Eigler  
 
        * sid.scm (with-any-profile?): New function clone.
 
2000-05-19  Frank Ch. Eigler  
 
        * utils-gen.scm (gen-multi-ifld-extract): Fix decode hook for sim.
 
2000-05-18  Frank Ch. Eigler  
 
        * ifield.scm (-multi-ifield-parse): Add encode/decode args.
        (-multi-ifield-read): Parse them.
        (define-full-multi-ifield): Pass #f/#f as defaults for them.
        * opcodes.scm (multi-ifield gen-insert): Add encode hook.
        (multi-ifield gen-extract): Add decode hook.
        * utils-gen.scm (gen-multi-ifld-extract): Add decode hook for sim.
 
        * insn.scm (syntax-break-out): More correctly handle \-escaped
        syntax characters.
        (syntax-make-elements): Ditto.
        * opc-itab.scm (compute-syntax): Ditto.
 
2000-05-17  Ben Elliston  
 
        * gas-test.scm (cgen-build.sh): Log the correct script filename.
 
2000-05-15  Frank Ch. Eigler  
 
        * gas-test.scm (build-test-set): Return (()) for an instruction
        with no operands, so it too is included in the generated test set.
 
2000-05-15  Frank Ch. Eigler  
 
        * desc-cpu.scm (-gen-hash-defines): Define CGEN_ACTUAL_MAX values for
        IFMT_OPERANDS and SYNTAX_BYTES.
 
2000-05-15  Frank Ch. Eigler  
 
        * sim.scm (with-any-profile?): New function.
        * utils-sim.scm (-sfmt-contents): Use above instead of `with-profile?'
        to decide whether or not to include profiling counters.
 
2000-05-10  Frank Ch. Eigler  
 
        Fuller derived-operand support for opcodes.
        * insn.scm (non-multi-insns): New filter to oppose `multi-insns'.
        * desc-cpu.scm (-define-hash-defines): Compute CGEN_MAX_SYNTAX_BYTES.
        Correctly compute ..._IFMT_OPERANDS.  Omit useless ..._INSN_OPERANDS.
        (gen-operand-table): Omit derived- and anyof- operands from table.
        (gen-insn-table): Omit multi-insns from table.
        * iformat.scm (ifmt-expanded-fields): New function to expand
        subfields of derived-ifields.
        (ifmt-compute!): Ignore remaining multi-insns.
        * mach.scm (isa-min-insn-bitsize, isa-max-insn-bitsize): Ignore
        multi-insns.
        * opc-itab.scm (-gen-ifmt-table-1): Use ifmt-expanded-ifields.
        (-gen-insn-enum, -gen-insn-opcode-table): Ignore multi-insns.
        * opcodes.scm (derived-operand): Define abort()ing gen-insert,
        gen-extract, gen-fget, gen-fset, gen-parse, gen-print functions.
        (gen-switch): Omit anyof-operands.
        * operand.scm (-anyof-syntax): New function.
        (-anyof-merge-syntax): Call it.
        * utils.scm (collect): New idiomatic function.
 
2000-05-10  Ben Elliston  
 
        * m68k.cpu: New file (work in progress).
 
2000-05-05  Frank Ch. Eigler  
 
        * Makefile.am (all-local): New target.  Create stamp-cgen.
        * Makefile.in: Regenerated.
        * doc/Makefile.in: Regenerated.
 
2000-04-26  Frank Ch. Eigler  
 
        * operand.scm (-operand-g/setter-syntax): Correct off-by-one error.
        (-operand-parse-setter): Ditto.
        * utils-sim.scm (needed-iflds): Store ifield (index) in argbuf, even
        for CACHE-ADDR operands.
        * sid-decode.scm (-gen-record-args): Remove newly duplicated extract
        trace entries.  Widen byte-wide values for printing.
        * sid.scm (-op-gen-set-trace): Enhance result trace with op indices.
        Widen byte-wide values for printing.  Hexify memory addresses.
 
2000-04-23  matthew green  
 
        * m32r.cpu: Fix a typo.
 
Fri Apr 21 22:18:48 2000  Jim Wilson  
 
        * ia64.cpu (define-model): Change merced to Itanium.
        (f-qp): Change quilifying to qualifying.
        (movbr_ph, movbr_pvec): Delete.
        (I-I21): Delete uses of movbr_ph and movbr_pvec.
 
2000-04-07  Ben Elliston  
 
        * doc/porting.texi (Building a simulator test suite): Clarify
        where generated test cases are placed.
 
2000-04-07  Ben Elliston  
 
        * Makefile.am (gas-test): Remove dependency on `cgen'.
        (sim-test): Ditto.
        * Makefile.in: Regenerate.
 
2000-04-04  Frank Ch. Eigler  
 
        * hardware.scm ( parse): Allow user to set type for pc register.
        * mode.scm (mode-finish!): Add placeholder code for mach-dependent
        type reconfiguration.
        * utils-sim.scm (-sfmt-contents): Add profile-counters only if
        with-profile?.
 
2000-03-30  Ben Elliston  
 
        * doc/rtl.texi (Enumerated constants): Add concept index entries.
 
2000-03-24  Ben Elliston  
 
        * Makefile.am (stamp-cgen): Reinstate target.
        * Makefile.in: Regenerate.
 
2000-03-22  Ben Elliston  
 
        * slib/ppfile.scm: Remove; unused.
        * slib/defmacex.scm: Likewise.
 
2000-03-21  Ben Elliston  
 
        * doc/internals.texi (Source file overview): Document.
 
        * Makefile.am (GUILEDIR): Remove.
        (CGEN): Ditto. Callers use $(GUILE) instead.
        (GUILEFLAGS): Ditto.
        (CGENFILES): Ditto.
        (APPDESCFILES): Ditto.
        (OPCODESFILES): Ditto.
        (SIMFILES): Ditto.
        (pkgdata_SCRIPTS): Ditto.
        (stamp-cgen): Remove target.
        * Makefile.in: Regenerate.
 
        * configure.in: Remove header and library tests.
        * configure: Regenerate.
        * config.in: Likewise.
 
2000-03-20  Ben Elliston  
 
        * read.scm: Cease loading "hob-sup.scm".
        * utils.scm: Inherit the fastcall family of procedures (for now).
        * hob-sup.scm: Remove.
 
2000-03-20  Ben Elliston  
 
        * configure.in (AC_OUTPUT): Do not emit .gdbinit.
        * configure: Regenerate.
        * gdbinit.in: Remove.
 
2000-03-17  Ben Elliston  
 
        * Makefile.am (CGEN): Use guile, not cgen.
        (CGENCFLAGS, LIBIBERTY, INCLUDES): Remove.
        (bin_PROGRAMS, cgen_SOURCES): Likewise.
        (CGENFILES): Fold CGEN_HOB_INPUT_FILES and CGEN_NOHOB_FILES.
        (HOBBIT_INPUT_FILES, HOBBIT_OUTPUT_FILE): Remove.
        (HOB_OBJS): Likewise.
        (CGEN_HOB_SRC, CGEN_HOB_OBJ): Likewise.
        (CGENOBJS): Likewise.
        (cgen_DEPENDENCIES, cgen_LDFLAGS, cgen_LDADD): Likewise.
        (hobbit, hobbit.o, hobbit.c): Remove targets.
        (cos.o, cgen.o, cgen-gh.o, hob-sup.o): Likewise.
        (CLEANFILES): Update.
        * acconfig.h (WITH_HOBBIT): Remove.
        * configure.in: Do not test for 3 arg scm_make_vector. Remove
        option --with-cgen-hobbit.
        * cos.h, cos.c, hob-main.c, hob-sup.c, hob-sup.h, hob.sh: Remove.
        * cgen-gh.h, cgen-gh.c, cgen-hob.scm, cgen.c: Likewise.
        * hobbit.c, hobbit.h, hobbit.scm: Likewise.
        * hobscmif.h, hobslib.scm, scmhob.h: Likewise.
        * Makefile.in: Regenerate.
        * config.in: Likewise.
        * aclocal.m4: Likewise.
        * configure: Likewise.
        * README (Hobbit support): Remove.
        * doc/internals.texi (Conventions): Do not mention Hobbit.
        * doc/porting.texi (Supported Guile versions): Likewise.
 
2000-03-16  Frank Ch. Eigler  
 
        * sid-cpu.scm (-gen-sem-switch-engine): Adjust calling &
        callback convention to new sid sidutil::basic_cpu code.
        (-gen-sfrag-engine-fn): Ditto.
        * sid.scm (-create-virtual-insns!): Ditto.
        (-hw-gen-set-quiet-pc): Mark delay slot execution specially in pbb
        mode.
        (cxmake-skip): Implement properly for pbb mode.
 
2000-03-03  Ben Elliston  
 
        * doc/internals.texi: New file.
 
2000-02-29  Ben Elliston  
 
        * doc/rtl.texi (Derived operands): Remove unnecessary footnote.
        * doc/porting.texi: Formatting tweaks.
 
2000-02-25  Nick Clifton  
 
        * desc-cpu.scm (*_cgen_cpu_open): Initialise signed_overflow_ok_p
        field.
 
Thu Feb 24 14:09:01 2000  Doug Evans  
 
        * operand.scm (,make!): Initialize mode-name, not
        mode.
 
2000-02-23  Andrew Haley  
 
        * m32r.cpu (pcmpbz): Make pcmpbz a special (i.e. hidden)
        instruction.
 
2000-02-24  Ben Elliston  
 
        * doc/rtl.texi (Derived operands): Add some cindex entries.
 
2000-02-23  Ben Elliston  
 
        * ia32.cpu (dndo): Move general purpose macro from here ..
        * simplify.inc (dndo): .. to here.
 
2000-02-18  Frank Ch. Eigler  
 
        * arm.cpu (h-tbit): Add c-call setter function.
        (h-mbits): Ditto.
 
2000-02-17  Frank Ch. Eigler  
 
        * sem-frags.scm (-frag-hash-compute!): Add appstuff arg for traversal.
        (-frag-cost-compute!): Ditto.
        * utils.scm (copyright-cygnus): Add Y2K.
        * sid-cpu.scm (@prefix@_pbb_run): Add unsigned& argument.
 
2000-01-25  Nick Clifton  
 
        * desc-cpu.scm (@arch@_cgen_cpu_open): Add code to initialise
        flags field of the CGEN_CPU_TABLE structure.
 
Sun Dec 12 14:20:36 1999  Doug Evans  
 
        * operand.scm (): Renamed from .
        All references updated.
 
Tue Nov 30 11:06:22 1999  Doug Evans  
 
        * ia32.cpu: Rewrite addressing mode support.
 
        * ifield.scm (): New member `follows'.
        (ifld-known-values): New proc.
        (): New method set-word-offset!.
        (ifld-set-word-offset!): New proc.
        (ifld-new-word-offset): New proc.
        (): New method next-word.
        (): New method next-word.
        (ifld-next-word): New proc.
        (ifld-precedes?): New proc.
        (-ifield-parse): New args word-offset,word-length,follows.
        All callers updated.  Handle CISC-style vs RISC-style ifields.
        (-ifield-read): Recognize word-offset,word-length,follows specs.
        (-ifld-parse-follows): New proc.
        (-multi-ifield-make-default-insert): New proc.
        (-multi-ifield-make-default-extract): New proc.
        (-multi-ifield-parse): Provide default values for insert,extract
        handlers if not specified.
        (): New class.
        (derived-ifield?): New predicate.
        (ifld-derived-operand?): New predicate.
        (f-anyof): New global.
        (ifld-anyof?,ifld-anyof-operand?): New predicates.
        (f-derived,ifld-derived?): Delete.
        (ifield-builtin!): Delete init of f-derived.  Init f-anyof.
        * insn.scm (-sub-insn-ifields): New proc.
        (-sub-insn-make!): New proc.
        (multi-insn-instantiate!): Provide initial implementation.
        (-insn-parse): If insn contains "anyof" operands, create a
         object instead of a plain .
        (-parse-insn-format-symbol): Rewrite derived operand handling.
        Add anyof operand handling.
        (-parse-insn-format-ifield-spec): Rewrite.
        (-parse-insn-format-operand-spec): Delete.
        (-parse-insn-format-list): Delete support for `(operand value)'.
        (anyof-operand-format?): Replaces derived-operand-format?.
        * operand.scm (-operand-parse-getter): Improve error messages.
        (-operand-parse-setter): Ditto.
        (): New members args,syntax,base-ifield,encoding,
        ifield-assertion.
        (): Change baseclass from  to
        .  Delete member values.  New members base-ifield,choices.
        (anyof-operand?): New predicate.
        (-derived-parse-encoding,-derived-parse-ifield-assertion): New procs.
        (-derived-operand-parse): Rewrite.
        (-derived-operand-read): Rewrite.
        (-anyof-parse-choice): New proc.
        (-anyof-operand-parse): Rewrite.
        (-anyof-operand-read,define-anyof-operand): New procs.
        (): Rewrite.
        (-anyof-initial-known): New proc.
        (anyof-satisfies-assertions?): New proc.
        (-anyof-merge-syntax,-anyof-merge-encoding): New procs.
        (-anyof-merge-getter,-anyof-merge-setter): New procs.
        (-anyof-merge-semantics,-anyof-merge-ifield-assertion): New procs.
        (-anyof-merge-subchoices,-anyof-all-subchoices): New procs.
        (-anyof-value-from-derived): New proc.
        (-anyof-all-choices-1,anyof-all-choices): New procs.
        (operand-init!): Create define-anyof-operand reader command.
 
        * insn (syntax-break-out): Take syntax as argument instead of insn.
        All callers updated.
        (syntax-make): Move here, from ???.
 
        * types.scm (): Rename accessors from bitrange:foo to
        bitrange-foo. All uses updated.
        (bitrange-next-word): New proc.
 
        * semantics.scm (-solve-expr-fn,rtx-solve): New procs.
 
        * rtl.scm (rtx-canonicalize): Provide initial implementation.
        (rtx-make-const,rtx-make-enum): New procs.
        (rtx-arg1,rtx-arg2): Renamed from -rtx-arg[12].  All callers updated.
        (rtx-mem-addr,rtx-mem-sel): New procs.
        (rtx-change-address): New proc.
        (rtx-make-ifield,rtx-make-operand,rtx-make-local): New proc.
        (rtx-make-set,rtx-single-set?): New procs.
        (rtx-combine): New proc.
 
        * rtl.scm (rtx-traverse): New arg `appstuff'.  All callers updated.
        (rtx-traverse-with-locals): Ditto.
        (-rtx-traverse,-rtx-traverse-*): Ditto.
 
        * rtl.scm (define-subr): New proc.
        (rtl-init!): Create reader command `define-subr'.
 
        * cos.c (_object_mi_p): Ensure argument is an object.
        (indent): New function.
        (_object_print_elms): Add pretty-printing support.
        (_object_print): Ditto.
 
        * hobbit.scm (*reckless-s->c-fun-table*): Add fastcall7.
        (*floats-s->c-fun-table*): Ditto.
        * hobbit.c,hobbit.h: Rebuild.
        * hob-sup.c (fastcall7): New proc.
        * hob-sup.h (fastcall7): Declare.
        * hob-sup.scm (fastcall7): New macro.
 
        * mach.scm (): New member subr-list.
        (current-subr-list,current-subr-add!,current-subr-lookup): New procs.
        (arch-finish!): Reverse recorded subr list.
 
        * read.scm (debug-env): New global.
        (debug-var-names,debug-var,debug-repl-env): New procs.
        (debug-repl): Rewrite.  New arg `env-list'.  All callers updated.
        (debug-quit): Renamed from `continue'.
 
        * simplify.inc (dsmf): New pmacro.
 
        * utils.scm (plus-scan): New proc.
        (split-bits): Rewrite.
        (split-value): New proc.
 
1999-10-13  Doug Evans  
 
        * doc/Makefile.am (DOCFILES): Add notes.texi.
        * doc/Makefile.in: Rebuild.
 
1999-10-11  Doug Evans  
 
        * ifield.scm (ifld-derived?): New proc.
        (f-derived): New global.
        (ifield-builtin!): Create ifield f-derived.
        (): New class.
        (multi-insn?): New predicate.
        (multi-insn-instantiate!): New proc.
        (-insn-parse): Create  objects for insns with derived
        ifields.
        (-parse-insn-format-symbol): Handle derived ifields.
        (-parse-insn-format-ifield-spec): New proc.
        (-parse-insn-format-operand-spec): New proc.
        (-parse-insn-format-list): Simplify.
        (-parse-insn-format): No longer allow (ifield-object value) spec.
        (derived-operand-format?): New proc.
        (insn-alias?): New proc.
        (non-alias-insns): Rewrite.
        (insn-real?): Renamed from real-insn?, all callers updated.
        (virutal-insns): Rewrite.
        (multi-insns): New proc.
        * mach.scm (arch-analyze-insns!): Instantiate multi-insns if present.
        * operand.scm (op-ifield): Renamed from op:ifield, all callers updated.
        Return #f if operand doesn't have an index or if index is not an
        ifield.
        (hw-index-anyof): New proc.
        (-operand-parse): Allow integer indices.
        (): New class.
        (derived-operand?): New predicate.
        (): New class.
        (): New class.
        (-anyof-parse-value,-anyof-operand-parse): New procs.
        (-derived-operand-parse,-derived-operand-read): New procs.
        (define-derived-operand,define-full-derived-operand): New procs.
        (operand-init!): New reader command define-derived-operand.
 
        * utils.scm (list-take): Handle negative amount.
        (element?): Rewrite.
 
1999-10-10  Doug Evans  
 
        * dev.scm: quick-utils.scm renamed to ~/.cgenrc.
 
1999-10-04  Richard Henderson  
 
        * ia64.cpu: Checkpoint.
 
1999-09-29  Doug Evans  
 
        * sim-cpu.scm (-gen-semantic-fn-table): Virtual insns are always valid.
 
        * sim.scm (sim-finish!,x-invalid): Always set pc.  Set vpc based on
        default-insn-bitsize.  Pass vpc to sim_engine_invalid_insn.
 
Wed Sep 29 14:39:39 1999  Dave Brolley  
 
        * sim.scm (sim-finish!): Don't call sim_io_error for invalid insn. Use
        PC returned by sim_engine_invalid_insn.
 
1999-09-28  Doug Evans  
 
        * ia32.cpu: New file.
 
1999-09-25  Doug Evans  
 
        * utils.scm (bit-set?): Fix off by one error.
 
        * rtl-c.scm (s-sequence): Fix non-void-mode result output.
 
        * rtl.scm (hw): Check for valid hardware element before trying to
        get its mode.
 
        * arm.cpu (arm7f cpu): Renamed from arm.  All users updated.
        * arm7.cpu (bx): Fix name of target address operand in assembler spec.
        (*): arm_compute_operand2_foo renamed to compute_operand2_foo.
        * thumb.cpu (*): arm_compute_operand2_foo renamed to
        compute_operand2_foo.
 
        * cgen-sid.scm (sim_arguments): Add support for building defs.h.
        * sid.scm (-hw-gen-set-quiet-pc): Handle #:delay modifier.
        Call delayed_branch/branch methods instead of assigning to `vpc'.
        (,cxmake-skip): Call skip method.
        (-gen-hw-selector): Call rtl-c++ instead of rtl-c.
        (,cxmake-skip): Ditto.
        (-create-virtual-insns!): Ditto.
        (op:read): Call estate-make-for-normal-c++ instead of estate-...-c.
        (op:write): Ditto.
        (op:record-profile): Specify #:output-language "c++".
        * sid-cpu.scm (-gen-insn-attr-decls): Rename @cpu@_insn_attr to
        @arch@_insn_attr.
        (cgen-desc.h): Use @arch@ namespace instead of @cpu@.
        Define enums here.
        (-gen-reg-access-defns): Use rtl-c++ instead of rtl-c.
        (gen-semantic-code): Ditto.
        (-gen-sem-case,-gen-sfrag-code): Ditto.
        (-gen-hardware-types): Delete class @cpu@_cpu_base.
        (cgen-cpu.h): File is now #included by main cpu class, rather than
        subclassing.
        (cgen-defs.h): New proc.
        (-gen-scache-semantic-fn): Change result type to sem_status.
        New local `status'.  Call done_cti_insn/done_insn method at end.
        (cgen-semantics.cxx): Include @cpu@.h instead of @arch@-main.h,
        cgen-ops.h.
        (cgen-sem-switch.cxx): Ditto.
        * sid-decode.scm (-gen-idesc-decls): Update return type of
        @prefix@_sem_fn.
        (cgen-decode.h): Add using namespace @arch@.
        (cgen-decode.cxx): Include @cpu@.h instead of @arch@-main.h.
 
        * rtl-c.scm (): New member output-language.
        (estate-output-language-c?,estate-output-language-c++?): New procs.
        (,vmake!): Handle #:output-language.
        (estate-make-for-normal-rtl-c++): New proc.
        (rtl-c++-parsed,rtl-c++): New proc.
        (s-c-call): Invoke cpu class method if c++.
        (join): Use s-c-raw-call.
 
        * rtl-c.scm (subword): Don't pass current_cpu to SUBWORD.
        (nop): Rewrite.
 
        * rtl-c.scm (delay): Mark the sequence as #:delay'd.
        * rtl.scm (): New member `modifiers'.
        (,vmake!): Handle #:modifiers.
        (estate-with-modifiers): New proc.
 
        * rtl.scm (rtx-side-effects?): New proc.
        (rtx-canonical-bool): Don't change expr if it has side effects.
        * semantics.scm (-simplify-expr-fn): Handle exprs with side-effects
        better.
 
1999-09-23  Doug Evans  
 
        * sim.scm (gen-scache-type): Fix typo in last patch.
 
Tue Sep 21 17:12:55 1999  Dave Brolley  
 
        * sim.scm (gen-scache-type): Add last_insn_p flag for parallel support.
 
1999-09-05  Doug Evans  
 
        * sid.scm (,cxmake-skip): New method.
        (,cxmake-skip): New method.
 
        * decode.scm (decode-build-table): Delete args startbit,index-list.
        All callers updated.
        * utils-sim.scm (gen-decoder): Delete args startbit,index-list.
        All callers updated.
        * sim-decode.scm (-gen-decode-fn): Always pass 0 for startbit
        to decode-get-best-bits.
        * sid-decode.scm (-gen-decode-fn): Ditto.
 
        * hardware.scm (hw-bits): New proc.
        (-hw-parse): New arg layout.  All callers updated.
        (define-full-hardware): New arg layout.  All callers updated.
        (-hw-validate-layout): New proc.
        (-hw-create-[gs]etter-from-layout): New procs.
        (,parse!): Handle layout spec.
        * types.scm (type-bits): New proc.
 
        * sem-frags.scm (-frag-cost-compute!): Fix calculation of
        UNARY, BINARY, TRINARY rtxs.
 
        * attr.scm (,parse-value): Allow strings.
        * enum.scm (parse-enum-vals): Use reverse! instead of reverse.
        Support '- as "unused spot" indicator.
 
1999-09-03  Doug Evans  
 
        * pgmr-tools.scm (pgmr-pretty-print-insn-format): Fix typo.
 
1999-09-02  Doug Evans  
 
        * rtx-funcs.scm (subword): Fix mode spec of `value'.
 
        * rtl.scm (-rtx-traverse-operands): Fix debugging message
        construction.
        (tstate-make): New arg `depth'.  All callers updated.
        (tstate-depth,tstate-set-depth!): New procs.
        (tstate-incr-depth!,tstate-decr-depth!): New procs.
        (-rtx-traverse-operands): Indent debugging output by traversal depth.
        (-rtx-traverse): Ditto.  Keep track of traversal depth.
 
1999-09-01  Doug Evans  
 
        * sim-decode.scm (-gen-decoder+supporting cast): Move to utils-sim.scm.
        * sid-decode.scm (-gen-decoder+supporting cast): Ditto.
        * utils-sim.scm: Decoder generator support moved here.
        (-decode-equiv-entries?,-decode-sort-entries): New procs.
        (-gen-decoder-switch): Sort entries for more fall-throughs.
 
        * Makefile.am (gas-test,sim-test): Specify ISA when invoking cgen.
        * Makefile.in: Rebuild.
        * sim-test.scm (build-sim-testcase): Add logging message.
        * dev.scm (cload): Recognize SIM-TEST application.
        (load-stest): Set APPLICATION to SIM-TEST.
 
        * desc-cpu.scm (-gen-hash-defines): Add \n to output.
 
        * ifield.scm (-ifield-parse): Allow bit numbers up to 127.
        * mach.scm (-isa-parse): Allow insn bitsizes from 8 to 128.
        * mode.scm (mode-make-int,mode-make-uint): Allow values up to 64 bits.
 
        * insn.scm (syntax-break-out): Handle ${foo}.
 
Sun Aug 29 11:11:15 1999  Doug Evans  
 
        * Makefile.am (noinst_PROGRAMS,noinst_LIBRARIES): Delete.
        (bin_PROGRAMS): Define.
        (CGEN_HOB_INPUT_FILES): Remove $(srcdir)/.
        (cgen-hob.c): Prepend $(srcdir)/ here.
        (APPDESCFILES,OPCODESFILES,SIMFILES,pkgdata_SCRIPTS): Define.
        (libcpu_a_SOURCES): Delete.
        (cgen_DEPENDENCIES,cgen_LDADD): Rewrite.
        (CGEN_HOB_OBJ,CGENOBJS): New variables.
        * configure.in (LIBS): Replace -Wl,-rpath with -R.
        Add AC_CHECK_LIB(guile,main).
        * Makefile.in: Rebuild.
        * doc/Makefile.in: Rebuild.
        * aclocal.m4: Rebuild.
        * config.in: Rebuild.
        * configure: Rebuild.
 
1999-08-28  Doug Evans  
 
        Rename rtx functions from name: to name, accept optional leading
        modifier and mode.
        VM -> VOID, DM -> DFLT, use DFLT instead of VM for default mode.
        * attr.scm (-attr-eval): Update.
        * hardware.scm (hw-mode-ok?): Rename arg mode to new-mode-name.
        (,mode-ok?): Disallow VOID.
        (,mode-ok?): Disallow VOID.
        (,mode-ok?): Disallow VOID.
        * mode.scm (mode-name?): New proc.
        (VOID): Renamed from VM.
        (DFLT): Renamed from DM.
        (mode-builtin!): Update.
        * opcodes.scm (,gen-insert): Update.
        (,gen-extract): Update.
        (,gen-insert,gen-extract): Update.
        * operand.scm (op:mode): Update.
        (,make!): Update.
        (op:new-mode): Update.
        (-operand-read): Update.
        * rtl.scm (-rtx-valid-types): Add OPTIONS, EXPLNUMMODE,
        NONVOIDMODE, DFLTMODE.  Rename VMMODE to VOIDMODE.
        (def-rtx-dual-mode,define-rtx-dual-mode): Delete.
        (-rtx-lazy-sem-mode): Renamed from -rtx-mode.  All callers updated.
        (rtx-make): Call -rtx-munge-mode&options.
        (rtx accessors): Rewrite.
        (rtx-pretty-name): Update.
        (-rtx-traverse-*): Update.
        (-rtx-traverse-explnummode,-rtx-traverse-nonvoidmode): New procs.
        (-rtx-traverse-voidmode,-rtx-traverse-dfltmode): New procs.
        (-rtx-make-traverse-table): Update.
        (-rtx-traverse-operands): Update.
        (-rtx-option?,-rtx-option-list?): New procs.
        (-rtx-munge-mode&options): New proc.
        (-rtx-traverse-expr): Call -rtx-munge-mode&options.
        (-rtx-traverse): Update.
        (rtx-traverse,rtx-traverse-with-locals,rtx-compile): Update.
        (rtx-compile-time-constant?): Update.
        (rtx-true?,rtx-false?,rtx-true,rtx-false): Update.
        (rtx-value): Update.
        (hw,reg,mem): Renamed from foo:.  Update.  All callers updated.
        * rtx-funcs.scm (*): Update.
        * rtl-c.scm (rtl-c-get): Update.
        (rtl-c-set-quiet,rtl-c-set-trace): Update.
        (s-c-call,s-c-raw-call): Update.
        (s-boolifop,s-convop,s-if,s-cond): Update.
        (s-case-vm,-gen-non-vm-case-test,s-case): Update.
        (-par-replace-set-dests,-par-replace-set-srcs): Update.
        (s-parallel,s-sequence): Update.
        (rtl-c-build-table): Update.
        * sem-frags.scm (-frag-hash-compute!): Update.
        (-frag-cost-compute!): Improperly handle unary,binary,trinary ops
        for temporary bug compatibility with previous version.
        (-frag-expr-locals,-frag-expr-stmts): Update.
        (-frag-compute-desired-frags,-frag-pick-best): Update.
        * semantics.scm (-simplify-expr-fn): Update.
        (rtx-simplify): Update.
        (-rtx-ref-type): Update.  Account for modifiers.
        (-build-operand!,-build-reg-operand!,-build-mem-operand!): Update.
        (-build-ifield-operand!): Update.
        (-build-known-values): Update.
        (semantic-compile): Update.
        (-gen-reg-access-defns): Update.
        (gen-semantic-code,-gen-sem-case): Update.
        (-gen-sfrag-code,-gen-sfrag-case): Update.
        * sim-cpu (gen-semantic-code): Update.
        * sim.scm (,gen-write,cxmake-skip): Update.
        (,gen-write,gen-set-macro,cxmake-get-raw): Update.
        (-hw-cxmake-get): Update.
        (,cxmake-get,gen-set-quiet,gen-write): Update.
        (,cxmake-get): Update.
        (,gen-type,gen-read,cxmake-get): Update.
        (,gen-set-quiet,gen-set-trace): Update.
        (,cxmake-get): Update.
        (sim-finish!): Update.
        * utils-gen.scm (-gen-ifld-extract-base): Update.
        (-gen-ifld-extract-beyond): Update.
        (gen-multi-ifld-extract): Update.
        * sid-decode.scm (-decode-expr-ifield-values-used): Update.
        * sid.scm (,gen-write): Update.
        (-gen-decode-insn-globals): Update.
        (-hw-cxmake-get): Update.
        (,cxmake-get-raw): Update.
        (,cxmake-get,gen-set-quiet,gen-write): Update.
        (,cxmake-get): Update.
        (,gen-type,gen-read,cxmake-get): Update.
        (,gen-set-quiet,gen-set-trace): Update.
        (,cxmake-get): Update.
        (-create-virtual-insns!): Update.
        (-decode-split-build-assertion): Update.
        * *.cpu: Update.
        * simplify.inc: Update.
 
1999-08-20  Doug Evans  
 
        * sim.scm (-op-gen-queued-write): Fix memory address calculation.
        Prefix queue function name with sim_ instead of @cpu@_.
 
        * sim.scm (-with-parallel-only?): New global.
        (option-init!): Initialize it.
        (option-set!): Set it.
        (with-parallel-only?): New proc.
        * sim-decode.scm (-gen-decode-insn-globals): Don't include parallel
        and writeback markers if with-parallel-only.
        (-gen-idesc-init-fn): Update.
        * sim-cpu.scm (cgen-cpu.h): Don't generate struct parexec if
        with-generic-write.
 
Wed Aug 18 15:04:30 1999  Doug Evans  
 
        * sim-cpu.scm (-gen-semantic-fn-table): Handle unsupported insns
        with the invalid insn handler.
 
        * utils.scm (list-maybe-ref): New proc.
 
        * mach.scm (-isa-parse): Signal error if isa wasn't specified in
        define-arch.
        (-mach-parse): Signal error if mach wasn't specified in define-arch.
 
        * i960.cpu (test*-*): Delete `expr' arg.
        (test-op,branch-op): Update.
 
1999-08-09  Doug Evans  
 
        * sim.scm (gen-reg-getter-fn,gen-reg-setter-fn): New procs.
        (gen-reg-access-decl): Replace `name' arg with `hw'.  All callers
        updated.
        (gen-reg-access-defn): Ditto.
        (-gen-hw-addr): Rewrite.
        (-op-gen-queued-write): Rewrite.
        * sim-cpu.scm (-gen-cpu-reg-access-decls):
        (-gen-scache-semantic-fn): Handle with-generic-write.
        (-gen-no-scache-semantic-fn): Ditto.
 
1999-08-08  Doug Evans  
 
        * utils-gen.scm (gen-define-ifmt-ifields): Tweak output.
 
        * sim.scm (-with-generic-write?): New global.
        (option-init!): Initialize it.
        (option-set!): Set it.
        (with-generic-write?): New proc.
        (-gen-hw-addr): New proc.
        (-op-gen-queued-write): New proc.
        (-op-gen-set-{quiet,trace}-parallel): Use it if with-generic-write?.
 
        * sim-cpu.scm (-gen-hardware-types): Output code with parallel support
        turned off.
        (-gen-sem-switch): Preserve existing with-parallel? value.
        (-gen-sem-parallel-switch): Ditto.
        (-gen-write-case): Add /indent support.
        (cgen-write.c): Rewrite.
 
        * utils.scm (-current-print-state): New global.
        (make-print-state): New proc.
        (pstate-indent,pstate-set-indent!): New procs.
        (pstate-cmd?,pstate-cmd-do): New procs.
        (/indent): New global.
        (/indent-set,/indent-add): New procs.
        (string-write): Set -current-print-state.
        (-string-write): New arg pstate, all callers updated.
        Handle print-state commands.
        (-string-list-flatten): New proc.
        (string-list->string): Use it.
 
        * sim-cpu.scm (-gen-sem-fn-name): Move here from sim-decode.scm.
        (-gen-sem-fn-table-entry): New proc.
        (-gen-semantic-fn-table): New proc.
        (-gen-scache-semantic-fn): Make fn static.
        (-gen-no-scache-semantic-fn): Ditto.
        (cgen-semantics.c): Define macro SEM_FN_NAME.
        * sim-decode.scm (-gen-decode-insn-globals): Delete FMT,TYPE,IDX,
        FAST,FULL.  Update @cpu@_insn_sem contents.
        (-gen-semf-fn-name): Delete.
        (-gen-sem-fn-decls): Delete.
        (-gen-idesc-decls): Output prototypes of @cpu@_sem_init_idesc_table,
        @cpu@_semf_init_idesc_table.
        (-gen-idesc-init-fn): Update.  Don't initialize pointers to semantic
        handlers here.
        (cgen-decode.h): Print sfmt enum.
        * sid-decode.scm (-gen-semf-fn-name): Delete.
        * utils-gen.scm (gen-sfmt-enum-decl): New proc.
 
        * iformat.scm (sfmt-build): Rename sformats from fmt-foo to sfmt-foo.
        (ifmt-compute!): Ditto.
        * sim-decode.scm (-gen-decoder-switch): Ditto.
        * sid-decode.scm (-gen-decode-expr-entry): Ditto.
        (-gen-decoder-switch): Ditto.
 
        * insn.scm (insn-virtual?): New proc.
 
        * enum.scm (gen-enum-decl): Speed up, build string as list and then
        convert to string.
        * mach.scm (): attr-list is now a pair of lists.
        (current-attr-list): Rewrite.
        (current-attr-add!,current-attr-lookup): Rewrite.
        * sim.scm (gen-cpu-insn-enum-decl): Replace append with append!.
 
1999-08-06  Richard Henderson  
 
        * ia64.cpu: Initial checkpoint.
 
1999-08-06  Doug Evans  
 
        * pmacros.scm (-pmacro-apply): Fix definition, takes only 1 arg.
        (pmacros-init!): Update .apply help string.
 
1999-08-03  Doug Evans  
 
        * sim.scm (-hw-gen-set-quiet-pc): Update call to SEM_BRANCH_VIA_CACHE.
        (,cxmake-skip): New method.
        (,cxmake-skip): New method.
        (-gen-argbuf-fields-union): Add branch_target to `chain' member.
        (gen-argbuf-type): New member `skip_count'.
        (sim-finish!): Update calls to @cpu@_pbb_cti_chain.
        * utils-cgen.scm (atlist-cti?): Don't include SKIP-CTI insns.
 
        * utils-sim.scm: New file.
        * dev.scm (load-sim): Load it.
        (load-sid): Load it.
        * cgen-sid.scm: Load it.
        * cgen-sim.scm: Load it.
        * iformat.scm (): New member sbuf, not initialized by
        default make.
        * rtx-funcs.scm (skip): Rewrite.
        * rtl-c.scm (skip): Rewrite.
        * m32r.cpu (sc,snc): Update `skip' usage.
        * mode.scm (mode-real-mode): New proc.
        * sem-frags.scm (-frag-split-by-sbuf): Rename from -frag-split-by-sfmt.
        Distinguish fragments by the  they use.
        * sim.scm (gen-profile-index-type): Delete.
        (ifield argbuf support): Move to utils-sim.scm and sim-decode.scm.
        (-gen-ifld-decoded-val): Delete, use gen-extracted-ifld-value instead.
        (hardware argbuf support): Move to utils-sim.scm and sim-decode.scm.
        (operand argbuf support): Move to utils-sim.scm and sim-decode.scm.
        (-gen-argbuf-elm): Rewrite.
        (-gen-argbuf-hw-elm): Delete.
        (-gen-argbuf-fields-union): Generate structs for each sbuf instead
        of each sfmt.
        (-sim-sformat-argbuf-list,-sim-insns-analyzed?): New globals.
        (sim-init!): Initialize them.
        (sim-analyze-insns!): Set them.
        (current-sbuf-list): New proc.
        * sim-cpu.scm (-gen-no-scache-semantic-fn): Update calls to
        gen-sfmt-op-argbuf-defns,gen-sfmt-op-argbuf-assigns.
        * sim-model.scm (-gen-model-insn-fn): Ditto.
        * sim-decode.scm (-gen-extract-decls): Delete.
        (-gen-record-argbuf-ifld,-gen-trace-argbuf-ifld): New procs.
        (,gen-extract,gen-trace-extract): Move here from
        sim.scm.
        (
        (
        (-gen-op-extract,-gen-op-trace-extract): New procs.
        (gen-sfmt-op-argbuf-defns,gen-sfmt-op-argbuf-assigns): Rename from
        gen-sfmt-argvars-foo and rewrite.
        (-gen-record-args): Rewrite.
        (-gen-extract-case): Tweak.
        * sid.scm (gen-profile-index-type): Delete.
        (ifield argbuf support): Move to utils-sim.scm.
        (-gen-ifld-decoded-val): Delete, use gen-extracted-ifld-value instead.
        (hardware argbuf support): Move to utils-sim.scm and sid-decode.scm.
        (operand argbuf support): Move to utils-sim.scm and sid-decode.scm.
        (-sim-sformat-argbuf-list): New global.
        (sim-init!): Initialize it.
        (sim-analyze-insns!): Set it.
        (current-sbuf-list): New proc.
        * sid-decode.scm (-gen-argbuf-elm): Rewrite.
        (-gen-argbuf-hw-elm): Delete.
        (-gen-argbuf-fields-union): Generate structs for each sbuf instead
        of each sfmt.
        (-gen-record-argbuf-ifld,-gen-trace-argbuf-ifld): New procs.
        (-gen-extract-decls): Delete.
        (,gen-extract,gen-trace-extract): Move here from
        sid.scm.
        (
        (
        (-gen-op-extract,-gen-op-trace-extract): New procs.
        (gen-sfmt-op-argbuf-defns,gen-sfmt-op-argbuf-assigns): Rename from
        gen-sfmt-argvars-foo and rewrite.
        (-gen-record-args): Rewrite.
        (-gen-extract-case): Tweak.
 
        * cgen-gh.c (gh_putc,gh_puts): New functions.
        * cgen-gh.h (gh_putc,gh_puts): Declare them.
        * cos.c (_object_print_elms,_object_print): Use them.
        * hob-sup.c (fastcall_print): Use them.
        * configure.in: Check for scm_gen_puts, scm_puts.
        * config.in: Rebuild.
        * configure: Rebuild.
        * aclocal.m4: Rebuild.
        * Makefile.in: Rebuild.
 
        * dev.scm (load-opc): Use load instead of maybe-load.
        (load-gtest,load-sim,load-stest): Ditto.
        (load-sid): Ditto.
 
1999-07-23  Doug Evans  
 
        * sid-cpu.scm (-gen-sem-switch-engine): Move definition of `count'
        up to avoid g++ 'goto crosses initialization' warning.
        (-gen-sfrag-engine-fn): Delete vpc arg to NEXT_FRAG.
        (-gen-sfrag-case): Update use of NEXT_FRAG.
 
1999-07-22  Doug Evans  
 
        * cos.c (cos_init): Protect _make_x_symbol from garbage collection.
 
        * read.scm: Load sem-frags.scm.
        * sem-frags.scm (*): Lots rewritten.
        * sid.scm (-with-sem-frags?): New global
        (with-sem-frags?): New proc.
        (option-init!): Initialize -with-sem-frags?.
        (option-set!): Recognize with-sem-frags.
        (sim-init!): Call sim-sfrag-init! if with-sem-frags.
        * sid-cpu.scm (cgen-sem-switch.cxx): Generate semantic frag version
        if asked to.
        (-gen-sfrag-engine-decls): New proc.
        (-gen-sfrag-code,-gen-sfrag-case,-gen-sfrag-enum-decl): New procs.
        (-gen-sfrag-engine-frag-table,-gen-sfrag-engine-fn): New procs.
        (-gen-sfrag-engine): New proc.
        (-gen-sem-case): Emit setup-semantics if specified.
        (-gen-sem-switch-engine): Update init/use of computed goto label.
        * sid-decode.scm (-gen-decode-expr-entry): Fetch ifield values
        from local vars.
        (-gen-idesc-decls): Replace sem_address with cgoto.
        (-gen-scache-decls): Rewrite definition of `execute' member.
        * arm.cpu (arm isa): Enable decode-splits.
        * arm7.cpu (multiply insns): Rename result to mul-result.
 
        Rename decode-specialize to decode-split.
        * decode.scm (*): Update.
        * insn.scm (*): Update.
        * mach.scm (*): Update.
        * sid.scm (*): Update.
 
1999-07-19  Doug Evans  
 
        Record objects as a smob.
        * cos.c (scm_tc16_object): New static global.
        (cos_init): Initialize it.
        (OBJECT_P,OBJECT_ELEMENTS,OBJECT_CLASS_DESC): Update macros.
        (OBJECT_CLASS,OBJECT_ELEMENT_OFFSET): Update.
        (_object_tag): Delete.
        (_object_make_smob): New function.
        (_object_make_x,_object_make_with_values_x): Rewrite.
        (_object_elements,_object_class_desc): Rewrite.
        (_object_copy,object_p): Rewrite.
        (_object_specialize): Rewrite.
        (_object_print_elms,_object_print): New functions.
        (object_smob): New static global.
        (default_make_x): Use OBJECT_ELEMENT_OFFSET instead of magic number.
 
        * cos.c (_make_x_symbol): New static global.
        (object_make): Use it.
        (cos_init): Initialize it.
 
1999-07-15  Doug Evans  
 
        * rtl-c.scm (ifield): Back out last patch, use estate-ifield-var?
        instead to determine whether to use FLD macro.
        (): New member ifield-var?.
        (,vmake!): Recognize #:ifield-var?.
        * utils-gen.scm (-gen-ifld-extract-base): Specify #:ifield-var? #f.
        (-gen-ifld-extract-beyond,gen-multi-ifld-extract): Ditto.
 
        * rtl.scm (rtx-sequence-assq-locals): New proc.
 
        * cos.scm (-object-error): Don't crash on non-objects.
 
        * Makefile.am (CLEANFILES): Add hobbit.
        * Makefile.in: Rebuild.
 
        * rtl-c.scm (s-c-call): Delete unnecessary code.
 
1999-07-14  Doug Evans  
 
        * rtl-c.scm (ifield): Always reference value via `FLD'.
 
        * cos.c (elm_bound_p): Return problem SCM boolean values.
 
        * utils-cgen.scm (display-argv): New proc.
        * cgen-opc.scm (cgen): Call it.
        * cgen-sim.scm (cgen): Ditto.
        * cgen-gas.scm (cgen): Ditto.
        * cgen-stest.scm (cgen): Ditto.
        * cgen-sid.scm (cgen): Ditto.
 
1999-07-05  Doug Evans  
 
        * opc-asmdis.scm (-gen-parse-switch): New local var `junk'.
        * opc-ibld.scm (-gen-insert-switch): Initialize result to NULL.
        (-gen-extract-switch): Initialize result to 1.
        * opcodes.scm (gen-ifield-default-type): New proc.
        (gen-ifield-value-decl): Renamed from gen-ifield-type.  All callers
        updated.
        (,gen-insert): Handle non-ifield indices.
        (,gen-extract): Ditto.
        (,gen-parse): Ditto.
        (,gen-print): Ditto.
        (,gen-parse): Ditto.
        (,gen-print): Ditto.
        (,gen-fget): Ditto.
        (,gen-fset): Ditto.
 
        * sim.scm (-gen-hw-index-raw): Handle scalar indices.
        (-gen-hw-index): Ditto.
        * sid.scm (-gen-hw-index-raw): Handle scalar indices.
        (-gen-hw-index): Ditto.
 
        * sem-frags.scm: New file.
 
        * attr.scm (attr-parse): Add better checking of input.
 
        * hardware.scm (-hw-parse-getter): Renamed from -hw-parse-get.
        All uses updated.
        (-hw-parse-setter): Renamed from -hw-parse-set.  All uses updated.
 
        * ifield.scm (ifld-nil?): New proc.
 
        * operand.scm (): New members getter,setter.
        (,make!): New args getter,setter.  All uses updated.
        (op:getter,op:setter): New procs.
        (,field-start): Return 0 for non-ifield indices.
        (,field-length): Return 0 for non-ifield indices.
        (-operand-parse-getter,-operand-parse-setter): New procs.
        (-operand-parse): New args getter,setter.  All callers updated.
        Always use hw-index-scalar for scalar operands.
        (-operand-read): Handle getter,setter.
        (define-full-operand): New args getter,setter.  All uses updated.
        * semantics.scm (-build-ifield-operand!): Update.
        (-build-index-of-operand!): Update.
        * sim.scm (,cxmake-get): If operand has getter, use it.
        * simplify.inc (define-normal-operand): Update.
 
        * rtl.scm (abs,sqrt,cos,sin,min,max,umin,umax): New rtx fns.
        * rtl-c.scm (s-unop): Indirect fp ops through fpu op vector.
        (s-binop,s-cmpop,s-convop): Ditto.
        (abs,sqrt,cos,sin,min,max,umin,umax): New rtx fns.
        * sparc.cpu (insn-fmt2): Add FPOPS1,FPOPS2.
        (fcc-tests): New insn-enum.
        (fcc-value): Rename from fcc-type.
        * sparcfpu.cpu: New file.  All fp support moved here.
 
        * rtl.scm (): New member class.
        (rtx-class-*?): New procs.
        (def-rtx-node): New arg class.  All callers updated.
        (def-rtx-syntax-node,def-rtx-operand-node,def-rtx-dual-node): Ditto.
        * rtx-funcs.scm (*): Specify class.
 
        * utils-cgen.scm (context-make-reader): New proc.
 
        * utils.scm (assert-fail-msg): New variable.
        (assert): Use it.
        (list-drop,list-tail-drop): New procs.
 
1999-06-22  Doug Evans  
 
        * desc-cpu.scm (-gen-hash-defines): Restore generation of
        CGEN_MIN_INSN_SIZE deleted on March 22.
 
        * ifield.scm (,needed-iflds): New method.
        (,needed-iflds): New method.
        (ifld-needed-iflds): New proc.
        (multi-ifield?): New proc.
        * iformat.scm (): Delete member ifmt.  New members length,iflds.
        (-sfmt-search-key): Include insn length in key.
        (-sfmt-order-iflds,-sfmt-used-iflds): New procs.
        (): Delete members ifmt-key,sfmt-key.  New member used-iflds.
        (-ifmt-lookup-ifmt!): Compute key here.
        (-ifmt-lookup-sfmt!): Compute key here.  Delete arg ifmt.
        All callers updated.
        (ifmt-build): Delete arg desc.  New args search-key,iflds.
        All callers updated.
        (sfmt-build): Delete args desc,ifmt.  New args search-key,cti?,
        in-ops,out-ops,sorted-used-iflds.  All callers updated.
        * minsn.scm (minsn-make-alias): Use insn-set-ifmt!.  Update call
        to ifmt-build.
        * operand.scm (op-iflds-used): New proc.
        * utils-gen.scm (gen-ifld-type): Move here from sim.scm
        and sim-cpu.scm.
        And from sid.scm,sid-cpu.scm as well.
        (gen-ifld-extract-decl,-gen-ifld-extract-base): Ditto.
        (-gen-extract-word,-gen-ifld-extract-beyond): Ditto.
        (gen-ifld-extract,gen-multi-ifld-extract): Ditto.
        (gen-extracted-ifld-value): Ditto.
        (-extract-chunk-specs): Ditto.
        (gen-define-ifields,gen-define-ifmt-ifields): Ditto.
        (-extract-chunk,-gen-extract-beyond-var-list): Ditto.
        (gen-extract-ifields,gen-extract-ifmt-ifields): Ditto.
        (-extract-insert-subfields): New function.
        * sim.scm (gen-record-argbuf-ifld): Renamed from gen-ifld-extract.
        (gen-record-argvar-ifld): Renamed from gen-ifld-extract-argvar.
        * sim-cpu.scm (-gen-extract-ifmt-macro): Replace calls to
        gen-define-ifields with gen-define-ifmt-ifields.  Ditto for
        gen-extract-foo.
        (-gen-no-scache-semantic-fn): Ditto.
        (-gen-sem-case): Ditto.
        (-gen-read-case): Update calls to gen-define-ifields,
        gen-extract-ifields.
        * sim-decode.scm (-gen-record-args): Update.
        (-gen-sfmt-argvars-assigns): Update.
        (-gen-extract-case): Update.
        * sim-model.scm (-gen-model-insn-fn): Replace calls to
        gen-define-ifields with gen-define-ifmt-ifields.  Ditto for
        gen-extract-foo.
        * sid.scm (gen-ifld-argbuf-defn): Use gen-ifld-type.
        (gen-record-argbuf-ifld): Rename from gen-ifld-extract.
        (gen-record-argvar-ifld): Rename from gen-ifld-extract-argvar.
        * sid-decode.scm (-gen-decode-expr-entry): Update calls to
        gen-define-ifields, gen-extract-ifields.
        (-gen-record-args): Update.
        (gen-sfmt-argvars-assigns): Update.
        (-gen-extract-case): Replace calls to gen-define-ifmt-ifields
        with gen-define-ifields.  Ditto for gen-extract-foo.
        (-gen-decode-fn): Use gen-ifld-extract-decl/gen-ifld-extract
        procs rather than method calls.
 
1999-06-18  Doug Evans  
 
        * sid.scm (-create-virtual-insns!): New local `context', pass it
        to insn-read.
 
        * rtl.scm (-rtx-traverse): Output symbol shortcuts in source form,
        (operand name) not (operand object), (local name) not (local object).
        (rtx-traverse-with-locals): New proc.
        (-compile-expr-fn): New proc.
        (rtx-compile): Rewrite.
        * rtl-c.scm (rtl-c-get): Handle operand/local names for src arg.
        (rtl-c-set-quiet): Don't accept operand/local names for dest arg.
        (rtl-c-set-trace): Ditto.
        (operand define-fn): Recognize operand name argument.
        (local define-fn): Recognize sequence temp name argument.
        * rtx-funcs.scm (operand): Argument is operand name, not object,
        so call current-op-lookup.
        (local): Similarily, so call rtx-temp-lookup.
 
        * rtl.scm (rtx-field?): Use rtx-name instead of car.
        (rtx-operand?): Ditto.
        (rtx-pretty-name): Ditto.
        (rtx-local-obj): Flag symbol argument as an error.
        (rtx-local-name): New proc.
        (rtx-sequence-locals,rtx-sequence-exprs): New procs.
 
        * rtl.scm (-rtx-traverse-operands): Fix debugging output of arg-types.
 
        * read.scm (debug-repl): Renamed from -debug-repl.  All callers
        updated.
 
        * arm7.cpu (do-word/byte-store): Use (trunc: QI rd) rather than
        (and: QI rd #xff).
 
        * hobbit.scm (*reckless-s->c-fun-table*): Add fastcall4, fastcall6.
        (*floats-s->c-fun-table*): Ditto.
        * hobbit.c,hobbit.h: Rebuild.
        * rtl.scm (-rtx-traverse-expr): Use fastcall6.
        * semantics.scm (rtx-simplify): Use /fastcall-make.
 
        * iformat.scm (-sfmt-search-key): Don't include memory modes.
 
        * insn.scm (): Delete members condition, compiled-condition.
        (,make!): Update
        ( getters,setters): Update.
        (-insn-parse,insn-read,define-full-insn): Update.
        * minsn.scm (minsn-make-alias): Update.
        * iformat.scm (ifmt-analyze): Delete insn-condition reference.
        (ifmt-compute!): Ditto.
        * sim.scm (sim-finish!): Update.
        * simplify.inc: (define-normal-insn): Update.
        * sid-cpu.scm (gen-semantic-code): Update.
 
        * iformat.scm (-ifmt-lookup-ifmt!): Use insn-set-ifmt!.
        (-ifmt-lookup-sfmt!): Use insn-set-sfmt!.
        (ifmt-compute!): Ditto.
 
1999-06-16  Doug Evans  
 
        * minsn.scm (minsn-compute-iflds): Print better error message for
        missing ifields.
 
1999-06-12  Doug Evans  
 
        * rtl.scm (tstate->estate): Don't copy over expr-fn.
 
        * Makefile.am (HOBFLAGS): New variable.
        (cgen-hob.c): Use it.
        (hobbit.c): Use it.
        (libcpu_a_SOURCES): Add hob-sup.c.
        (hob-sup.o): New rule.
        * Makefile.in: Rebuild.
        * cgen.c: #include hob-sup.h.
        (cgen_init_c): Call hobbit_init_support.
        * hobbit.scm (*fastcall-make*,*c-symbol*): New variables.
        (*special-scm->c-functions*): Add them.
        (display-c-expression): Handle *c-symbol*.
        (*reckless-s->c-fun-table*): Add *fastcall-make*, fastcall5.
        (*floats-s->c-fun-table*): Ditto.
        (normalize): Recognize /fastcall-make.
        (normalize-fastcall-make): New proc.
        * hobbit.c,hobbit.h: Rebuild.
        * hob-sup.scm: New file.
        * hob-sup.c: New file.
        * hob-sup.h: New file.
        * read.scm: Load hob-sup.scm.
        * rtl.scm (-rtx-name-list): New variable.
        (rtx-name-list): New proc.
        (rtx-lookup): Try symbol first.
        (def-rtx-node): Add name to -rtx-name-list.
        (def-rtx-syntax-node,def-rtx-operand-node,def-rtx-macro-node): Ditto.
        (-rtx-traverse-anymode): New proc.
        (-rtx-traverse-{emode,intmode,floatmode,nummode,vmmode}): New procs.
        (-rtx-traverse-{rtx,setrtx,testrtx,condrtx,casertx}): New procs.
        (-rtx-traverse-{locals,env,attrs,symbol,string,number}): New procs.
        (-rtx-traverse-{symornum,object}): New procs.
        (-rtx-make-traverse-table): Rewrite.
        (-rtx-traverse-operands): Rewrite arg-types handling.
        Handle #f result of traverser.
        (-rtx-traverse): Renamed from -rtx-traverse-normal.
        Move debug handling here.
        (-rtx-traverse-debug): Delete.
        (rtl-finish!): Change -rtx-traverse-table into list of handlers
        for each rtx.
        * semantics.scm (semantic-compile:process-expr!): Fix call to
        -rtx-traverse.
        * utils.scm (map1-improper): New proc.
 
1999-06-08  Doug Evans  
 
        * arm.sim (h-tbit): Replace FUN-ACCESS with FUN-SET.
        (h-mbits): Ditto.
        * sid.scm (-hw-cxmake-get): s/FUN-ACCESS/FUN-GET/.
        (-hw-gen-set-quiet): s/FUN-ACCESS/FUN-SET/.
        (,cxmake-get): Tweak.
        (sim-finish!): Delete FUN-ACCESS attribute.  Create FUN-GET,FUN_SET.
 
1999-06-07  Doug Evans  
 
        * thumb.cpu (dnti): Delete timing spec.
        (all insn): Update.
 
        * arm.cpu (arm isa): New fields condition, setup-semantics.
        (thumb isa): New field setup-semantics.
        (h-gr): Add attribute CACHE-ADDR.
        * arm7.cpu (dnai): Delete condition.
        (eval-cond): Delete.
 
        * mach.scm (): New member setup-semantics.
        (-isa-parse-setup-semantics): New proc.
        (-isa-parse): New arg setup-semantics.
        (-isa-read): Recognize setup-semantics.
 
        * sid-cpu.scm (gen-extract-fields): Split into two:
        gen-extract-ifields, gen-extract-ifmt-ifields.
        (-gen-scache-semantic-fn): Delete `taken_p'.  Delete
        tracing begin/end messages (done by caller now).
        (-gen-sem-case): Delete `taken_p'.  Add npc,br_status.  Delete
        tracing begin/end messages (done by x-before,x-after virtual insns).
        (-gen-sem-switch-engine): Redo vpc initialization.  Save vpc at
        end so don't have to look it up again next time.
        * sid-decode.scm (-decode-expr-ifield-values): New proc.
        (-decode-expr-ifield-tracking-key): New proc.
        (-decode-expr-ifield-tracking): New proc.
        (-decode-expr-ifield-values-used): New proc.
        (-decode-expr-ifield-mark-used!): New proc.
        (-gen-decode-expr-set-itype): New proc.
        (-gen-decode-expr-entry): Rewrite.
        (-gen-decode-table-entry): New proc.
        (-gen-decoder-switch): Use it.
        (-gen-virtual-insn-finder): New proc.
        (-gen-argbuf-elm): Move here from sid.scm.
        (-gen-argbuf-hw-elm): Ditto.
        (-gen-argbuf-fields-union): Add entries for chain,before insns.
        (-gen-scache-decls): Add `cond' member to @prefix@_scache for
        conditional-execution isas.
        (-gen-decode-fn): Record conditional-exec ifield.
        * sid.scm (-current-pbb-engine?): New global.
        (current-pbb-engine?,set-current-pbb-engine?!): New procs.
        (,gen-ifld-extract): New arg `indent'.
        (,gen-ifld-extract): Ditto.
        (-hw-gen-set-quiet-pc): Add pbb support.  Delete `taken_p'.
        (-op-gen-set-trace): Don't print tracing messages for pbb engine.
        (-gen-arch-model-decls): Only scan real insns.
        (scache-engine-insns,pbb-engine-insns): New procs.
        (-create-virtual-insns!): New proc.
        (sim-finish!): Call it.
        (-decode-specialize-insn?): New proc.
        (-decode-specialize-build-assertion): New proc.
        (-decode-specialize-insn-1): New proc.
        (-decode-specialize-insn): New proc.
        (-fill-sim-insn-list!): New proc.
        (sim-analyze!): Create copies of insns to be specialized.
        * utils-cgen.scm (obj-set-name!): New proc.
 
        * attr.scm (-attr-eval): Rewrite calls to rtx-simplify/rtx-compile.
        * iformat.scm (ifmt-analyze): Pass `insn' to semantic-compile,
        semantic-attrs.
        (ifmt-compute!): Delete arg `arch'.  Result is list of iformats,
        sformats.
        * mach.scm (arch-analyze-insns!): Update call to ifmt-compute!.
        * rtl-c.scm (rtl-c-get): Use DM for default mode instead of VM.
        Avoid infinite loop when rtx-eval-with-estate leaves expr alone.
        (attr): Rewrite test for insn owner.
        (member): New rtx function.
        * rtl.scm (rtx-* accessors): Define as cxr directly rather than
        as separate function.
        (rtx-ifield?,rtx-ifield-name): New procs.
        (rtx-operand-obj): Rewrite.
        (rtx-operand-name): New proc.
        (rtx-cmp-op-mode,rtx-cmp-op-arg): New procs.
        (rtx-number-list-values,rtx-member-value,rtx-member-set): New procs.
        (tstate-make): New args owner, known.  All callers updated.
        (tstate-known-lookup): New proc.
        (rtx-traverse): New arg owner.  All callers updated.
        (rtx-make-bool): New proc.
        (rtl-find-ifields): Rewrite.
        (rtx-simplify,rtx-simplify-eq-attr-{insn,mach}): Moved to ...
        * semantics.scm: ... here.
        (rtx-const-equal,rtx-const-list-equal): New procs.
        (-build-known-values): New proc.
        (semantic-compile): New arg `insn'.  Call rtx-simplify.
        (semantic-attrs): Ditto.
        * rtx-funcs.scm (member,number-list): New rtx functions.
 
        * attr.scm (attr-remove-meta-attrs-alist): Delete leading '-' in name.
        Rewrite.  Delete arg `all-attrs'. All callers updated.
        (attr-remove-meta-attrs): Delete leading '-' in name.  All callers
        updated.
        * utils-cgen.scm (gen-bool-attrs): Remove meta attrs.
 
        * decode.scm (subdtable-add): Handle `expr' entries.
        (exprtable-entry-make): Use vector.  Record ifields refered to by expr.
        (exprtable-entry-*): Update.
        (exprtable-entry-iflds): New proc.
        (exprentry-cost): New proc.
        (exprtable-sort,-gen-exprtable-name): New procs.
        (exprtable-make): New arg `name'.  All callers updated.  use vector.
        (exprtable-*): Update.
        (-build-decode-table-entry): Don't issue collision warning if all are
        specialized insns.  Sort exprtable entries before building table.
 
        * read.scm (-reader-process-expanded-1): Move pretty printing of
        input to logging level 4.
 
        * utils.scm (string-list->string): New proc.
 
        * insn.scm (): Define setters for ifield-assertion, condition,
        semantics.
        (insn-read): Delete leading '-' in name.  All callers updated.
        (real-insn?): New proc.
        (real-insns): Rewrite.
        (insn-has-ifield?): New proc.
        (insn-builtin!): Create insn attribute SPECIALIZED.
 
        * mach.scm (): Delete member app-data.
        (current-raw-insn-list): New proc.
        (insn-list-car,insn-list-splice!): New procs.
        (): New class.
        (-isa-parse-decode-specialize): New proc.
        (-isa-parse-decode-specializes): New proc.
        (): New members `condition', `decode-specializes'.
        (-isa-parse-condition): New proc.
        (-isa-parse): New args condition, decode-specializes.
        (-isa-read): Recognize condition, decode-specializes.
        (-isa-add-decode-specialize!): New proc.
        (modify-isa): New proc.
        (isa-conditional-exec?,state-conditional-exec?): New procs.
        (arch-init!): New reader command `modify-isa'.
 
        * mode.scm (mode-class-signed?,mode-class-unsigned?): New procs.
        (mode-signed,mode-unsigned?): New procs.
 
Thu Jun  3 16:00:40 1999  Doug Evans  
 
        * types.scm (): New method get-shape.
        * hardware.scm (): Forward get-shape,get-num-elms
        onto type.
        (hw-shape,hw-num-elms): New procs.
        * sim.scm (,gen-profile-index-type): Use "unsigned short"
        if there's more than 255 registers.
        * sid.scm (,gen-profile-index-type): Ditto.
 
        * hardware.scm (-hw-parse): Flag as error CACHE-ADDR specified
        with get/set specs.
 
1999-05-21  Doug Evans  
 
        * cgen-sid.scm (sim-arguments): Add -X.
        * sid-cpu.scm (-gen-hardware-types): Comment out scache vars.
        (-gen-all-semantic-fns): Don't include PBB support virtual insns.
        (-gen-sem-case): Use CASE/NEXT macros again.  Tweak indenting.
        Simplify by supporting pbb engine only.
        (-gen-sem-switch-init): New proc.
        (-gen-sem-switch-engine): Rename from -gen-sem-switch-fn.
        (cgen-sem-switch.cxx): New proc.
        * sid-decode.scm (-gen-decode-insn-globals): Replace with-sem-switch?
        with with-pbb?.  Support dual scache/pbb engines.
        (-gen-idesc-decls): Replace with-sem-switch? with with-pbb?.
        Support dual scache/pbb engines.
        (cgen-decode.h): Generate semantic fn decls if with-scache?.
        * sid.scm (*) with-pbb? replaces with-sem-switch?.
        (sim-finish!): Create pbb support virtual insns if with-pbb?.
 
1999-05-10  Ben Elliston  
 
        * arm7.cpu: Remove coprocessor related fields, operands and insn
        definitions for now. Take the undefined instruction trap instead.
        (ldmda-wb): New instruction.
        (ldmib-wb): Likewise.
        (ldmdb-wb): Likewise.
        (stmdb-wb): Likewise.
        (stmib-wb): Likewise.
        (stmda-wb): Likewise.
 
1999-05-08  Doug Evans  
 
        * sid.scm (,cxmake-get): Call GETMEM method, not function.
        (,gen-set-quiet): Call SETMEM method, not function.
 
        * utils-cgen.scm (keyword-list->arg-list): Fix call to substring,
        hobbit can't handle optional third arg.
 
1999-05-07  Doug Evans  
 
        * arm.cpu (h-tbit): Delete set spec.
        (h-mbits): Don't call arm_mbits_set in set spec.
        * arm.sim: New file.
        * hardware.scm (modify-hardware): New proc.
        (hardware-init!): Add modify-hardware command.
        * sid.scm (-hw-cxmake-get): Use method call if FUN-ACCESS specified.
        (-hw-gen-set-quiet): Ditto.
        (sim-finish!): Call invalid_insn method.  Define FUN-ACCESS builtin
        hardware attribute.  Load $arch.sim file if present.
        * utils-cgen.scm (keyword-list?): New proc.
        (keyword-list->arg-list,arg-list-validate-name): New procs.
        (arg-list-check-no-args,arg-list-symbol-arg): New procs.
 
        * arm7.cpu (eval-cond): Pass pc to @cpu@_eval_cond handler.
 
        * sid-cpu.scm (-gen-hardware-types): Rename @cpu@_cpu to
        @cpu@_cpu_cgen.
 
        * attr.scm (obj-prepend-atlist!): New proc.
 
        * opc-opinst.scm (cgen-opinst.c): Analyze instructions if necessary.
 
        * sid.scm (,profilable?): Use op:type.
        * sim.scm (,profilable?): Use op:type.
 
1999-05-04  Doug Evans  
 
        * utils.scm (find-index,find): Be more stack friendly.
 
        * arm7.cpu (arith-imm-op): Compute pc before setting cpsr.
        (bic-imm): Ditto.
 
1999-05-01  Doug Evans  
 
        * arm.cpu (h-gr-usr): New hardware element.
        (h-gr-fiq,h-gr-svc,h-gr-abt,h-gr-irq,h-gr-und): New hardware elements.
        (arm-mode): New keyword.
        (h-mbits): Add set spec.
        (h-spsr): Implement get/set specs.
 
        * read.scm: Load slib/pp.scm, slib/genwrite.scm.
        (-reader-process-expanded-1): Pretty print logging output.
 
        * sid-cpu.scm (-gen-reg-access-defns): Make getters `const'.
        (cgen-cpu.h): Print enums before hardware elements.
        (cgen-semantics.cxx): @arch@-cgen.h renamed to @arch@-main.h.
        * sid-decode.scm (cgen-decode.cxx): Ditto.
        * sid-model.scm (cgen-model.cxx): Ditto.
 
        * utils-cgen.scm (context-error): Accept variable number of
        trailing args.
 
        * rtx-funcs.scm (error:): New rtx function.
        * rtl-c.scm (s-case-vm): New proc.
        (-gen-non-vm-case-get,s-case-non-vm): New procs.
        (s-case): Simplify, handle non-VM result.
        (error:): New rtx function.
 
1999-04-30  Doug Evans  
 
        * arm.cpu (h-pc): Add set spec to zero bottom bits.
        (test-hi,test-ls): Fix cbit handling.
        (shift-type,h-operand2-shifttype): Move here ...
        * arm7.cpu: ... from here.
        (set-cond,set-cond-maybe,dnix): Delete, unused.
        (set-zn-flags,set-logical-cc,set-add-flags,set-sub-flags): Move ...
        * arm.cpu: ... to here.
        * thumb.cpu (cmp,alu-cmp): Use set-sub-flags.
        (alu-cmn): Use set-add-flags.
        (alu-tst): Use set-zn-flags.
        (alu-cmp): Use set-sub-flags.
        (lsl,lsr,asr): Set condition codes.
        (add,addi,sub,subi,mov,addi8,subi8): Ditto.
        (alu-op): Split into three: alu-logical-op,alu-arith-op,
        alu-shift-op.
        (hireg-op): Split sem-fn into lo-dest-sem-fn,hi-dest-sem-fn.
        All callers updated.
        (sub-sp): Rename from add-sp-neg.
        (f-lbwl-offset): Delete.
        (f-lbwl-hi,f-lbwl-lo): New ifields.
        (lbwl-hi,lbwl-lo): Update.
        (bl-hi): Add 4 to pc.
        (push-reg,pop-reg): Simplify.
        (push,push-lr): Push registers in correct order.
        (pop,pop-pc): Pop registers in correct order.
        (save-reg-inc,load-reg-inc): Simplify.
        (ldmia): Save registers in correct order.
 
1999-04-30  Ben Elliston  
 
        * arm7.cpu (f-op-hdt): Remove; unused.
        (f-ror-imm8-value,f-ror-imm-rotate): New fields.
        (f-ror-imm8): New multi-ifield.
        (f-operand2-bit7): Remove; use the generic `f-bit7' instead. All
        callers updated.
        (f-uimm12): New field.
        (ror-imm8): New operand.
        (uimm12): Likewise.
        (hdt-offset8): Reinstate operand.
        (offset4-hi,offset4-lo): Remove.
        (set-cond): Remove macro; unused.
        (set-cond-maybe): Likewise.
        (load-word/byte): Use uimm12 operand for a true 12-bit immediate.
        (store-word/byte): Likewise.
        (load-halfword): Use hdt-offset8 multifield operand instead of two
        4-bit operands that are explicitly combined by semantic code.
        (do-halfword-store): Bug fix. Set address when not preindexing.
        (store-halfword): Also use hdt-offset8 operand.
        (arith-op): Avoid clobbering source registers when one of them is
        the destination register.
        (arith-imm-op): Likewise.
        (tst-imm): Use ror-imm8 operand. Handle special case of rot 0.
        (teq-imm): Likewise.
        (ldm-p): Rename to ldmdb.
        (stm-pw): Rename to stmdb-wb.
        (multi-action): New macro; test reg-list bits and execute a
        semantic fn if the bit is set.
        (ldmda,ldmib,ldmia,ldmia-wb,ldmdb): New multiple load insns.
        (stmdb,stmib,stmia,stmia-wb,stmda,stmdb-wb): Store insns.
        (all insns): Use dnai entries for simplicity rather than dni.
        (*): Use short-form of (const ..).
 
1999-04-29  Doug Evans  
 
        * rtl.scm (): Rename member type to style.  Rename
        member eval to evaluator.
        (rtx-foo accessors): Rename from rtx:foo.  All callers updated.
        (tstate-make): Delete arg op-fn.  All callers updated.
        (tstate-op-fn,tstate-set-op-fn!): Delete.
        (rtx-traverse): Delete op-fn arg.  All callers updated.
        * semantics.scm (-simplify-for-compilation-process-expr): New proc,
        split out of -simplify-for-compilation.
 
        * Makefile.am (CGEN_NONHOB_FILES,CGENFILES): New variables.
        (cgen_DEPENDENCIES): Add stamp-cgen.
        (stamp-cgen): New rule.
        * Makefile.in: Rebuild.
 
        * rtl-c.scm (enum:): Define emitter for.
        * rtl.scm (rtx-constant?): Rename from rtx-const? and check for
        enums as well.
        (rtx-constant-value,rtx-enum-value): New procs.
        (-rtx-traverse-normal): Expand enum-value to (enum enum-value).
        (rtx-compile-time-constant?): Return #t for enums.
        (rtx-true?,rtx-false?): Handle enums.
        (rtx-simplify-eq-attr-mach): Use rtx-true,rtx-false instead of
        building result by hand.
        (rtx-simplify-eq-attr-insn): Ditto.
        * rtx-funcs.scm (enum:,enum): New rtx functions.
 
        * mach.scm (): New members insns-analyzed?, semantics-analyzed?,
        aliases-analyzed?.
        (arch-analyze-insns!): New proc.
        * opcodes.scm (opcodes-analyze!): Call arch-analyze-insns! instead
        of calling ifmt-compute! directly.
        * sid.scm (-sim-insns-analyzed?): Delete.
        (sim-analyze!): Call arch-analyze-insns! instead of calling
        ifmt-compute! directly.
        * sim.scm (-sim-insns-analyzed?): Delete.
        (sim-analyze!): Call arch-analyze-insns! instead of calling
        ifmt-compute! directly.
 
        * utils.scm (string-take-with-filler): New proc.
        (string-take): Use it.
 
        * pgmr-tools.scm: New file.
        * read.scm: Load it.
        * insn.scm (pretty-print-insn-format): Move to pgmr.scm.
 
        * insn.scm (insn-base-mask): Renamed from insn:mask.
        All callers updated.
        (insn-base-mask-length): Renamed from insn:mask-length.
        All callers updated.
        (insn-foo): Renamed from insn:foo.  All callers updated.
        * minsn.scm (minsn-foo): Renamed from minsn:foo.  All callers updated.
        * iformat.scm (compute-insn-base-mask-length): Renamed from
        compute-insn-mask-length.  All callers updated.
        (compute-insn-base-mask): Renamed from compute-insn-mask.
        All callers updated.
 
        * enum.scm (-enum-parse-prefix): New proc.
        (,make!): Don't parse enum values here.
        (-enum-parse): Do it here.  Call -enum-parse-prefix.
        (define-full-insn-enum): Ditto.
        (enum-vals-upcase): New proc.
        * hardware.scm (define-keyword): Make enum prefix uppercase.
        * hobscmif.h (CHAR_LOWERP,CHAR_UPPERP,CHAR_WHITEP): New macros.
 
        * ifield.scm (,field-mask): Allow container to be #f.
        (,field-extract): New method.
        (,field-extract): New method.
        (ifld-extract): New proc.
        * opcodes.scm (ifld-insert-fn-name): Renamed from ifld-insert.
        (ifld-extract-fn-name): Renamed from ifld-extract.
 
        * ifield.scm (ifld-new-value): Renamed from ifield-make.
        All callers updated.
 
        * ifield.scm (ifld-lsb0?): New proc.
        (sort-ifield-list): New arg up?.  All callers updated.
        * iformat.scm (compute-insn-mask): Get lsb0? flag from argument,
        rather than global state.
 
1999-04-27  Doug Evans  
 
        * insn.scm (pretty-print-insn-format): New proc.
 
        * Makefile.in: Rebuild.
        * aclocal.m4: Rebuild
        * configure: Rebuild.
 
Mon Apr 26 10:30:18 1999  Doug Evans  
 
        * configure.in (AM_INIT_AUTOMAKE): Update version to 0.7.2.
        * configure: Rebuild.
        * aclocal.m4: Rebuild.
        * Makefile.in: Rebuild.
        * doc/Makefile.in: Rebuild.
        * doc/version.texi: Rebuild.
 
1999-04-25  Doug Evans  
 
        * utils.scm (bits->bools): New proc.
 
1999-04-23  Doug Evans  
 
        * sid.scm (,gen-ifld-extract-decl): Fix call to
        subfield's gen-ifld-extract-decl method.
 
1999-04-23  Ben Elliston  
 
        * arm7.cpu (ldrsh-pu): Remove.
        (do-halfword-load): New pmacro.
        (load-halfword): Likewise.
        (do-halfword-store): Likewise.
        (store-halfword): Likewise.
        (strh-*): New instructions.
        (ldrsb-*): Likewise.
        (ldrh-*): Likewise.
        (ldrsh-*): Likewise.
 
1999-04-22  Doug Evans  
 
        * ifield.scm (ifld-constant?): Delete special handling of RESERVED
        fields.
 
        * arm7.cpu (do-word/byte-store): Fix typo.
 
1999-04-22  Ben Elliston  
 
        * arm7.cpu (do-word/byte-load): Handle cases where the destination
        register is the program counter (R15).
 
        * arm7.cpu (do-word/byte-store,store-word/byte): New pmacros.
        (str-*): Implement using store-word-byte. Remove older versions.
        (bic): Use the `inv' rtx for obtaining bitwise complements.
        (bic-imm): Likewise.
        (mvn): Likewise.
        (mvn-imm): Likewise.
        (store-indev-reg): Remove crufty pmacro.
        (load-indiv-reg): Likewise.
        (ldm-p): Reverse the order of register processing for decrement.
        (stm-p): Likewise.
        (stbi): Remove; handled by the str-* insns.
 
1999-04-21  Doug Evans  
 
        * thumb.cpu (cmp): Fix carry bit computation.
        (alu-cmp): Ditto.
 
1999-04-20  Doug Evans  
 
        * arm.cpu (h-tbit): Specify set spec.
        (h-cpsr): Ditto.
        * arm7.cpu (bx): Don't call C routine, just set h-tbit.
        (set-sub-flags): Interpret "carry bit" as a borrow.
        (all sub/cmp insns): Carry bit is actually a borrow bit.
        * thumb.cpu (bx-rs,bx-hs): Don't call C routine, just set h-tbit.
        (add-carry,sub-carry,thumb-neg,thumb-bic,thumb-inv): Delete.  Use
        .pmacro instead.
        (hireg-add,hireg-cmp,hireg-move): Ditto.
 
        * read.scm (-CGEN-VERSION): Change version to 0.7.2.
        (-CGEN-LANG-VERSION): Ditto.
 
1999-04-18  Doug Evans  
 
        * pmacros.scm (-pmacro-make): New arg `default-values',
        all callers updated.
        (-pmacro-default-values): New proc.
        (-pmacro-process-keyworded-args): New proc.
        (-pmacro-process-args): New proc.
        (-pmacro-invoke): Process arguments before expanding macro.
        (-pmacro-get-arg-spec,-pmacro-get-default-values): New procs.
        (define-pmacro): Handle default values specified in arg list.
        * rtl.scm (rtx-alu-op-mode,rtx-alu-op-arg): New procs.
        (rtx-boolif-op-arg[01]): New procs.
        (rtx-true,rtx-false,rtx-canonical-bool): New procs.
        (rtx-simplify): Handle not,orif,andif.
        * semantics.scm (-simplify-for-compilation): Simplify not,orif,andif.
        * utils.scm (alist-copy): New proc.
        * arm7.cpu (do-word/byte-load,load-word/byte): New pmacros.
        (ldr*): Rewrite.
        (swi): Explicitly set pc.
 
        * thumb.cpu (bx-rs,bx-hs): Reverse test for switch to arm mode.
 
1999-04-17  Ben Elliston  
 
        * arm7.cpu (ldr-pu): Do not add 8 to R15; the step() method
        correctly adjusts the program counter now.
 
        * arm7.cpu (f-halfword?): Rename from `f-hdt-halfword?'.
        (f-signed?): Rename from `f-hdt-signed?'.
        (f-offset4-hi): Rename from `h-hdt-off4-ms'.
        (f-offset4-lo): Rename from `h-hdt-off4-ls'.
        (f-hdt-offset8): Use new field names.
        (ldr): Use `imm12' field, not `offset12', since we do our own
        address arithmetic.
        (str, str-*): Likewise.
        (ldu-*): Remove most; better not implemented than broken.
        (ldrh*): Likewise.
        (ldrsh-pu): New insn.
        (stri): Likewise.
        (stri-p): Likewise.
        (stbi): Likewise.
        (ldm-p): Likewise; replace (load-indiv-reg) version.
 
1999-04-15  Doug Evans  
 
        * arm.cpu (h-pc): Delete VIRTUAL attribute, get/set specs.
        * arm7.cpu (*): Fix mode of result of arm_compute_carry_out_*.
        (*): Explicitly specify mode in c-call.
        (logical-op): Recognize sets of h-gr[15] as sets of pc.
        (arith-op): Ditto.
        (and-imm,orr-imm,xor-imm,mov-imm,bic-imm,mvn-imm): Ditto.
        (arith-imm-op): New pmacro.
        (add-imm,adc-imm,sub-imm,sbc-imm,rsb-imm,rsc-imm): Use it.
        * thumb.cpu (bx-rs,bx-hs): Rewrite.
 
1999-04-14  Doug Evans  
 
        * rtl.scm (rtx-simplify-eq-attr-insn): Fix call to context-error.
 
        * rtl.scm (rtl-find-ifields): Implement.
 
        * utils-gen.scm: New file.
        * read.scm: Load it.
        * desc.scm: Move generic attribute code to utils-gen.scm.
        * Makefile.am (CGEN_HOB_INPUT_FILES): Add it.
        * Makefile.in: Rebuild.
 
        * arm7.cpu (R15-OFFSET): New attribute.
        (dnai): New pmacro.
        (logical-op): Delete arg `result?'.  All callers updated.  Use dnai.
        Delete use of eval-cond (dnai specifies it).  Specify R15-OFFSET of 12
        for reg-shift version.
        (arith-op): Ditto.
        (data processing insns): Reorganize.  Use dnai.
 
        * attr.scm (attr-kind): New proc.
        (attr-list-enum-list): Rewrite.
        (-attr-sort): Split result into two lists, bools and non-bools.
        (current-attr-list-for): Update.
 
        * cgen-sid.scm (sim-arguments): Add -H -> build desc.h file.
        * sid-cpu.scm (-gen-attr-decls): New proc.
        (-gen-insn-attr-decls): New proc.
        (cgen-desc.h): New proc.
        (cgen-cpu.h): Put everything in @cpu@ namespace.
        (gen-parallel-exec-type): Change prefix of parexec struct from
        @cpu@ to @prefix@.
        (-gen-trace-record-type): Ditto for trace_record struct.
        (-gen-write-case): Update.
        (-gen-scache-semantic-fn): Change function prefix from @cpu@ to
        @prefix@.  Update scache struct references.
        (-gen-sem-case): Update scache struct references.
        (-gen-sem-switch-fn): Update idesc struct reference.
        Update insn_type enum reference.
        (cgen-write.cxx): Update scache,argbuf references.
        (cgen-semantics.cxx): Simplify namespace choice (always @cpu@).
        * sid-decode.scm (IDESC-TABLE-VAR): Change prefix of insn_data
        from @cpu@ to @prefix@.
        (-gen-decode-insn-entry): Use gen-cpu-insn-enum.
        (-gen-decode-expr-entry): Ditto.  Change prefix of INSN_X_INVALID
        from @CPU@ to @PREFIX@.
        (-gen-decoder-switch): Change prefix of INSN_X_INVALID
        from @CPU@ to @PREFIX@.
        (-gen-decode-insn-globals): Generate insn attributes.
        (-gen-sem-fn-name): Change function prefix from @cpu@ to @prefix@.
        (-gen-sem-fn-decls): Use -gen-sem-fn-name.  Add `using' for
        semantic fn typedef.
        (-gen-idesc-decls): Simplify cpu class name (always @cpu@_cpu).
        Change prefix of scache struct from @cpu@ to @prefix@.
        Change prefix of semantic fn typedef from @cpu@ to @prefix@.
        Change prefix of idesc struct from @cpu@ to @prefix@.
        Change prefix of insn_type enum from @cpu@ to @prefix@.
        (-gen-argbuf-fields-union): Change prefix of sem_fields union
        from @cpu@ to @prefix@.
        (-gen-scache-decls): Change prefix of scache struct from
        @cpu@ to @prefix@.  Update idesc struct name.
        Update decode,execute methods.
        (-gen-extract-case): Update to type name changes.
        (-gen-decode-fn): Ditto.
        (cgen-decode.h): Put everything in @cpu@ namespace (except
        semantic fn decls).  Change prefix of insn_word from @cpu@ to @prefix@.
        (cgen-decode.cxx): Add using namespace @cpu@.
        * sid-model.scm (-gen-hw-profile-decls): Change prefix of
        model_mark_get/set from @cpu@ to @prefix@.
        (gen-model-unit-fn-name): Change function prefix from @cpu@ to
        @prefix@.
        (gen-model-fn-decls): Update idesc struct name.  Change prefix
        of model_insn_before/after from @cpu@ to @prefix@.
        (-gen-model-insn-fn): Update scache/idesc/argbuf struct names.
        Update insn_word type name.
        (-gen-model-timing-table): Update INSN_TIMING struct name.
        (-gen-model-init-fn): Update MODEL_DATA struct name.
        (-gen-mach-defns): Update name of init_idesc_table fn.
        (cgen-model.cxx): Add using namespace @cpu@.
        * sid.scm (gen-cpu-class): Delete.
        (gen-attr-type): New proc.
        (gen-obj-attr-sid-defn): New proc.
        (,gen-profile-code): Update name of model_mark_get/set fn.
        (gen-cpu-insn-enum-decl): Change prefix of insn_type enum from
        @CPU@ to @PREFIX@.
        (gen-cpu-insn-enum): Update name of insn enum.
        * thumb.cpu (bx-rs): Rename @cpu@_do_bx to @prefix@_do_bx.
        (bx-hs): Ditto.
        (swi): Rename @cpu@_swi to @prefix@_swi.
 
        * decode.scm (-build-decode-table-entry): Remove heuristic for
        distinguishing insns, and use insn ifield-assertion specs.
 
        * desc-cpu.scm (gen-A-attr-mask): Simplify.
        (gen-ifld-defns): Boolean attributes begin at number 0 now.
        (gen-hw-table-defns,gen-operand-table,gen-insn-table): Ditto.
        * opc-itab.scm (-gen-macro-insn-table): Ditto.
        * utils-cgen.scm (gen-attr-enum-decl): Change type arg to prefix,
        all callers updated.
        (gen-attr-name): New proc
        (gen-attr-mask): Use it.  Boolean attributes start at 0 now.
        (gen-obj-attr-defn): Delete num_nonbools count.
 
        * iformat.scm (ifmt-analyze): Handle insn-condition.
        (ifmt-compute!): Ditto.
        * insn.scm (): Specify default value for condition,
        post-cond-trap,compiled-condition,compiled-semantics.
        (,make!): New arg condition.
        (): Add getters for condition,compiled-condition.
        (-insn-parse): New arg condition, all callers updated.
        (-insn-read): Recognize condition spec.
        (define-full-insn): New arg condition.
        * minsn.scm (minsn-make-alias): Update call to (make  ...).
        * semantics.scm (semantic-compile): Change arg sem-code to
        sem-code-list.
        (semantic-attrs): Ditto.
        * sim.scm (sim-finish!): Update calls to define-full-insn.
        * simplify.inc (define-normal-insn): Update call to define-full-insn.
        * sid-cpu.scm (gen-semantic-code): Handle insn-condition.
        * sid.scm (sim-finish!): Update call to define-full-insn.
 
Tue Apr 13 17:04:34 1999  Doug Evans  
 
        * Makefile.am (sim-cpu): Allow specification of ISA.
        * Makefile.in: Rebuild.
 
Sun Apr 11 00:37:56 1999  Jim Wilson  
 
        * i960.cpu (sll-expr, srl-expr, sra-expr): Handle large shift counts.
 
1999-04-10  Doug Evans  
 
        * sparccom.cpu (check-fp-enable): Wrap TRAP32_FP_DIS in c-code.
 
        * arm.cpu (gr-names): Put pc first so it gets prefered in disassembly.
 
        * attr.scm (atlist?): New proc.
        (-attr-eval): Rewrite.
        (attr-parse): New proc.
        (atlist-parse): Use it.
 
        * decode.scm (exprtable-entry-make): New proc.
        (exprtable-entry-insn,exprtable-entry-expr): New procs.
        (exprtable-make,exprtable-insns): New procs.
 
        * hardware.scm (hw-mode-ok?): Delete argument `set?'.
        All uses updated.
        (hardware-builtin!): Make h-memory a vector.
 
        * iformat.scm (ifmt-ifields): Renamed from ifmt-fields.
        All callers updated.
        (ifmt-analyze): Use csem-* accessors on result of semantic-compile.
 
        * insn.scm (). Rename ifld-assertions to ifield-assertion.
        All uses updated.
        (-insn-parse): Set semantics to #f if not specified.
        (define-insn,define-full-insn): Take out code that ignores ALIAS's
        if simulator.
        (-parse-insn-format): Recognize `=' iformat spec.
 
        * mach.scm (isa-min-insn-bitsize): Ignore ALIAS's.
        (isa-max-insn-bitsize): Ditto.
 
        * opcodes.scm (,gen-insert): Call rtl-c instead of
        rtl-c-with-alist.
        (,gen-extract): Ditto.
        (,gen-insert,gen-extract): Ditto.
        * sid-cpu.scm (-gen-reg-access-defns): Ditto.
        (gen-define-ifmt-ifields): New proc.
        (gen-semantic-code): Rewrite.
        * sid-decode.scm (-gen-decode-expr-entry): New proc.
        (-gen-decoder-switch): Handle expression tables.
        (-gen-extract-case): Call gen-define-ifmt-ifields instead of
        gen-define-fields.
        * sid-model.scm (-gen-model-insn-fn): Call gen-define-ifmt-ifields
        instead of gen-define-fields.
        * sid.scm (,gen-ifld-extract-decl): New arg `indent', all
        callers updated.
        (
        (-gen-ifld-extract-base): Call rtl-c instead of rtl-c-with-alist.
        (-gen-ifld-extract-beyond): Ditto.
        (,gen-ifld-extract): Ditto.
        (<*>,cxmake-get,gen-set-quiet,gen-set-trace,gen-write): Update to new
        rtl evaluation code.
        (op:read): Build an  to pass to gen-read.
        (op:write): Build an  to pass to gen-write.
        (op:record-profile): Build an  to pass to
        gen-record-profile.
        * sim-cpu.scm (gen-semantic-code): Rewrite.
        * sim.scm (-gen-ifld-extract-base): Call rtl-c instead of
        rtl-c-with-alist.
        (-gen-ifld-extract-beyond): Ditto.
        (,gen-ifld-extract): Ditto.
        (,gen-get-macro,gen-set-macro): Ditto.
        (<*>,cxmake-get,gen-set-quiet,gen-set-trace,gen-write): Update to new
        rtl evaluation code.
        (op:read): Build an  to pass to gen-read.
        (op:write): Build an  to pass to gen-write.
        (op:record-profile): Build an  to pass to
        gen-record-profile.
 
        * operand.scm (): Give `selector' default value of #f.
        Give `num' default value of -1.  Give `cond?' default value of #f.
        (op:new-mode): Delete arg `set?', all uses updated.
 
        * read.scm (reader-error): Handle #f return from port-filename.
        (-init-parse-cpu!): Call rtl-c-init!.
        (reader-install-builtin!): Call rtl-builtin!.
 
        * rtl-c.scm: New file.
        * semantics.scm: New file.
        * read.scm: Load them.
        * rtl.scm: C generation moved to rtl-c.scm.  Semantic analysis moved
        to semantics.scm.
        (): Delete members syntax?,macro,c,expr.  New members
        type,eval,num.
        (rtx-lookup): Renamed from -rtx-func-lookup.  All callers updated.
        (-rtx-num-text,-rtx-max-num): New globals.
        (def-rtx-operand-node,define-rtx-operand-node): New procs.
        (-rtx-macro-lookup): New proc.
        (rtx-lvalue-mode-name): Renamed from rtx-expr-mode-name.
        (rtx-env-stack-empty?,rtx-env-stack-head): New procs.
        (rtx-env-var-list,rtx-env-empty-stack,rtx-env-init-stack1): New procs.
        (rtx-env-make,rtx-env-empty?,rtx-env-make-locals): New procs.
        (rtx-env-push,rtx-temp-lookup,-rtx-closure-make): New procs.
        (rtx-make,rtx-kind?,rtx-const?,rtx-const-value,rtx-symbol-name,
        rtx-operand?,rtx-operand-obj,rtx-local?,rtx-local-obj, rtx-xop-obj,
        rtx-index-of-value,rtx-if-mode,rtx-if-test,rtx-if-then,rtx-if-else,
        rtx-eq-attr-owner,rtx-eq-attr-attr,rtx-eq-attr-value): New procs.
        (rtx-pretty-name): New proc.
        (-rtx-traverser-table,-rtx-make-traverse-table): New procs.
        (rtx-traverse-*): Rewrite rtx traversing.
        (rtx-eval-*): Rewrite rtx evaluation.
        (rtx-compile): New proc.
        (rtx-simplify): New proc.
        (rtx-simply-eq-attr-mach,rtx-simplify-eq-attr-insn): New procs.
        * rtx-funcs.scm: C generation moved to rtl-c.scm.
        (ifield,index-of): Rewrite.
        (name): Renamed from `operand:'.
        (operand,xop,local): New rtx's.
        (current-insn): Rewrite.
        * Makefile.am (CGEN_HOB_INPUT_FILES): Add rtl-c.scm, semantics.scm.
        (cgen-hob.h): Remove rule for.
        (cgen-hob.o): Depend on cgen-hob.c only.
        * Makefile.in: Rebuild.
 
        * utils-cgen.scm (vmake): New proc.
        (): New class.
        (context-make-prefix,context-error): New procs.
 
Fri Apr  9 19:26:28 1999  Jim Wilson  
 
        * i960.cpu: Add some ??? comments.
        (xnor, ornot): New instructions.
        (*): Delete obsolete COND-CTI and UNCOND-CTI attributes.
 
1999-04-08  Doug Evans  
 
        * cos.scm (-object-error): Print better error message.
 
        * pmacros.scm (-pmacro-env-make): Renamed from -env-make.
        (-pmacro-env-ref): Renamed from -env-ref.
 
1999-03-31  Doug Evans  
 
        * hardware.scm (,parse!): Allow get/set specs.
        (h-pc): Delete.
        (hardware-builtin!): Delete h-pc builtin.
        * arm.cpu (h-pc): Define.
        (h-gr): Delete get,set specs.  Make array of 16 regs again.
        * arm7.cpu (set-logical-cc-maybe): Delete.
        (set-zn-flags,set-add-flags,set-sub-flags): New macros.
        (data processing insns): Rewrite.
        * m32r.cpu (h-pc): Define.
        * fr30.cpu (h-pc): Define.
        * i960.cpu (h-pc): Define.
        * sparc.cpu (h-pc): Define.
 
        * rtl.scm (-rtx-traverse-operands): Add some error checking to LOCALS.
        (s-parallel): Replace do {...} while (0) with {...}.
        (s-sequence): Ditto.
 
        * sid-cpu.scm (gen-parallel-exec-type): Make type of `written'
        consistent.
        (-gen-write-case,-gen-sem-case): Ditto.
        (-gen-sem-case): Only specify `written' if profiling or
        parallel-write-back.
        (-gen-scache-semantic-fn,-gen-all-semantic-fns): Put procs back in.
        (-gen-sem-switch-fn): New proc.
        (cgen-semantics.cxx): Emit either semantic fns or semantic switch
        based on with-sem-switch option.
        * sid-decode.scm (-gen-decode-insn-globals): Only define
        idesc_table_initialized_p if with-sem-switch.  Record semantic fn
        addresses in idesc_table if !with-sem-switch.
        (-gen-sem-fn-decls): Rewrite.
        (-gen-idesc-decls): Define @cpu@_sem_fn type.  Define `execute'
        member based on with-sem-switch.  Only define
        `idesc_table_initialized_p' member if with-sem-switch.
        (cgen-decode.h): If !with-sem-switch, declare semantic fns.
        * sid.scm (-with-sem-switch?): New variable.
        (option-init!): Initialize it.
        (option-set!): Set it.
        (with-sem-switch?): New proc.
        (-op-gen-set-trace): Only emit `written' reference if profiling.
        (sim-finish!): Use h_pc_set to set pc.
 
1999-03-30  Doug Evans  
 
        * sparccom.cpu (arith-cc-binop): New args s32-set-flags,s64-set-flags.
        All callers updated.
        (arith-carry-cc-binop): New arg set-flags.  All callers updated.
 
        * sid.scm (gen-argbuf-type): Delete.
        (-gen-argbuf-fields-union): Move to ...
        * sid-decode.scm: ... here.
 
        * read.scm (-reader-process-expanded-1): New proc.
        (-reader-process-expanded): Call it to catch nested begin's.
        (reader-process): Move `begin' handling to -reader-process-expanded.
 
        * insn.scm (-insn-read): Fix name of `format' spec.
 
        * pmacros.scm (.pmacro): New builtin.
        (scan-symbol): If procedure macro, return macro rather than its symbol.
        (check-macro): Don't do lookup, instead check if (car expr) is
        macro object.
        (scan-list): Handle .pmacro.
        (scan): No longer re-examine text for another macro invocation.
        (-pmacro-build-lambda): New proc.
        (define-pmacro): Rewrite.  If defining one pmacro to be an alias of
        another, fetch the other's value (rather than doing it during
        expansion).
 
1999-03-27  Doug Evans  
 
        * Makefile.am (CGEN_HOB_INPUT_FILES): Add decode.scm.
        * Makefile.in: Rebuild.
 
        * decode.scm (decode-get-best-bits): Use memq instead of element?.
        (-fill-slot!): Simplify.
        (-build-slots): Simplify.
 
        * dev.scm (load-sid): Don't load sid-arch.scm.
 
        * sid-decode.scm: Replace computed goto decoder/extractor with plain
        switch's.
        * sim-decode.scm: Replace computed goto decoder/extractor with plain
        switch's.
 
1999-03-26  Doug Evans  
 
        * sim-decode.scm: Clean up pass.  Move decoder computation into ...
        * decode.scm: ... here.  New file.
        * sid-decode.scm: Use decoder computation code in decode.scm.
        * read.scm: Load decode.scm.
 
        * arm.cpu (arm710 model): Add u-exec function unit.
        (h-gr): Delete CACHE-ADDR for now.  Make array of 15, not 16 regs.
        Add get/set specs to redirect reg 15 to h-pc.
        (h-*): Indicate for both ARM and THUMB isas.
        (cbit,nbit,vbit,zbit): Ditto.
        (h-ibit,h-fbit,h-tbit,h-mbits): New hardware elements.
        (h-cpsr): Make virtual.  Add get/set specs.
        (h-spsr-fiq,h-spsr-svc,h-spsr-abt,h-spsr-irq,h-spsr-und): New hw.
        (h-spsr): New virtual reg.
        * arm7.cpu (shift-type): New explicitly defined keyword.
        (h-operand2-shifttype): Use it.
        (set-logical-cc-maybe): Delete carry-out arg.  New args arg1,arg2.
        All callers updated.  Don't set cbit.
        (logical-op): Add rm to ifield list.  Change case to case:.  Use
        shift-type enum as case choices.  Set cbit.
        (and,orr,eor,add-imm): Uncomment out.
        (undefined): Temporarily comment out.
        * thumb.scm (mov,cmp,addi8,subi8,str-sprel,ldr-sprel): s/rd/bit10-rd/.
        (lda-pc,lda-sp): Ditto.
        (ldr-pc): Rename from ldr.
        (cbranch): Mark insns as being thumb insns.
 
        * attr.scm (,parse-value): Recognize strings.
 
        * cgen-sid.scm: Don't load sid-arch.scm.
        (sim-arguments): Delete unused entries.
        * sid-arch.scm: Delete.
 
        * insn.scm (,iflds): Renamed from flds.  All uses updated.
        (,ifld-assertions): New member.
        (,make!): New arg ifld-assertions, all callers updated.
        ( accessors): Change insn:foo to insn-foo.  All callers updated.
        (insn:fields): Delete.
        (-insn-parse): New arg ifld-assertions.  All callers updated.
        (-insn-read,define-insn): New procs.
        (define-full-insn): New arg ifld-assertions.  All callers updated.
        (insn-init!): New comment define-insn.
 
        * model.scm (-model-parse): Ensure at least one unit specified.
 
        * rtl.scm (-rtx-traverse-operands): Recognize environments.
        (,get-name): New method.
        (-rtx-make-current-closure,s-closure): New proc.
        (hw:): Wrap rtx indices in a closure.
        (-gen-case-prefix): New proc.
        (s-case): Simplify.
        * rtx-funcs.scm (case:): Fix call to s-case.
        (closure): New rtx func.
 
        * hardware.scm (): New member isas-cache.
        (,get-isas): New method.
        (hardware-builtin): Indicate for all isas.
        * ifield.scm (-ifield-parse): Only keep if isa+mach are kept.
        * mach.scm (current-arch-mach-name-list): Return list of names.
        (current-isa-mach-name-list): Ditto.
        (define-arch): Install builtin objects here.
        * read.scm (keep-atlist?): Only keep if both mach and isa are
        being kept.
        (keep-mach-atlist?): New proc.
        (keep-isa-multiple?,current-keep-isa-name-list): New proc.
        (reader-install-builtin!): Renamed from -install-builtin!.
        * sid-cpu.scm (-gen-reg-access-defns): Renamed from
        -gen-cpu-reg-access-defns.  Rewrite.
        (gen-reg-access-defn): Delete.
        (-gen-hardware-struct): New proc.
        (-gen-hardware-types): Simplify.  Add multiple-isa support.
        (gen-semantic-fn,-gen-all-semantics): Delete.
        (-gen-read-args,-gen-read-case,-gen-read-switch): Delete.
        (cgen-cpu.c,cgen-read.c,cgen-sem-switch.c,cgen-mainloop.in): Delete.
        (cgen-write.cxx,cgen-semantics.cxx,cgen-decode.cxx): Renamed from *.c.
        Call sem-analyze-insns!.
        (cgen-semantics.cxx): Add multiple-isa support.
        * sid-decode.c (-gen-idesc-decls): Add multiple-isa support.
        (-gen-scache-decls,-gen-decode-fn): Ditto.
        (cgen-decode.h): Call sem-analyze-insns!.
        * sid-model.scm (cgen-model.cxx): Renamed from cgen-model.c.
        * sid.scm (-with-multiple-isa?): New variable.
        (option-init!): Initialize it.
        (option-set!): Set it.
        (with-multiple-isa?): New proc.
        (gen-cpu-ref): New arg isas.  All callers updated.
        (gen-cpu-class): New proc.
        (*-get-macro,*-set-macro): Delete.
        (gen-reg-get-fun-name,gen-reg-set-fun-name): New procs.
        (-hw-gen-fun-get): Call gen-reg-get-fun-name.
        (-hw-gen-fun-set): Call gen-reg-set-fun-name.
        (-gen-hw-index): Call rtx-c instead of rtx-c-with-temps for rtxs.
        (-sim-insns-analyzed): New global variable.
        (sim-init!): Reset it.
        (sim-analyze-insns!): New proc.
        (sim-analyze!): Don't do instruction analysis here.
        (sim-finish!): Specify isa of x-invalid insn.
        * sim.scm (sim-finish!): Specify isa of added x-* virtual insns.
 
1999-03-22  Doug Evans  
 
        * thumb.cpu (cpu,mach,model): Delete.
        (dntf): New pmacro.  Use it for all field definitions.
        (dntop): New pmacro.  Use it for all operand definitions.
        (asr): Correct field list.
        (add,addi,sub,subi,add-sp,add-sp-neg): Ditto.
 
        * utils-cgen.scm (define-getters): New macro to simplify
        writing class accessors.
        (define-setters): Ditto.
        (sanitize): Recognize isa elements.
 
        * sid-cpu.scm (*): Replace cpu:parallel-exec? call with
        state-parallel-exec?.
        * sid-model.scm (*): Ditto.
        * sid-decode.scm (*): Ditto.  Replace cpu:decode-assist with
        state-decode-assist.
 
        * sid-decode.scm (decode-bits): Replace list-reverse! with reverse!.
        (-gen-decode-switch): Rewrite to not generate deeply nested lists.
        * sim-decode.scm (-gen-decode-switch): Ditto.
 
        * sim-arch.scm (-regs-for-access-fns): Delete.
        (-biggest-reg-mode,-gen-arch-reg-access-decls): Delete.
        (-gen-arch-reg-access-defns): Delete.
 
        * sim-cpu.scm (*): Replace cpu:liw-insns with state-liw-insns,
        cpu:parallel-insns with state-parallel-insns, cpu:parallel-exec?
        with state-parallel=exec?.
        (cgen-*): Call sim-analyze-insns! here.
        * sim-decode.scm (cgen-*): Ditto.
        * sim-model.scm (cgen-*): Ditto.
        * sim.scm (-sim-insns-analyzed): New global variable.
        (sim-init!): Reset it.
        (sim-analyze-insns!): Renamed from sim-analyze!.  Keep track if we've
        already done the analysis.
 
        * sim-model.scm (-gen-mach-defns): Add mach attribute number to
        MACH struct.
 
        * arm.cpu: Only include arm7.cpu,thumb.cpu if necessary.
        (arm arch): Update isa spec.
        (arm,thumb isas): Define.
        (arm7 cpu): default-insn-bitsize,base-insn-bitsize moved to isas.
        (arm7tdmi mach): Add isa spec.
        * arm7.cpu (*): Replace subreg: with subword:.  Remove unnecessary
        `const' on word number.
        * fr30.cpu (fr30 arch): Update isa spec.
        (fr30 isa): Define.
        (fr30bf cpu): default-insn-bitsize,base-insn-bitsize,decode-assist,
        moved to isa spec.
        * i960.cpu (i960 arch): Update isa spec.
        (i960 isa): Define.
        (i960base cpu): default-insn-bitsize,base-insn-bitsize,decode-assist,
        liw-insns,parallel-insns moved to isas spec.
        * m32r.cpu (m32r arch): Update isas spec.
        (m32r isa): Define.
        (m32rbf cpu): default-insn-bitsize,base-insn-bitsize,decode-assist,
        liw-insns,parallel-insns moved to isa spec.
        * sparc.cpu (sparc arch): Update isas spec.
        (sparc isa): Define.
        * sparc32.cpu (sparc32 cpu): default-insn-bitsize,base-insn-bitsize,
        decode-assist moved to isa spec.
        * sparc64.cpu (sparc64 cpu): Ditto.
        * sparccom.cpu (trap insns): Correct mode of result of c-call:.
        * desc-cpu.scm (-gen-isa-table-defns): New proc.
        (-gen-mach-table-defns): Output mach table.
        (-gen-hash-defines): Delete insn size macros, except for
        CGEN_MAX_INSN_SIZE.
        (-cgen-cpu-open): Rewrite cpu_open handling.  Take stdarg list of args.
        (cgen-desc.h): Define MAX_ISAS.
        (cgen-desc.c): Include stdarg.h.  Call -gen-isa-table-defns.
        * mach.scm (): Rename arch-data to data.  New member isa-list.
        (arch-* accessors): Renamed from arch:*.  All callers updated.
        (current-arch-isa-name-list): New proc.
        (-arch-parse-isas): Renamed from -arch-parse-isa.
        (def-isa-attr!): Rewrite.
        (): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5330</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<itype>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5331</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<isa>): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5332</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (isa-min-insn-bitsize,isa-max-insn-bitsize): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5333</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (isa-integral-insn?,isa-parallel-exec?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5334</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-isa-parse,-isa-read,define-isa): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5335</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<cpu>): Members default-insn-bitsize,base-insn-bitsize,decode-assist,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5336</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        liw-insns moved to <isa>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5337</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cpu-* accessors): Renamed from cpu:*.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5338</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-cpu-parse,-cpu-read): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5339</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (state-*): Renamed from state:*.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5340</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (state-default-insn-bitsize,state-base-insn-bitsize): Use isa spec,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5341</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        not cpu.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5342</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (state-parallel-insns,state-parallel-exec?,state-liw-insns): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5343</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (state-decode-assist): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5344</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<derived-arch-data>): Delete min-insn-bitsize,max-insn-bitsize.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5345</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-adata-set-derived!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5346</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (adata-integral-insn?): Renamed from adata:integral-insn?.  All</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5347</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5348</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (arch-init!): Add define-isa command.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5349</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * read.scm (<reader>): Default keep-isa member to (all).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5350</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (reader-* accessors): Renamed from reader:*.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5351</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-keep-isa-set!): Call string->symbol on isa name list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5352</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (keep-isa-validate!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5353</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-isa): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5354</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (keep-isa?): Recognize "all".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5355</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-init-parse-cpu!): New arg keep-isa.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5356</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Call -keep-isa-set!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5357</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cmd-if): Recognize keep-isa?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5358</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cpu-load): New arg keep-isa.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5359</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-opt-spec-update): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5360</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (common-arguments): First arg is string, not symbol.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5361</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-cgen): Call -opt-spec-update.  Rewrite argument parsing.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5362</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5363</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (rtx-get): Default mode of string arg is INT.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5364</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5365</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (s-subword): Renamed from s-subreg.  All uses updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5366</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5367</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (join:): Pass cpu to handler.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5368</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5369</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure.in (guile_include_dir): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5370</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5371</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5372</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5373</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5374</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid-cpu.scm (-extract-chunk-specs): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5375</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-define-fields): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5376</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-extract-chunk): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5377</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-extract-beyond-var-list): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5378</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-extract-fields): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5379</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5380</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-22  Ben Elliston  <bje@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5381</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5382</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * arm7.cpu (ldri-p): New instruction.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5383</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (swi): Do not vector through 0x8 yet--there is nothing there.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5384</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (addi): Reinstate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5385</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (movi): Likewise.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5386</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (all): Use (const x) in subreg expressions.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5387</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5388</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-19  Ben Elliston  <bje@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5389</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5390</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * arm7.cpu (smull): Use operand field `rs', not `mul-rn'. Thinko.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5391</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (smlal): Likewise.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5392</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5393</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-17  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5394</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5395</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (define-arch): Specify "forced" default-alignment.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5396</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (-parse-alignment): Recognize "forced" alignment.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5397</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (-extract-chunk-specs): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5398</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-define-fields): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5399</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-extract-chunk): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5400</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-extract-beyond-var-list): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5401</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-extract-fields): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5402</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5403</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Port to guile 1.3.1.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5404</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (GUILEINCDIR,GUILELDFLAGS,GUILELDADD): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5405</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (LIBIBERTY): New var.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5406</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (HOB_OBJS): Add cgen-gh.o.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5407</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hobbit): Delete $(CFLAGS) from link, add $(LIBS) $(LIBIBERTY).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5408</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5409</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * acconfig.h: Add HAVE_3_ARG_SCM_MAKE_VECTOR.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5410</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * config.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5411</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure.in: Add checks for libdl, libreadline, libnsl, libsocket,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5412</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        libncurses, libtermcap.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5413</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Add checks for needed functions in guile 1.2 not in guile 1.3,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5414</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        and vice versa.  Add test for 3 argument scm_make_vector.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5415</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5416</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-gh.c (scm_list_length,scm_list_append,scm_list_reverse): Provide</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5417</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        definitions if guile doesn't have them.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5418</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gh_make_vector,gh_length,gh_vector_set_x,gh_vector_ref):</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5419</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgh_vector): Replace gh_vector with gh_make_vector.  Replace gh_vset</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5420</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        with gh_vector_set_x.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5421</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgh_qsort): Replace gh_list_length with gh_length.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5422</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-gh.h: Add decls for added functions.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5423</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgh_qsort): Don't declare if IN_HOBBIT.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5424</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cos.c: Include config.h.  Replace gh_vref with gh_vector_ref,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5425</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        gh_vset with gh_vector_set_x, gh_list_length with gh_length,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5426</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        scm_make_vector with gh_make_vector.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5427</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cos.scm: Use vector-length instead of length on vectors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5428</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * dev.scm (cload): Make varargs proc with keyword/value args.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5429</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobscmif.h: Include config.h, cgen-gh.h.  Undef make_vector and</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5430</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        provide version that works with guile 1.2 or 1.3.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5431</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Include private copy of scmhob.h.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5432</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * scmhob.h: New file.  Keep our own copy for now.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5433</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5434</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Tue Mar 16 13:22:01 1999  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5435</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5436</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (-rtx-traverse-error): Ensure expression is output in</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5437</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        plain text.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5438</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-operands): Dump cx temp stack if debugging.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5439</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-cx-temp-dump-stack): Pretty up output.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5440</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5441</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * arm.cpu: comment out thumb.cpu until isa support ready.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5442</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * arm7.cpu (bl): Replace lr with (reg h-gr 14).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5443</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (f-imm12,f-offset24,swi,undef): Fix thinko, add `const'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5444</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * thumb.cpu (h-gr-t,h-lr-t,h-sp-t,dnti,h-hiregs): s/MACH/ISA/.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5445</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5446</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid-decode.scm (cgen-decode.c): Call rtl-gen-init!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5447</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5448</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-11  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5449</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5450</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (<hw-immediate>,mode-ok?): Ensure result is boolean.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5451</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>,mode-ok?): unsigned/signed are compatible.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5452</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5453</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand (op:new-mode): Improve error message.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5454</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5455</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * arm.cpu: Move arm isa into arm7.cpu.  Include arm7.cpu, thumb.cpu.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5456</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * arm7.cpu: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5457</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5458</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-12  Ben Elliston  <bje@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5459</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5460</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * arm.cpu: Lots of minor fixes after desk checking.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5461</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5462</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-11  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5463</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5464</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * thumb.cpu: snapshot of current work</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5465</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5466</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (rtx-get): Tweak error message.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5467</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5468</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-10  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5469</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5470</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (cos.o,cgen.o,cgen-gh.o): Fix dependencies.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5471</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5472</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5473</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cos.c (cos_vector_copy): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5474</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (_object_copy): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5475</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5476</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mode.scm (mode:eq?): Clean up.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5477</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (cx-new-mode): Copy attributes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5478</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-get): Don't make copy if <c-expr> with identical mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5479</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5480</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (define-arch): Delete default-insn-word-bitsize,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5481</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        add new isas spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5482</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gr-names): h-gr register names moved here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5483</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-gr): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5484</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cr-names): h-cr register names moved here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5485</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-cr): update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5486</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (dr-names): h-dr register names moved here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5487</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-dr): update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5488</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-ps): Replace FUN-ACCESS attribute with get/set specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5489</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-sbit,h-ccr,h-scr,h-ilm): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5490</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * i960.cpu (define-arch): Delete default-insn-word-bitsize,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5491</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        add new isas spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5492</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (define-arch): Delete default-insn-word-bitsize,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5493</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        add new isas spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5494</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gr-names): h-gr register names moved here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5495</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-gr): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5496</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cr-names): h-cr register names moved here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5497</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-cr): update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5498</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-accum): Replace FUN-ACCESS attribute with get/set specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5499</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-accums,h-psw): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5500</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc.cpu (define-arch): Delete default-insn-word-bitsize,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5501</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        add new isas spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5502</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gr-names): h-gr register names moved here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5503</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-gr-indices): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5504</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sparc32 h-gr): Update.  Replace FUN-ACCESS with get/set specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5505</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sparc64 h-gr): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5506</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-y): Add get/set specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5507</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (fp regs): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5508</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (fp operands): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5509</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc32.cpu (h-psr): Replace FUN-ACCESS with get/set specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5510</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-tbr,h-cwp,h-wim): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5511</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc64.cpu (h-fpsr): Add get/set specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5512</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparccom.cpu (ldd-reg+reg): Load value all at once.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5513</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (fp-ld-op): New arg `dest', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5514</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (*): Replace `make-di' with `join'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5515</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5516</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid-cpu.scm (-gen-cpu-reg-access-defns): Use get/set specs if</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5517</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        present.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5518</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-semantic-code): Save/restore rtl generator state.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5519</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-cpu.h): Call rtl-gen-init!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5520</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid.scm (-gen-ifld-extract-base): Update call to rtx-c-with-alist.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5521</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-ifld-extract-beyond): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5522</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<multi-ifield>,gen-ifld-extract): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5523</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (all gen-read,gen-write,cxmake-get,gen-set-* methods): New arg</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5524</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        `gstate'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5525</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-gen-set-quiet-pc): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5526</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-pc>,gen-write): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5527</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-cxmake-get): Ditto.  Call getter function if present.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5528</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,cxmake-get-raw): New method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5529</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,gen-set-quiet-raw): New method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5530</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-gen-set-quiet): New arg `gstate'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5531</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-fun-access?): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5532</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-reg-access-defn): Output function contents.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5533</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-index-raw): Update call to rtx-c.  Update cxmake-get</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5534</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        invocation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5535</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-index): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5536</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:read): Update gen-read invocation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5537</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:write): Update gen-write invocation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5538</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,cxmake-get,gen-set-quiet,gen-set-trace): Handle raw-reg</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5539</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        operands.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5540</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-gen-set-quiet,-op-gen-set-quiet-parallel): New arg `gstate'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5541</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-gen-set-trace,-op-gen-set-trace-parallel): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5542</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<unit>,gen-profile-code): Update to sim.scm version.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5543</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5544</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-arch.scm (-regs-for-access-fns): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5545</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-biggest-reg-mode): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5546</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-arch-reg-access-decls,-gen-arch-reg-access-defns): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5547</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (-gen-hardware-types): Output get/set handlers for</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5548</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        virtual regs separately.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5549</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-cpu-reg-access-defns): Replace fun-access? with new</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5550</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        get/set specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5551</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-semantic-code): Save/restore rtl generator state.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5552</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-cpu.h): Call rtl-gen-init!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5553</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-cpu.c): Ditto.  #include cgen-ops.h.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5554</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-model.scm: mach:cpu renamed to mach-cpu.  mach:bfd-name</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5555</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        renamed to mach-bfd-name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5556</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (-gen-ifld-extract-base): Update call to rtx-c-with-alist.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5557</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-ifld-extract-beyond): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5558</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<multi-ifield>,gen-ifld-extract): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5559</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<scalar>,gen-sym-get-macro): Update call to gen-get-macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5560</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<scalar>,gen-sym-set-macro): Update call to gen-set-macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5561</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (all gen-read,gen-write,cxmake-get,gen-set-* methods): New arg</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5562</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        `gstate'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5563</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-fun-access?): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5564</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-gen-set-quiet-pc): New arg `gstate'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5565</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,gen-get-macro): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5566</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,gen-set-macro): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5567</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-gen-fun-get,-hw-gen-fun-set): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5568</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-cxmake-get): New arg `gstate'.  Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5569</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,cxmake-get-raw): New method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5570</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-gen-set-quiet): New arg `gstate'.  Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5571</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,gen-set-quiet-raw): New method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5572</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-index-raw): Update call to rtx-c.  Update cxmake-get</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5573</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        invocation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5574</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-index): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5575</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-index>): New arg `gstate'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5576</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-selector): Update call to rtx-c.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5577</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<pc>): New arg `gstate'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5578</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:read): Update gen-read invocation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5579</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:write): Update gen-write invocation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5580</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,cxmake-get): Handle raw-reg.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5581</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-gen-set-quiet,-op-gen-set-quiet-parallel): New arg `gstate'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5582</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-gen-set-trace,-op-gen-set-trace-parallel): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5583</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,gen-set-quiet): Handle raw-reg.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5584</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,gen-set-trace): Handle raw-reg.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5585</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-mach-data): mach:cpu renamed to mach-cpu.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5586</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5587</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * desc-cpu.scm (gen-operand-decls): Take nub of operands for</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5588</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        cgen_operand_type enum.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5589</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-operand-table): Add operand type enum.  Replace pointer to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5590</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        hardware element with its enum.  Null terminate table.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5591</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-cpu-open): Add new `isa' argument to @arch@_cgen_cpu_open.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5592</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Build operand table.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5593</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (-ifield-parse): Recognize ISA attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5594</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (<arch-data>): New member `isas'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5595</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (adata-isas): New accessor.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5596</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<isa>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5597</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (isa-default-insn-word-bitsize): New accessor.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5598</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (isa-enum): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5599</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-arch-default-insn-word-bitsize): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5600</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-isa-list,current-isa-lookup): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5601</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-arch-parse-isa): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5602</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-arch-parse): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5603</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-arch-read): Recognize `isas'.  Delete `default-insn-word-bitsize'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5604</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-arch): Define ISA attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5605</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-isa-attr!,isa-supports?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5606</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<mach>): New member `isas'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5607</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mach-isas): New accessor.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5608</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-mach-parse): New arg `isas', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5609</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-mach-read): Recognize `isas'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5610</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (arch-finish!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5611</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opc-ibld.scm (-gen-fget-switch): Add `cd' arg to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5612</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        @arch@_cgen_get_{int,vma}_operand.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5613</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-fset-switch): Add `cd' arg to @arch@_cgen_set_{int,vma}_operand.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5614</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opc-opinst.scm (-gen-operand-instance): Output operand enum instead</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5615</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        of pointer to table entry.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5616</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (gen-switch): Handle multiply defined operands.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5617</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (op-sort): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5618</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5619</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (<hardware-base>): Rename getters/setters to get/set.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5620</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-getter,hw-setter): Renamed from hw-getters,hw-setter.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5621</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-enum): Accept symbol argument.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5622</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hardware-builtin!): Delete attribute FUN-ACCESS.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5623</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (ifld-encode-mode,ifld-decode-mode): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5624</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5625</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * attr.scm (atlist-source-form): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5626</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (attr-builtin!): New attr `PRIVATE'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5627</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * desc.scm (<keyword>,gen-defn): Make keyword entry table static.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5628</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * desc-cpu.scm (-gen-hw-defn): Only output index and value tables</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5629</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        if they have `PRIVATE' attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5630</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-hw-table-defns): Output definitions of explicitly defined</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5631</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        keyword tables.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5632</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (<keyword>): New member print-name.  Rename member</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5633</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        `value' to `values', all uses updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5634</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (kw-mode,kw-print-name,kw-prefix,kw-values): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5635</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (keyword-parse): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5636</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-keyword-read): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5637</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-keyword): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5638</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-parse-keyword): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5639</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-parse-indices): Rewrite keyword handling, support new index spec</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5640</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        `extern-keyword'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5641</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-parse-values): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5642</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-parse-get,-hw-parse-set): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5643</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hardware-init!): Add new comment define-keyword.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5644</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (<arch>): New member `kw-list'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5645</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (arch:kw-list,arch_set-kw-list!): New accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5646</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-kw-list,current-kw-add!,current-kw-lookup): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5647</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5648</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (<hw-register>,mode-ok?): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5649</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mode.scm (mode-class-integral?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5650</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode-class-float?,mode-class-numeric?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5651</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode-integral?,mode-float?,mode-numeric?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5652</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode-compatible?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5653</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (<ifield>,gen-insert): Update alist arg to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5654</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        rtx-c-with-alist.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5655</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>,gen-extract): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5656</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (-rtl-simulator?,-rtx-current-obj): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5657</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<gstate>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5658</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gstate-simulator?,gstate-set-simulator?!): New accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5659</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gstate-context,gstate-set-context!): New accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5660</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gstate-macro?,gstate-set-macro?!): New accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5661</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gstate-make,gstate-copy): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5662</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtl-current-gstate): New global.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5663</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-gstate-simulator?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5664</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-gstate-context,current-gstate-macro?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5665</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-gstate,current-gstate-set!): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5666</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtl-gen-init!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5667</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-valid-types): Add INTMODE, FLOATMODE, NUMMODE.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5668</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (tstate-make): New arg `gstate', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5669</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (tstate-set-expr-fn!,tstate-set-op-fn!): New accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5670</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (tstate-set-cond?!,tstate-set?,tstate-set-set?!): New accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5671</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (tstate-gstate,tstate-set-gstate!): New accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5672</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (tstate-copy): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5673</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (tstate-new-cond?,tstate-new-set?): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5674</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-operands): Handle INTMODE, FLOATMODE, NUMMODE.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5675</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-traverse): New arg `gstate', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5676</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-strdump): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5677</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-simplify-for-compilation): New arg `gstate', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5678</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (semantic-in-out-operands): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5679</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (semantic-attrs): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5680</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-eval): Rewrite.  New arg `gstate', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5681</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-eval-with-temps,rtx-eval-with-alist): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5682</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-value): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5683</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr>,gen-name): New method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5684</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr>,gen-set-quiet): New arg `gstate', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5685</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr>,gen-set-trace): New arg `gstate', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5686</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cx-new-mode): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5687</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-c-with-tstate): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5688</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-c,rtx-c-with-temps,rtx-c-with-alist): New arg `gstate', all</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5689</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5690</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-mode): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5691</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-mode-compatible?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5692</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr-temp>): New member `value'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5693</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cx-temp:value): New accessor.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5694</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr-temp>,make!): Override default method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5695</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr-temp>,cxmake-get): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5696</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr-temp>,gen-set-quiet): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5697</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr-temp>,gen-set-trace): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5698</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-temp-defs): Use cx-temp:value.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5699</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (record-temp!): New arg value, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5700</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cx-temp:cx:make): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5701</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-cx-temp-dump-stack): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5702</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-get): New arg `gstate', all callers updated.  Do mode</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5703</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        compatibility checks.  Ensure result has specified mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5704</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-set-quiet): New arg `gstate', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5705</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-set-trace): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5706</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-c-call): New arg `tstate', all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5707</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-c-raw-call): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5708</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-unop,s-binop,s-binop-with-with,s-shop,s-boolifop,s-convop): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5709</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-cmpop,s-if,e-if): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5710</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-subreg): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5711</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-par-new-temp!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5712</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-par-next-temp!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5713</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-par-replace-set-dests): Use -par-new-temp!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5714</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-parallel): Rewrite temp handling.  Use -rtx-c-with-state.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5715</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-sequence): Use -rtx-c-with-state.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5716</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (*): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5717</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (raw-reg:): New rtx function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5718</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (make-di): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5719</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (join:,subreg:): New rtx functions.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5720</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5721</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (<insn>): New members pre-cond-trap, condition,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5722</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        post-cond-trap, compiled-condition.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5723</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5724</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (syntax-break-out): Replace eval with current-op-lookup.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5725</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5726</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (<pc>,cxmake-get): New arg `selector'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5727</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5728</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (parse-symbol): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5729</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse-string): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5730</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-get-macro,gen-set-macro): New arg `index-args'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5731</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-set-macro2): Ditto.  Enclose code in do { } while (0).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5732</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Prepend \ to newlines.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5733</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5734</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (alist-remove-duplicates): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5735</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5736</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid.scm (sim-init!): Delete private debugging code.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5737</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5738</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-10  Frank Ch. Eigler  <fche@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5739</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5740</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-sid.scm: New file for C++ simulator application.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5741</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid-arch.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5742</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid-cpu.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5743</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid-decode.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5744</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid-model.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5745</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sid.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5746</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (gen-mach-sid-name): Remove this accident.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5747</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5748</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-05  Ben Elliston  <bje@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5749</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5750</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * arm.cpu: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5751</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5752</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-03  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5753</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5754</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (CGEN_HOB_INPUT_FILES): Add hardware.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5755</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5756</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5757</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * attr.scm (<integer-attribute>,parse-value-def): Tweak.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5758</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-attr-parse): Validate default value.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5759</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5760</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * read.scm (-CGEN-VERSION): Change to 0.7.1.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5761</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-CGEN-LANG-VERSION): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5762</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-keep-all-machs): Renamed from -keep-all, all uses updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5763</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<reader>): New member keep-isa plus accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5764</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-keep-isa-set!,keep-isa-validate!): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5765</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (keep-isa?,keep-isa-atlist?,keep-isa-obj?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5766</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (common-arguments): New variable.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5767</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-usage,getarg,catch-with-backtrace,option-arg): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5768</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-debug-repl,continue): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5769</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-cgen,cgen): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5770</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-gas.scm: Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5771</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-opc.scm: Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5772</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-sim.scm: Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5773</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-stest.scm: Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5774</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5775</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * gas-test.scm (gas-test-init!): Call opcodes-init!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5776</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gas-test-finish!): Call opcodes-finish!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5777</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gas-test-analyze!): Call opcodes-analyze!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5778</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>): New method test-data.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5779</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,testdata): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5780</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-test.scm (sim-test-init!): Call opcodes-init!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5781</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sim-test-finish!): Call opcodes-finish!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5782</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sim-test-analyze!): Call opcodes-analyze!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5783</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>): New method test-data.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5784</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,testdata): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5785</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5786</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-03-01  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5787</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5788</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fixup.scm (reverse!): Define if missing.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5789</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * *.scm: Use reverse! instead of list-reverse!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5790</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5791</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (leading-id-char?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5792</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (id-char?): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5793</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (chars-until-delimiter): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5794</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opc-itab.scm (extract-syntax-operands): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5795</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (strip-mnemonic): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5796</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (compute-syntax): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5797</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5798</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * pmacros.scm (-pmacro-substr): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5799</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (pmacros-init!): Add builtin .substr.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5800</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5801</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-02-26  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5802</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5803</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * thumb.cpu: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5804</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5805</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-02-24  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5806</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5807</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (CGENCFLAGS): New variable.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5808</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (WITH_HOBBIT): Use automake conditional.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5809</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (CGEN_HOB_SRC): New variable.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5810</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (libcpu_a_SOURCES): Use $(CGEN_HOB_SRC).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5811</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (*.o): Compile with CGENCFLAGS.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5812</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-hob.c): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5813</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-nohob.c): New rule.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5814</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hobbit): Renamed from hob.x.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5815</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (CLEANFILES): Add cgen-nohob.c.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5816</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5817</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5818</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure.in (AM_INIT_AUTOMAKE): Update CGEN version to 0.7.1.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5819</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (WITH_HOBBIT): Use AM_CONDITIONAL.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5820</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5821</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * aclocal.m4: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5822</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5823</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-arch.scm (-gen-arch-reg-access-defns): Replace string-map</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5824</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        with string-write-map.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5825</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5826</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (hw-need-storage?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5827</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hardware-types): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5828</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-parallel-exec-elm): Call op-save-index?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5829</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5830</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (cgen-decode.c): Call rtl-gen-init!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5831</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5832</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (-gen-ifld-extract-base): Use mode:class instead of</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5833</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        UNSIGNED attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5834</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-ifld-extract-beyond): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5835</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<integer>): Delete all references.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5836</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<sim-hardware>): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5837</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-profilable?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5838</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hardware-base>): New methods gen-get-macro,gen-set-macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5839</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>): Rename method get-index-mode to save-index?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5840</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>): New methods gen-get-macro,gen-set-macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5841</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,gen-sym-decl): Make virtual.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5842</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>,gen-sym-decl): Make virtual.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5843</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>): Rename method get-index-mode to save-index?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5844</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>,gen-sym-decl): Make virtual.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5845</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>): New method save-index?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5846</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sim-init!): Delete calls to sim-hw-init!,sim-hw-init-parsers!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5847</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5848</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opc-itab.scm (opc-{parse,insert,extract,print}-handlers): opc-</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5849</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        prefix added.  All uses updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5850</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5851</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opc-opinst.scm (-gen-operand-instance): Output hw enum value</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5852</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        rather than pointer to table entry.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5853</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5854</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm: Remove all attribute support, lives in desc.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5855</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Remove all hw-asm,op-asm support.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5856</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-parse-number,-gen-parse-address): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5857</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<keyword>,gen-parse): Redo function name computation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5858</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<keyword>,gen-print): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5859</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,gen-function-name): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5860</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,gen-fget,gen-fset,gen-parse,gen-print): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5861</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (opcodes-init!): Delete call to add-parser!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5862</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5863</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * desc-cpu.scm (gen-hw-decls): Rename enum hw_type to cgen_hw_type.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5864</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Define enum using hardware semantic name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5865</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-decl,-gen-hw-defn): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5866</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-hw-table-decls): Use -gen-hw-decl.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5867</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-hw-table-defns): Use -gen-hw-defn.  Rewrite generation of</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5868</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        CGEN_HW_ENTRY structs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5869</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-operand-table): Output hw's enum, not pointer to table entry.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5870</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-cpu-open): Build table of selected hardware elements.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5871</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5872</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * desc.scm (-hw-asm-specs,-parse-hw-asm): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5873</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hardware> support): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5874</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>): Delete, moved to hardware.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5875</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (normal-hw-asm,hw-asm:parse,hw-asm:print): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5876</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>,gen-table-entry): New method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5877</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>,parse!): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5878</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<keyword>,gen-table-entry): New method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5879</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<keyword>,parse!): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5880</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-{register,memory,immediate,address}>): Delete forwarding methods</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5881</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        for gen-decl,gen-defn,gen-ref,gen-init.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5882</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (desc-init!): Don't create parser for operand asm specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5883</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5884</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * attr.scm (attr-builtin!): Delete UNSIGNED attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5885</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (<ifield>): New member `mode'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5886</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>,make!): New arg `mode'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5887</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifld-mode): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5888</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifld-hw-type): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5889</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>,min-value): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5890</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>,max-value): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5891</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-ifield-parse): New arg `mode'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5892</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-ifield-read): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5893</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-full-ifield): New arg `mode'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5894</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-full-multi-ifield): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5895</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-multi-ifield-parse): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5896</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-multi-ifield-read): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5897</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-full-multi-ifield): New arg `mode'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5898</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifield-builtin!): Update definition of f-nil.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5899</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * simplify.inc (define-normal-ifield): Update call to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5900</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        define-full-ifield.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5901</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-normal-multi-ifield): Update call to define-full-multi-ifield.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5902</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-normal-hardware): Delete arg asm.  New args indices, values,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5903</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        handlers.  Update call to define-full-hardware.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5904</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-simple-hardware,dsh): New pmacros.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5905</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-normal-operand): Update call to define-full-operand.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5906</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (f-*): Delete UNSIGNED attribute.  Default is now UNSIGNED.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5907</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Specify INT/UINT mode instead.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5908</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-gr,h-cr): Use "indices" instead of "asm".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5909</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-dr,h-ps): Update keyword syntax.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5910</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-r13,h-r14,h-r15): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5911</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-nbit,h-zbit,h-vbit,h-cbit): Use dsh instead of dnh.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5912</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-d0bit,h-d1bit,h-ibit,h-sbit,h-tbit,h-ccr,h-scr,h-ilm): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5913</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (m4): Fix typo on HASH-PREFIX.  Use "handlers" instead of "asm".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5914</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (reglist_low_ld,reglist_hi_ld,reglist_low_st,reglist_hi_st): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5915</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * i960.cpu (f-*): Delete UNSIGNED attribute.  Default is now UNSIGNED.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5916</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Specify INT/UINT mode instead.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5917</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-gr): Use "indices" instead of "asm".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5918</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-cc): Update keyword syntax.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5919</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (f-*): Delete UNSIGNED attribute.  Default is now UNSIGNED.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5920</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Specify INT/UINT mode instead.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5921</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-hi16,h-slo16,h-ulo16): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5922</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-gr,h-cr): Use "indices" instead of "asm".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5923</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-accum,h-cond,h-psw,h-bpsw,h-bbpsw,h-lock): Use dsh instead of dnh.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5924</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-accums): Update keyword syntax.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5925</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hash,hi16,slo16,ulo16): Use "indices" instead of "asm".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5926</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc.cpu (f-*): Delete UNSIGNED attribute.  Default is now UNSIGNED.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5927</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Specify INT/UINT mode instead.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5928</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-gr-indices): New pmacro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5929</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-gr32,h-gr64): Split up from h-gr.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5930</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-a): Update type spec.  Use values instead of asm spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5931</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-icc-[cnvz],h-xcc-[cnvz]): Use dsh instead of dnh.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5932</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-y,h-annul-p): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5933</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-asr): Update keyword spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5934</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-lo10,h-lo13,h-hi22): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5935</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (get-freg-spec,set-freg-spec): New pmacros.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5936</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-fr32,h-fr64): Split up from h-fr.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5937</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rdd): Comment out get/set specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5938</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (lo10,lo13,hi22): Use "handlers" instead of "asm".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5939</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc32.cpu (h-psr): Use dsh instead of dnh.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5940</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-s,h-ps,h-pil,h-et,h-tbr,h-cwp,h-ag,h-ec,h-ef,h-fsr): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5941</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc64.cpu (f-*): Delete UNSIGNED attribute.  Default is now</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5942</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        UNSIGNED.  Specify INT/UINT mode instead.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5943</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-*): Use dsh instead of dnh where appropriate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5944</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-ixcc): Update type spec.  Use "values" instead of "asm".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5945</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-p,h-membarmask): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5946</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (membarmask): Use "handlers" instead of "asm".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5947</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5948</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (<hardware-base>): New member sem-name,type,indices,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5949</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        values,handlers,getters,setters plus accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5950</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-mode-ok?,hw-default-mode): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5951</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hardware-base>): Rename method new-mode to mode-ok?</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5952</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hardware-base>): New method get-index-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5953</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-index-mode): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5954</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (pc?): Delete, moved to operand.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5955</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (address?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5956</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hardware>): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5957</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>): Definition moved here from desc.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5958</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (keyword-parse): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5959</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hardware-parsers): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5960</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-parse-hw-type,-parse-hw-asm,-parse-hw-profile): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5961</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-parse-indices,-hw-parse-values,-hw-parse-handlers): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5962</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-parse-get,-hw-parse-set): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5963</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-parse): Delete args aasm,profile,extra.  New args semantic-name,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5964</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        indices,values,handlers,get,set.  Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5965</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-read-extra): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5966</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-read): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5967</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-hardware): Don't add object if not selected.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5968</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-full-hardware): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5969</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-hw-sem-lookup,current-hw-sem-lookup-1): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5970</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>): Member `type' moved to baseclass.  Delete member</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5971</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        hw-asm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5972</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,parse!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5973</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>): Delete methods get-rank,get-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5974</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>): Method new-mode renamed to mode-ok?</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5975</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>): New method get-index-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5976</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-pc>,parse!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5977</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>): Member `type' moved to baseclass.  Delete member hw-asm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5978</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>,parse!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5979</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>): Delete methods get-rank,get-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5980</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>): Method new-mode renamed to mode-ok?</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5981</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>): New method get-index-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5982</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-immediate>): Member `type' moved to baseclass.  Delete member</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5983</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        hw-asm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5984</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-immediate>,parse!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5985</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-immediate>): Delete methods get-rank,get-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5986</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-immediate>): Method new-mode renamed to mode-ok?</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5987</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>): Delete member hw-asm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5988</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>,parse!): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5989</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>): Delete methods get-rank,get-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5990</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>): Method new-mode renamed to mode-ok?</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5991</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-profilable?): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5992</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hardware-init!): Delete hardware-parsers reference.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5993</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Update argument specs of command define-full-hardware.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5994</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hardware-builtin!): Update definitions of hardware builtins.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5995</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (<operand>): New members hw-name,mode-name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5996</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Delete member op-asm.  New member handlers.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5997</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,make!): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5998</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:hw-name,op:mode-name,op:handlers): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>5999</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:type): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6000</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:mode): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6001</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>): New method get-index-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6002</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<pc>,make!): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6003</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:new-mode): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6004</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (operand-parsers): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6005</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-operand-parse): Rewrite.  Return #f if insn not selected.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6006</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-read-extra): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6007</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-operand-read): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6008</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-operand,define-full-operand): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6009</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (operand-init!): Delete operand-parsers reference.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6010</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Update syntax of define-full-operand command.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6011</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6012</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (-insn-parse): Rewrite.  Return #f if insn not selected.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6013</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-full-insn): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6014</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * minsn.scm (-minsn-parse): Rewrite.  Return #f if insn not selected.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6015</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-full-minsn): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6016</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6017</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mode.scm (<mode>): New member class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6018</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode:class): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6019</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode?): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6020</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-mode-parse): New arg class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6021</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-full-mode): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6022</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode-find): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6023</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode-make-int,mode-make-uint): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6024</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode-init!): Update syntax of define-full-mode command.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6025</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode-builtin!): Update definitions of builtin modes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6026</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6027</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * model.scm (<profile>): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6028</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6029</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * read.scm (keep-atlist?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6030</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (keep-multiple?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6031</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<parser-list>): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6032</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (add-parser!,parse-spec!): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6033</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6034</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (def-rtx-node): Prepend arg *tstate* to all handlers.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6035</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-rtx-syntax-node): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6036</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-debug?): New variable.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6037</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (tstate-make): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6038</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (tstate-expr-fn,tstate-op-fn,tstate-cond?,tstate-set?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6039</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (tstate-new-cond?,tstate-new-set?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6040</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-normal): Delete args cond?,expr-fn,op-fn.  New arg</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6041</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        tstate.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6042</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-expr,-rtx-traverse-debug): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6043</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-list,-rtx-traverse-operands): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6044</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-build-operand!): Replace arg cond? with tstate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6045</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-build-reg-operand!,-build-mem-operand!): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6046</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-build-index-of-operand!): Update making of <operand> object.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6047</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-ifield): New arg tstate.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6048</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw:): New arg tstate.  All callers updated.  Replace call to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6049</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        current-hw-lookup with current-hw-sem-lookup-1.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6050</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-index-of): New arg tstate.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6051</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (reg:,mem:): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6052</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-use-sem-fn?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6053</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-unop,s-binop,s-shop): Use it.  Only use semantic mode when using</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6054</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        semantic cover fns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6055</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-convop): Only use semantic mode when using semantic cover fns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6056</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-cmpop): Call -rtx-use-sem-fn?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6057</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-cond,s-case): New arg tstate.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6058</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-parallel,s-sequence): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6059</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6060</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (set,set-quiet:): Use SETRTX to mark the set dest.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6061</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6062</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * types.scm (<scalar>): Rewrite implementation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6063</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<integer>): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6064</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse-type): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6065</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6066</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (parse-handlers): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6067</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6068</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (!=): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6069</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6070</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Tue Feb 23 12:10:29 1999  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6071</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6072</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * pmacros.scm (-pmacro-expand): Fix typo.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6073</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6074</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-02-12  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6075</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6076</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * pmacros.scm (-pmacro-hex,-pmacro-upcase,-pmacro-downcase): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6077</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (pmacros-init!): Install builtins .hex, .upcase, .downcase.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6078</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * i960.cpu (build-hex2): New pmacro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6079</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn-opcode): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6080</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn-opcode2): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6081</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6082</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-sim.scm (catch-with-backtrace): Comment out debugging printf.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6083</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-stest.scm (catch-with-backtrace): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6084</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6085</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-02-11  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6086</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6087</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * pmacros.scm (-pmacro-lookup): Renamed from -pmacro-ref.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6088</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6089</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-pmacro-invoke): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6090</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-pmacro-sym,-pmacro-str): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6091</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-pmacro-iota,-pmacro-map,-pmacro-apply): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6092</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (pmacros-init!): Install builtins .iota, .map, .apply.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6093</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc.cpu (cc-tests): Add CC_NZ,CC_Z,CC_GEU,CC_LU aliases.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6094</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-fr): Simplify register name spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6095</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc64.cpu (cond-move-1): New arg mnemonic.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6096</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (num-args-ok?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6097</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6098</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-02-10  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6099</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6100</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * pmacros.scm (-pmacro-error): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6101</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-pmacro-expand): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6102</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-pmacro-splice): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6103</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (pmacros-init!): Install new builtin .splice.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6104</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6105</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc.cpu: Include sparc64.cpu when appropriate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6106</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (f-mmask,f-simm11): Moved to sparc64.cpu.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6107</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn-fmt2): Add FLUSH,FLUSHW,IMPDEP1,IMPDEP2,MEMBAR,MOVCC.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6108</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ANNUL attribute): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6109</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (test-* pmacros): New arg cc, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6110</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (uncond-br-sem,cond-br-sem): New arg cc, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6111</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc32.cpu (atom-op): Moved to sparccom.cpu and renamed to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6112</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        atomic-opc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6113</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ldstub,swap): Moved to sparccom.cpu.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6114</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc64.cpu: Add more insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6115</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6116</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-02-09  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6117</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6118</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (cgen-semantics.c): Replace CGEN_INSN_ATTR with</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6119</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        CGEN_ATTR_VALUE.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6120</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-sem-switch.c): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6121</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (-gen-idesc-decls): struct idesc definition</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6122</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        moved to cgen-engine.h.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6123</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-insn-sem-type): Delete, struct insn_sem mvoed to cgen-engine.h.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6124</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-idesc-init-fn,init_idesc): Lookup insn table via descriptor, not</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6125</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        global.  Cache attributes and insn length in IDESC.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6126</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-model.scm (-gen-cpu-defns): Generate new func @cpu@_prepare_run.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6127</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        @cpu@_opcode renamed to @cpu@_get_idata.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6128</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-mach-defns,@mach@_init_cpu): Don't initialize IDESC table here,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6129</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        done later underneath sim_resume.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6130</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (@mach@_mach): Record @cpu@_prepare_run.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6131</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<hardware-base>,cxmake-get): New arg selector, all callers</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6132</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6133</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-gen-set-quiet-pc): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6134</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-cxmake-get,-hw-gen-set-quiet): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6135</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>,cxmake-get,gen-set-quiet): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6136</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-addr>,cxmake-get): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6137</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-iaddr>,cxmake-get): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6138</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<pc>,cxmake-get): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6139</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,cxmake-get,gen-set-quiet,gen-set-trace): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6140</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-gen-set-quiet,-op-gen-set-quiet-parallel): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6141</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-gen-set-trace,-op-gen-set-trace-parallel): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6142</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-pc>,gen-write): Use hw-selector-default.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6143</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,gen-write): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6144</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>,gen-write): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6145</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-index-raw,-gen-hw-index): Handle selector.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6146</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-selector): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6147</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6148</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * desc.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6149</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * desc-cpu.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6150</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm: Split up into several smaller files.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6151</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opc-asmdis.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6152</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opc-ibld.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6153</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opc-itab.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6154</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opc-opinst.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6155</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (desc): New target.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6156</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (opcodes): Update args to cgen-opc.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6157</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6158</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * aclocal.m4: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6159</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * config.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6160</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure.in: Update arg to AC_INIT.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6161</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Update version number to 0.7.0.  Change AM_EXEEXT to AC_EXEEXT.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6162</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Update AC_PREREG arg to 2.13.  Change AM_PROG_INSTALL to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6163</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        AC_PROG_INSTALL.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6164</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6165</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-gas.scm: Update files to load.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6166</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-opc.scm: Ditto.  Reorganize option letters.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6167</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-sim.scm: Update files to load.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6168</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-stest.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6169</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * dev.scm (cload): New app "DESC".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6170</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (load-opc): Update files to load.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6171</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (load-gtest,load-sim,load-stest): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6172</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6173</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * attr.scm (bool-attr?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6174</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (attr-list-enum-list): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6175</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-attr-sort): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6176</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (attr-builtin!): Give ALIAS attribute a fixed index.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6177</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (gen-attr-enum-decl): Call attr-list-enum-list to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6178</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        calculate attribute enum list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6179</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-attr-mask): Subtract CGEN_ATTR_BOOL_OFFSET from attribute's enum.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6180</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6181</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (-insn-parse): Renamed from parse-insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6182</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6183</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (-hw-parse): New arg errtxt, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6184</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-read): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6185</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6186</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mode.scm (-mode-parse): Renamed from parse-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6187</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6188</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (<operand>): New member `selector'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6189</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,make!): Use default selector.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6190</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-selector-default): New variable.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6191</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-selector-default?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6192</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6193</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * pmacros.scm (pmacros-init!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6194</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-pmacro-{make,name,arg-spec,transformer,comment}): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6195</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-env-set!): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6196</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-pmacro-expand): New proc apply-macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6197</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Use it in scan-list,scan.  Scan list first, then see if macro</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6198</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        invocation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6199</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-pmacro): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6200</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * read.scm (-init-parse-cpu!): Call utils-init!,parse-init!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6201</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6202</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (-simplify-for-compilation): Ensure at least one mach</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6203</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        selected if (current-mach) seen.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6204</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx?): Renamed from rtx-uneval?, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6205</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr>,gen-set-quiet,gen-set-trace): New arg selector, all callers</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6206</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6207</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<c-expr-temp>,cxmake-get,gen-set-quiet,gen-set-trace): New arg</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6208</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        selector, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6209</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw:): New arg selector, all callers updated.  Delete old comments</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6210</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        and code.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6211</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (reg:,mem:): Handle selectors</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6212</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (reg:): Handle selectors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6213</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6214</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * read.scm: Renamed from cpu.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6215</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<command>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6216</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<reader>): New member commands.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6217</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (reader-add-command!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6218</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (reader-lookup-command): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6219</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (reader-error,-reader-process-expanded,reader-process): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6220</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (reader-read-file!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6221</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (include): Call reader-read-file!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6222</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cmd-if): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6223</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cpu-load): Call reader-read-file!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6224</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (num-args): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6225</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * simplify.inc: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6226</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * *.scm: Delete def-foo procs.  Rewrite define-foo/define-full-foo</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6227</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        procs.  Move define-normal-foo procs (and abbreviated forms) to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6228</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        simplify.inc.  Install define-foo/define-full-foo commands in foo-init!</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6229</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        routines.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6230</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu: Include simplify.inc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6231</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc: CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6232</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * i960.cpu: Include simplify.inc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6233</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu: Include simplify.inc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6234</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.opc: CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6235</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (CGEN_PRINT_NORMAL): Use CGEN_BOOL_ATTR.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6236</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc.cpu: Include simplify.inc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6237</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc.opc: CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6238</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (parse-error): Moved to read.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6239</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sanitize): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6240</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (utils-init!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6241</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6242</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-02-02  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6243</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6244</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc.cpu: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6245</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc32.cpu: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6246</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc64.cpu: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6247</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparccom.cpu: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6248</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sparc.opc: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6249</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6250</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-27  Frank Eigler  <fche@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6251</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6252</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (gen-copyright): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6253</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6254</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-27  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6255</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6256</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Parameterize rtl parsing, rather than having lots of little handlers.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6257</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (<rtx-func>): New members arg-types,arg-modes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6258</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Delete member traverse.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6259</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx:set-traverse!): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6260</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-valid-types,-rtx-valid-matches): New variables.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6261</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-func-lookup): Take symbol or <rtx-func> object as argument</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6262</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        instead of expression.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6263</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-rtx-node): New args arg-types,arg-modes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6264</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-rtx-syntax-node): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6265</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-rtx-dual-mode): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6266</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-macro-expand-list): Renamed from -rtx-macro-maybe-expand-list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6267</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6268</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-macro-expand): Renamed from -rtx-macro-maybe-expand.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6269</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6270</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-macro-expand): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6271</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-check-args): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6272</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-normal): Call -rtx-traverse-expr rather than calling</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6273</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        an rtx specific traverser.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6274</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-any-mode?,-rtx-symornum?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6275</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-rtx-list,-rtx-traverse-error): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6276</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-no-mode): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6277</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-syntax-expr,-rtx-traverse-syntax-no-mode): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6278</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-operands): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6279</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-expr): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6280</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-traverse): Don't expand macros here, leave for caller to do.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6281</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-simplify): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6282</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-compile-time-constant?): Rewrite.  Handle FALSE/TRUE for boolean</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6283</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        attributes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6284</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-true?,rtx-false?): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6285</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-ref-type): Set dest is operand 1 now.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6286</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-simplify-for-compilation): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6287</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (semantic-in-out-operands): Recognize regno as an alias for index-of.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6288</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Expand macros before calling rtx-traverse.  Sort operands by name</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6289</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        to avoid unnecessary semantic formats.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6290</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (semantic-attrs): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6291</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-uneval?): Handle (<rtx-func> ...).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6292</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-boolifop): Delete arg mode.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6293</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (all non-macros): Add arg-type and arg-mode specs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6294</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (eq-attr): New arg obj.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6295</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (eq-attr:): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6296</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (rach): Update calls to andif.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6297</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6298</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * minsn.scm (-minsn-parse-expansion): Renamed from</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6299</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        parse-minsn-expansion.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6300</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-minsn-parse): Renamed from parse-minsn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6301</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-minsn-read): Renamed from read-minsn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6302</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-minsn): Don't check APPLICATION here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6303</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-full-minsn): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6304</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-macro-insn): Check APPLICATION here.  Expand macros.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6305</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-normal-macro-insn): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6306</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6307</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (word-value): New arg start-lsb?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6308</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (word-mask,word-extract): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6309</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (split-bits,powers-of-2): Use integer-expt instead of expt.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6310</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (bit-set?): Handle 32 bit values (which are bignums).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6311</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cg-logand,cg-logxor): New functions.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6312</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (<ifield>,field-mask): Update call to word-mask.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6313</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>,field-value): Update call to word-value.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6314</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>,min-value): Use integer-expt instead of expt.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6315</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>,max-value): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6316</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6317</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (<hw-register>,new-mode): Rename local mode to cur-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6318</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6319</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (def-full-insn): Discard ALIAS insns if simulator.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6320</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6321</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Compute raw instruction format in addition to semantic based format.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6322</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * iformat.scm: Delete members cti?,sem-in-ops,sem-out-ops.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6323</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<iformat> accessors): Rename accessors to ifmt-*.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6324</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<sformat>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6325</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (fmt-enum): Renamed from fmt:enum.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6326</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-ifmt-search-key): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6327</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-sfmt-search-key): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6328</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifmt-analyze): Rename arg include-sem-operands? to compute-sformat?</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6329</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Compute iformat and sformat search keys.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6330</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifmt-build): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6331</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sfmt-build): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6332</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-ifmt-lookup-ifmt!,-ifmt-lookup-sfmt!): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6333</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifmt-compute!): Compute instruction format <iformat> based on</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6334</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        instruction fields alone.  Compute new semantic format <sformat></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6335</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        based on instruction fields and semantic information.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6336</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifmt:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6337</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (<arch>): New member sfmt-list, plus accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6338</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-sfmt-list): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6339</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (<insn>): Rename member fmt-tmp to tmp.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6340</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Rename member fmt to ifmt.  New members fmt-desc, sfmt.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6341</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn-length,insn-length-bytes): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6342</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn:mask-length,insn:mask): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6343</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn-lookup-op): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6344</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * gas-test.scm (gas-test-analyze!): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6345</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-gas-test): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6346</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-test.scm (sim-test-analyze!): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6347</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-sim-test): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6348</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (gen-operand-instance-table): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6349</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-operand-instance-ref): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6350</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (max-operand-instances): Use heuristic if semantics not parsed.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6351</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifmt-opcode-operands): Renamed from fmt-opcode-operands.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6352</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (opcodes-analyze!): Only scan semantics of building operand instance</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6353</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        tables.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6354</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (*) Update calls to <iformat>/<sformat> accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6355</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-extract-ifmt-macro): Renamed from -gen-extract-fmt-macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6356</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (*) Update calls to <iformat>/<sformat> accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6357</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-sfmt-argvars-defns): Renamed from gen-ifmt-argvars-defns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6358</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-sfmt-argvars-assigns): Renamed from gen-ifmt-argvars-assigns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6359</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-model.scm (*) Update calls to <iformat>/<sformat> accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6360</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (*) Update calls to <iformat>/<sformat> accessors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6361</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6362</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (usable-decode-bit?): Rename from decode-bit?</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6363</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        New arg lsb0?  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6364</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (decode-bits): New arg lsb0?.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6365</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (opcode-slots): Update call to bit-set?.  Call integer-expt instead</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6366</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        of expt.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6367</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-decode-bits): New arg lsb0?.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6368</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (build-slots): Call integer-expt instead of expt.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6369</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (build-decode-table-entry): Handle crossing word boundaries better.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6370</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-decode-switch): New arg lsb0?.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6371</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-extract-decls): Rename decode format entry from ifmt to sfmt.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6372</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6373</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * enum.scm (define-enum): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6374</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-normal-enum): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6375</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-full-insn-enum): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6376</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-normal-insn-enum): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6377</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6378</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * attr.scm (<bitset-attribute>,gen-value-for-defn): Ensure result is</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6379</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        valid C.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6380</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<{integer,enum}-attribute>,gen-value-for-defn): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6381</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6382</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * dev.scm: Add sid support.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6383</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6384</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (opcodes,sim-arch,sim-cpu): New targets.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6385</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (CLEANFILES): Add tmp-*.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6386</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6387</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6388</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/Makefile.am: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6389</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/Makefile.in: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6390</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/cgen.texi: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6391</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (SUBDIRS): Define.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6392</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6393</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure.in: Create doc/Makefile.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6394</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6395</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6396</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-18  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6397</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6398</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (insn:syn): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6399</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6400</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-15  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6401</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6402</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (model fr30-1): Add state variables load-regs,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6403</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        load-regs-pending.  Delete h-gr.  Clean up operand names of all units.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6404</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (model m32r/d): Clean up operand names of u-exec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6405</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (model m32rx): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6406</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (addi): Simplify function unit usage spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6407</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ld-plus): Rewrite operand names in function unit usage spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6408</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mvtachi,mvtachi-a,mvtaclo,mvtaclo-a,st-plus,st-minus): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6409</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<unit>,gen-profile-code): Redo how operand names are</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6410</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        overridden.  Allow operand to appear in input and output spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6411</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<insn>,gen-profile-code): string-append -> string-list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6412</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6413</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (define-ifield): Call pmacro-expand.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6414</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-full-ifield,define-normal-ifield): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6415</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-multi-ifield,define-normal-multi-ifield): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6416</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6417</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (gen-argbuf-type): Keep leading part of ARGBUF same for</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6418</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        with-scache and without-scache cases.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6419</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6420</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-14  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6421</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6422</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (fr30-1): Add state variable h-gr.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6423</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Add units u-cti, u-load, u-store, u-ldm, u-stm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6424</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (all insns): First pass at providing cycle counts.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6425</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<unit>,gen-profile-code): Only check for output operands</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6426</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        when initializing unit output operands, ditto for input operands.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6427</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6428</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (insn-length,insn-length-bytes): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6429</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (-adata-set-derived!): Use them.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6430</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (-gen-sem-case): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6431</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6432</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (-gen-trace-record-type): PCADDR->IADDR.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6433</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-write-case): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6434</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-semantic-fn): Ditto.  Split into two:</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6435</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        -gen-scache-semantic-fn and -gen-no-scache-semantic-fn.  Fix bitrot</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6436</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        in non-scache case.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6437</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-all-semantic-fns): Renamed from -gen-all-semantics.  Handle</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6438</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        scache/no-scache appropriately.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6439</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-sem-case): PCADDR->IADDR.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6440</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (gen-argbuf-type): PCADDR->IADDR.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6441</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6442</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (*): Replace string-append,string-map with</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6443</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        string-list,string-list-map where the result is sufficiently large.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6444</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-decode-insn-table): Go back to simple version for non-scache</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6445</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        case: just record IDESC in decoder tables and leave field extraction</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6446</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        to the caller.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6447</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-decode-switch): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6448</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-decode-fn): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6449</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-extract-decls): Only emit format enum if with-scache?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6450</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-model.scm (-gen-model-insn-fn): Extract ifields here in</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6451</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        non-scache case.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6452</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-model-insn-fns): Don't emit model fns for virtual insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6453</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-insn-timing): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6454</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (gen-argbuf-type): Only output sem_fields union in</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6455</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        with-scache case.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6456</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6457</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (-hw-gen-fun-get): Use GET_<H-NAME> macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6458</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-gen-fun-set): Use SET_<H-NAME> macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6459</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6460</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-12  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6461</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6462</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cpu.scm (keep-mach-validate!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6463</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (include): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6464</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6465</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (current-arch-mach-name-list): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6466</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-parse-arch-machs): Always return canonical form.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6467</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-arch): Validate user specified machs to be kept.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6468</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-mach-attr!): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6469</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6470</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (-opcodes-build-operand-instance-table?): New global.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6471</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (option-init!): Initialize it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6472</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (option-set!): Set it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6473</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-insn-table-entry): Emit 0 for operand instance ref if not</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6474</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        output operand instance tables.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6475</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-opc.in): Only output operand instance tables if asked to.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6476</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6477</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (option-init!,option-set!): Clarify returned value.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6478</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6479</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (gen-mach-bfd-name): Move from here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6480</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm: To here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6481</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6482</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-11  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6483</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6484</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (ilm): Fix comment field.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6485</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cond-branch): Remove explicit setting of COND-CTI, let cgen</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6486</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        compute it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6487</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6488</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (rtx-simplify,rtx-compile-time-constant?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6489</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rtx-true?, rtx-false?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6490</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (annul): Rename vpc to pc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6491</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-if): Improve determination of whether then/else parts</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6492</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        are conditionally executed.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6493</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6494</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (-gen-argbuf-fields-union): Move definition of union to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6495</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        outer level.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6496</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-argbuf-type): Simplify generated definition (big sem_fields</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6497</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        union moved outside).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6498</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6499</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-11  Ben Elliston  <bje@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6500</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6501</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/porting.texi: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6502</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6503</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/intro.texi: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6504</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (Layout): Use @example to insert preformatted ASCII text (such as</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6505</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        diagrams). @code is inappropriate here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6506</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6507</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-06  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6508</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6509</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (-multi-ifield-read): Fix handling of insert/extract.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6510</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6511</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.opc (print_hash): Cast dis_info.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6512</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6513</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (-gen-hardware-types): Sanitize get/set macros.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6514</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<sim-hardware>,make!): Emit a comment for user-written</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6515</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        get/set macros.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6516</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6517</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1999-01-05  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6518</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6519</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * i960.cpu (f-br-disp): Remove RELOC attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6520</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (f-ctrl-disp): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6521</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (callx-disp): set-quiet -> set for (reg h-gr 2).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6522</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (callx-indirect,callx-indirect-offset): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6523</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6524</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (gas-test): Fix dependencies.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6525</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6526</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-gas.asm: File creation args are -<uppercase-letter>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6527</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * gas-test.scm (break-out-syntax,make-file-name): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6528</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gas-test-analyze!): Use syntax-break-out.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6529</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-test.scm (break-out-syntax,make-file-name): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6530</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sim-test-analyze!): Use syntax-break-out.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6531</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-build.sh): Use gen-file-name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6532</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-allinsn.exp): Compute and pass all machs to run_sim_test.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6533</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (syntax-break-out): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6534</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (gen-file-name): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6535</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6536</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fixup.scm (nil,<?,<=?,>?): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6537</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6538</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (count-true): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6539</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6540</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * slib/sort.scm: Move sort.scm to slib directory.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6541</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cpu.scm: Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6542</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6543</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * iformat.scm (ifmt-compute!): Record empty format.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6544</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6545</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (semantic-in-out-operands): Simplify by moving several</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6546</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        internal procs outside.  Handle expression register numbers.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6547</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Handle index-of.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6548</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6549</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (annul): Rename new_pc to vpc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6550</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6551</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (-gen-cpu-reg-access-defns): Define access fns for</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6552</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        every register.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6553</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-write-case): Pass vpc to SEM_BRANCH_FINI.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6554</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-semantic-fn,-gen-sem-case): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6555</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-cpu.c): Define WANT_CPU to @cpu@.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6556</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-semantics.c): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6557</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (-gen-extract-decls): Handle non-with-scache case.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6558</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ifmt-argvars-defns): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6559</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ifmt-argvars-assigns): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6560</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-all-extractors): Delete FMT_EMPTY case, now handled like others.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6561</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-decode-fn): Handle non-with-scache case.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6562</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-decode.c): Define WANT_CPU to @cpu@.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6563</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-models.scm (-gen-mach-defns): Emit bfd name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6564</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-model.c): Define WANT_CPU to @cpu@.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6565</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (gen-ifld-extract-argvar): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6566</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<sim-hardware>,make!): Don't emit [GS]ET_H_FOO macros for elements</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6567</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        with FUN-ACCESS specified.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6568</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-fun-access?): New proc, as <hardware-base>:fun-access? method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6569</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>,gen-extract): New arg local?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6570</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>,gen-extract): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6571</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-cxmake-get): Handle non-with-scache case.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6572</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-gen-set-quiet): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6573</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>,cxmake-get): Handle non-with-scache case.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6574</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-op-extract-argvar): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6575</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,gen-record-profile): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6576</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>,gen-profile-code): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6577</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<unit>,gen-profile-code): Use -gen-argfld-ref.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6578</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-argbuf-fields-union): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6579</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-argbuf-type): Use it.  Handle non-scache case.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6580</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6581</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * *.scm: class:foo procs renamed to class-foo.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6582</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * attr.scm (<attribute>): New member `for'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6583</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-attr-parse): New first value in list for default if</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6584</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        none specified.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6585</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (non-bool-attr-list,attr:add!): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6586</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-attr): Use current-attr-add!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6587</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (atlist-attr-value-no-default): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6588</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (attr-lookup-default): Handle boolean attributes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6589</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-attr-enum): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6590</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-attr-remove-meta-attrs-alist): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6591</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (attr-nub): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6592</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-attr-list-for): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6593</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-{ifld,hw,op,insn}-attr-list): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6594</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (attr-builtin!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6595</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cpu.scm (keep-obj?): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6596</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-init-parse-cpu!): Call arch-init!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6597</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-install-builtin!): Call {attr,mode,ifield,insn}-builtin!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6598</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-finish-parse-cpu!): Call arch-finish!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6599</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * enum.scm (enum-list,enum:add,enum:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6600</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-enum,def-full-enum): Use current-enum-add!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6601</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-obj-list-enums): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6602</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (hw:add!,hw:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6603</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-hardware,def-hardware-ext): Use current-hw-add!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6604</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw:std-attrs,hw:attr-list): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6605</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hardware-builtin!): Define builtin hardware attributes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6606</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (ifld:add!,ifld:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6607</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-ifield,def-full-ifield): Use current-ifld-add!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6608</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifld:std-attrs,ifld:attr-list): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6609</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifield-builtin!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6610</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (insn:add!,insn:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6611</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-full-insn): Use current-insn-add!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6612</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn:std-attrs): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6613</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn-builtin!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6614</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (<arch>): New members attr-list,enum-list,op-list,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6615</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        minsn-list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6616</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<arch-data>): New member machs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6617</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-attr-list,current-enum-list): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6618</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-op-list,current-minsn-list): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6619</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-{attr,enum,ifld,op,hw,insn,minsn,cpu,mach,model}-add!): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6620</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-{attr,enum,ifld,op,hw,insn,minsn,cpu,mach,model}-lookup):</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6621</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6622</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-parse-arch-machs): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6623</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-arch-parse): New arg machs, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6624</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-arch-read): Handle machs spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6625</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-arch): Define MACH attribute here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6626</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mach-init!,mach-finish!): Not here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6627</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cpu:add!,cpu:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6628</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-cpu): Use current-cpu-add!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6629</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<mach>): New member bfd-name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6630</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-mach-parse): New arg bfd-name, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6631</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-mach-read): Handle bfd-name spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6632</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mach:add!,mach:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6633</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-mach): Use current-mach-add!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6634</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-mach-attr!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6635</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (arch-init!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6636</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (arch-finish!): New proc.  Reverse all object lists here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6637</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * minsn.scm (minsn-list,minsn-add!,minsn:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6638</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-minsn): Use current-minsn-add!.  Ignore minsn if mach not kept.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6639</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-normal-macro-insn): Ignore minsn if mach not kept.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6640</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mode.scm (mode-builtin!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6641</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * model.scm (model:add!,model:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6642</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-model): Use current-model-add!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6643</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (insn:attr-list): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6644</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (attr-bool-gen-decl,attr-bool-gen-defn): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6645</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-attr-table-defn): Emit value for default.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6646</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-attr-table-defns): Emit bool_attr.  Emit ifield attr table.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6647</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:attr-list): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6648</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-operand-decls,gen-insn-decls): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6649</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (compute-insn-attr-list): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6650</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-opc.h): Reorganize and simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6651</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (-operand-list,operand-list,op:add,op:lookup): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6652</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-operand,def-full-operand): Use current-op-add!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6653</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:std-attrs): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6654</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (operand-enum): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6655</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (operand-builtin!): Define builtin operand attrs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6656</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (sanitize): Update calls to lookup procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6657</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-attr-enum-decl): Use gen-obj-list-enums.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6658</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-obj-attr-defn): Renamed from gen-attr-defn, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6659</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6660</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (define-arch): Add machs spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6661</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (f-i4): SIGNED attribute -> !UNSIGNED.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6662</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (f-disp8,f-disp9,f-disp10,f-s10,f-rel9,f-rel12): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6663</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (HASH-PREFIX): Define operand attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6664</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (NOT-IN-DELAY-SLOT): Define insn attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6665</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * i960.cpu (define-arch): Add machs spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6666</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (define-arch): Add machs spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6667</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-hi16): Remove UNSIGNED,SIGN-OPT attributes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6668</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (HASH-PREFIX): Define operand attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6669</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (FILL-SLOT): Define insn attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6670</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6671</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Dec 17 17:15:06 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6672</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6673</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (stilm): Correct mask for and operation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6674</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6675</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-12-17  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6676</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6677</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-test.scm (cgen-build.sh): Use `mach' to specify machs, not `cpu'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6678</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Replace START/EXIT with start/pass.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6679</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-sim-test): Delete ".text".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6680</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6681</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Wed Dec 16 16:16:39 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6682</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6683</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (cond-branch): Conditional branches not allowed in delay slots.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6684</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6685</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Tue Dec 15 17:30:01 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6686</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6687</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu: Add NOT-IN-DELAY-SLOT as appropriate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6688</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-sbit): Make it FUN-ACCESS.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6689</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-gr): Reorder so that general regs are always printed by number.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6690</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6691</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-12-14  James E Wilson  <wilson@wilson-pc.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6692</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6693</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * i960.cpu (flushreg): Use nop.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6694</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6695</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-12-14  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6696</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6697</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (default-alignment): Specify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6698</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (<arch-data>): New member default-alignment.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6699</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (adata:default-alignment): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6700</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-arch-default-alignment): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6701</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-arch-parse): New arg default-alignment.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6702</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse-alignment): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6703</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-arch-read): Handle default-alignment spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6704</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6705</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (attr:): Pass attr-name through gen-c-symbol.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6706</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6707</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (f-%): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6708</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (gen-define-fields): Delete support for f-%.  Can</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6709</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        be readded if proved useful.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6710</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-extract-fields): Ditto.  Use gen-ifetch.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6711</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<hw-memory>,cxmake-get): Pass pc to GETMEM*.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6712</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>,gen-set-quiet): Pass pc to SETMEM*.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6713</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6714</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Mon Dec 14 16:20:59 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6715</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6716</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (div2): Set zbit properly when remainder not zero.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6717</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6718</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-12-14  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6719</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6720</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu: Remove stub macros.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6721</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (div1): Shift bits from mdl into mdh. Don't use addc/subc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6722</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (div2): Don't use addc/subc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6723</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6724</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-12-11  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6725</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6726</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (gen-obj-sanitize): Only catch spelling errors</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6727</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        if opcodes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6728</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6729</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Dec 10 18:37:34 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6730</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6731</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (div0s,div0u,div1,div2,div3,div4s): Implemented.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6732</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6733</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Dec 10 12:28:53 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6734</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6735</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cpu.scm (keep-all?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6736</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (assert-keep-all): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6737</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (gen-ifmt-table-1): Use gen-obj-sanitize.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6738</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (gen-obj-sanitize): Handle macro-insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6739</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Check for spelling errors.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6740</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6741</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-12-09  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6742</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6743</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (s-convop): Call -rtx-sem-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6744</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6745</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Tue Dec  8 10:58:38 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6746</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6747</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (-parse-hw-type): parse! no longer returns a result.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6748</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-parse-hw-profile): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6749</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>, parse!): Return `void' result.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6750</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-pc>, parse!): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6751</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>, parse!): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6752</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-immediate>, parse!): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6753</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>, parse!): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6754</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6755</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (-ifield-parse): Validate encode/decode fields.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6756</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-ifld-parse-encode-decode): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6757</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-ifld-parse-encode,-ifld-parse-decode): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6758</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-multi-ifield-parse): Set encode/decode to #f.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6759</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifld:decode-mode): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6760</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (nub): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6761</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (op-nub): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6762</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<ifield>, gen-type): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6763</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-ifld-argbuf-defn): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6764</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ifld-extract,gen-ifld-trace-extract): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6765</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<sim-hardware>): Forward gen-trace-extract onto `type'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6766</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Ditto for needed-iflds.  gen-argbuf-defn renamed from gen-argbuf-elm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6767</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hardware-base>): New method needed-iflds.  gen-argbuf-defn</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6768</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        renamed from gen-argbuf-elm, return "".  Rewrite gen-extract.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6769</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        New method gen-trace-extract.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6770</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>): New method needed-iflds.  gen-argbuf-defn renamed</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6771</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        from gen-argbuf-elm, return "" if not caching register address.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6772</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Rewrite gen-extract.  New method gen-trace-extract.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6773</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>): New methods needed-iflds, gen-argbuf-defn,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6774</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        gen-extract, gen-trace-extract, cxmake-get.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6775</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-iaddress>): New method cxmake-get.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6776</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op-needed-iflds): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6777</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>): Delete methods gen-argbuf-elm, gen-extract.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6778</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-op-argbuf-defn): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6779</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-op-extract): Renamed from op:extract.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6780</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-op-trace-extract): Renamed from op:trace-extract.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6781</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (fmt-extractable-operands): Renamed from fmt-semantic-operands</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6782</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        and rewritten.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6783</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-argbuf-elm): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6784</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (-gen-record-args): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6785</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6786</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (c-cpu-macro): Renamed from cpu-deref.  All uses changed.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6787</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6788</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * pmacros.scm (-pmacro-expand): Handle procedural macros in</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6789</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        argument position.  Flag symbolic macros in function position as</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6790</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        an error.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6791</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-pmacro): Handle quoting in definition of symbolic macros.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6792</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (pmacro-trace): Call -pmacro-expand, not -pmacro-ref.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6793</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6794</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Tue Dec  8 13:06:44 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6795</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6796</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc (parse_register_list): Account for reverse masks</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6797</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        for load and store.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6798</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (print_register_list): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6799</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_low_register_list_ld): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6800</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_hi_register_list_ld): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6801</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_low_register_list_st): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6802</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_hi_register_list_st): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6803</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (print_hi_register_list_ld): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6804</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (print_hi_register_list_st): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6805</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (print_low_register_list_ld): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6806</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (print_low_register_list_st): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6807</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (ldr15dr): Implement workaround.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6808</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ldm0,ldm1,stm0,stm1): Implemented.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6809</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6810</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-12-08  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6811</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6812</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure.in: Rename --with-hobbit to --with-cgen-hobbit.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6813</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure: Regenerate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6814</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (WITH_HOBBIT): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6815</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-hob.c): Remove Makefile dependency.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6816</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen.o): Depend on cgen-gh.h, config.h.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6817</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Regenerate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6818</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * aclocal.m4: Regenerate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6819</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6820</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-12-07  James E Wilson  <wilson@wilson-pc.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6821</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6822</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * i960.cpu, i960.opc: New files.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6823</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6824</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Mon Dec  7 14:30:24 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6825</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6826</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc (parse_register_number): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6827</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_register_list): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6828</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_low_register_list): Use parse_register_list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6829</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_hi_register_list): Use parse_register_list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6830</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (sth): Fix assembler syntax. Implement more</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6831</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6832</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6833</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Fri Dec  4 16:07:13 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6834</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6835</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (cgen-sem-switch.c): Update definition of TRACE_RESULT.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6836</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (-gen-record-args): Update call to TRACE_EXTRACT.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6837</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (-op-gen-set-trace): Update call to TRACE_RESULT.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6838</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-gen-set-trace-parallel): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6839</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-argbuf-type): New ARGBUF members trace_p,profile_p;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6840</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6841</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (call,calld): Fix setting of pc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6842</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (f-op5): Fix start bit number.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6843</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6844</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Fri Dec  4 17:06:28 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6845</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6846</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (st): Fix operand ordering. Implement more</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6847</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6848</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6849</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Dec  3 23:59:40 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6850</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6851</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (ifld:mode,ifld:hw-type): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6852</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * iformat.scm (fmt-opcode-operands): Move to opcodes.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6853</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (fmt-semantic-operands): Move to sim.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6854</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (fmt-opcode-operands): Moved here from iformat.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6855</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (<hw-index>): New member `name'.  All builders updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6856</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-index>): New method get-name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6857</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op-profilable?): Moved to sim.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6858</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op-nub): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6859</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (fmt-semantic-operands): Moved here from iformat.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6860</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op-profilable?): Moved here from operand.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6861</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-extract-type): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6862</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (c-argfld-macro): Renamed from c-ifield-macro.  All uses updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6863</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-argfld-ref): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6864</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-ifld-argfld-name): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6865</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ifld-argfld-ref): Renamed from -gen-ifld-ref.  All uses updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6866</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-ifld-decoded-val): Renamed from -gen-ifld-raw-val.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6867</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-index-argfld-name,-gen-hw-index-argfld-ref): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6868</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hardware-base>): Delete method gen-extract-type.  New method</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6869</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        gen-argbuf-elm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6870</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register): Ditto.  Update method gen-extract.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6871</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>, method gen-argbuf-elm): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6872</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (semantic-in-out-operands): Handle (ifield f-name).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6873</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-cmpop): Fix handling of eq,ne for unsigned modes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6874</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (eq,ne,lt,le,gt,ge,ltu,leu,gtu,geu): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6875</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6876</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (-gen-record-args): Tweak.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6877</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6878</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (gen-argbuf-elm): Handle case of all constant opcode fields.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6879</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6880</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Dec  3 14:23:27 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6881</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6882</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/porting: Fix typo: gas->sim.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6883</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc (print_m4): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6884</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu: Implemented many insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6885</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6886</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Dec  3 00:03:16 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6887</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6888</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (build-reg-operand!): Remove redundant setting of hw-name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6889</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6890</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (f-rel9): Delete RELOC attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6891</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (f-rel12): Add PCREL-ADDR attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6892</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (label9): Make an h-iaddr, not h-uint.  Delete asm print spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6893</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (label12): Delete PCREL-ADDR attribute.  Make an h-iaddr, not h-sint.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6894</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc (print_label9): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6895</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6896</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * iformat.scm (ifmt-analyze): Check attributes derived from semantic</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6897</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        code for CTI indicators.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6898</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (insn-cti?): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6899</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (atlist:cti?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6900</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6901</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-11-30  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6902</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6903</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (arch): default-insn-bitsize -> default-insn-word-bitsize.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6904</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (f-i20-4,f-i20-16,f-i20): New fields.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6905</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (i20): New operand.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6906</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ldi8): Implement.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6907</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ldi20): New insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6908</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ldi32m): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6909</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (jmpd): Implement.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6910</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc (CGEN_DIS_HASH_SIZE,CGEN_DIS_HASH): Define in opc.h.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6911</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (arch): default-insn-bitsize -> default-insn-word-bitsize.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6912</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (arch-data): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6913</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-arch-default-insn-word-bitsize): Renamed from</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6914</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        current-arch-default-insn-bitsize [ya, that's a pretty long name].</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6915</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-arch-read): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6916</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6917</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (hw:attr-list): Move here ...</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6918</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm: ... from here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6919</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6920</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (fld:bitrange): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6921</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (fld:word-offset,fld:word-length): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6922</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifield?): Use class-instance.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6923</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>, method field-start): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6924</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifld:enum): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6925</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>, methods field-mask,field-value): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6926</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-ifield-parse): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6927</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<multi-ifield> support): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6928</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifld-beyond-base?): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6929</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifld:std-attrs): New variable.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6930</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifld:attr-list): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6931</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * iformat.scm (-compute-insn-mask): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6932</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (-parse-insn-format): New arg errtxt, all callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6933</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6934</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-parse-insn-format-symbol,-parse-insn-format-list): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6935</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (<hardware>): No longer forward gen-insert,gen-extract</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6936</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        onto type.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6937</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>): Ditto.  Forward onto index instead.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6938</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ifld-decls,gen-ifld-defns): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6939</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifld:insert,ifld:extract): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6940</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>): New methods gen-insert, gen-extract.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6941</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<multi-ifield>): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6942</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-index>): Forward gen-insert,gen-extract onto value.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6943</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>): Delete insert/extract support.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6944</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register,hw-memory,hw-immediate>): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6945</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-hash-defines): Use string-list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6946</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Define CGEN_MAX_IFMT_OPERANDS.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6947</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-switch): Use string-list,string-list-map.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6948</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-fget-switch,gen-fset-switch): Use string-list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6949</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-parse-switch,gen-insert-switch): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6950</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-extract-switch,gen-print-switch): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6951</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-insert-switch,gen-extract-switch): New local `total_length'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6952</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ifmt-table-1,gen-ifmt-table): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6953</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ifmt-entry): Renamed from gen-iformat-entry, rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6954</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ivalue-entry): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6955</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-insn-table-entry): Use string-list.  Update iformat,ivalue</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6956</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        computation.  Use 0 for operand ref table if ALIAS insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6957</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-minsn-table-entry): Use string-list.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6958</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-macro-insn-table): Temporarily emit format tables for ALIAS insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6959</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-opcode-open): Record address of ifield table.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6960</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-opc.h): Call gen-ifld-decls.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6961</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-opc.in): Call gen-ifld-defns, gen-ifmt-table.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6962</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * types.scm (<bitrange>): New members word-offset,word-length.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6963</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Delete member total-length.  Delete methods start,mask,value.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6964</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (bitrange:word-offset,bitrange:word-length): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6965</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (gen-define-fields): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6966</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-extract-fields): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6967</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<ifield>, gen-ifld-extract): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6968</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>): New methods gen-ifld-extract-decl.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6969</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Delete method gen-ifld-extract-beyond.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6970</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<multi-ifield>): New methods gen-ifld-extract-decl.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6971</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<multi-ifield>, method gen-ifld-extract): Implement.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6972</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-ifld-extract-base,-gen-ifld-extract-beyond): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6973</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ifld-exttact,gen-ifld-extract-beyond): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6974</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6975</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (-rtx-traverse-no-mode): Process operands.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6976</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-rtx-traverse-syntax-no-mode): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6977</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (semantic-in-out-operands): Watch for `delay' and add DELAY-SLOT attr.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6978</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-ifield): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6979</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-shop): Don't prepend `unsigned' for unsigned modes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6980</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (ifield): New rtx function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6981</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ref,symbol): Use standard -rtx-traverse-syntax-no-mode.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6982</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (delay): New rtx function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6983</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (insn:std-attrs): Add DELAY-SLOT.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6984</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6985</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cos.scm (-elm-make-method-getter): Fix typo.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6986</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6987</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (backslash): Handle lists of strings.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6988</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6989</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Nov 26 11:47:29 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6990</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6991</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (f-rel9): Correct for pc+2.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6992</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (label9): Use print_label9.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6993</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc (print_label9): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6994</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6995</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Tue Nov 24 11:19:35 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6996</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6997</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu: Change $r13,$r14,$r15 to uppercase.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6998</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc (parse_low_register_list): Renamed.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>6999</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_hi_register_list): Renamed.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7000</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (print_hi_register_list): Renamed.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7001</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (print_low_register_list): Renamed.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7002</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7003</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Mon Nov 23 18:26:36 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7004</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7005</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (f-rel9): Now a pc relative offset.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7006</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7007</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-11-23  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7008</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7009</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (op-asm): Move to here, from operands.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7010</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<op-asm>, method parse!): Validate arguments.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7011</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>, method gen-function-name): Fix thinko.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7012</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (<operand>, method make!): Don't set op-asm here.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7013</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (list-elements-ok?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7014</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7015</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm: Clean up pass.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7016</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7017</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-11-20  Doug Evans  <devans@tobor.to.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7018</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7019</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (int): Defer saving of ps,pc and setting ibit,sbit to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7020</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        the fr30_int function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7021</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-cr): Remove PROFILE,CACHE-ADDR attributes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7022</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-dr): Add FUN-ACCESS attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7023</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7024</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-11-20  James E Wilson  <wilson@wilson-pc.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7025</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7026</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-model.scm (-gen-mach-defns): Use gen-sym instead of obj:name</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7027</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        for C symbol for models array.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7028</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7029</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Nov 19 15:57:45 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7030</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7031</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc (parse_reglist_low): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7032</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_reglist_hi): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7033</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (print_reglist_low): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7034</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (print_reglist_hi): New function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7035</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu: Finish remaining insn stubs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7036</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7037</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-11-19  Doug Evans  <devans@tobor.to.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7038</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7039</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (-gen-extract-word): Handle fields shorter than entire word.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7040</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7041</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (ldi32m): Don't use for disassembly.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7042</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7043</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Wed Nov 18 21:34:41 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7044</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7045</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (int): Implement it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7046</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7047</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>1998-11-18  Doug Evans  <devans@casey.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7048</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7049</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (nop): Fix C code.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7050</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7051</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (semantic-in-out-operands): Fix setting of sem-attrs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7052</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7053</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (f-i32): New ifield.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7054</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (i32): New operand.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7055</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ldi32): New insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7056</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ldi32m): New macro insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7057</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (inte): Provide simple version for now.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7058</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7059</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-arch.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7060</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm: Move architecture support generation to sim-arch.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7061</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-sim.scm: Load sim-arch.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7062</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * dev.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7063</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7064</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (pc?) New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7065</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (class <hardware-base>): Rewrite method 'pc?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7066</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (class <hardware>): Forward 'pc? to the hardware type.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7067</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (class <hw-pc>): New method 'pc?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7068</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7069</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Add support for variable length ISAs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7070</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (ifld-beyond-base?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7071</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu: Remove integral-insn? spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7072</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (arch:derived,arch:set-derived!): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7073</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (arch:app-data,arch:set-app-data!): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7074</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (class <arch>): New members derived, app-data.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7075</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (class <cpu>): Delete member integral-insn?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7076</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cpu:integral-insn?): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7077</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-cpu-parse): Delete arg integral-insn?.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7078</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-cpu-read): Delete integral-insn? support.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7079</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (state:decode-assist): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7080</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (state:int-insn?): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7081</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<derived-arch-data>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7082</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-adata-set-derived!): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7083</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mach-finish!): Call it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7084</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (<hw-asm>, method gen-extract): Pass pc to C handler.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7085</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-operand-instance): Add COND_REF support.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7086</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-operand-instance-table): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7087</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-hash-defines): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7088</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-extract-switch): Update type of `insn_value' arg.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7089</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-opcode-open): Update type of `value' arg of dis_hash_insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7090</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (-rtx-ref-type): Renamed from -rtx-set?.  All callers</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7091</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7092</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (semantic-in-out-operands): Compute UNCOND-CTI,COND-CTI from rtl.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7093</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (gen-define-fields): Create vars to hold insn value</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7094</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        beyond the base insn (for large insns).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7095</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-extract-beyond-var-list): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7096</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-extract-fields): Handle large insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7097</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-write-case): Update sem_arg computation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7098</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Update initial vpc computation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7099</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-semantic-fn): Ditto.  Update type of `insn'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7100</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-sem-case): Update sem_arg computation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7101</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Update initial vpc computation.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7102</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<ifield>, gen-ifld-extract): Renamed from `extract'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7103</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-extract-word): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7104</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>): New method gen-ifld-extract-beyond.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7105</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-ifld-extract-beyond): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7106</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * types.scm (bitrange-overlap?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7107</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7108</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (bits->bytes): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7109</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (bytes->bits): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7110</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7111</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Move extraction support into decoder.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7112</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (-gen-record-args,-gen-record-profile-args,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7113</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        -gen-extractor,-gen-all-extractors,cgen-extract.c): Move extraction</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7114</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        support to sim-decode.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7115</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (-gen-decode-insn-table): Change decoder data to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7116</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        be array of IDESC,FMT entries.  Make the array const.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7117</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-gcc-label-table): Make array const.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7118</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-decode-switch): Branch to extraction code after insn has been</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7119</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        identified.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7120</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-decode-insn-globals): Delete extract handler from</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7121</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        @cpu@_insn_sem.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7122</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-decode-fn): Add extraction support.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7123</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-sem-fn-decls): Delete extraction fn decls.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7124</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-idesc-decls): Update @cpu@_decode decl.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7125</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-idesc-init-fn): Delete extraction support.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7126</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-extract-decls): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7127</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7128</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (cgen-sem-switch.c): Update switch test.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7129</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sim-finish!): Surround pbb only code with #if WITH_SCACHE_PBB.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7130</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7131</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (build-decode-table-entry): New arg invalid insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7132</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7133</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (table-entry:make): Record insn value as insn object, not name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7134</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        All uses updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7135</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7136</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobbit.scm (path_basename): Renamed from `basename' to avoid</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7137</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        collision with C function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7138</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (path_dirname): Similarily.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7139</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobbit.c,hobbit.h: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7140</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7141</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Wed Nov 18 11:26:17 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7142</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7143</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (dir2r15-predec-stub): Reference to R15 must be indirect.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7144</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7145</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Mon Nov 16 19:19:50 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7146</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7147</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu: Implement more instruction stubs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7148</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7149</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Nov 12 19:20:28 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7150</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7151</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu: Implement more instruction stubs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7152</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7153</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Tue Nov 10 10:53:55 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7154</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7155</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (-rtx-expr-mode-name): Handle sequence locals.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7156</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7157</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (zflag:,zflag,nflag:,nflag): New rtx fns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7158</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7159</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (<pc>, method make!): FAKE renamed to SEM-ONLY.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7160</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:std-attrs): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7161</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (gen-operand-instance): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7162</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-switch): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7163</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (condbit,accum): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7164</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (nbit,vbit,zbit,cbit): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7165</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7166</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Mon Nov  9 14:30:51 1998  Doug Evans  <devans@seba.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7167</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7168</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * enum.scm (-enum-read): Fix typo.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7169</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7170</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * iformat.scm (-ifmt-search-key): Simplify a little.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7171</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7172</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Mon Nov  9 12:07:56 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7173</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7174</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/porting: semantics.c -> sem.c.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7175</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Regenerate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7176</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu (add): Change ADD to add. Add more registers and set</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7177</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        status bits on 'add' instruction.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7178</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7179</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Fri Nov  6 18:15:05 1998  James E Wilson  <wilson@wilson-pc.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7180</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7181</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (-gen-arch-model-decls):  Default MAX_UNITS to 1 instead</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7182</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        of 0.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7183</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7184</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Fri Nov  6 17:43:16 1998  Doug Evans  <devans@seba.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7185</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7186</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * minsn.scm (minsn:enum): Update, call current-arch-name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7187</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7188</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * pmacros.scm (-pmacro-expand): Make `cep' a variable.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7189</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7190</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (CGEN_HOB_INPUT_FILES): Add pmacros.scm,enum.scm,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7191</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        mach.scm,model.scm,types.scm,ifield.scm,minsn.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7192</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ARCH,CGEN,CGENFLAGS): New variables.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7193</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gas-test,sim-test): New rules.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7194</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7195</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure.in (arch): Define.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7196</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7197</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7198</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-hob.scm (*UNSPECIFIED*): Renamed from UNSPECIFIED.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7199</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * All .scm files: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7200</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7201</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * dev.scm: Fix gas-test call to cpu-load.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7202</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * gas-test.scm: Clean up pass to remove bit-rot.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7203</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-test.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7204</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7205</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * enum.scm (read-enum): Fix typo in `vals' handling.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7206</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7207</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (-parse-hw-type): Fix typo.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7208</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse-hardware): Rename `asm' to `aasm' to avoid GCC reserved word.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7209</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (def-hardware,define-normal-hardware): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7210</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7211</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobbit.scm (*case-sensitive-flag*): New configuration variable.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7212</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (display-var): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7213</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobbit.c: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7214</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobbit.h: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7215</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7216</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (-ifield-read): Rename local `length' to `length-' to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7217</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        avoid hobbit problem.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7218</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (-cpu-read): Rename local `parallel-insns' to</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7219</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        `parallel-insns-' to avoid hobbit problem.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7220</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7221</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Fri Nov  6 17:19:12 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7222</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7223</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.opc (parse_hi16): Fix call to cgen_parse_address.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7224</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse_slo16,parse_ulo16): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7225</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (<hw-address>, method gen-parse): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7226</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7227</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Thu Nov  5 13:04:53 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7228</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7229</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (GUILELDFLAGS,GUILELDADD): New variables.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7230</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen_LDFLAGS,cgen_LDADD,hob.x): Use them.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7231</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Rebuild.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7232</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (define-normal-insn): Expand pmacros.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7233</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mode.scm (<mode>): New member `host?'.  All uses updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7234</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mode:host?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7235</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm (define-rtx-node): Make a syntax proc, not a macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7236</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-rtx-syntax-node,define-rtx-macro-node): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7237</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (define-rtx-dual-mode): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7238</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-index-of): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7239</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-unop): Use plain C for host mode operations.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7240</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (s-binop,s-shop,s-boolifop,s-cmpop): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7241</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm (index-of): New rtx function.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7242</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<hw-index>): New method cxmake-get.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7243</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7244</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Wed Nov  4 23:58:08 1998  Doug Evans  <devans@seba.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7245</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7246</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (-gen-engine-decls): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7247</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7248</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Wed Nov  4 18:40:47 1998  Dave Brolley  <brolley@cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7249</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7250</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/rtl (Example): Correct Typo.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7251</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * doc/porting: Add 'make dep' step to opcodes port instructions.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7252</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.opc: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7253</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * fr30.cpu: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7254</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7255</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Wed Oct 28 13:36:15 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7256</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7257</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure.in: Handle guile $exec_prefix = $prefix/foo.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7258</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am (GUILEINCDIR): New variable.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7259</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (INCLUDES): Use it.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7260</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure: Regenerate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7261</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7262</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * aclocal.m4: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7263</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7264</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Mon Oct 19 13:19:34 1998  Doug Evans  <devans@seba.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7265</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7266</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (cgen-extract.c): Delete #include cpu-sim.h</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7267</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-semantics.c): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7268</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (cgen-decode.c): Delete #include cpu-sim.h,cpu-opc.h.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7269</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-model.scm (cgen-model.c): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7270</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (cgen-arch.h): Delete #include @arch@-opc.h.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7271</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-arch.c): Delete #include cpu-sim.h,cpu-opc.h.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7272</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7273</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (read-cpu.opc): Handle empty file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7274</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7275</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cos.scm (-elm-make-method-setter): Fix typo.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7276</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7277</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cpu.scm (-init-parse-cpu!): Call types-init!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7278</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-finish-parse-cpu!): Call types-finish!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7279</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (<ifield>): Delete members start,length.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7280</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        New member bitrange.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7281</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>, methods field-start,field-length): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7282</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (fld:start): New arg insn-len.  All callers updated.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7283</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<ifield>, methods field-mask,field-value): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7284</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-ifield-parse): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7285</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifield-init!): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7286</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * iformat.scm (compute-insn-length): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7287</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (compute-insn-mask): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7288</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (insn:value): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7289</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (<arch-data>): New members default-insn-bitsize,insn-lsb0?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7290</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-arch-default-insn-bitsize): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7291</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (current-arch-insn-lsb0?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7292</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-arch-parse,-arch-read): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7293</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<cpu>): New member file-transform.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7294</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-cpu-parse,-cpu-read): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7295</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (<hw-asm>, method gen-extract): Pass ex_info to handler.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7296</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-hash-defines): Define CGEN_INSN_LSB0_P.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7297</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7298</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-insert-switch): Update args of @arch@_cgen_insert_operand.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7299</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-extract-switch): Update args of @arch@_cgen_extract_operand.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7300</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-opcode-open): Set CGEN_OPCODE_INSN_ENDIAN.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7301</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (op:start): Update call to field-start method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7302</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (opcode-slots): New arg lsb0?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7303</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (fill-slot!,build-slots): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7304</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (build-decode-table-entry,build-decode-table-guts): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7305</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-decoder-table,gen-decoder-switch,gen-decoder): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7306</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-decode-fn): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7307</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-decode.c): Update call to gen-decode-fn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7308</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (gen-argbuf-type): Move `semantic' to cpu specific part.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7309</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-cpu-header,-gen-cpuall-includes): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7310</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-cpuall.h): Call -gen-cpuall-includes.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7311</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * types.scm (<bitrange>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7312</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (types-init!,types-finish!): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7313</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (parse-number): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7314</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse-boolean): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7315</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (word-value): Renamed from shift-bits, rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7316</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (word-mask): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7317</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (define-arch): New fields default-insn-bitsize,insn-lsb0?.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7318</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (m32rxf): New field `file-transform'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7319</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.opc (my_print_insn): print_int_insn -> print_insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7320</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7321</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobbit.h: Fix include file name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7322</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7323</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Fri Oct  9 16:58:10 1998  Doug Evans  <devans@seba.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7324</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7325</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * slib: New directory of slib files used by cgen/hobbit.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7326</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobbit.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7327</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobbit.c: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7328</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobbit.h: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7329</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobscmif.h: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7330</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hob-main.c: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7331</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hobslib.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7332</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hob.sh: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7333</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.am: Add support for compiling hobbit, and using compiled</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7334</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        version of hobbit to compile cgen.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7335</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Makefile.in: Regenerate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7336</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure.in: Support --with-hobbit.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7337</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * configure: Regenerate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7338</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * acconfig.h (WITH_HOBBIT): Add.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7339</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * config.in: Regenerate.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7340</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7341</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtl.scm: New file, was cdl-c.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7342</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Definition of rtx funcs moved to rtx-funcs.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7343</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (semantic-in-out-operands): Rewrite to compute object form of</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7344</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        semantic code.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7345</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * rtx-funcs.scm: New file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7346</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7347</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-gh.c: #include "config.h".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7348</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gh_cadddr,gh_cddddr): New fns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7349</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgh_vector_to_list): New fn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7350</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgh_map1,cgh_map2,cgh_map1_fn2): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7351</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgh_init): Prefix qsort procs with "cgh-".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7352</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen-gh.h (gh_cadddr,gh_cddddr,cgh_vector_to_list): Declare.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7353</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cgen.c: #include "config.h".</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7354</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7355</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * attr.scm (bitset-attr?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7356</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<bitset-attribute>, method parse-value): Value syntax changed from</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7357</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (val1 val2 ...) to val1,val2,....</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7358</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<bitset-attribute>): New method gen-value.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7359</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<integer-attribute>): New method gen-value.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7360</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<enum-attribute>): New method gen-value.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7361</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * cpu.scm: Disable debugging evaluator if (not (defined? 'DEBUG-EVAL)).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7362</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<reader>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7363</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (CURRENT-ARCH,CURRENT-READER): New globals.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7364</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (keep-mach?): Move here from mach.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7365</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (arch,arch-comment,arch-default-mach): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7366</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<arch>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7367</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<arch-data>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7368</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<cpu>): Make subclass of <ident>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7369</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (*ENDIAN* variables): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7370</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (process-state-vars): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7371</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mach-finish!): Add `base' value to MACH attribute.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7372</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (<hardware>): Make subclass of <ident>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7373</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw:std-attrs): New global.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7374</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-profilable?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7375</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * ifield.scm (<ifield>): Make subclass of <ident>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7376</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sort-ifield-list): Move here from iformat.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7377</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * iformat.scm (<iformat>): Renamed from <insn-format>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7378</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Make subclass of <ident>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7379</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-ifmt-search-key): Include cti? in categorization of formats.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7380</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (ifmt-analyze): Compile semantics (turn to object form).</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7381</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * insn.scm (<insn>): Make subclass of <ident>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7382</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        New member compiled-semantics.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7383</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn:std-attrs): Add SKIP-CTI, VIRTUAL.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7384</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mode.scm (<mode>): Make subclass of <ident>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7385</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (UBI): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7386</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * model.scm (<unit>): Make subclass of <ident>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7387</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        New members inputs,outputs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7388</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<model>): Make subclass of <ident>.  New member state.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7389</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-unit-parse): Parse inputs,outputs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7390</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<iunit>): New class.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7391</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-insn-timing-parse-model): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7392</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (parse-insn-timing): Function unit spec rewritten.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7393</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * operand.scm (<operand>): Make subclass of <ident>.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7394</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        New members sem-name,num,cond?  New method gen-pretty-name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7395</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (hw-index-scalar): New global.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7396</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op-nub-hw): Move here from rtl.scm.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7397</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (op:lookup-sem-name,op-profilable?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7398</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * pmacros.scm: Rewrite to pass through hobbit.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7399</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils-cgen.scm (gen-attr-defn): Simplify using new gen-value method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7400</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (logit): Make a macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7401</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (bit-set?): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7402</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (high-part): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7403</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7404</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (define-arch): Move to top of file.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7405</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cpu family m32rbf): Renamed from m32rb.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7406</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (model m32r/d): Function unit spec rewritten.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7407</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (all insns): Ditto.  Replace UBI with BI.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7408</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7409</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (gen-attr-table-decls): Declare</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7410</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        @arch@_cgen_hw_attr_table.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7411</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-attr-table-defns): Generate hw attribute table.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7412</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7413</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (-gen-engine-decls): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7414</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-model-decls): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7415</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-parallel-exec-type): Add new member `written' to struct parexec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7416</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-record-args): Add SEM_BRANCH_INIT_EXTRACT if cti insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7417</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-record-profile-args): Simplify.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7418</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-parallel-sem-case): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7419</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-semantic-fn): Emit SEM_BRANCH_{INIT,FINI} if cti insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7420</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        New local `written'.  Delete profiling code.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7421</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-sem-case): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7422</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-uncond-written-mask,-any-cond-written?): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7423</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-sem-switch.c): Include duplicates of insns that can be executed</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7424</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        parallelly or serially, and write-back handlers for all parallel insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7425</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm (-gen-decode-insn-globals): Add parallel write-back</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7426</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        support to initialization of struct insn_sem.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7427</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-idesc-decls): Add parallel write-back support to struct idesc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7428</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-insn-sem-type): Add parallel write-back support to struct</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7429</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        insn_sem.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7430</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-idesc-init-fn): Add support for virtual insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7431</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Add parallel write-back support.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7432</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-model.scm (gen-model-profile-fn): Delete</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7433</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-model-fn-decls): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7434</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-model-insn-fn,-gen-model-insn-fns): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7435</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-model-init-fn): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7436</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-mach-defns): Initialize insn-name lookup and fast/full engine_fn</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7437</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        members in @mach@_init_cpu.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7438</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-model.c): Generate model handlers for each insn.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7439</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (gen-define-field-macro): Cti insns handled differently.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7440</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-pc>): New method gen-write.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7441</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>, method gen-write): New arg `mode'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7442</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-register>): Delete method gen-record-profile!.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7443</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        New method gen-profile-index-type.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7444</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-memory>, method gen-write): New arg `mode'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7445</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>, method gen-extract): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7446</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-address>, method gen-write): New arg `mode'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7447</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-index>, method get-write-index): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7448</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<pc>, method cxmake-get-direct): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7449</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<pc>): New method cxmake-get.  Comment out methods</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7450</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        gen-set-quiet,gen-set-trace.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7451</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<operand>): New methods gen-argbuf-elm,gen-profile-argbuf-elm,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7452</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        gen-profile-index-type,gen-profile-code.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7453</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Delete method gen-pretty-name.  Rewrite method gen-write.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7454</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Delete method cxmake-get-direct.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7455</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-gen-set-trace): Update `written'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7456</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-op-gen-set-trace-parallel): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7457</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-hw-index-raw,-gen-hw-index): Handle strings.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7458</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-cpu-insn-enum-decl): Add extra entries for parallel</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7459</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        insns and their write-back handlers.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7460</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (insn-op-lookup): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7461</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<unit>): New method gen-profile-code.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7462</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<iunit>): New method gen-profile-code.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7463</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-argbuf-elm): Add profiling elements.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7464</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-argbuf-type): Define cti insns separately in their own struct.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7465</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Add member `addr_cache' to this struct.  Add entries for pbb virtual</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7466</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        insns.  Move semantic entries here from struct scache.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7467</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Delete everything from struct scache except argbuf.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7468</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<insn>, method gen-profile-locals): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7469</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<insn>, method gen-profile-code): Rewrite.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7470</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (sim-finish!): Create virtual pbb insns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7471</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7472</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Tue Sep 15 15:22:02 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7473</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7474</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (h-cr): Add bbpc,bbpsw.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7475</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-sm,h-bsm,h-ie,h-bie,h-bcond,h-bpc): Delete.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7476</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (h-psw,h-bpsw,h-bbpsw): Define.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7477</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (rte,trap): Handle bbpc,bbpsw.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7478</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (max-operand-instances): Fix typo.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7479</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (<hardware-base>, method 'fun-access?): Don't force virtual</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7480</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        hardware elements to be fun-access.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7481</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-gen-fun-get,-hw-gen-fun-set): Fix handling of scalars.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7482</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7483</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Wed Sep  9 15:28:55 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7484</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7485</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (trap): Pass `pc' to m32r_trap.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7486</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7487</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Mon Aug 10 14:29:33 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7488</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7489</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (gen-insn-table-entry): Comment out generation of cdx.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7490</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7491</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Mon Aug  3 11:51:04 1998  Doug Evans  <devans@seba.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7492</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7493</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.cpu (cpu m32rb): Renamed from m32r to distinguish from</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7494</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        architecture name.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7495</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (mach m32r): Update.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7496</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7497</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * mach.scm (mach:supports?): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7498</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm (gen-cpu-reg-access-{decls,defns}): Renamed from</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7499</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        gen-reg-access-{decls,defns}.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7500</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm (gen-reg-access-{decl,defn}): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7501</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-mach-bfd-name): New proc.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7502</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-arch-reg-access-{decls,defns}): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7503</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (cgen-arch.[ch]): Output register access cover fns.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7504</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7505</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * hardware.scm (hardware-builtin!): Set print handlers for</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7506</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        h-addr,h-iaddr.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7507</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * m32r.opc (parse_hash,parse_hi16,parse_slo16,parse_ulo16): New arg</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7508</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        `od'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7509</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (CGEN_PRINT_NORMAL,print_hash): Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7510</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (my_print_insn): Ditto.  Delete args buf, buflen.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7511</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm: Pass `od' (opcode-descriptor) to all C handlers.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7512</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-hw-asm-specs): Add `handlers' spec.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7513</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-parse-hw-asm): Lookup class at runtime.  If no asm-spec, use</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7514</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        `normal-hw-asm'.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7515</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>): Renamed from <opval>.  New elements parse,insert,extract,</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7516</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        print.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7517</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>, gen-insert,gen-extract,gen-print): Use them.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7518</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (<hw-asm>, parse!): New method.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7519</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-insn-table-entry): Print semantics.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7520</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-opcode-open): Renamed from gen-opcode-table.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7521</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7522</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * utils.scm (string-write): No longer a macro.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7523</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-string-write): Handle procedure args.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7524</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm: Update all calls to string-write.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7525</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-cpu.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7526</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-decode.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7527</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim-model.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7528</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * sim.scm: Ditto.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7529</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7530</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Fri Jul 31 14:40:38 1998  Doug Evans  <devans@seba.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7531</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7532</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (cgen-ibd.h,gen-extra-ibd.h): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7533</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (-gen-insn-builders,-gen-insn-builder): New procs.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7534</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7535</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Fri Jul 24 11:38:59 1998  Doug Evans  <devans@canuck.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7536</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7537</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * opcodes.scm (gen-syntax-entry): Fix bracketing for -Wall.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7538</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        (gen-opcode-table): Properly terminate comment.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7539</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7540</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>Tue Jul 21 10:51:42 1998  Doug Evans  <devans@seba.cygnus.com></code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7541</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>&nbsp;</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7542</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        * Version 0.6.0.</code></pre></td>
      </tr>
      <tr valign="middle">
         <td>7543</td>
         <td></td>
         <td></td>
         <td class="code"><pre><code>        Clean up pass over everything, so starting fresh.</code></pre></td>
      </tr>
   </tbody>
</table>


<script type='text/javascript'>
/* <![CDATA[ */
var rev = new Array();
var a = document.getElementsByTagName('a');
for (var i = 0; i < a.length; i++) {
  if (a[i].className == 'blame-revision') {
    var id = a[i].id;
    addEvent(a[i], 'mouseover', function() { mouseover(this) } );
    addEvent(a[i], 'mouseout', function() { mouseout(this) } );
  }
}

function mouseover(a) {
  // Find the revision by using the link
  var m = /rev=(\d+)/.exec(a.href);
  var r = m[1];

  div = document.createElement('div');
  div.className = 'blame-popup';
  div.innerHTML = rev[r];
  a.parentNode.appendChild(div);
}

function mouseout(a) {
  var div = a.parentNode.parentNode.getElementsByTagName('div');
  for (var i = 0; i < div.length; i++) {
    if (div[i].className = 'blame-popup') {
      div[i].parentNode.removeChild(div[i]);
    }
  }
}

function addEvent(obj, type, func) {
  if (obj.addEventListener) {
    obj.addEventListener(type, func, false);
    return true;
  } else if (obj.attachEvent) {
    return obj.attachEvent('on' + type, func);
  } else {
    return false;
  }
}
rev[6] = '<div class="info"><span class="date">2011-10-13 07:53:45 GMT<\/span><\/div><div class="msg">First checkin.<\/div>';
/* ]]> */
</script>

</div>
</div>
<div id="websvnfooter">
    <p style="padding:0; margin:0"><small>powered by: <a href="http://www.websvn.info">WebSVN 2.1.0</a></small></p>
</div>
        </div>

                
        <div style="clear: both; margin-left: 200px;">
            <ins
                class="adsbygoogle"
                style="display:inline-block;width:728px;height:90px"
                data-ad-client="ca-pub-8561717607970465"
                data-ad-slot="4128044249"></ins>
            <script type="text/javascript">(adsbygoogle = window.adsbygoogle || []).push({});</script>
        </div>
        
            </div>
    <div class="bot">
        &copy; copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores&reg;, registered trademark.
    </div>
</div>

<!-- Old browser warning -->
<script type="text/javascript">
  if (!('borderImage' in document.createElement('div').style)) {
    var div = document.getElementById('old-browser-warning')
    div.innerHTML = '<b>Your browser is out-of-date!</b>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Update your browser to view this website correctly.'
    div.setAttribute('style', 'background-color: red; border-bottom: 2px solid black; margin: 0 -12px 12px -12px; padding: 12px; text-align: center;')
  }
</script>
<!-- /Old browser warning -->
<!-- Google search -->
<script type="text/javascript" src="//www.google.com/jsapi"></script>
<script type="text/javascript">google.load("elements", "1", {packages: "transliteration"});</script>
<script type="text/javascript" src="//www.google.com/coop/cse/t13n?form=cse-search-box&amp;t13n_langs=en"></script>
<script type="text/javascript" src="//www.google.com/coop/cse/brand?form=cse-search-box&amp;lang=en"></script>
<!-- /Google search -->

</body>
</html>
Browse

Tools

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-binutils/] [binutils-2.19.1/] [cgen/] [ChangeLog] - Blame information for rev 6
