OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-binutils/] [binutils-2.19.1/] [cgen/] [cpu/] [mep-h1.cpu] - Blame information for rev 6

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 jlechner
; Insns introduced for the MeP-h1 core
2
;
3
(dnci stcb_r "store in control bus space" (VOLATILE (MACH h1))
4
     "stcb $rn,($rma)"
5
     (+ MAJ_7 rn rma (f-sub4 12))
6
     (c-call VOID "do_stcb" rn (and rma #xffff))
7
     ((mep (unit u-use-gpr (in usereg rn))
8
           (unit u-use-gpr (in usereg rma))
9
           (unit u-exec)
10
           (unit u-stcb))))
11
 
12
(dnci ldcb_r "load from control bus space" (VOLATILE (MACH h1) (LATENCY 3))
13
     "ldcb $rn,($rma)"
14
     (+ MAJ_7 rn rma (f-sub4 13))
15
     (set rn (c-call SI "do_ldcb" (and rma #xffff)))
16
      ((mep (unit u-use-gpr (in usereg rma))
17
            (unit u-ldcb)
18
            (unit u-exec)
19
            (unit u-ldcb-gpr (out loadreg rn)))))
20
 
21
(dnci pref "cache prefetch" ((MACH h1) VOLATILE)
22
     "pref $cimm4,($rma)"
23
     (+ MAJ_7 cimm4 rma (f-sub4 5))
24
     (sequence ()
25
               (c-call VOID "check_option_dcache" pc)
26
               (c-call VOID "do_cache_prefetch" cimm4 rma pc))
27
     ((mep (unit u-use-gpr (in usereg rma))
28
           (unit u-exec))))

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.