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[/] [scarts/] [trunk/] [toolchain/] [scarts-binutils/] [binutils-2.19.1/] [cgen/] [cpu/] [xc16x.cpu] - Blame information for rev 6

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1 6 jlechner 
; Infineon XC16X CPU description.  -*- Scheme -*-
2 
;
3 
; Copyright 2006, 2009 Free Software Foundation, Inc.
4 
;
5 
; Contributed by KPIT Cummins Infosystems Ltd.; developed under contract
6 
; from Infineon Systems, GMBH , Germany.
7 
;
8 
; This file is part of the GNU Binutils.
9 
;
10 
; This program is free software; you can redistribute it and/or modify
11 
; it under the terms of the GNU General Public License as published by
12 
; the Free Software Foundation; either version 2 of the License, or
13 
; (at your option) any later version.
14 
;
15 
; This program is distributed in the hope that it will be useful,
16 
; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 
; GNU General Public License for more details.
19 
;
20 
; You should have received a copy of the GNU General Public License
21 
; along with this program; if not, write to the Free Software
22 
; Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 
; 02110-1301, USA.
24 
 
25 
(define-rtl-version 0 8)
26 
 
27 
(include "simplify.inc")
28 
 
29 
; define-arch appears first
30 
 
31 
(define-arch
32 
  (name xc16x) ; name of cpu family
33 
  (comment "Infineon XC16X")
34 
  (default-alignment aligned)
35 
  (insn-lsb0? #t)
36 
  (machs xc16x)
37 
  (isas xc16x)
38 
)
39 
 
40 
; Attributes.
41 
; An attribute to describe which pipeline an insn runs in generally OS.
42 
(define-attr
43 
  (for insn)
44 
  (type enum)
45 
  (name PIPE)
46 
  (comment "parallel execution pipeline selection")
47 
  (values NONE OS)
48 
)
49 
 
50 
; Instruction set parameters.
51 
 
52 
(define-isa
53 
  (name xc16x)
54 
  (default-insn-bitsize 32)
55 
  (base-insn-bitsize 32)
56 
  (default-insn-word-bitsize 16)
57 
  (decode-assist (15 14 13 12))
58 
  ; The XC16X fetches 1 insn at a time.
59 
  (liw-insns 1)
60 
  (parallel-insns 1)
61 
)
62 
 
63 
; Cpu family definitions.
64 
 
65 
(define-cpu
66 
  ; cpu names must be distinct from the architecture name and machine names.
67 
  ; The "b" suffix stands for "base" and is the convention.
68 
  ; The "f" suffix stands for "family" and is the convention.
69 
  (name xc16xbf)
70 
  (comment "Infineon XC16X base family")
71 
  (endian little)
72 
  (insn-chunk-bitsize 32)
73 
  (word-bitsize 16)
74 
  (parallel-insns 1)
75 
)
76 
 
77 
(define-mach
78 
  (name xc16x)
79 
  (comment "Infineon XC16X cpu")
80 
  (cpu xc16xbf)
81 
)
82 
 
83 
; Model descriptions.
84 
 
85 
(define-model
86 
  (name xc16x) (comment "XC16X") (attrs)
87 
  (mach xc16x)
88 
 
89 
  (pipeline p-mem "" () ((prefetch) (fetch) (decode) (address) (memory) (execute) (writeback)))
90 
 
91 
    ; `state' is a list of variables for recording model state
92 
    (state
93 
     ; bit mask of h-gr registers, =1 means value being loaded from memory
94 
     (h-gr UINT)
95 
    )
96 
 
97 
  (unit u-exec "Execution Unit" ()
98 
        1 1 ; issue done
99 
        () ; state
100 
        ((dr INT -1) (sr INT -1)) ; inputs
101 
        ((dr INT -1)) ; outputs
102 
        () ; profile action (default)
103 
        )
104 
  (unit u-cmp "Compare Unit" ()
105 
        1 1 ; issue done
106 
        () ; state
107 
        ((src1 INT -1) (src2 INT -1)) ; inputs
108 
        () ; outputs
109 
        () ; profile action (default)
110 
        )
111 
  (unit u-cti "Jump & Call Unit" ()
112 
        1 1 ; issue done
113 
        () ; state
114 
        ((condbit) (sr INT -1)) ; inputs
115 
        ((pc)) ; outputs
116 
        () ; profile action (default)
117 
        )
118 
  (unit u-mov "Data Movement Unit" ()
119 
        1 1 ; issue done
120 
        () ;state
121 
        ((dr INT -1) (sr INT -1)) ; inputs
122 
        ((dr INT -1)) ; output
123 
        () ; profile action (default)
124 
        )
125 
 )
126 
 
127 
; Instruction fields.
128 
;
129 
; Attributes:
130 
; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
131 
; ABS-ADDR: absolute address (for reloc and disassembly purposes)
132 
; RELOC: there is a relocation associated with this field (experiment)
133 
 
134 
(define-attr
135 
  (for ifield operand)
136 
  (type boolean)
137 
  (name RELOC)
138 
  (comment "there is a reloc associated with this field (experiment)")
139 
)
140 
 
141 
(dnf f-op1       "op1"                 () 7  4)
142 
(dnf f-op2       "op2"                 () 3  4)
143 
(dnf f-condcode  "condcode"            () 7  4)  ;condition code required in other jmps and calls
144 
(dnf f-icondcode "indrct condcode"     () 15 4)  ;condition code required in other jmpi and calli
145 
(dnf f-rcond     "relative-cond"       () 7  4)  ;condition code required in JMPR
146 
(dnf f-qcond     "qbit"                () 7  4)  ;used in enum of bset/bclear macro
147 
(dnf f-extccode  "extended condcode"   () 15 5)  ;condition code required in other jmpa and calla
148 
(dnf f-r0        "r0"                  () 9  2)  ;required where 2 bit register used(only R0-R3)
149 
(dnf f-r1        "r1"                  () 15 4)
150 
(dnf f-r2        "r2"                  () 11 4)
151 
(dnf f-r3        "r3"                  () 12 4)
152 
(dnf f-r4        "r4"                  () 11 4)
153 
(dnf f-uimm2     "uimm2"               () 13 2)  ;used for immediate data,eg in ADD,MOV insns
154 
(dnf f-uimm3     "uimm3"               () 10 3)  ;used for immediate data,eg in ADD,SUB insns
155 
(dnf f-uimm4     "uimm4"               () 15 4)  ;used for immediate data,eg in MOV insns
156 
(dnf f-uimm7     "uimm7"               (PCREL-ADDR RELOC) 15 7) ;used in TRAP
157 
(dnf f-uimm8     "uimm8"               () 23 8)  ;used in immediate byte data,eg in ADDB,MOVB insns
158 
(dnf f-uimm16    "uimm16"              () 31 16) ;used for immediate word data
159 
(dnf f-memory    "memory"              () 31 16) ; used for memory operands
160 
(dnf f-memgr8    "memory"              () 31 16) ; memory location of gr
161 
(dnf f-rel8      "rel8"                (PCREL-ADDR RELOC) 15 8) ;used in JMPR,CALLR
162 
(dnf f-relhi8    "relhi8"              (PCREL-ADDR RELOC) 23 8) ;used in JB,JBC,JNB,JNBS
163 
(dnf f-reg8      "reg8"                () 15 8) ;required where 8bit gp register used
164 
(dnf f-regmem8   "regmem8"             () 15 8) ;required where 8bit register used
165 
(dnf f-regoff8   "regoff8"             () 15 8) ;required for offset calc
166 
(dnf f-reghi8    "reghi8"              () 23 8) ;required where 8bit register number used
167 
(dnf f-regb8     "regb8"               () 15 8) ;required for byte registers RL0,RH0, till RL8,RH8
168 
(dnf f-seg8      "seg8"                () 15 8) ;used as segment number in JMPS,CALLS
169 
(dnf f-segnum8   "segnum8"             () 23 8) ;used in EXTS,EXTSR
170 
(dnf f-mask8     "mask8"               () 23 8) ;used as mask in BFLDH,BFLDL insns
171 
(dnf f-pagenum   "page num"            () 25 10);used in EXTP,EXTPR
172 
(dnf f-datahi8   "datahi8"             () 31 8) ;used for filling with const data
173 
(dnf f-data8     "data8"               () 23 8) ;used for filling with const data
174 
(dnf f-offset16  "address offset16"    (ABS-ADDR RELOC) 31 16) ;used in JMPS,JMPA,CALLA,CALLS
175 
(dnf f-op-bit1   "gap of 1 bit"        () 11 1) ;used for filling with const data
176 
(dnf f-op-bit2   "gap of 2 bits"       () 11 2) ;used for filling with const data
177 
(dnf f-op-bit4   "gap of 4 bits"       () 11 4) ;used for filling with const data
178 
(dnf f-op-bit3   "gap of 3 bits"       () 10 3) ;used in CALLA, JMPA
179 
(dnf f-op-2bit   "gap of 2 bits"       () 10 2) ;used in CALLA
180 
(dnf f-op-bitone "gap of 1 bit "       () 10 1) ;used in JMPA
181 
(dnf f-op-onebit "gap of 1 bit "       () 9  1) ;used in JMPA
182 
(dnf f-op-1bit   "gap of 1 bit "       () 8  1) ;used in JMPA, CALLA
183 
(dnf f-op-lbit4  "gap of 4 bits"       () 15 4) ;used for filling with const data
184 
(dnf f-op-lbit2  "gap of 2 bits"       () 15 2) ;used for filling with const data
185 
(dnf f-op-bit8   "gap of 8 bits"       () 31 8) ;used for filling with const data
186 
(dnf f-op-bit16  "gap of 16 bits"      () 31 16) ;used for filling with const data
187 
(dnf f-qbit      "qbit"                () 7  4) ;used in bit field of bset/bclear
188 
(dnf f-qlobit    "qlobit"              () 31 4) ;used for filling with const data
189 
(dnf f-qhibit    "qhibit"              () 27 4) ;used for filling with const data
190 
(dnf f-qlobit2   "qlobit2"             () 27 2) ;used for filling with const data
191 
(dnf f-pof    "upof16"                 () 31 16) ; used for memory operands
192 
 
193 
; Enums.
194 
; insn-op1: bits 0-3
195 
(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
196 
  ("0" "1" "2" "3" "4" "5" "6" "7"
197 
   "8" "9" "10" "11" "12" "13" "14" "15")
198 
)
199 
 
200 
; insn-op2: bits 4-7
201 
(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
202 
  ("0" "1" "2" "3" "4" "5" "6" "7"
203 
   "8" "9" "10" "11" "12" "13" "14" "15")
204 
)
205 
 
206 
;/*for bclr/bset*/
207 
; insn-rcond: bits 0-3
208 
(define-normal-insn-enum insn-qcond "bit set/clear enums" () QBIT_ f-qcond
209 
  (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10)
210 
   ("11" 11) ("12" 12) ("13" 13) ("14" 14) ("15" 15))
211 
)
212 
;/************/
213 
; insn-rcond: bits 0-3
214 
(define-normal-insn-enum insn-rcond "relative jump condition code op2 enums" () COND_ f-rcond
215 
  (("UC" 0) ("NET" 1) ("Z" 2) ("NE_NZ" 3) ("V" 4)  ("NV" 5) ("N" 6) ("NN" 7)
216 
   ("C" 8) ("NC" 9) ("SGT" 10) ("SLE" 11) ("SLT" 12) ("SGE" 13) ("UGT" 14) ("ULE" 15)
217 
   ("EQ" 2) ("NE" 3) ("ULT" 8) ("UGE" 9))
218 
)
219 
 
220 
 
221 
 
222 
; Hardware pieces.
223 
; These entries list the elements of the raw hardware.
224 
; They're also used to provide tables and other elements of the assembly
225 
; language.
226 
 
227 
(dnh h-pc "program counter" (PC) (pc) () () ())
228 
 
229 
(define-keyword
230 
  (name gr-names)
231 
  (enum-prefix H-GR-)
232 
  (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
233 
          (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
234 
 
235 
)
236 
(define-hardware
237 
  (name h-gr)
238 
  (comment "general registers")
239 
  (attrs PROFILE CACHE-ADDR)
240 
  (type register HI (16))
241 
  (indices extern-keyword gr-names)
242 
)
243 
 
244 
(define-keyword
245 
  (name ext-names)
246 
  (enum-prefix H-EXT-)
247 
  (values (0x1 0) (0x2 1) (0x3 2) (0x4 3)
248 
          ("1" 0) ("2" 1) ("3" 2) ("4" 3))
249 
 
250 
)
251 
 
252 
(define-hardware
253 
  (name h-ext)
254 
  (comment "ext values")
255 
  (attrs PROFILE CACHE-ADDR)
256 
  (type register HI (8))
257 
  (indices extern-keyword ext-names)
258 
)
259 
 
260 
(define-keyword
261 
  (name psw-names)
262 
  (enum-prefix H-PSW-)
263 
  (values ("IEN" 136) ("r0.11" 240) ("r1.11" 241) ("r2.11" 242) ("r3.11" 243) ("r4.11" 244)
264 
                      ("r5.11" 245) ("r6.11" 246) ("r7.11" 247) ("r8.11" 248)
265 
                      ("r9.11" 249) ("r10.11" 250) ("r11.11" 251) ("r12.11" 252)
266 
                      ("r13.11" 253) ("r14.11" 254) ("r15.11" 255))
267 
)
268 
 
269 
(define-hardware
270 
  (name h-psw)
271 
  (comment "ext values")
272 
  (attrs PROFILE CACHE-ADDR)
273 
  (type register HI (1))
274 
  (indices extern-keyword psw-names)
275 
)
276 
 
277 
(define-keyword
278 
  (name grb-names)
279 
  (enum-prefix H-GRB-)
280 
  (values (rl0 0) (rh0 1) (rl1 2) (rh1 3) (rl2 4) (rh2 5) (rl3 6) (rh3 7)
281 
          (rl4 8) (rh4 9) (rl5 10) (rh5 11) (rl6 12) (rh6 13) (rl7 14) (rh7 15))
282 
)
283 
 
284 
(define-hardware
285 
  (name h-grb)
286 
  (comment "general registers")
287 
  (attrs PROFILE CACHE-ADDR)
288 
  (type register QI (16))
289 
  (indices extern-keyword grb-names)
290 
)
291 
 
292 
(define-keyword
293 
  (name conditioncode-names)
294 
  (enum-prefix H-CC-)
295 
  (values (cc_UC 0) (cc_NET 1) (cc_Z 2) (cc_EQ 2) (cc_NZ 3) (cc_NE 3) (cc_V 4) (cc_NV 5) (cc_N 6)  (cc_NN 7) (cc_ULT 8)  (cc_UGE 9)
296 
          (cc_C 8) (cc_NC 9) (cc_SGT 10) (cc_SLE 11) (cc_SLT 12) (cc_SGE 13) (cc_UGT 14)
297 
          (cc_ULE 15))
298 
)
299 
(define-hardware
300 
  (name h-cc)
301 
  (comment "condition codes")
302 
  (attrs PROFILE CACHE-ADDR)
303 
  (type register QI (16))
304 
  (indices extern-keyword conditioncode-names)
305 
)
306 
 
307 
(define-keyword
308 
  (name extconditioncode-names)
309 
  (enum-prefix H-ECC-)
310 
  (values(cc_UC 0) (cc_NET 2) (cc_Z 4) (cc_EQ 4) (cc_NZ 6) (cc_NE 6) (cc_V 8) (cc_NV 10) (cc_N 12)  (cc_NN 14) (cc_ULT 16)  (cc_UGE 18) (cc_C 16) (cc_NC 18) (cc_SGT 20)
311 
         (cc_SLE 22) (cc_SLT 24) (cc_SGE 26) (cc_UGT 28) (cc_ULE 30) (cc_nusr0 1)
312 
         (cc_nusr1 3) (cc_usr0 5) (cc_usr1 7))
313 
)
314 
(define-hardware
315 
  (name h-ecc)
316 
  (comment "extended condition codes")
317 
  (attrs PROFILE CACHE-ADDR)
318 
  (type register QI (4))
319 
  (indices extern-keyword extconditioncode-names)
320 
)
321 
 
322 
(define-keyword
323 
  (name grb8-names)
324 
  (enum-prefix H-GRB8-)
325 
  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
326 
          (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
327 
          (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
328 
          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
329 
          (zeros 142)  (ones 143) (spseg 134) (tfr 214)
330 
          (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247)
331 
          (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255))
332 
)
333 
 
334 
(define-hardware
335 
  (name h-grb8)
336 
  (comment "general byte registers")
337 
  (attrs PROFILE CACHE-ADDR)
338 
  (type register QI (36))
339 
  (indices extern-keyword grb8-names)
340 
)
341 
 
342 
(define-keyword
343 
  (name r8-names)
344 
  (enum-prefix H-R8-)
345 
  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
346 
          (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
347 
          (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
348 
          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
349 
          (zeros 142)  (ones 143) (spseg 134) (tfr 214)
350 
          (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247)
351 
          (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255))
352 
)
353 
 
354 
(define-hardware
355 
  (name h-r8)
356 
  (comment "registers")
357 
  (attrs PROFILE CACHE-ADDR)
358 
  (type register HI (36))
359 
  (indices extern-keyword r8-names)
360 
)
361 
 
362 
(define-keyword
363 
  (name regmem8-names)
364 
  (enum-prefix H-REGMEM8-)
365 
  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
366 
          (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
367 
          (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
368 
          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
369 
          (zeros 142)  (ones 143) (spseg 134) (tfr 214)
370 
          (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247)
371 
          (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255))
372 
)
373 
 
374 
(define-hardware
375 
  (name h-regmem8)
376 
  (comment "registers")
377 
  (attrs )
378 
  (type register HI (16))
379 
  (indices extern-keyword regmem8-names)
380 
)
381 
 
382 
(define-keyword
383 
  (name regdiv8-names)
384 
  (enum-prefix H-REGDIV8-)
385 
  (values (r0 0) (r1 17) (r2 34) (r3 51) (r4 68) (r5 85) (r6 102) (r7 119)
386 
          (r8 136) (r9 153) (r10 170) (r11 187) (r12 204) (r13 221) (r14 238) (r15 255))
387 
)
388 
 
389 
(define-hardware
390 
  (name h-regdiv8)
391 
  (comment "division insn registers")
392 
  (attrs PROFILE CACHE-ADDR)
393 
  (type register HI (16))
394 
  (indices extern-keyword regdiv8-names)
395 
)
396 
 
397 
(define-keyword
398 
  (name reg0-name)
399 
  (enum-prefix H-REG0-)
400 
  (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) (0x8 8) (0x9 9) (0xa 10) (0xb 11)
401 
          (0xc 12) (0xd 13) (0xe 14) (0xf 15)
402 
          ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
403 
          ("12" 12) ("13" 13) ("14" 14) ("15" 15))
404 
)
405 
 
406 
(define-hardware
407 
  (name h-r0)
408 
  (comment "for 4-bit data excuding 0")
409 
  (attrs PROFILE CACHE-ADDR)
410 
  (type register HI (30))
411 
  (indices extern-keyword reg0-name)
412 
)
413 
 
414 
(define-keyword
415 
  (name reg0-name1)
416 
  (enum-prefix H-REG01-)
417 
  (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7)
418 
          ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7))
419 
)
420 
 
421 
(define-hardware
422 
  (name h-r01)
423 
  (comment "for 4-bit data excuding 0")
424 
  (attrs PROFILE CACHE-ADDR)
425 
  (type register HI (14))
426 
  (indices extern-keyword reg0-name1)
427 
)
428 
 
429 
(define-keyword
430 
  (name regbmem8-names)
431 
  (enum-prefix H-REGBMEM8-)
432 
  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
433 
          (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
434 
          (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
435 
          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
436 
          (zeros 142)  (ones 143) (spseg 134) (tfr 214)
437 
          (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247)
438 
          (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255))
439 
)
440 
 
441 
(define-hardware
442 
  (name h-regbmem8)
443 
  (comment "registers")
444 
  (attrs PROFILE CACHE-ADDR)
445 
  (type register HI (36))
446 
  (indices extern-keyword regbmem8-names)
447 
)
448 
 
449 
(define-keyword
450 
  (name memgr8-names)
451 
  (enum-prefix H-MEMGR8-)
452 
  (values (dpp0 65024)  (dpp1 65026)  (dpp2 65028)  (dpp3 65030)
453 
          (psw 65296)   (cp 65040)    (mdl 65038)   (mdh  65036)
454 
          (mdc 65294)   (sp 65042)    (csp 65032)  (vecseg 65298)
455 
          (stkov 65044)  (stkun 65046) (cpucon1 65048) (cpucon2 65050)
456 
          (zeros 65308)  (ones 65310) (spseg 65292) (tfr 65452) )
457 
)
458 
 
459 
(define-hardware
460 
  (name h-memgr8)
461 
  (comment "memory location of registers")
462 
  (attrs )
463 
  (type register HI (20))
464 
  (indices extern-keyword memgr8-names)
465 
)
466 
 
467 
(dsh h-cond "condition bit" () (register BI))   ;any bit from PSW while comparison
468 
; This bit is part of the PSW register
469 
(dsh h-cbit  "carry bit"                () (register BI))
470 
 
471 
(dsh h-sgtdis "segmentation enable bit" () (register BI)) ;0 means segmentation enabled
472 
 
473 
;Instruction operands
474 
; -- layer between the assembler and the raw hardware description
475 
; -- the main means of manipulating instruction fields in the semantic code
476 
 
477 
; XC16X specific operand attributes:
478 
 
479 
(define-attr
480 
  (for operand)
481 
  (type boolean)
482 
  (name HASH-PREFIX)
483 
  (comment "immediates have an optional '#' prefix")
484 
)
485 
 
486 
(define-attr
487 
  (for operand)
488 
  (type boolean)
489 
  (name DOT-PREFIX)
490 
  (comment "bit addr have an optional '.' prefix")
491 
)
492 
 
493 
(define-attr
494 
  (for operand)
495 
  (type boolean)
496 
  (name POF-PREFIX)
497 
  (comment "page offset ")
498 
)
499 
 
500 
(define-attr
501 
  (for operand)
502 
  (type boolean)
503 
  (name PAG-PREFIX)
504 
  (comment "page ")
505 
)
506 
 
507 
(define-attr
508 
  (for operand)
509 
  (type boolean)
510 
  (name SOF-PREFIX)
511 
  (comment "segment offset selection")
512 
)
513 
 
514 
(define-attr
515 
  (for operand)
516 
  (type boolean)
517 
  (name SEG-PREFIX)
518 
  (comment "segment")
519 
)
520 
 
521 
(dnop sr      "source register"              () h-gr    f-r2)
522 
(dnop dr      "destination register"         () h-gr    f-r1)
523 
(dnop dri     "destination register"         () h-gr    f-r4)
524 
(dnop srb     "source register"              () h-grb   f-r2)
525 
(dnop drb     "destination register"         () h-grb   f-r1)
526 
(dnop sr2     "2 bit source register"        () h-gr    f-r0)
527 
(dnop src1    "source register 1"            () h-gr   f-r1)
528 
(dnop src2    "source register 2"            () h-gr   f-r2)
529 
(dnop srdiv   "source register 2"            () h-regdiv8   f-reg8)
530 
(dnop RegNam  "PSW bits"                     () h-psw f-reg8)
531 
(dnop uimm2   "2 bit unsigned number"        (HASH-PREFIX) h-ext f-uimm2)
532 
(dnop uimm3   "3 bit unsigned number"        (HASH-PREFIX) h-r01 f-uimm3)
533 
(dnop uimm4   "4 bit unsigned number"        (HASH-PREFIX) h-uint f-uimm4)
534 
(dnop uimm7   "7 bit trap number"            (HASH-PREFIX) h-uint f-uimm7)
535 
(dnop uimm8   "8 bit unsigned immediate"     (HASH-PREFIX) h-uint f-uimm8)
536 
(dnop uimm16  "16 bit unsigned immediate"    (HASH-PREFIX) h-uint f-uimm16)
537 
(dnop upof16  "16 bit unsigned immediate"    (POF-PREFIX) h-addr f-memory)
538 
(dnop reg8    "8 bit word register number"   () h-r8 f-reg8)
539 
(dnop regmem8 "8 bit word register number"   () h-regmem8 f-regmem8)
540 
(dnop regbmem8 "8 bit byte register number"  () h-regbmem8 f-regmem8)
541 
(dnop regoff8 "8 bit word register number"   () h-r8 f-regoff8)
542 
(dnop reghi8  "8 bit word register number"   () h-r8 f-reghi8)
543 
(dnop regb8   "8 bit byte register number"   () h-grb8 f-regb8)
544 
(dnop genreg  "8 bit word register number"   () h-r8 f-regb8)
545 
(dnop seg     "8 bit segment number"         () h-uint f-seg8)
546 
(dnop seghi8  "8 bit hi segment number"      () h-uint f-segnum8)
547 
(dnop caddr   "16 bit address offset"        () h-addr f-offset16)
548 
(dnop rel     "8 bit signed relative offset" () h-sint f-rel8)
549 
(dnop relhi   "hi 8 bit signed relative offset" () h-sint f-relhi8)
550 
(dnop condbit "condition bit"                (SEM-ONLY) h-cond f-nil)
551 
(dnop bit1    "gap of 1 bit"                 () h-uint f-op-bit1)
552 
(dnop bit2    "gap of 2 bits"                () h-uint f-op-bit2)
553 
(dnop bit4    "gap of 4 bits"                () h-uint f-op-bit4)
554 
(dnop lbit4   "gap of 4 bits"                () h-uint f-op-lbit4)
555 
(dnop lbit2   "gap of 2 bits"                () h-uint f-op-lbit2)
556 
(dnop bit8    "gap of 8 bits"                () h-uint f-op-bit8)
557 
(dnop u4      "gap of 4 bits"                () h-r0   f-uimm4)
558 
(dnop bitone  "field of 1 bit"               () h-uint f-op-onebit)
559 
(dnop bit01   "field of 1 bit"               () h-uint f-op-1bit)
560 
(dnop cond    "condition code"               () h-cc   f-condcode)
561 
(dnop icond   "indirect condition code"      () h-cc   f-icondcode)
562 
(dnop extcond "extended condition code"      () h-ecc  f-extccode)
563 
(dnop memory  "16 bit memory"                () h-addr f-memory)
564 
(dnop memgr8  "16 bit memory"                () h-memgr8 f-memgr8)
565 
(dnop cbit    "carry bit"                    (SEM-ONLY) h-cbit  f-nil)
566 
(dnop qbit    "bit addr"                     (DOT-PREFIX) h-uint  f-qbit)
567 
(dnop qlobit  "bit addr"                     (DOT-PREFIX) h-uint  f-qlobit)
568 
(dnop qhibit  "bit addr"                     (DOT-PREFIX) h-uint  f-qhibit)
569 
(dnop mask8   "8 bit mask"                   (HASH-PREFIX) h-uint f-mask8)
570 
(dnop masklo8 "8 bit mask"                   (HASH-PREFIX) h-uint f-datahi8)
571 
(dnop pagenum "10 bit page number"           (HASH-PREFIX) h-uint f-pagenum)
572 
(dnop data8   "8 bit data"                   (HASH-PREFIX) h-uint f-data8)
573 
(dnop datahi8 "8 bit data"                   (HASH-PREFIX) h-uint f-datahi8)
574 
(dnop sgtdisbit "segmentation enable bit"    (SEM-ONLY) h-sgtdis f-nil)
575 
(dnop upag16  "16 bit unsigned immediate"    (PAG-PREFIX) h-uint f-uimm16)
576 
(dnop useg8   "8 bit segment "               (SEG-PREFIX) h-uint f-seg8)
577 
(dnop useg16  "16 bit address offset"        (SEG-PREFIX) h-uint f-offset16)
578 
(dnop usof16  "16 bit address offset"        (SOF-PREFIX) h-uint f-offset16)
579 
 
580 
; define hash operator
581 
(define-operand (name hash) (comment "# prefix") (attrs)
582 
  (type h-sint)
583 
  (index f-nil)
584 
  (handlers (parse "hash") (print "hash"))
585 
)
586 
 
587 
; define dot operator
588 
(define-operand (name dot) (comment ". prefix") (attrs)
589 
  (type h-sint)
590 
  (index f-nil)
591 
  (handlers (parse "dot") (print "dot"))
592 
)
593 
 
594 
; define pof operator
595 
(define-operand (name pof) (comment "pof: prefix") (attrs)
596 
  (type h-sint)
597 
  (index f-nil)
598 
  (handlers (parse "pof") (print "pof"))
599 
)
600 
 
601 
; define pag operator
602 
(define-operand (name pag) (comment "pag: prefix") (attrs)
603 
  (type h-sint)
604 
  (index f-nil)
605 
  (handlers (parse "pag") (print "pag"))
606 
)
607 
 
608 
; define sof operator
609 
(define-operand (name sof) (comment "sof: prefix") (attrs)
610 
  (type h-sint)
611 
  (index f-nil)
612 
  (handlers (parse "sof") (print "sof"))
613 
)
614 
 
615 
; define seg operator
616 
(define-operand (name segm) (comment "seg: prefix") (attrs)
617 
  (type h-sint)
618 
  (index f-nil)
619 
  (handlers (parse "seg") (print "seg"))
620 
)
621 
 
622 
; IDOC attribute for instruction documentation.
623 
(define-attr
624 
  (for insn)
625 
  (type enum)
626 
  (name IDOC)
627 
  (comment "insn kind for documentation")
628 
  (attrs META)
629 
  (values
630 
   (MOVE - () "Data Movement")
631 
   (ALU  - () "Arithmatic & logical")
632 
   (CMP  - () "Compare")
633 
   (JMP  - () "Jump & Call")
634 
   (MISC - () "Miscellaneous")
635 
   (SYSC - () "System control")
636 
  )
637 
)
638 
 
639 
; Include the instruction set descriptions from their respective
640 
; source files.
641 
 
642 
;Arithmatic insns
643 
;******************************************************************
644 
 
645 
;add/sub register and immediate
646 
(define-pmacro (arithmetic16 name insn insn1 opc1 opc2 op1 op2 mode dir)
647 
  (dni name
648 
       (.str name "arithmetic" )
649 
       ((PIPE OS) (IDOC ALU))
650 
       (.str insn " $"op1 ",$"dir"$"op2)
651 
       (+ opc1 opc2 op1 op2)
652 
       (set mode op1 (insn1 mode op1 (mem HI op2)))
653 
       ()
654 
  )
655 
)
656 
(arithmetic16 addrpof add add OP1_0 OP2_2 reg8 upof16 HI "pof")
657 
(arithmetic16 subrpof sub sub OP1_2 OP2_2 reg8 upof16 HI "pof")
658 
(arithmetic16 addbrpof addb add OP1_0 OP2_3 regb8 upof16 QI "pof")
659 
(arithmetic16 subbrpof subb sub OP1_2 OP2_3 regb8 upof16 QI "pof")
660 
(arithmetic16 addrpag add add OP1_0 OP2_2 reg8 upag16 HI "pag")
661 
(arithmetic16 subrpag sub sub OP1_2 OP2_2 reg8 upag16 HI "pag")
662 
(arithmetic16 addbrpag addb add OP1_0 OP2_3 regb8 upag16 QI "pag")
663 
(arithmetic16 subbrpag subb sub OP1_2 OP2_3 regb8 upag16 QI "pag")
664 
 
665 
;add/sub register and immediate
666 
(define-pmacro (arithmetic17 name insn insn1 opc1 opc2 op1 op2 mode dir)
667 
  (dni name
668 
       (.str name "arithmetic" )
669 
       ((PIPE OS) (IDOC ALU))
670 
       (.str insn " $"op1 ",$"dir"$"op2)
671 
       (+ opc1 opc2 op1 op2)
672 
       (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
673 
       ()
674 
  )
675 
)
676 
(arithmetic17 addcrpof addc addc OP1_1 OP2_2 reg8 upof16 HI "pof")
677 
(arithmetic17 subcrpof subc subc OP1_3 OP2_2 reg8 upof16 HI "pof")
678 
(arithmetic17 addcbrpof addcb addc OP1_1 OP2_3 regb8 upof16 QI "pof")
679 
(arithmetic17 subcbrpof subcb subc OP1_3 OP2_3 regb8 upof16 QI "pof")
680 
(arithmetic17 addcrpag addc addc OP1_1 OP2_2 reg8 upag16 HI "pag")
681 
(arithmetic17 subcrpag subc subc OP1_3 OP2_2 reg8 upag16 HI "pag")
682 
(arithmetic17 addcbrpag addcb addc OP1_1 OP2_3 regb8 upag16 QI "pag")
683 
(arithmetic17 subcbrpag subcb subc OP1_3 OP2_3 regb8 upag16 QI "pag")
684 
 
685 
;add/sub register and immediate
686 
(define-pmacro (arithmetic18 name insn insn1 opc1 opc2 op1 op2 mode dir)
687 
  (dni name
688 
       (.str name "arithmetic" )
689 
       ((PIPE OS) (IDOC ALU))
690 
       (.str insn " $"dir"$"op1 ",$"op2)
691 
       (+ opc1 opc2 op2 op1)
692 
       (set (mem HI op1) (insn1 (mem HI op1) op2 ))
693 
       ()
694 
  )
695 
)
696 
(arithmetic18 addrpofr add add OP1_0 OP2_4 upof16 reg8 HI "pof")
697 
(arithmetic18 subrpofr sub sub OP1_2 OP2_4 upof16 reg8 HI "pof")
698 
(arithmetic18 addbrpofr addb add OP1_0 OP2_5 upof16 regb8 QI "pof")
699 
(arithmetic18 subbrpofr subb sub OP1_2 OP2_5 upof16 regb8 QI "pof")
700 
 
701 
;add/sub register and immediate
702 
(define-pmacro (arithmetic19 name insn insn1 opc1 opc2 op1 op2 mode dir)
703 
  (dni name
704 
       (.str name "arithmetic" )
705 
       ((PIPE OS) (IDOC ALU))
706 
       (.str insn " $"dir"$"op1 ",$"op2)
707 
       (+ opc1 opc2 op2 op1)
708 
       (set (mem HI op1) (insn1 mode (mem HI op1) op2 cbit))
709 
       ()
710 
  )
711 
)
712 
(arithmetic19 addcrpofr addc addc OP1_1 OP2_4 upof16 reg8 HI "pof")
713 
(arithmetic19 subcrpofr subc subc OP1_3 OP2_4 upof16 reg8 HI "pof")
714 
(arithmetic19 addcbrpofr addcb addc OP1_1 OP2_5 upof16 regb8 QI "pof")
715 
(arithmetic19 subcbrpofr subcb subc OP1_3 OP2_5 upof16 regb8 QI "pof")
716 
 
717 
;add/sub register and immediate
718 
(define-pmacro (arithmetic20 name insn insn1 opc1 opc2 op1 op2 mode dir)
719 
  (dni name
720 
       (.str name "arithmetic" )
721 
       ((PIPE OS) (IDOC ALU))
722 
       (.str insn " $"op1 ",$hash$"dir"$"op2)
723 
       (+ opc1 opc2 op1 op2)
724 
       (set mode op1 (insn1 mode op1 op2))
725 
       ()
726 
  )
727 
)
728 
(arithmetic20 addrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pof")
729 
(arithmetic20 subrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pof")
730 
(arithmetic20 addbrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pag")
731 
(arithmetic20 subbrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pag")
732 
 
733 
;add/sub register and immediate
734 
(define-pmacro (arithmetic21 name insn insn1 opc1 opc2 op1 op2 mode dir)
735 
  (dni name
736 
       (.str name "arithmetic" )
737 
       ((PIPE OS) (IDOC ALU))
738 
       (.str insn " $"op1 ",$hash$"dir"$"op2)
739 
       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
740 
       (set mode op1 (insn1 mode op1 op2))
741 
       ()
742 
  )
743 
)
744 
(arithmetic21 addrhpof3 add add OP1_0 OP2_8 dr uimm3 HI "pof")
745 
(arithmetic21 subrhpof3 sub sub OP1_2 OP2_8 dr uimm3 HI "pof")
746 
(arithmetic21 addbrhpag3 addb add OP1_0 OP2_9 drb uimm3 QI "pag")
747 
(arithmetic21 subbrhpag3 subb sub OP1_2 OP2_9 drb uimm3 QI "pag")
748 
(arithmetic21 addrhpag3 add add OP1_0 OP2_8 dr uimm3 HI "pag")
749 
(arithmetic21 subrhpag3 sub sub OP1_2 OP2_8 dr uimm3 HI "pag")
750 
(arithmetic21 addbrhpof3 addb add OP1_0 OP2_9 drb uimm3 QI "pof")
751 
(arithmetic21 subbrhpof3 subb sub OP1_2 OP2_9 drb uimm3 QI "pof")
752 
 
753 
;add/sub register and immediate
754 
(define-pmacro (arithmetic22 name insn insn1 opc1 opc2 op1 op2 mode dir)
755 
  (dni name
756 
       (.str name "arithmetic" )
757 
       ((PIPE OS) (IDOC ALU))
758 
       (.str insn " $"op1 ",$hash$"dir"$"op2)
759 
       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
760 
       (set mode op1 (insn1 mode op1 op2))
761 
       ()
762 
  )
763 
)
764 
(arithmetic22 addrbhpof addb add OP1_0 OP2_7 regb8 uimm8 QI "pof")
765 
(arithmetic22 subrbhpof subb sub OP1_2 OP2_7 regb8 uimm8 QI "pof")
766 
(arithmetic22 addbrhpag addb add OP1_0 OP2_7 regb8 uimm8 QI "pag")
767 
(arithmetic22 subbrhpag subb sub OP1_2 OP2_7 regb8 uimm8 QI "pag")
768 
 
769 
;add/sub register and immediate
770 
(define-pmacro (arithmetic23 name insn insn1 opc1 opc2 op1 op2 mode dir)
771 
  (dni name
772 
       (.str name "arithmetic" )
773 
       ((PIPE OS) (IDOC ALU))
774 
       (.str insn " $"op1 ",$hash$"dir"$"op2)
775 
       (+ opc1 opc2 op1 op2)
776 
       (set mode op1 (insn1 mode op1 op2 cbit))
777 
       ()
778 
  )
779 
)
780 
(arithmetic23 addcrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pof")
781 
(arithmetic23 subcrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pof")
782 
(arithmetic23 addcbrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pag")
783 
(arithmetic23 subcbrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pag")
784 
 
785 
;add/sub register and immediate
786 
(define-pmacro (arithmetic24 name insn insn1 opc1 opc2 op1 op2 mode dir)
787 
  (dni name
788 
       (.str name "arithmetic" )
789 
       ((PIPE OS) (IDOC ALU))
790 
       (.str insn " $"op1 ",$hash$"dir"$"op2)
791 
       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
792 
       (set mode op1 (insn1 mode op1 op2 cbit))
793 
       ()
794 
  )
795 
)
796 
(arithmetic24 addcrhpof3 addc addc OP1_1 OP2_8 dr uimm3 HI "pof")
797 
(arithmetic24 subcrhpof3 subc subc OP1_3 OP2_8 dr uimm3 HI "pof")
798 
(arithmetic24 addcbrhpag3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pag")
799 
(arithmetic24 subcbrhpag3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pag")
800 
(arithmetic24 addcrhpag3 addc addc OP1_1 OP2_8 dr uimm3 HI "pag")
801 
(arithmetic24 subcrhpag3 subc subc OP1_3 OP2_8 dr uimm3 HI "pag")
802 
(arithmetic24 addcbrhpof3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pof")
803 
(arithmetic24 subcbrhpof3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pof")
804 
 
805 
;add/sub register and immediate
806 
(define-pmacro (arithmetic25 name insn insn1 opc1 opc2 op1 op2 mode dir)
807 
  (dni name
808 
       (.str name "arithmetic" )
809 
       ((PIPE OS) (IDOC ALU))
810 
       (.str insn " $"op1 ",$hash$"dir"$"op2)
811 
       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
812 
       (set mode op1 (insn1 mode op1 op2 cbit))
813 
       ()
814 
  )
815 
)
816 
(arithmetic25 addcrbhpof addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pof")
817 
(arithmetic25 subcrbhpof subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pof")
818 
(arithmetic25 addcbrhpag addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pag")
819 
(arithmetic25 subcbrhpag subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pag")
820 
 
821 
;add/sub register and immediate
822 
(define-pmacro (arithmetic10 name insn insn1 opc1 opc2 op1 op2 mode)
823 
  (dni name
824 
       (.str name "arithmetic" )
825 
       ((PIPE OS) (IDOC ALU))
826 
       (.str insn " $"op1 ",$hash$"op2)
827 
       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
828 
       (set mode op1 (insn1 mode op1 op2))
829 
       ()
830 
  )
831 
)
832 
(arithmetic10 addri add add OP1_0 OP2_8 dr uimm3 HI)
833 
(arithmetic10 subri sub sub OP1_2 OP2_8 dr uimm3 HI)
834 
(arithmetic10 addbri addb add OP1_0 OP2_9 drb uimm3 QI)
835 
(arithmetic10 subbri subb sub OP1_2 OP2_9 drb uimm3 QI)
836 
 
837 
;add/sub register and immediate
838 
(define-pmacro (arithmetic11 name insn insn1 opc1 opc2 op1 op2 mode)
839 
  (dni name
840 
       (.str name "arithmetic" )
841 
       ((PIPE OS) (IDOC ALU))
842 
       (.str insn " $"op1 ",$hash$"op2)
843 
       (+ opc1 opc2 op1 op2)
844 
       (set mode op1 (insn1 mode op1 op2))
845 
       ()
846 
  )
847 
)
848 
(arithmetic11 addrim add add OP1_0 OP2_6 reg8 uimm16 HI)
849 
(arithmetic11 subrim sub sub OP1_2 OP2_6 reg8 uimm16 HI)
850 
 
851 
;add/sub register and immediate
852 
(define-pmacro (arithmetic12 name insn insn1 opc1 opc2 op1 op2 mode)
853 
  (dni name
854 
       (.str name "arithmetic" )
855 
       ((PIPE OS) (IDOC ALU))
856 
       (.str insn " $"op1 ",$hash$"op2)
857 
       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
858 
       (set mode op1 (insn1 mode op1 op2))
859 
       ()
860 
  )
861 
)
862 
(arithmetic12 addbrim addb add OP1_0 OP2_7 regb8 uimm8 QI)
863 
(arithmetic12 subbrim subb sub OP1_2 OP2_7 regb8 uimm8 QI)
864 
 
865 
;add/sub register and immediate with carry
866 
(define-pmacro (arithmetic13 name insn insn1 opc1 opc2 op1 op2 mode)
867 
  (dni name
868 
       (.str name "arithmetic" )
869 
       ((PIPE OS) (IDOC ALU))
870 
       (.str insn " $"op1 ",$hash$"op2)
871 
       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
872 
       (set mode op1 (insn1 mode op1 op2 cbit))
873 
       ()
874 
  )
875 
)
876 
(arithmetic13 addcri addc addc OP1_1 OP2_8 dr uimm3 HI)
877 
(arithmetic13 subcri subc subc OP1_3 OP2_8 dr uimm3 HI)
878 
(arithmetic13 addcbri addcb addc OP1_1 OP2_9 drb uimm3 QI)
879 
(arithmetic13 subcbri subcb subc OP1_3 OP2_9 drb uimm3 QI)
880 
 
881 
;add/sub register and immediate with carry
882 
(define-pmacro (arithmetic14 name insn insn1 opc1 opc2 op1 op2 mode)
883 
  (dni name
884 
       (.str name "arithmetic" )
885 
       ((PIPE OS) (IDOC ALU))
886 
       (.str insn " $"op1 ",$hash$"op2)
887 
       (+ opc1 opc2 op1 op2)
888 
       (set mode op1 (insn1 mode op1 op2 cbit))
889 
       ()
890 
  )
891 
)
892 
(arithmetic14 addcrim addc addc OP1_1 OP2_6 reg8 uimm16 HI)
893 
(arithmetic14 subcrim subc subc OP1_3 OP2_6 reg8 uimm16 HI)
894 
 
895 
;add/sub register and immediate with carry
896 
(define-pmacro (arithmetic15 name insn insn1 opc1 opc2 op1 op2 mode)
897 
  (dni name
898 
       (.str name "arithmetic" )
899 
       ((PIPE OS) (IDOC ALU))
900 
       (.str insn " $"op1 ",$hash$"op2)
901 
       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
902 
       (set mode op1 (insn1 mode op1 op2 cbit))
903 
       ()
904 
  )
905 
)
906 
(arithmetic15 addcbrim addcb addc OP1_1 OP2_7 regb8 uimm8 QI)
907 
(arithmetic15 subcbrim subcb subc OP1_3 OP2_7 regb8 uimm8 QI)
908 
 
909 
 
910 
;add/sub registers
911 
(define-pmacro (arithmetic name insn insn1 opc1 opc2 op1 op2 mode)
912 
  (dni name
913 
       (.str name "arithmetic" )
914 
       ((PIPE OS) (IDOC ALU))
915 
       (.str insn " $"op1 ",$"op2)
916 
       (+ opc1 opc2 op1 op2)
917 
       (set mode op1 (insn1 mode op1 op2))
918 
       ()
919 
  )
920 
)
921 
(arithmetic addr add add OP1_0 OP2_0 dr sr HI)
922 
(arithmetic subr sub sub OP1_2 OP2_0 dr sr HI)
923 
(arithmetic addbr addb add OP1_0 OP2_1 drb srb QI)
924 
(arithmetic subbr subb sub OP1_2 OP2_1 drb srb QI)
925 
 
926 
;add/sub register and indirect memory
927 
(define-pmacro (arithmetic1 name insn insn1 opc1 opc2 op1 op2 mode)
928 
  (dni name
929 
       (.str name "arithmetic" )
930 
       ((PIPE OS) (IDOC ALU))
931 
       (.str insn " $"op1 ",[$"op2"]")
932 
       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
933 
       (set mode op1 (insn1 mode op1 (mem HI op2)))
934 
       ()
935 
  )
936 
)
937 
(arithmetic1 add2 add add OP1_0 OP2_8 dr sr2 HI)
938 
(arithmetic1 sub2 sub sub OP1_2 OP2_8 dr sr2 HI)
939 
(arithmetic1 addb2 addb add OP1_0 OP2_9 drb sr2 QI)
940 
(arithmetic1 subb2 subb sub OP1_2 OP2_9 drb sr2 QI)
941 
 
942 
;add/sub register and indirect memory post increment
943 
(define-pmacro (arithmetic2 name insn insn1 opc1 opc2 op1 op2 mode)
944 
  (dni name
945 
       (.str name "arithmetic" )
946 
       ((PIPE OS) (IDOC ALU))
947 
       (.str insn " $"op1 ",[$"op2"+]")
948 
       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
949 
       (sequence ()
950 
           (set mode op1 (insn1 mode op1 (mem HI op2)))
951 
           (set HI op2 (add HI op2 (const 2)))
952 
       )
953 
       ()
954 
  )
955 
)
956 
(arithmetic2 add2i add add OP1_0 OP2_8 dr sr2 HI)
957 
(arithmetic2 sub2i sub sub OP1_2 OP2_8 dr sr2 HI)
958 
(arithmetic2 addb2i addb add OP1_0 OP2_9 drb sr2 QI)
959 
(arithmetic2 subb2i subb sub OP1_2 OP2_9 drb sr2 QI)
960 
 
961 
;add/sub registers with carry
962 
(define-pmacro (arithmetic3 name insn insn1 opc1 opc2 op1 op2 mode)
963 
  (dni name
964 
       (.str name "arithmetic" )
965 
       ((PIPE OS) (IDOC ALU))
966 
       (.str insn " $"op1 ",$"op2)
967 
       (+ opc1 opc2 op1 op2)
968 
       (set mode op1 (insn1 mode op1 op2 cbit))
969 
       ()
970 
  )
971 
)
972 
(arithmetic3 addcr addc addc OP1_1 OP2_0 dr sr HI)
973 
(arithmetic3 subcr subc subc OP1_3 OP2_0 dr sr HI)
974 
(arithmetic3 addbcr addcb addc OP1_1 OP2_1 drb srb QI)
975 
(arithmetic3 subbcr subcb subc OP1_3 OP2_1 drb srb QI)
976 
 
977 
 
978 
;add/sub register and indirect memory
979 
(define-pmacro (arithmetic4 name insn insn1 opc1 opc2 op1 op2 mode)
980 
  (dni name
981 
       (.str name "arithmetic" )
982 
       ((PIPE OS) (IDOC ALU))
983 
       (.str insn " $"op1 ",[$"op2"]")
984 
       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
985 
       (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
986 
       ()
987 
  )
988 
)
989 
(arithmetic4 addcr2 addc addc OP1_1 OP2_8 dr sr2 HI)
990 
(arithmetic4 subcr2 subc subc OP1_3 OP2_8 dr sr2 HI)
991 
(arithmetic4 addbcr2 addcb addc OP1_1 OP2_9 drb sr2 QI)
992 
(arithmetic4 subbcr2 subcb subc OP1_3 OP2_9 drb sr2 QI)
993 
 
994 
;add/sub register and indirect memory post increment
995 
(define-pmacro (arithmetic5 name insn insn1 opc1 opc2 op1 op2 mode)
996 
  (dni name
997 
       (.str name "arithmetic" )
998 
       ((PIPE OS) (IDOC ALU))
999 
       (.str insn " $"op1 ",[$"op2"+]")
1000 
       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
1001 
       (sequence ()
1002 
           (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
1003 
           (set HI op2 (add HI op2 (const 2)))
1004 
       )
1005 
       ()
1006 
  )
1007 
)
1008 
(arithmetic5 addcr2i addc addc OP1_1 OP2_8 dr sr2 HI)
1009 
(arithmetic5 subcr2i subc subc OP1_3 OP2_8 dr sr2 HI)
1010 
(arithmetic5 addbcr2i addcb addc OP1_1 OP2_9 drb sr2 QI)
1011 
(arithmetic5 subbcr2i subcb subc OP1_3 OP2_9 drb sr2 QI)
1012 
 
1013 
;add/sub register and direct memory
1014 
(define-pmacro (arithmetic6 name insn insn1 opc1 opc2 op1 op2 mode)
1015 
  (dni name
1016 
       (.str name "arithmetic" )
1017 
       ((PIPE OS) (IDOC ALU))
1018 
       (.str insn " $"op1 ",$"op2)
1019 
       (+ opc1 opc2 op1 op2)
1020 
       (set mode op1 (insn1 mode op1 op2))
1021 
       ()
1022 
  )
1023 
)
1024 
 
1025 
;add/sub register and direct memory
1026 
(define-pmacro (arithmetic7 name insn insn1 opc1 opc2 op1 op2 mode)
1027 
  (dni name
1028 
       (.str name "arithmetic" )
1029 
       ((PIPE OS) (IDOC ALU))
1030 
       (.str insn " $"op1 ",$"op2)
1031 
       (+ opc1 opc2 op2 op1)
1032 
       (set (mem HI op1) (insn1 (mem HI op1) op2))
1033 
       ()
1034 
  )
1035 
)
1036 
(arithmetic6 addrm2 add add OP1_0 OP2_2 regmem8 memgr8 HI)
1037 
(arithmetic7 addrm3 add add OP1_0 OP2_4 memgr8 regmem8 HI)
1038 
(arithmetic6 addrm add add OP1_0 OP2_2 reg8 memory HI)
1039 
(arithmetic7 addrm1 add add OP1_0 OP2_4 memory reg8 HI)
1040 
(arithmetic6 subrm3 sub sub OP1_2 OP2_2 regmem8 memgr8 HI)
1041 
(arithmetic7 subrm2 sub sub OP1_2 OP2_4 memgr8 regmem8 HI)
1042 
(arithmetic6 subrm1 sub sub OP1_2 OP2_2 reg8 memory HI)
1043 
(arithmetic7 subrm sub sub OP1_2 OP2_4 memory reg8 HI)
1044 
(arithmetic6 addbrm2 addb add OP1_0 OP2_3 regbmem8 memgr8 QI)
1045 
(arithmetic7 addbrm3 addb add OP1_0 OP2_5 memgr8 regbmem8 QI)
1046 
(arithmetic6 addbrm addb add OP1_0 OP2_3 regb8 memory QI)
1047 
(arithmetic7 addbrm1 addb add OP1_0 OP2_5 memory regb8 QI)
1048 
(arithmetic6 subbrm3 subb sub OP1_2 OP2_3 regbmem8 memgr8 QI)
1049 
(arithmetic7 subbrm2 subb sub OP1_2 OP2_5 memgr8 regbmem8 QI)
1050 
(arithmetic6 subbrm1 subb sub OP1_2 OP2_3 regb8 memory QI)
1051 
(arithmetic7 subbrm subb sub OP1_2 OP2_5 memory regb8 QI)
1052 
 
1053 
;add/sub registers with carry
1054 
(define-pmacro (arithmetic8 name insn insn1 opc1 opc2 op1 op2 mode)
1055 
  (dni name
1056 
       (.str name "arithmetic" )
1057 
       ((PIPE OS) (IDOC ALU))
1058 
       (.str insn " $"op1 ",$"op2)
1059 
       (+ opc1 opc2 op1 op2)
1060 
       (set mode op1 (insn1 mode op1 op2 cbit))
1061 
       ()
1062 
  )
1063 
)
1064 
 
1065 
;add/sub registers with carry
1066 
(define-pmacro (arithmetic9 name insn insn1 opc1 opc2 op1 op2 mode)
1067 
  (dni name
1068 
       (.str name "arithmetic" )
1069 
       ((PIPE OS) (IDOC ALU))
1070 
       (.str insn " $"op1 ",$"op2)
1071 
       (+ opc1 opc2 op2 op1)
1072 
       (set (mem HI op1) (insn1 (mem HI op1) op2 cbit))
1073 
       ()
1074 
  )
1075 
)
1076 
(arithmetic8 addcrm2 addc addc OP1_1 OP2_2 regmem8 memgr8 HI)
1077 
(arithmetic9 addcrm3 addc addc OP1_1 OP2_4  memgr8 regmem8 HI)
1078 
(arithmetic8 addcrm addc addc OP1_1 OP2_2 reg8 memory HI)
1079 
(arithmetic9 addcrm1 addc addc OP1_1 OP2_4  memory reg8 HI)
1080 
(arithmetic8 subcrm3 subc subc OP1_3 OP2_2  regmem8 memgr8 HI)
1081 
(arithmetic9 subcrm2 subc subc OP1_3 OP2_4 memgr8 regmem8 HI)
1082 
(arithmetic8 subcrm1 subc subc OP1_3 OP2_2  reg8 memory HI)
1083 
(arithmetic9 subcrm subc subc OP1_3 OP2_4 memory reg8 HI)
1084 
(arithmetic8 addcbrm2 addcb addc OP1_1 OP2_3 regbmem8 memgr8 QI)
1085 
(arithmetic9 addcbrm3 addcb addc OP1_1 OP2_5  memgr8 regbmem8 QI)
1086 
(arithmetic8 addcbrm addcb addc OP1_1 OP2_3 regb8 memory QI)
1087 
(arithmetic9 addcbrm1 addcb addc OP1_1 OP2_5  memory regb8 QI)
1088 
(arithmetic8 subcbrm3 subcb subc OP1_3 OP2_3  regbmem8 memgr8 QI)
1089 
(arithmetic9 subcbrm2 subcb subc OP1_3 OP2_5 memgr8 regbmem8 QI)
1090 
(arithmetic8 subcbrm1 subcb subc OP1_3 OP2_3  regb8 memory QI)
1091 
(arithmetic9 subcbrm subcb subc OP1_3 OP2_5 memory regb8 QI)
1092 
 
1093 
; MUL Rwn,Rwm
1094 
(dni muls "signed multiplication"
1095 
     ((PIPE OS) (IDOC ALU))
1096 
     "mul $src1,$src2"
1097 
     (+ OP1_0 OP2_11 src1 src2)
1098 
     (reg SI h-md 0)
1099 
     ()
1100 
)
1101 
; MULU Rwn,Rwm
1102 
(dni mulu "unsigned multiplication"
1103 
     ((PIPE OS) (IDOC ALU))
1104 
     "mulu $src1,$src2"
1105 
     (+ OP1_1 OP2_11 src1 src2)
1106 
     (reg SI h-md 0)
1107 
     ()
1108 
)
1109 
; DIV Rwn
1110 
(dni div "16-by-16 signed division"
1111 
     ((PIPE OS) (IDOC ALU))
1112 
     "div $srdiv"
1113 
     (+ OP1_4 OP2_11 srdiv )
1114 
     (sequence ()
1115 
         (set HI (reg HI h-cr 6) (div HI (reg HI h-cr 6) srdiv))
1116 
         (set HI (reg HI h-cr 7) (mod HI (reg HI h-cr 6) srdiv))
1117 
     )
1118 
     ()
1119 
)
1120 
; DIVL Rwn
1121 
(dni divl "32-by16 signed division"
1122 
     ((PIPE OS) (IDOC ALU))
1123 
     "divl $srdiv"
1124 
     (+ OP1_6 OP2_11 srdiv )
1125 
     (sequence ()
1126 
         (set HI (reg HI h-cr 6) (div SI (reg SI h-md 0) srdiv))
1127 
         (set HI (reg HI h-cr 7) (mod SI (reg SI h-md 0) srdiv))
1128 
     )
1129 
     ()
1130 
)
1131 
; DIVLU Rwn
1132 
(dni divlu "32-by16 unsigned division"
1133 
     ((PIPE OS) (IDOC ALU))
1134 
     "divlu $srdiv"
1135 
     (+ OP1_7 OP2_11 srdiv )
1136 
     (sequence ()
1137 
         (set HI (reg HI h-cr 6) (udiv SI (reg SI h-md 0) srdiv))
1138 
         (set HI (reg HI h-cr 7) (umod SI (reg SI h-md 0) srdiv))
1139 
     )
1140 
     ()
1141 
)
1142 
; DIVU Rwn
1143 
(dni divu "16-by-16 unsigned division"
1144 
     ((PIPE OS) (IDOC ALU))
1145 
     "divu $srdiv"
1146 
     (+ OP1_5 OP2_11 srdiv )
1147 
     (sequence ()
1148 
         (set HI (reg HI h-cr 6) (udiv HI (reg HI h-cr 6) srdiv))
1149 
         (set HI (reg HI h-cr 7) (umod HI (reg HI h-cr 6) srdiv))
1150 
     )
1151 
     ()
1152 
)
1153 
 
1154 
;Integer one's complement
1155 
; CPL Rwn
1156 
(dni cpl "Integer Ones complement"
1157 
     ((PIPE OS) (IDOC MISC))
1158 
     "cpl $dr"
1159 
     (+ OP1_9 OP2_1 dr (f-op-bit4 0))
1160 
     (set dr (inv HI dr))
1161 
     ()
1162 
)
1163 
 
1164 
;Bytes one's complement
1165 
; CPLB Rbn
1166 
(dni cplb "Byte Ones complement"
1167 
     ((PIPE OS) (IDOC MISC))
1168 
     "cplb $drb"
1169 
     (+ OP1_11 OP2_1 drb (f-op-bit4 0))
1170 
     (set drb (inv QI drb))
1171 
     ()
1172 
)
1173 
;Integer two's complement
1174 
; NEG Rwn
1175 
(dni neg "Integer two's complement"
1176 
     ((PIPE OS) (IDOC MISC))
1177 
     "neg $dr"
1178 
     (+ OP1_8 OP2_1 dr (f-op-bit4 0))
1179 
     (set dr (neg HI dr))
1180 
     ()
1181 
)
1182 
;Bytes two's complement
1183 
; NEGB Rbn
1184 
(dni negb "byte twos complement"
1185 
     ((PIPE OS) (IDOC MISC))
1186 
     "negb $drb"
1187 
     (+ OP1_10 OP2_1 drb (f-op-bit4 0))
1188 
     (set drb (neg QI drb))
1189 
     ()
1190 
)
1191 
 
1192 
;****************************************************************
1193 
;logical insn
1194 
;****************************************************************
1195 
;and/or/xor registers
1196 
(define-pmacro (logical name insn insn1 opc1 opc2 op1 op2 mode)
1197 
  (dni name
1198 
       (.str name "logical" )
1199 
       ((PIPE OS) (IDOC ALU))
1200 
       (.str insn " $"op1 ",$"op2)
1201 
       (+ opc1 opc2 op1 op2)
1202 
       (set mode op1 (insn1 mode op1 op2))
1203 
       ()
1204 
  )
1205 
)
1206 
 
1207 
(logical andr and and OP1_6 OP2_0 dr sr HI)
1208 
(logical orr or or OP1_7 OP2_0 dr sr HI)
1209 
(logical xorr xor xor OP1_5 OP2_0 dr sr HI)
1210 
(logical andbr andb and OP1_6 OP2_1 drb srb QI)
1211 
(logical orbr orb or OP1_7 OP2_1 drb srb QI)
1212 
(logical xorbr xorb xor OP1_5 OP2_1 drb srb QI)
1213 
 
1214 
;and/or/xor register and immediate
1215 
(define-pmacro (logical1 name insn insn1 opc1 opc2 op1 op2 mode)
1216 
  (dni name
1217 
       (.str name "logical" )
1218 
       ((PIPE OS) (IDOC ALU))
1219 
       (.str insn " $"op1 ",$hash$"op2)
1220 
       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
1221 
       (set mode op1 (insn1 mode op1 op2))
1222 
       ()
1223 
  )
1224 
)
1225 
(logical1 andri and and OP1_6 OP2_8 dr uimm3 HI)
1226 
(logical1 orri or or OP1_7 OP2_8 dr uimm3 HI)
1227 
(logical1 xorri xor xor OP1_5 OP2_8 dr uimm3 HI)
1228 
(logical1 andbri andb and OP1_6 OP2_9 drb uimm3 QI)
1229 
(logical1 orbri orb or OP1_7 OP2_9 drb uimm3 QI)
1230 
(logical1 xorbri xorb xor OP1_5 OP2_9 drb uimm3 QI)
1231 
 
1232 
;and/or/xor register and immediate
1233 
(define-pmacro (logical2 name insn insn1 opc1 opc2 op1 op2 mode)
1234 
  (dni name
1235 
       (.str name "logical" )
1236 
       ((PIPE OS) (IDOC ALU))
1237 
       (.str insn " $"op1 ",$hash$"op2)
1238 
       (+ opc1 opc2 op1 op2)
1239 
       (set mode op1 (insn1 mode op1 op2))
1240 
       ()
1241 
  )
1242 
)
1243 
(logical2 andrim and and OP1_6 OP2_6 reg8 uimm16 HI)
1244 
(logical2 orrim or or OP1_7 OP2_6 reg8 uimm16 HI)
1245 
(logical2 xorrim xor xor OP1_5 OP2_6 reg8 uimm16 HI)
1246 
 
1247 
;and/or/xor register and immediate
1248 
(define-pmacro (logical3 name insn insn1 opc1 opc2 op1 op2 mode)
1249 
  (dni name
1250 
       (.str name "logical" )
1251 
       ((PIPE OS) (IDOC ALU))
1252 
       (.str insn " $"op1 ",$hash$"op2)
1253 
       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
1254 
       (set mode op1 (insn1 mode op1 op2))
1255 
       ()
1256 
  )
1257 
)
1258 
(logical3 andbrim andb and OP1_6 OP2_7 regb8 uimm8 QI)
1259 
(logical3 orbrim orb or OP1_7 OP2_7 regb8 uimm8 QI)
1260 
(logical3 xorbrim xorb xor OP1_5 OP2_7 regb8 uimm8 QI)
1261 
 
1262 
;and/or/xor register and indirect memory
1263 
(define-pmacro (logical4 name insn insn1 opc1 opc2 op1 op2 mode)
1264 
  (dni name
1265 
       (.str name "logical" )
1266 
       ((PIPE OS) (IDOC ALU))
1267 
       (.str insn " $"op1 ",[$"op2"]")
1268 
       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
1269 
       (set mode op1 (insn1 mode op1 (mem HI op2)))
1270 
       ()
1271 
  )
1272 
)
1273 
(logical4 and2 and and OP1_6 OP2_8 dr sr2 HI)
1274 
(logical4 or2 or or OP1_7 OP2_8 dr sr2 HI)
1275 
(logical4 xor2 xor xor OP1_5 OP2_8 dr sr2 HI)
1276 
(logical4 andb2 andb and OP1_6 OP2_9 drb sr2 QI)
1277 
(logical4 orb2 orb or OP1_7 OP2_9 drb sr2 QI)
1278 
(logical4 xorb2 xorb xor OP1_5 OP2_9 drb sr2 QI)
1279 
 
1280 
;and/or/xor register and indirect memory post increment
1281 
(define-pmacro (logical5 name insn insn1 opc1 opc2 op1 op2 mode)
1282 
  (dni name
1283 
       (.str name "logical" )
1284 
       ((PIPE OS) (IDOC ALU))
1285 
       (.str insn " $"op1 ",[$"op2"+]")
1286 
       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
1287 
       (sequence ()
1288 
           (set mode op1 (insn1 mode op1 (mem HI op2)))
1289 
           (set HI op2 (add HI op2 (const 2)))
1290 
       )
1291 
       ()
1292 
  )
1293 
)
1294 
(logical5 and2i and and OP1_6 OP2_8 dr sr2 HI)
1295 
(logical5 or2i or or OP1_7 OP2_8 dr sr2 HI)
1296 
(logical5 xor2i xor xor OP1_5 OP2_8 dr sr2 HI)
1297 
(logical5 andb2i andb and OP1_6 OP2_9 drb sr2 QI)
1298 
(logical5 orb2i orb or OP1_7 OP2_9 drb sr2 QI)
1299 
(logical5 xorb2i xorb xor OP1_5 OP2_9 drb sr2 QI)
1300 
 
1301 
;add/sub register and immediate
1302 
(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode dir)
1303 
  (dni name
1304 
       (.str name "arithmetic" )
1305 
       ((PIPE OS) (IDOC ALU))
1306 
       (.str insn " $"dir"$"op1 ",$"op2)
1307 
       (+ opc1 opc2 op1 op2)
1308 
       (set (mem HI op1) (insn1 (mem HI op1) op2 ))
1309 
       ()
1310 
  )
1311 
)
1312 
(logical7 andpofr and and OP1_6 OP2_2 reg8 upof16 HI "pof")
1313 
(logical7 orpofr or or OP1_7 OP2_2 reg8 upof16 HI "pof")
1314 
(logical7 xorpofr xor xor OP1_5 OP2_2 reg8 upof16 HI "pof")
1315 
(logical7 andbpofr andb and OP1_6 OP2_3 regb8 upof16 QI "pof")
1316 
(logical7 orbpofr orb or OP1_7 OP2_3 regb8 upof16 QI "pof")
1317 
(logical7 xorbpofr xorb xor OP1_5 OP2_3 regb8 upof16 QI "pof")
1318 
 
1319 
;add/sub register and immediate
1320 
(define-pmacro (logical8 name insn insn1 opc1 opc2 op1 op2 mode dir)
1321 
  (dni name
1322 
       (.str name "arithmetic" )
1323 
       ((PIPE OS) (IDOC ALU))
1324 
       (.str insn " $"dir"$"op1 ",$"op2)
1325 
       (+ opc1 opc2 op1 op2)
1326 
       (set (mem HI op1) (insn1 (mem HI op1) op2 ))
1327 
       ()
1328 
  )
1329 
)
1330 
(logical8 andrpofr and and OP1_6 OP2_4 upof16 reg8 HI "pof")
1331 
(logical8 orrpofr or or OP1_7 OP2_4 upof16 reg8 HI "pof")
1332 
(logical8 xorrpofr xor xor OP1_5 OP2_4 upof16 reg8 HI "pof")
1333 
(logical8 andbrpofr andb and OP1_6 OP2_5 upof16 regb8 QI "pof")
1334 
(logical8 orbrpofr orb or OP1_7 OP2_5 upof16 regb8 QI "pof")
1335 
(logical8 xorbrpofr xorb xor OP1_5 OP2_5 upof16 regb8 QI "pof")
1336 
 
1337 
;and/or/xor register and direct memory
1338 
(define-pmacro (logical6 name insn insn1 opc1 opc2 op1 op2 mode)
1339 
  (dni name
1340 
       (.str name "arithmetic" )
1341 
       ((PIPE OS) (IDOC ALU))
1342 
       (.str insn " $"op1 ",$"op2)
1343 
       (+ opc1 opc2 op1 op2)
1344 
       (set mode op1 (insn1 mode op1 op2))
1345 
       ()
1346 
  )
1347 
)
1348 
 
1349 
;and/or/xor register and direct memory
1350 
(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode)
1351 
  (dni name
1352 
       (.str name "arithmetic" )
1353 
       ((PIPE OS) (IDOC ALU))
1354 
       (.str insn " $"op1 ",$"op2)
1355 
       (+ opc1 opc2 op2 op1)
1356 
       (set (mem HI op1) (insn1 (mem HI op1) op2))
1357 
       ()
1358 
  )
1359 
)
1360 
(logical6 andrm2 and and OP1_6 OP2_2 regmem8 memgr8 HI)
1361 
(logical7 andrm3 and and OP1_6 OP2_4 memgr8 regmem8 HI)
1362 
(logical6 andrm and and OP1_6 OP2_2 reg8 memory HI)
1363 
(logical7 andrm1 and and OP1_6 OP2_4 memory reg8 HI)
1364 
(logical6 orrm3 or or OP1_7 OP2_2 regmem8 memgr8 HI)
1365 
(logical7 orrm2 or or OP1_7 OP2_4 memgr8 regmem8 HI)
1366 
(logical6 orrm1 or or OP1_7 OP2_2 reg8 memory HI)
1367 
(logical7 orrm or or OP1_7 OP2_4 memory reg8 HI)
1368 
(logical6 xorrm3 xor xor OP1_5 OP2_2 regmem8 memgr8 HI)
1369 
(logical7 xorrm2 xor xor OP1_5 OP2_4 memgr8 regmem8 HI)
1370 
(logical6 xorrm1 xor xor OP1_5 OP2_2 reg8 memory HI)
1371 
(logical7 xorrm xor xor OP1_5 OP2_4 memory reg8 HI)
1372 
(logical6 andbrm2 andb and OP1_6 OP2_3 regbmem8 memgr8 QI)
1373 
(logical7 andbrm3 andb and OP1_6 OP2_5 memgr8 regbmem8 QI)
1374 
(logical6 andbrm andb and OP1_6 OP2_3 regb8 memory QI)
1375 
(logical7 andbrm1 andb and OP1_6 OP2_5 memory regb8 QI)
1376 
(logical6 orbrm3 orb or OP1_7 OP2_3 regbmem8 memgr8 QI)
1377 
(logical7 orbrm2 orb or OP1_7 OP2_5 memgr8 regbmem8 QI)
1378 
(logical6 orbrm1 orb or OP1_7 OP2_3 regb8 memory QI)
1379 
(logical7 orbrm orb or OP1_7 OP2_5 memory regb8 QI)
1380 
(logical6 xorbrm3 xorb xor OP1_5 OP2_3 regbmem8 memgr8 QI)
1381 
(logical7 xorbrm2 xorb xor OP1_5 OP2_5 memgr8 regbmem8 QI)
1382 
(logical6 xorbrm1 xorb xor OP1_5 OP2_3 regb8 memory QI)
1383 
(logical7 xorbrm xorb xor OP1_5 OP2_5 memory regb8 QI)
1384 
 
1385 
;****************************************************************
1386 
;logical insn
1387 
;****************************************************************
1388 
;mov registers
1389 
(define-pmacro (move name insn opc1 opc2 op1 op2 mode)
1390 
  (dni name
1391 
       (.str name "mov registers" )
1392 
       ((PIPE OS) (IDOC MOVE))
1393 
       (.str insn " $"op1 ",$"op2)
1394 
       (+ opc1 opc2 op1 op2)
1395 
       (set mode op1 op2)
1396 
       ()
1397 
  )
1398 
)
1399 
(move movr mov OP1_15 OP2_0 dr sr HI)
1400 
(move movrb movb OP1_15 OP2_1 drb srb HI)
1401 
 
1402 
;mov register and immediate
1403 
(define-pmacro (move1 name insn opc1 opc2 op1 op2 mode)
1404 
  (dni name
1405 
       (.str name "move" )
1406 
       ((PIPE OS) (IDOC MOVE))
1407 
       (.str insn " $"op1 ",$hash$"op2)
1408 
       (+ opc1 opc2 op2 op1)
1409 
       (set mode op1 op2)
1410 
       ()
1411 
  )
1412 
)
1413 
(move1 movri mov  OP1_14 OP2_0 dri u4 HI)
1414 
(move1 movbri movb  OP1_14 OP2_1 srb u4 QI)
1415 
 
1416 
; MOV Rwn,#data16
1417 
(dni movi "move immediate to register"
1418 
     ((PIPE OS) (IDOC MOVE))
1419 
     "mov $reg8,$hash$uimm16"
1420 
     (+ OP1_14 OP2_6 reg8 uimm16)
1421 
     (set HI reg8 uimm16)
1422 
     ()
1423 
)
1424 
 
1425 
; MOVB reg,#data8
1426 
(dni movbi "move immediate to register"
1427 
     ((PIPE OS) (IDOC MOVE))
1428 
     "movb $regb8,$hash$uimm8"
1429 
     (+ OP1_14 OP2_7 regb8 uimm8 (f-op-bit8 0))
1430 
     (set QI regb8 uimm8)
1431 
     ()
1432 
)
1433 
 
1434 
;move and indirect memory
1435 
(define-pmacro (mov2 name insn opc1 opc2 op1 op2 mode)
1436 
  (dni name
1437 
       (.str name "move" )
1438 
       ((PIPE OS) (IDOC MOVE))
1439 
       (.str insn " $"op1 ",[$"op2"]")
1440 
       (+ opc1 opc2 op1 op2)
1441 
       (set mode op1 (mem HI op2))
1442 
       ()
1443 
  )
1444 
)
1445 
(mov2 movr2 mov OP1_10 OP2_8 dr sr HI)
1446 
(mov2 movbr2 movb OP1_10 OP2_9 drb sr QI)
1447 
 
1448 
;move and indirect memory
1449 
(define-pmacro (mov3 name insn opc1 opc2 op1 op2 mode)
1450 
  (dni name
1451 
       (.str name "move" )
1452 
       ((PIPE OS) (IDOC MOVE))
1453 
       (.str insn " [$"op2 "],$"op1)
1454 
       (+ opc1 opc2 op1 op2)
1455 
       (set mode op1 (mem HI op2))
1456 
       ()
1457 
  )
1458 
)
1459 
(mov3 movri2 mov OP1_11 OP2_8 dr sr HI)
1460 
(mov3 movbri2 movb OP1_11 OP2_9 drb sr QI)
1461 
 
1462 
;move and indirect memory
1463 
(define-pmacro (mov4 name insn opc1 opc2 op1 op2 mode)
1464 
  (dni name
1465 
       (.str name "move" )
1466 
       ((PIPE OS) (IDOC MOVE))
1467 
       (.str insn " [-$"op2 "],$"op1)
1468 
       (+ opc1 opc2 op1 op2)
1469 
       (sequence HI ()
1470 
          (set op1 (sub op2 (const HI 2)))
1471 
          (set HI (mem HI op2) op1)
1472 
       )
1473 
       ()
1474 
  )
1475 
)
1476 
(mov4 movri3 mov OP1_8 OP2_8 dr sr HI)
1477 
(mov4 movbri3 movb OP1_8 OP2_9 drb sr QI)
1478 
 
1479 
;mov register and indirect memory post increment
1480 
(define-pmacro (mov5 name insn opc1 opc2 op1 op2 mode)
1481 
  (dni name
1482 
       (.str name "move" )
1483 
       ((PIPE OS) (IDOC MOVE))
1484 
       (.str insn " $"op1 ",[$"op2"+]")
1485 
       (+ opc1 opc2 op1 op2)
1486 
       (sequence ()
1487 
           (set mode op1 (mem HI op2))
1488 
           (set HI op2 (add HI op2 (const 2)))
1489 
       )
1490 
       ()
1491 
  )
1492 
)
1493 
(mov5 mov2i mov OP1_9 OP2_8 dr sr HI)
1494 
(mov5 movb2i movb OP1_9 OP2_9 drb sr HI)
1495 
 
1496 
;mov indirect memory
1497 
(define-pmacro (mov6 name insn opc1 opc2 op1 op2 mode)
1498 
  (dni name
1499 
       (.str name "move" )
1500 
       ((PIPE OS) (IDOC MOVE))
1501 
       (.str insn " [$"op1 "],[$"op2"]")
1502 
       (+ opc1 opc2 op1 op2)
1503 
       (set HI (mem HI op1) (mem HI op2))
1504 
       ()
1505 
  )
1506 
)
1507 
(mov6 mov6i mov OP1_12 OP2_8 dr sr HI)
1508 
(mov6 movb6i movb OP1_12 OP2_9 dr sr HI)
1509 
 
1510 
;mov indirect memory
1511 
(define-pmacro (mov7 name insn opc1 opc2 op1 op2 mode)
1512 
  (dni name
1513 
       (.str name "move" )
1514 
       ((PIPE OS) (IDOC MOVE))
1515 
       (.str insn " [$"op1 "+],[$"op2"]")
1516 
       (+ opc1 opc2 op1 op2)
1517 
       (sequence ()
1518 
          (set mode (mem mode op1) (mem mode op2))
1519 
          (set mode op1 (add mode op1 (const mode 2)))
1520 
       )
1521 
       ()
1522 
  )
1523 
)
1524 
(mov7 mov7i mov OP1_13 OP2_8 dr sr HI)
1525 
(mov7 movb7i movb OP1_13 OP2_9 dr sr HI)
1526 
 
1527 
;mov indirect memory
1528 
(define-pmacro (mov8 name insn opc1 opc2 op1 op2 mode)
1529 
  (dni name
1530 
       (.str name "move" )
1531 
       ((PIPE OS) (IDOC MOVE))
1532 
       (.str insn " [$"op1 "],[$"op2"+]")
1533 
       (+ opc1 opc2 op1 op2)
1534 
       (sequence ()
1535 
          (set mode (mem mode op1) (mem mode op2))
1536 
          (set mode op2 (add mode op2 (const mode 2)))
1537 
       )
1538 
       ()
1539 
  )
1540 
)
1541 
(mov8 mov8i mov OP1_14 OP2_8 dr sr HI)
1542 
(mov8 movb8i movb OP1_14 OP2_9 dr sr HI)
1543 
 
1544 
;mov indirect memory
1545 
(define-pmacro (mov9 name insn opc1 opc2 op1 op2 mode)
1546 
  (dni name
1547 
       (.str name "move" )
1548 
       ((PIPE OS) (IDOC MOVE))
1549 
       (.str insn " $"op1 ",[$"op2"+$hash$"uimm16"]")
1550 
       (+ opc1 opc2 op1 op2 uimm16)
1551 
       (sequence mode ((mode tmp1))
1552 
           (set mode tmp1 (add HI op2 uimm16))
1553 
           (set mode op1 (mem HI tmp1))
1554 
       )
1555 
       ()
1556 
  )
1557 
)
1558 
(mov9 mov9i mov OP1_13 OP2_4 dr sr HI)
1559 
(mov9 movb9i movb OP1_15 OP2_4 drb sr QI)
1560 
 
1561 
;mov indirect memory
1562 
(define-pmacro (mov10 name insn opc1 opc2 op1 op2 mode)
1563 
  (dni name
1564 
       (.str name "move" )
1565 
       ((PIPE OS) (IDOC MOVE))
1566 
       (.str insn " [$"op2"+$hash$"uimm16 "],$"op1)
1567 
       (+ opc1 opc2 op1 op2 uimm16)
1568 
       (sequence mode ((mode tmp1))
1569 
           (set mode tmp1 (add HI op1 uimm16))
1570 
           (set mode (mem HI tmp1) op1)
1571 
       )
1572 
       ()
1573 
  )
1574 
)
1575 
(mov10 mov10i mov OP1_12 OP2_4 dr sr HI)
1576 
(mov10 movb10i movb OP1_14 OP2_4 drb sr QI)
1577 
 
1578 
;move and indirect memory
1579 
(define-pmacro (mov11 name insn opc1 opc2 op1 op2 mode)
1580 
  (dni name
1581 
       (.str name "move" )
1582 
       ((PIPE OS) (IDOC MOVE))
1583 
       (.str insn " [$"op1 "],$"op2)
1584 
       (+ opc1 opc2 (f-op-lbit4 0) op1 op2)
1585 
       (set (mem mode op1) (mem HI op2))
1586 
       ()
1587 
  )
1588 
)
1589 
(mov11 movri11 mov OP1_8 OP2_4 src2 memory HI)
1590 
(mov11 movbri11 movb OP1_10 OP2_4 src2 memory HI)
1591 
 
1592 
;move and indirect memory
1593 
(define-pmacro (mov12 name insn opc1 opc2 op1 op2 mode)
1594 
  (dni name
1595 
       (.str name "move" )
1596 
       ((PIPE OS) (IDOC MOVE))
1597 
       (.str insn " $"op2 ",[$"op1"]")
1598 
       (+ opc1 opc2 (f-op-lbit4 0) op1 op2)
1599 
       (set (mem HI op2) (mem mode op1))
1600 
       ()
1601 
  )
1602 
)
1603 
(mov12 movri12 mov OP1_9 OP2_4 src2 memory HI)
1604 
(mov12 movbri12 movb OP1_11 OP2_4 src2 memory HI)
1605 
 
1606 
(define-pmacro (movemem3 name insn opc1 opc2 op1 op2  dir)
1607 
  (dni name
1608 
       (.str name "move" )
1609 
       ((PIPE OS) (IDOC MOVE))
1610 
       (.str insn " $"op1 ",$hash$"dir"$"op2)
1611 
       (+ opc1 opc2 op1 op2)
1612 
       (set HI op1 op2)
1613 
       ()
1614 
  )
1615 
)
1616 
(movemem3 movehm5 mov OP1_14 OP2_6 regoff8 upof16 "pof")
1617 
(movemem3 movehm6 mov OP1_14 OP2_6 regoff8 upag16 "pag")
1618 
(movemem3 movehm7 mov OP1_14 OP2_6 regoff8 useg16 "segm")
1619 
(movemem3 movehm8 mov OP1_14 OP2_6 regoff8 usof16 "sof")
1620 
 
1621 
(define-pmacro (movemem4 name insn opc1 opc2 op1 op2 dir)
1622 
  (dni name
1623 
       (.str name "move" )
1624 
       ((PIPE OS) (IDOC MOVE))
1625 
       (.str insn " $"op1 ",$hash$"dir"$"op2)
1626 
       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
1627 
       (set QI op1 op2)
1628 
       ()
1629 
  )
1630 
)
1631 
(movemem4 movehm9 movb OP1_14 OP2_7 regb8 uimm8 "pof")
1632 
(movemem4 movehm10 movb OP1_14 OP2_7 regoff8 uimm8 "pag")
1633 
 
1634 
(define-pmacro (movemem name insn opc1 opc2 op1 op2 mode dir)
1635 
  (dni name
1636 
       (.str name "move" )
1637 
       ((PIPE OS) (IDOC MOVE))
1638 
       (.str insn " $"op1 ",$"dir"$"op2)
1639 
       (+ opc1 opc2 op1 op2)
1640 
       (set mode op1 (mem HI op2))
1641 
       ()
1642 
  )
1643 
)
1644 
(movemem movrmp mov OP1_15 OP2_2 regoff8 upof16 HI "pof")
1645 
(movemem movrmp1 movb OP1_15 OP2_3 regb8 upof16 QI "pof")
1646 
(movemem movrmp2 mov OP1_15 OP2_2 regoff8 upag16 HI "pag")
1647 
(movemem movrmp3 movb OP1_15 OP2_3 regb8 upag16 QI "pag")
1648 
 
1649 
(define-pmacro (movemem1 name insn opc1 opc2 op1 op2 dir)
1650 
  (dni name
1651 
       (.str name "move" )
1652 
       ((PIPE OS) (IDOC MOVE))
1653 
       (.str insn " $"dir"$"op1 ",$"op2)
1654 
       (+ opc1 opc2 op2 op1)
1655 
       (set (mem HI op1) op2 )
1656 
       ()
1657 
  )
1658 
)
1659 
(movemem1 movrmp4 mov OP1_15 OP2_6  upof16 regoff8 "pof")
1660 
(movemem1 movrmp5 movb OP1_15 OP2_7 upof16 regb8 "pof")
1661 
 
1662 
(define-pmacro (movemem2 name insn opc1 opc2 op1 op2 mode dir)
1663 
  (dni name
1664 
       (.str name "move" )
1665 
       ((PIPE OS) (IDOC MOVE))
1666 
       (.str insn " $"op1 ",$hash$"dir"$"op2)
1667 
       (+ opc1 opc2 op2 op1)
1668 
       (set mode op1 op2)
1669 
       ()
1670 
  )
1671 
)
1672 
(movemem2 movehm1 mov OP1_14 OP2_0 dri u4 HI "pof")
1673 
(movemem2 movehm2 movb OP1_14 OP2_1 srb u4 QI "pof")
1674 
(movemem2 movehm3 mov OP1_14 OP2_0 dri u4 HI "pag")
1675 
(movemem2 movehm4 movb OP1_14 OP2_1 srb u4 QI "pag")
1676 
 
1677 
;move register and direct memory
1678 
(define-pmacro (move12 name insn opc1 opc2 op1 op2 mode)
1679 
  (dni name
1680 
       (.str name "move" )
1681 
       ((PIPE OS) (IDOC MOVE))
1682 
       (.str insn " $"op1 ",$"op2)
1683 
       (+ opc1 opc2 op1 op2)
1684 
       (set mode op1 (mem HI op2))
1685 
       ()
1686 
  )
1687 
)
1688 
 
1689 
;move register and direct memory
1690 
(define-pmacro (move13 name insn opc1 opc2 op1 op2 mode)
1691 
  (dni name
1692 
       (.str name "move" )
1693 
       ((PIPE OS) (IDOC MOVE))
1694 
       (.str insn " $"op1 ",$"op2)
1695 
       (+ opc1 opc2 op2 op1)
1696 
       (set (mem HI op1) op2)
1697 
       ()
1698 
  )
1699 
)
1700 
(move12 mve12 mov OP1_15 OP2_2 regmem8 memgr8 HI)
1701 
(move13 mve13 mov OP1_15 OP2_6 memgr8 regmem8 HI)
1702 
(move12 mover12 mov OP1_15 OP2_2 reg8 memory HI)
1703 
(move13 mvr13 mov OP1_15 OP2_6 memory reg8 HI)
1704 
(move12 mver12 movb OP1_15 OP2_3 regbmem8 memgr8 QI)
1705 
(move13 mver13 movb OP1_15 OP2_7 memgr8 regbmem8 QI)
1706 
(move12 movr12 movb OP1_15 OP2_3 regb8 memory QI)
1707 
(move13 movr13 movb OP1_15 OP2_7 memory regb8 QI)
1708 
 
1709 
; MOVBS Rw,Rb
1710 
(dni movbsrr "mov byte register with sign extension to word register"
1711 
     ((PIPE OS) (IDOC MOVE))
1712 
     "movbs $sr,$drb"
1713 
     (+ OP1_13 OP2_0 drb sr)
1714 
     (sequence ()
1715 
         (if QI (and QI drb (const 128))
1716 
                (set HI sr (or HI (const HI 65280) drb)))
1717 
         (set HI sr (and HI (const HI 255) drb))
1718 
     )
1719 
     ()
1720 
)
1721 
 
1722 
; MOVBZ Rw,Rb
1723 
(dni movbzrr "mov byte register with zero extension to word register"
1724 
     ((PIPE OS) (IDOC MOVE))
1725 
     "movbz $sr,$drb"
1726 
     (+ OP1_12 OP2_0 drb sr)
1727 
     (set HI sr (and HI (const HI 255) drb))
1728 
     ()
1729 
)
1730 
 
1731 
; MOVBS reg,POF mem
1732 
(dni movbsrpofm "mov memory to byte register"
1733 
     ((PIPE OS) (IDOC MOVE))
1734 
     "movbs $regmem8,$pof$upof16"
1735 
     (+ OP1_13 OP2_2 regmem8 upof16)
1736 
     (set QI regmem8 (mem HI upof16))
1737 
     ()
1738 
)
1739 
 
1740 
; MOVBS pof,reg
1741 
(dni movbspofmr "mov memory to byte register"
1742 
     ((PIPE OS) (IDOC MOVE))
1743 
     "movbs $pof$upof16,$regbmem8"
1744 
     (+ OP1_13 OP2_5 upof16 regbmem8 )
1745 
     (set QI  (mem HI upof16) regbmem8)
1746 
     ()
1747 
)
1748 
 
1749 
; MOVBZ reg,POF mem
1750 
(dni movbzrpofm "mov memory to byte register"
1751 
     ((PIPE OS) (IDOC MOVE))
1752 
     "movbz $reg8,$pof$upof16"
1753 
     (+ OP1_12 OP2_2 reg8 upof16)
1754 
     (set QI reg8 (mem HI upof16))
1755 
     ()
1756 
)
1757 
 
1758 
; MOVBZ pof,reg
1759 
(dni movbzpofmr "mov memory to byte register"
1760 
     ((PIPE OS) (IDOC MOVE))
1761 
     "movbz $pof$upof16,$regb8"
1762 
     (+ OP1_12 OP2_5 upof16 regb8 )
1763 
     (set QI  (mem HI upof16) regb8)
1764 
     ()
1765 
)
1766 
 
1767 
;move register and direct memory
1768 
(define-pmacro (move14 name insn opc1 opc2 op1 op2 )
1769 
  (dni name
1770 
       (.str name "move" )
1771 
       ((PIPE OS) (IDOC MOVE))
1772 
       (.str insn " $"op1 ",$"op2)
1773 
       (+ opc1 opc2 op1 op2)
1774 
       (set HI op1 (and HI (const HI 255) (mem QI op2)))
1775 
       ()
1776 
  )
1777 
)
1778 
 
1779 
;move register and direct memory
1780 
(define-pmacro (move15 name insn opc1 opc2 op1 op2 )
1781 
  (dni name
1782 
       (.str name "move" )
1783 
       ((PIPE OS) (IDOC MOVE))
1784 
       (.str insn " $"op1 ",$"op2)
1785 
       (+ opc1 opc2 op2 op1)
1786 
       (set HI (mem HI op1) (and HI (const HI 255) op2))
1787 
       ()
1788 
  )
1789 
)
1790 
(move14 movebs14 movbs OP1_13 OP2_2 regmem8 memgr8 )
1791 
(move15 movebs15 movbs OP1_13 OP2_5 memgr8 regbmem8 )
1792 
(move14 moverbs14 movbs OP1_13 OP2_2 reg8 memory )
1793 
(move15 movrbs15 movbs OP1_13 OP2_5 memory regb8 )
1794 
(move14 movebz14 movbz OP1_12 OP2_2 regmem8 memgr8 )
1795 
(move15 movebz15 movbz OP1_12 OP2_5 memgr8 regbmem8 )
1796 
(move14 moverbz14 movbz OP1_12 OP2_2 reg8 memory )
1797 
(move15 movrbz15 movbz OP1_12 OP2_5 memory regb8 )
1798 
 
1799 
 
1800 
;mov registers
1801 
(define-pmacro (moveb1 name insn opc1 opc2 op1 op2)
1802 
  (dni name
1803 
       (.str name "move" )
1804 
       ((PIPE OS) (IDOC MOVE))
1805 
       (.str insn " $"op2 ",$"op1)
1806 
       (+ opc1 opc2 op1 op2)
1807 
       (sequence ()
1808 
           (if QI (and QI op1 (const 128))
1809 
                  (set HI op2 (or HI (const HI 65280) op1)))
1810 
           (set HI op2 (and HI (const HI 255) op1))
1811 
       )
1812 
       ()
1813 
  )
1814 
)
1815 
(moveb1 movrbs movbs OP1_13 OP2_0 drb sr )
1816 
(moveb1 movrbz movbz OP1_12 OP2_0 drb sr )
1817 
 
1818 
 
1819 
 
1820 
;jump and call insns
1821 
;******************************************************************
1822 
;Absolute conditional jump
1823 
(define-pmacro (jmpabs name insn)
1824 
  (dni name
1825 
     (.str name "Absolute conditional jump" )
1826 
     ((PIPE OS) (IDOC JMP))
1827 
     (.str insn " $extcond,$caddr")
1828 
     (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone bit01 caddr)
1829 
     (sequence ((HI tmp1) (HI tmp2))
1830 
        (set tmp1 (mem HI caddr))
1831 
        (set tmp2 (sub HI pc (mem HI caddr)))
1832 
        (if (gt tmp2 (const 0)) (lt tmp2 (const 32)) (eq tmp2 (const 32))
1833 
            (set bitone (const 1)))
1834 
        (if (lt tmp2 (const 0)) (eq tmp2 (const 0)) (gt tmp2 (const 32))
1835 
            (set bitone (const 0)))
1836 
        (if (eq extcond (const 1) (ne extcond cc_Z))
1837 
             (set bit01 (const 0))
1838 
             (set HI pc (mem HI caddr)))
1839 
        (if (ne extcond (const 1) (eq extcond cc_Z))
1840 
             (set bit01 (const 1))
1841 
             (set HI pc (add HI pc (const 2))))
1842 
     )
1843 
     ()
1844 
  )
1845 
)
1846 
 
1847 
(jmpabs jmpa0 jmpa+)
1848 
(jmpabs jmpa1 jmpa)
1849 
 
1850 
; JMPA- cc,caddr
1851 
(dni jmpa- "Absolute conditional jump"
1852 
     (COND-CTI (PIPE OS) (IDOC JMP))
1853 
     "jmpa- $extcond,$caddr"
1854 
     (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone (f-op-1bit 1) caddr)
1855 
     (sequence ((HI tmp1) (HI tmp2))
1856 
        (set tmp1 (mem HI caddr))
1857 
        (set tmp2 (sub HI pc (mem HI caddr)))
1858 
        (if (gt tmp2 (const 0)) (lt tmp2 (const 32)) (eq tmp2 (const 32))
1859 
            (set bitone (const 1)))
1860 
        (if (lt tmp2 (const 0)) (eq tmp2 (const 0)) (gt tmp2 (const 32))
1861 
            (set bitone (const 0)))
1862 
        (set HI pc (add HI pc (const 2)))
1863 
     )
1864 
     ()
1865 
)
1866 
 
1867 
; JMPI cc,[Rwn]
1868 
(dni jmpi "Indirect conditional jump"
1869 
     (COND-CTI (PIPE OS) (IDOC JMP))
1870 
     "jmpi $icond,[$sr]"
1871 
     (+ OP1_9 OP2_12 icond sr)
1872 
     (sequence ()
1873 
        (if (eq icond (const 1))
1874 
             (set HI pc (mem HI sr)))
1875 
             (set HI pc (add HI pc (const 2)))
1876 
     )
1877 
     ()
1878 
)
1879 
 
1880 
(define-pmacro (jmprel name insn opc1)
1881 
  (dni name
1882 
       (.str name "conditional" )
1883 
       (COND-CTI (PIPE OS) (IDOC JMP))
1884 
       (.str insn " $cond,$rel")
1885 
       (+ opc1 OP2_13 rel)
1886 
       (sequence ()
1887 
           (if (eq cond (const 1))
1888 
               (sequence ()
1889 
                    (if QI (lt QI rel (const 0))
1890 
                           (sequence ()
1891 
                                (neg QI rel)
1892 
                                (add QI rel (const 1))
1893 
                                (mul QI rel (const 2))
1894 
                                (set HI pc (sub HI pc rel))
1895 
                           ))
1896 
                    (set HI pc (add HI pc (mul QI rel (const 2))))
1897 
               )
1898 
            )
1899 
            (set HI pc pc)
1900 
       )
1901 
       ()
1902 
  )
1903 
)
1904 
 
1905 
(jmprel jmpr_nenz jmpr  COND_NE_NZ )
1906 
(jmprel jmpr_sgt jmpr  COND_SGT )
1907 
(jmprel jmpr_z jmpr  COND_Z )
1908 
(jmprel jmpr_v jmpr  COND_V )
1909 
(jmprel jmpr_nv jmpr  COND_NV )
1910 
(jmprel jmpr_n jmpr  COND_N )
1911 
(jmprel jmpr_nn jmpr  COND_NN )
1912 
(jmprel jmpr_c jmpr  COND_C )
1913 
(jmprel jmpr_nc jmpr  COND_NC )
1914 
(jmprel jmpr_eq jmpr  COND_EQ )
1915 
(jmprel jmpr_ne jmpr  COND_NE )
1916 
(jmprel jmpr_ult jmpr  COND_ULT )
1917 
(jmprel jmpr_ule jmpr  COND_ULE )
1918 
(jmprel jmpr_uge jmpr  COND_UGE )
1919 
(jmprel jmpr_ugt jmpr  COND_UGT )
1920 
(jmprel jmpr_sle jmpr  COND_SLE )
1921 
(jmprel jmpr_sge jmpr  COND_SGE )
1922 
(jmprel jmpr_net jmpr  COND_NET )
1923 
(jmprel jmpr_uc jmpr  COND_UC )
1924 
(jmprel jmpr_slt jmpr  COND_SLT )
1925 
 
1926 
 
1927 
 
1928 
 
1929 
; JMPS seg,caddr
1930 
(dni jmpseg "absolute inter-segment jump"
1931 
     (UNCOND-CTI(PIPE OS) (IDOC JMP))
1932 
     "jmps $hash$segm$useg8,$hash$sof$usof16"
1933 
     (+ OP1_15 OP2_10 seg usof16)
1934 
     (sequence ()
1935 
          (if QI (eq BI sgtdisbit (const BI 0))
1936 
                 (set QI (reg h-cr 10) useg8))
1937 
                 (nop)
1938 
          (set HI pc usof16)
1939 
     )
1940 
     ()
1941 
)
1942 
 
1943 
; JMPS seg,caddr
1944 
(dni jmps "absolute inter-segment jump"
1945 
     (UNCOND-CTI(PIPE OS) (IDOC JMP))
1946 
     "jmps $seg,$caddr"
1947 
     (+ OP1_15 OP2_10 seg caddr)
1948 
     (sequence ()
1949 
          (if QI (eq BI sgtdisbit (const BI 0))
1950 
                 (set QI (reg h-cr 10) seg))
1951 
                 (nop)
1952 
          (set HI pc caddr)
1953 
     )
1954 
     ()
1955 
)
1956 
 
1957 
 
1958 
;relative jump if bit set
1959 
;JB bitaddrQ.q,rel
1960 
(dni jb "relative jump if bit set"
1961 
     ((PIPE OS) (IDOC JMP))
1962 
     "jb $genreg$dot$qlobit,$relhi"
1963 
     (+ OP1_8 OP2_10 genreg relhi qlobit (f-qhibit 0))
1964 
     (sequence ((HI tmp1) (HI tmp2))
1965 
          (set HI tmp1 genreg)
1966 
          (set HI tmp2 (const 1))
1967 
          (sll HI tmp2 qlobit)
1968 
          (set HI tmp2 (and tmp1 tmp2))
1969 
          (if (eq tmp2 (const 1))
1970 
             (sequence ()
1971 
                (if QI (lt QI relhi (const 0))
1972 
                       (set HI pc (add HI pc (mul QI relhi (const 2)))))
1973 
             ))
1974 
         (set HI pc (add HI pc (const 4)))
1975 
     )
1976 
     ()
1977 
)
1978 
 
1979 
;relative jump if bit set and clear bit
1980 
;JBC bitaddrQ.q,rel
1981 
(dni jbc "relative jump if bit set and clear bit"
1982 
     ((PIPE OS) (IDOC JMP))
1983 
     "jbc $genreg$dot$qlobit,$relhi"
1984 
     (+ OP1_10 OP2_10 genreg relhi qlobit (f-qhibit 0))
1985 
     (sequence ((HI tmp1) (HI tmp2))
1986 
          (set HI tmp1 genreg)
1987 
          (set HI tmp2 (const 1))
1988 
          (sll HI tmp2 qlobit)
1989 
          (set HI tmp2 (and tmp1 tmp2))
1990 
          (if (eq tmp2 (const 1))
1991 
             (sequence ()
1992 
                (if QI (lt QI relhi (const 0))
1993 
                       (set tmp2 (const 1))
1994 
                       (set tmp1 genreg)
1995 
                       (sll tmp2 qlobit)
1996 
                       (inv tmp2)
1997 
                       (set HI tmp1(and tmp1 tmp2))
1998 
                       (set HI genreg tmp1)
1999 
                       (set HI pc (add HI pc (mul QI relhi (const 2)))))
2000 
             ))
2001 
          (set HI pc (add HI pc (const 4)))
2002 
     )
2003 
     ()
2004 
)
2005 
 
2006 
;relative jump if bit set
2007 
;JNB bitaddrQ.q,rel
2008 
(dni jnb "relative jump if bit not set"
2009 
     ((PIPE OS) (IDOC JMP))
2010 
     "jnb $genreg$dot$qlobit,$relhi"
2011 
     (+ OP1_9 OP2_10 genreg relhi qlobit (f-qhibit 0))
2012 
     (sequence ((HI tmp1) (HI tmp2))
2013 
          (set HI tmp1 genreg)
2014 
          (set HI tmp2 (const 1))
2015 
          (sll HI tmp2 qlobit)
2016 
          (set HI tmp2 (and tmp1 tmp2))
2017 
          (if (eq tmp2 (const 0))
2018 
             (sequence ()
2019 
                (if QI (lt QI relhi (const 0))
2020 
                       (set HI pc (add HI pc (mul QI relhi (const 2)))))
2021 
             ))
2022 
          (set HI pc (add HI pc (const 4)))
2023 
     )
2024 
     ()
2025 
)
2026 
 
2027 
;relative jump if bit not set and set bit
2028 
;JNBS bitaddrQ.q,rel
2029 
(dni jnbs "relative jump if bit not set and set bit"
2030 
     ((PIPE OS) (IDOC JMP))
2031 
     "jnbs $genreg$dot$qlobit,$relhi"
2032 
     (+ OP1_11 OP2_10 genreg relhi qlobit (f-qhibit 0))
2033 
     (sequence ((HI tmp1) (HI tmp2))
2034 
          (set HI tmp1 genreg)
2035 
          (set HI tmp2 (const 1))
2036 
          (sll HI tmp2 qlobit)
2037 
          (set HI tmp2 (and tmp1 tmp2))
2038 
          (if (eq tmp2 (const 0))
2039 
             (sequence ()
2040 
                (if QI (lt QI relhi (const 0))
2041 
                       (set tmp2 (const 1))
2042 
                       (set tmp1 reg8)
2043 
                       (sll tmp2 qbit)
2044 
                       (set BI tmp1(or tmp1 tmp2))
2045 
                       (set HI reg8 tmp1)
2046 
                       (set HI pc (add HI pc (mul QI relhi (const 2)))))
2047 
             ))
2048 
          (set HI pc (add HI pc (const 4)))
2049 
     )
2050 
     ()
2051 
)
2052 
 
2053 
 
2054 
;Absolute conditional call
2055 
(define-pmacro (callabs name insn)
2056 
  (dni name
2057 
     (.str name "Absolute conditional call" )
2058 
     ((PIPE OS) (IDOC JMP))
2059 
     (.str insn " $extcond,$caddr")
2060 
     (+ OP1_12 OP2_10 extcond (f-op-2bit 0) bit01 caddr)
2061 
     (sequence ()
2062 
        (if (eq extcond (const 1))
2063 
          (set bit01 (const 0))
2064 
          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2065 
          (set HI (mem HI (reg h-cr 9)) pc)
2066 
          (set HI pc (mem HI caddr)))
2067 
        (if (ne extcond (const 1))
2068 
          (set bit01 (const 1))
2069 
          (set HI pc (add HI pc (const 2))))
2070 
     )
2071 
     ()
2072 
  )
2073 
)
2074 
 
2075 
(callabs calla0 calla+)
2076 
(callabs calla1 calla)
2077 
 
2078 
; CALLA- cc,caddr
2079 
(dni calla- "Absolute conditional call"
2080 
     (COND-CTI (PIPE OS) (IDOC JMP))
2081 
     "calla- $extcond,$caddr"
2082 
     (+ OP1_12 OP2_10 extcond (f-op-bit3 1) caddr)
2083 
     (sequence ()
2084 
        (if (eq extcond (const 1))
2085 
          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2086 
          (set HI (mem HI (reg h-cr 9)) pc)
2087 
          (set HI pc (mem HI caddr)))
2088 
        (set HI pc (add HI pc (const 2)))
2089 
     )
2090 
     ()
2091 
)
2092 
 
2093 
; CALLI cc,[Rwn]
2094 
(dni calli "indirect subroutine call"
2095 
     (COND-CTI (PIPE OS) (IDOC JMP))
2096 
     "calli $icond,[$sr]"
2097 
     (+ OP1_10 OP2_11 icond sr)
2098 
     (sequence ()
2099 
         (if (eq icond (const 1))
2100 
             (sequence ()
2101 
                     (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2102 
                     (set HI (mem HI (reg h-cr 9)) pc)
2103 
                     (set HI pc (mem HI sr))
2104 
             )
2105 
         )
2106 
         (set HI pc (add HI pc (const 2)))
2107 
     )
2108 
     ()
2109 
)
2110 
 
2111 
; CALLR rel
2112 
(dni callr "Call subroutine with PC relative signed 8 bit offset"
2113 
     ( COND-CTI (PIPE OS) (IDOC JMP))
2114 
     "callr $rel"
2115 
     (+ OP1_11 OP2_11 rel)
2116 
     (sequence ()
2117 
          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2118 
          (set HI (mem HI (reg h-cr 9)) pc)
2119 
          (sequence ()
2120 
                (if QI (lt QI rel (const 0))
2121 
                       (sequence ()
2122 
                           (neg QI rel)
2123 
                           (add QI rel (const 1))
2124 
                           (mul QI rel (const 2))
2125 
                           (set HI pc (sub HI pc rel))
2126 
                       ))
2127 
                (set HI pc (add HI pc (mul QI rel (const 2))))
2128 
          )
2129 
      )
2130 
      ()
2131 
)
2132 
 
2133 
 
2134 
; CALLS seg,caddr
2135 
(dni callseg "call inter-segment subroutine"
2136 
     (UNCOND-CTI (PIPE OS) (IDOC JMP))
2137 
     "calls $hash$segm$useg8,$hash$sof$usof16"
2138 
     (+ OP1_13 OP2_10 useg8 usof16)
2139 
     (sequence ()
2140 
          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2141 
          (set HI (mem HI (reg h-cr 9)) (reg h-cr 10))
2142 
          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2143 
          (set HI (mem HI (reg h-cr 9)) pc)
2144 
          (if QI (eq BI sgtdisbit (const BI 0))
2145 
                 (set QI (reg h-cr 10) useg8))
2146 
                 (nop)
2147 
          (set HI pc usof16)
2148 
     )
2149 
     ()
2150 
)
2151 
 
2152 
; CALLS seg,caddr
2153 
(dni calls "call inter-segment subroutine"
2154 
     (UNCOND-CTI (PIPE OS) (IDOC JMP))
2155 
     "calls $seg,$caddr"
2156 
     (+ OP1_13 OP2_10 seg caddr)
2157 
     (sequence ()
2158 
          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2159 
          (set HI (mem HI (reg h-cr 9)) (reg h-cr 10))
2160 
          (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2161 
          (set HI (mem HI (reg h-cr 9)) pc)
2162 
          (if QI (eq BI sgtdisbit (const BI 0))
2163 
                 (set QI (reg h-cr 10) seg))
2164 
                 (nop)
2165 
          (set HI pc caddr)
2166 
     )
2167 
     ()
2168 
)
2169 
 
2170 
; PCALL reg,caddr
2171 
(dni pcall "push word and call absolute subroutine"
2172 
       (UNCOND-CTI (PIPE OS) (IDOC JMP))
2173 
       "pcall $reg8,$caddr"
2174 
       (+ OP1_14 OP2_2 reg8 caddr)
2175 
       (sequence ((HI tmp1))
2176 
            (set HI tmp1 reg8)
2177 
            (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2178 
            (set HI (mem HI (reg h-cr 9)) tmp1)
2179 
            (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2180 
            (set HI (mem HI (reg h-cr 9)) pc)
2181 
            (set HI pc caddr)
2182 
       )
2183 
       ()
2184 
)
2185 
 
2186 
; TRAP #uimm7
2187 
(dni trap "software trap"
2188 
       (UNCOND-CTI (PIPE OS) (IDOC JMP))
2189 
       "trap $hash$uimm7"
2190 
       (+ OP1_9 OP2_11 uimm7 (f-op-1bit 0))
2191 
       (sequence ()
2192 
            (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2193 
            (set HI (mem HI (reg h-cr 9)) (reg h-cr 4))
2194 
              (if QI (eq BI sgtdisbit (const BI 0))
2195 
                     (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2196 
                     (set HI (mem HI (reg h-cr 9)) (reg h-cr 10) )
2197 
              )
2198 
              (nop)
2199 
            (set HI (reg h-cr 10) (reg h-cr 11))
2200 
            (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2201 
            (set HI (mem HI (reg h-cr 9)) pc)
2202 
            (set HI pc (mul QI uimm7 (const 4)))
2203 
       )
2204 
       ()
2205 
)
2206 
 
2207 
;Return insns
2208 
; RET
2209 
(dni ret "return from subroutine"
2210 
       (UNCOND-CTI (PIPE OS) (IDOC JMP))
2211 
       "ret"
2212 
       (+ OP1_12 OP2_11 (f-op-bit8 0))
2213 
       (sequence ()
2214 
           (set HI pc (mem HI (reg h-cr 9)))
2215 
           (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
2216 
       )
2217 
       ()
2218 
)
2219 
 
2220 
; RETS
2221 
(dni rets "return from inter-segment sunroutine"
2222 
       (UNCOND-CTI (PIPE OS) (IDOC JMP))
2223 
       "rets"
2224 
       (+ OP1_13 OP2_11 (f-op-bit8 0))
2225 
       (sequence ()
2226 
           (set HI pc (mem HI (reg h-cr 9)))
2227 
           (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
2228 
              (if QI (eq BI sgtdisbit (const BI 0))
2229 
                     (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
2230 
              )
2231 
              (nop)
2232 
           (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
2233 
       )
2234 
       ()
2235 
)
2236 
 
2237 
; RETP reg
2238 
(dni retp "return from subroutine and pop word register"
2239 
       (UNCOND-CTI (PIPE OS) (IDOC JMP))
2240 
       "retp $reg8"
2241 
       (+ OP1_14 OP2_11 reg8)
2242 
       (sequence ((HI tmp1))
2243 
            (set HI pc (mem HI (reg h-cr 9)))
2244 
            (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
2245 
            (set HI tmp1 (mem HI (reg h-cr 9)))
2246 
            (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
2247 
            (set HI reg8 tmp1)
2248 
       )
2249 
       ()
2250 
)
2251 
 
2252 
; RETI
2253 
(dni reti "return from ISR"
2254 
       (UNCOND-CTI (PIPE OS) (IDOC JMP))
2255 
       "reti"
2256 
       (+ OP1_15 OP2_11 (f-op-lbit4 8) (f-op-bit4 8))
2257 
       (sequence ()
2258 
           (set HI pc (mem HI (reg h-cr 9)))
2259 
           (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
2260 
              (if QI (eq BI sgtdisbit (const BI 0))
2261 
                  (sequence ()
2262 
                       (set HI (reg h-cr 10) (mem HI (reg h-cr 9)))
2263 
                       (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
2264 
                  )
2265 
              )
2266 
              (nop)
2267 
           (set HI (reg h-cr 4) (mem HI (reg h-cr 9)))
2268 
           (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
2269 
       )
2270 
       ()
2271 
)
2272 
 
2273 
;stack operation insn
2274 
;******************************************************************
2275 
; POP reg
2276 
(dni pop "restore register from system stack"
2277 
     ((PIPE OS) (IDOC MISC))
2278 
     "pop $reg8"
2279 
     (+ OP1_15 OP2_12 reg8)
2280 
     (sequence ((HI tmp1))
2281 
           (set HI tmp1 (mem HI (reg h-cr 9)))
2282 
           (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2)))
2283 
           (set HI reg8 tmp1)
2284 
     )
2285 
     ()
2286 
)
2287 
 
2288 
; PUSH reg
2289 
(dni push "save register on system stack"
2290 
     ((PIPE OS) (IDOC MISC))
2291 
     "push $reg8"
2292 
     (+ OP1_14 OP2_12 reg8)
2293 
     (sequence ((HI tmp1))
2294 
           (set HI tmp1 reg8)
2295 
           (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2)))
2296 
           (set HI (mem HI (reg h-cr 9)) tmp1)
2297 
     )
2298 
     ()
2299 
)
2300 
 
2301 
;context switching insns
2302 
; SCXT reg,#data16
2303 
(dni scxti "Push word register on stack and update same with immediate data"
2304 
     ((PIPE OS) (IDOC MISC))
2305 
     "scxt $reg8,$hash$uimm16"
2306 
     (+ OP1_12 OP2_6 reg8 uimm16)
2307 
     (sequence ((HI tmp1) (HI tmp2))
2308 
         (set HI tmp1 reg8)
2309 
         (set HI tmp2 uimm16)
2310 
         (sub HI (reg HI h-cr 9) (const 2))
2311 
         (set HI (reg HI h-cr 9) tmp1)
2312 
         (set HI reg8 tmp2)
2313 
     )
2314 
     ()
2315 
)
2316 
 
2317 
; SCXT reg,POF mem
2318 
(dni scxtrpofm "mov memory to byte register"
2319 
     ((PIPE OS) (IDOC MOVE))
2320 
     "scxt $reg8,$pof$upof16"
2321 
     (+ OP1_13 OP2_6 reg8 upof16)
2322 
     (set QI reg8 (mem HI upof16))
2323 
     ()
2324 
)
2325 
 
2326 
; SCXT regmem8,memgr8
2327 
(dni scxtmg "Push word register on stack and update same with direct memory"
2328 
     ((PIPE OS) (IDOC MISC))
2329 
     "scxt $regmem8,$memgr8"
2330 
     (+ OP1_13 OP2_6 regmem8 memgr8)
2331 
     (sequence ((HI tmp1) (HI tmp2))
2332 
         (set HI tmp1 regmem8)
2333 
         (set HI tmp2 memgr8)
2334 
         (sub HI (reg HI h-cr 9) (const 2))
2335 
         (set HI (reg HI h-cr 9) tmp1)
2336 
         (set HI regmem8 tmp2)
2337 
     )
2338 
     ()
2339 
)
2340 
 
2341 
; SCXT reg,mem
2342 
(dni scxtm "Push word register on stack and update same with direct memory"
2343 
     ((PIPE OS) (IDOC MISC))
2344 
     "scxt $reg8,$memory"
2345 
     (+ OP1_13 OP2_6 reg8 memory)
2346 
     (sequence ((HI tmp1) (HI tmp2))
2347 
         (set HI tmp1 reg8)
2348 
         (set HI tmp2 memory)
2349 
         (sub HI (reg HI h-cr 9) (const 2))
2350 
         (set HI (reg HI h-cr 9) tmp1)
2351 
         (set HI reg8 tmp2)
2352 
     )
2353 
     ()
2354 
)
2355 
 
2356 
;No operation
2357 
; NOP
2358 
(dni nop "nop"
2359 
     ((PIPE OS) (IDOC MISC))
2360 
     "nop"
2361 
     (+ OP1_12 OP2_12 (f-op-bit8 0))
2362 
     ()
2363 
     ()
2364 
)
2365 
 
2366 
;*********system control instructions *********************/
2367 
 
2368 
(define-pmacro (sysctrl name insn opc1 opc2 op1 op2 op3)
2369 
  (dni name
2370 
       (.str name "miscellaneous" )
2371 
       ((PIPE OS) (IDOC MISC))
2372 
       (.str insn )
2373 
       (+ opc1 opc2 (f-op-lbit4 op1) (f-op-bit4 op2) (f-data8 op3) (f-op-bit8 op3))
2374 
       ()
2375 
       ()
2376 
  )
2377 
)
2378 
(sysctrl srstm srst  OP1_11 OP2_7 4 8 183 )
2379 
(sysctrl idlem idle  OP1_8 OP2_7 7 8 135)
2380 
(sysctrl pwrdnm pwrdn  OP1_9 OP2_7 6 8 151)
2381 
(sysctrl diswdtm diswdt  OP1_10 OP2_5 5 10 165)
2382 
(sysctrl enwdtm enwdt  OP1_8 OP2_5 7 10 133)
2383 
(sysctrl einitm einit  OP1_11 OP2_5 4 10 181)
2384 
(sysctrl srvwdtm srvwdt  OP1_10 OP2_7 5 8 167 )
2385 
 
2386 
;s/w brk
2387 
; SBRK
2388 
(dni sbrk "sbrk"
2389 
     ((PIPE OS) (IDOC MISC))
2390 
     "sbrk"
2391 
     (+ OP1_8 OP2_12 (f-op-bit8 0))
2392 
     ()
2393 
     ()
2394 
)
2395 
 
2396 
; atomic sequence
2397 
; ATOMIC #irang2
2398 
(dni atomic "begin atomic sequence"
2399 
     ((PIPE OS) (IDOC SYSC))
2400 
     "atomic $hash$uimm2"
2401 
     (+ OP1_13 OP2_1 (f-op-lbit2 0) uimm2 (f-op-bit4 0))
2402 
     (sequence ((HI count))
2403 
          (set HI count uimm2)
2404 
          (cond HI
2405 
            ((ne HI count (const 0))
2406 
            (sequence ()
2407 
               (set HI pc (add HI pc (const 2)))
2408 
               (set HI count (sub HI count (const 1)))
2409 
            ))
2410 
          )
2411 
          (set HI count (const 0))
2412 
      )
2413 
      ()
2414 
)
2415 
 
2416 
;extended register sequence
2417 
; EXTR #irang2
2418 
(dni extr "begin extended register sequence"
2419 
     ((PIPE OS) (IDOC SYSC))
2420 
     "extr $hash$uimm2"
2421 
     (+ OP1_13 OP2_1 (f-op-lbit2 2) uimm2 (f-op-bit4 0))
2422 
     (sequence ((HI count))
2423 
          (set HI count uimm2)
2424 
          (cond HI
2425 
            ((ne HI count (const 0))
2426 
            (sequence ()
2427 
               (set HI pc (add HI pc (const 2)))
2428 
               (set HI count (sub HI count (const 1)))
2429 
            ))
2430 
          )
2431 
          (set HI count (const 0))
2432 
      )
2433 
      ()
2434 
)
2435 
 
2436 
;extended page sequence
2437 
; EXTP Rw,#irang2
2438 
(dni extp "begin extended page sequence"
2439 
     ((PIPE OS) (IDOC SYSC))
2440 
     "extp $sr,$hash$uimm2"
2441 
     (+ OP1_13 OP2_12 (f-op-lbit2 1) uimm2 sr)
2442 
     (sequence ((HI count))
2443 
          (set HI count uimm2)
2444 
          (cond HI
2445 
            ((ne HI count (const 0))
2446 
            (sequence ()
2447 
               (set HI pc (add HI pc (const 2)))
2448 
               (set HI count (sub HI count (const 1)))
2449 
            ))
2450 
          )
2451 
          (set HI count (const 0))
2452 
      )
2453 
      ()
2454 
)
2455 
 
2456 
;extended page sequence
2457 
; EXTP #pag10,#irang2
2458 
(dni extp1 "begin extended page sequence"
2459 
     ((PIPE OS) (IDOC SYSC))
2460 
     "extp $hash$pagenum,$hash$uimm2"
2461 
     (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0))
2462 
     (sequence ((HI count))
2463 
          (set HI count uimm2)
2464 
          (cond HI
2465 
            ((ne HI count (const 0))
2466 
            (sequence ()
2467 
               (set HI pc (add HI pc (const 2)))
2468 
               (set HI count (sub HI count (const 1)))
2469 
            ))
2470 
          )
2471 
          (set HI count (const 0))
2472 
      )
2473 
      ()
2474 
)
2475 
 
2476 
; EXTP #pag10,#irang2
2477 
(dni extpg1 "begin extended page sequence"
2478 
     ((PIPE OS) (IDOC SYSC))
2479 
     "extp $hash$pag$upag16,$hash$uimm2"
2480 
     (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) upag16 )
2481 
     (sequence ((HI count))
2482 
          (set HI count uimm2)
2483 
          (cond HI
2484 
            ((ne HI count (const 0))
2485 
            (sequence ()
2486 
               (set HI pc (add HI pc (const 2)))
2487 
               (set HI count (sub HI count (const 1)))
2488 
            ))
2489 
          )
2490 
          (set HI count (const 0))
2491 
      )
2492 
      ()
2493 
)
2494 
 
2495 
;extended page and register sequence
2496 
; EXTPR Rw,#irang2
2497 
(dni extpr "begin extended page and register sequence"
2498 
     ((PIPE OS) (IDOC SYSC))
2499 
     "extpr $sr,$hash$uimm2"
2500 
     (+ OP1_13 OP2_12 (f-op-lbit2 3) uimm2 sr)
2501 
     (sequence ((HI count))
2502 
          (set HI count uimm2)
2503 
          (cond HI
2504 
            ((ne HI count (const 0))
2505 
            (sequence ()
2506 
               (set HI pc (add HI pc (const 2)))
2507 
               (set HI count (sub HI count (const 1)))
2508 
            ))
2509 
          )
2510 
          (set HI count (const 0))
2511 
      )
2512 
      ()
2513 
)
2514 
 
2515 
;extended page and register sequence
2516 
; EXTPR #pag10,#irang2
2517 
(dni extpr1 "begin extended page sequence"
2518 
     ((PIPE OS) (IDOC SYSC))
2519 
     "extpr $hash$pagenum,$hash$uimm2"
2520 
     (+ OP1_13 OP2_7 (f-op-lbit2 3) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0))
2521 
     (sequence ((HI count))
2522 
          (set HI count uimm2)
2523 
          (cond HI
2524 
            ((ne HI count (const 0))
2525 
            (sequence ()
2526 
               (set HI pc (add HI pc (const 2)))
2527 
               (set HI count (sub HI count (const 1)))
2528 
            ))
2529 
          )
2530 
          (set HI count (const 0))
2531 
      )
2532 
      ()
2533 
)
2534 
 
2535 
;extended segment sequence
2536 
; EXTS Rw,#irang2
2537 
(dni exts "begin extended segment sequence"
2538 
     ((PIPE OS) (IDOC SYSC))
2539 
     "exts $sr,$hash$uimm2"
2540 
     (+ OP1_13 OP2_12 (f-op-lbit2 0) uimm2 sr)
2541 
     (sequence ((HI count))
2542 
          (set HI count uimm2)
2543 
          (cond HI
2544 
            ((ne HI count (const 0))
2545 
            (sequence ()
2546 
               (set HI pc (add HI pc (const 2)))
2547 
               (set HI count (sub HI count (const 1)))
2548 
            ))
2549 
          )
2550 
          (set HI count (const 0))
2551 
      )
2552 
      ()
2553 
)
2554 
 
2555 
;extended segment sequence
2556 
; EXTS #seg8,#irang2
2557 
(dni exts1 "begin extended segment sequence"
2558 
     ((PIPE OS) (IDOC SYSC))
2559 
     "exts $hash$seghi8,$hash$uimm2"
2560 
     (+ OP1_13 OP2_7 (f-op-lbit2 0) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0))
2561 
     (sequence ((HI count))
2562 
          (set HI count uimm2)
2563 
          (cond HI
2564 
            ((ne HI count (const 0))
2565 
            (sequence ()
2566 
               (set HI pc (add HI pc (const 2)))
2567 
               (set HI count (sub HI count (const 1)))
2568 
            ))
2569 
          )
2570 
          (set HI count (const 0))
2571 
      )
2572 
      ()
2573 
)
2574 
 
2575 
;extended segment register sequence
2576 
; EXTSR Rwm,#irang2
2577 
(dni extsr "begin extended segment and register sequence"
2578 
     ((PIPE OS) (IDOC SYSC))
2579 
     "extsr $sr,$hash$uimm2"
2580 
     (+ OP1_13 OP2_12 (f-op-lbit2 2) uimm2 sr)
2581 
     (sequence ((HI count))
2582 
          (set HI count uimm2)
2583 
          (cond HI
2584 
            ((ne HI count (const 0))
2585 
            (sequence ()
2586 
               (set HI pc (add HI pc (const 2)))
2587 
               (set HI count (sub HI count (const 1)))
2588 
            ))
2589 
          )
2590 
          (set HI count (const 0))
2591 
      )
2592 
      ()
2593 
)
2594 
 
2595 
;extended segment register sequence
2596 
; EXTSR #pag10,#irang2
2597 
(dni extsr1 "begin extended segment and register sequence"
2598 
     ((PIPE OS) (IDOC SYSC))
2599 
     "extsr $hash$seghi8,$hash$uimm2"
2600 
     (+ OP1_13 OP2_7 (f-op-lbit2 2) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0))
2601 
     (sequence ((HI count))
2602 
          (set HI count uimm2)
2603 
          (cond HI
2604 
            ((ne HI count (const 0))
2605 
            (sequence ()
2606 
               (set HI pc (add HI pc (const 2)))
2607 
               (set HI count (sub HI count (const 1)))
2608 
            ))
2609 
          )
2610 
          (set HI count (const 0))
2611 
      )
2612 
      ()
2613 
)
2614 
 
2615 
;prioritize register
2616 
;PRIOR Rwn,Rwm
2617 
(dni prior "add registers"
2618 
     ((PIPE OS) (IDOC ALU))
2619 
     "prior $dr,$sr"
2620 
     (+ OP1_2 OP2_11 dr sr)
2621 
     (sequence ((HI count) (HI tmp1) (HI tmp2))
2622 
          (set HI count (const 0))
2623 
          (set HI tmp1 sr)
2624 
          (set HI tmp2 (and tmp1 (const 32768)))
2625 
          (cond HI
2626 
            ((ne HI tmp2 (const 1)) (ne HI sr (const 0))
2627 
               (sll HI tmp1 (const 1))
2628 
               (set HI tmp2 (and tmp1 (const 32768)))
2629 
               (set HI count (add HI count (const 1)))
2630 
            )
2631 
           )
2632 
           (set HI dr count)
2633 
      )
2634 
      ()
2635 
)
2636 
 
2637 
 
2638 
;bit instructions
2639 
;******************************************************************
2640 
;bit clear
2641 
(define-pmacro (bclear name insn opc1)
2642 
  (dni name
2643 
     (.str name "bit clear" )
2644 
     ((PIPE OS) (IDOC ALU))
2645 
     (.str insn " $reg8$dot$qbit")
2646 
     (+ opc1 OP2_14 reg8)
2647 
     (sequence ((HI tmp1) (HI tmp2))
2648 
     (set tmp2 (const 1))
2649 
     (set tmp1 reg8)
2650 
     (sll tmp2 qbit)
2651 
     (inv tmp2)
2652 
     (set BI tmp1(and tmp1 tmp2))
2653 
     (set HI reg8 tmp1))
2654 
     ()
2655 
  )
2656 
)
2657 
 
2658 
;clear direct bit
2659 
(dni bclr18 "bit logical MOVN"
2660 
     ((PIPE OS) (IDOC ALU))
2661 
     "bclr $RegNam"
2662 
     (+ OP1_11 OP2_14 RegNam)
2663 
     (sequence ((HI tmp1) (HI tmp2))
2664 
     (set tmp2 (const 1))
2665 
     (set tmp1 reg8)
2666 
     (sll tmp2 qbit)
2667 
     (inv tmp2)
2668 
     (set BI tmp1(and tmp1 tmp2))
2669 
     (set HI reg8 tmp1))
2670 
     ()
2671 
)
2672 
 
2673 
 
2674 
(bclear bclr0 bclr  QBIT_0 )
2675 
(bclear bclr1 bclr  QBIT_1 )
2676 
(bclear bclr2 bclr  QBIT_2 )
2677 
(bclear bclr3 bclr  QBIT_3 )
2678 
(bclear bclr4 bclr  QBIT_4 )
2679 
(bclear bclr5 bclr  QBIT_5 )
2680 
(bclear bclr6 bclr  QBIT_6 )
2681 
(bclear bclr7 bclr  QBIT_7 )
2682 
(bclear bclr8 bclr  QBIT_8 )
2683 
(bclear bclr9 bclr  QBIT_9 )
2684 
(bclear bclr10 bclr  QBIT_10 )
2685 
(bclear bclr11 bclr  QBIT_11 )
2686 
(bclear bclr12 bclr  QBIT_12 )
2687 
(bclear bclr13 bclr  QBIT_13 )
2688 
(bclear bclr14 bclr  QBIT_14 )
2689 
(bclear bclr15 bclr  QBIT_15 )
2690 
 
2691 
;set direct bit
2692 
(dni bset19 "bit logical MOVN"
2693 
     ((PIPE OS) (IDOC ALU))
2694 
     "bset $RegNam"
2695 
     (+ OP1_11 OP2_15 RegNam)
2696 
     (sequence ((HI tmp1) (HI tmp2))
2697 
     (set tmp2 (const 1))
2698 
     (set tmp1 reg8)
2699 
     (sll tmp2 qbit)
2700 
     (set BI tmp1(or tmp1 tmp2))
2701 
     (set HI reg8 tmp1))
2702 
     ()
2703 
)
2704 
 
2705 
;bit set
2706 
(define-pmacro (bitset name insn opc1)
2707 
  (dni name
2708 
     (.str name "bit set" )
2709 
     ((PIPE OS) (IDOC ALU))
2710 
     (.str insn " $reg8$dot$qbit")
2711 
     (+ opc1 OP2_15 reg8)
2712 
     (sequence ((HI tmp1) (HI tmp2))
2713 
     (set tmp2 (const 1))
2714 
     (set tmp1 reg8)
2715 
     (sll tmp2 qbit)
2716 
     (set BI tmp1(or tmp1 tmp2))
2717 
     (set HI reg8 tmp1))
2718 
     ()
2719 
  )
2720 
)
2721 
 
2722 
 
2723 
(bitset bset0 bset  QBIT_0 )
2724 
(bitset bset1 bset  QBIT_1 )
2725 
(bitset bset2 bset  QBIT_2 )
2726 
(bitset bset3 bset  QBIT_3 )
2727 
(bitset bset4 bset  QBIT_4 )
2728 
(bitset bset5 bset  QBIT_5 )
2729 
(bitset bset6 bset  QBIT_6 )
2730 
(bitset bset7 bset  QBIT_7 )
2731 
(bitset bset8 bset  QBIT_8 )
2732 
(bitset bset9 bset  QBIT_9 )
2733 
(bitset bset10 bset  QBIT_10 )
2734 
(bitset bset11 bset  QBIT_11 )
2735 
(bitset bset12 bset  QBIT_12 )
2736 
(bitset bset13 bset  QBIT_13 )
2737 
(bitset bset14 bset  QBIT_14 )
2738 
(bitset bset15 bset  QBIT_15 )
2739 
 
2740 
;mov direct bit
2741 
;BMOV bitaddrZ.z,bitaddrQ.q
2742 
(dni bmov "bit logical MOV"
2743 
     ((PIPE OS) (IDOC ALU))
2744 
     "bmov $reghi8$dot$qhibit,$reg8$dot$qlobit"
2745 
     (+ OP1_4 OP2_10 reg8 reghi8 qhibit qlobit)
2746 
     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
2747 
     (set HI tmp1 reghi8)
2748 
     (set HI tmp2 reg8)
2749 
     (set tmp3 (const 1))
2750 
     (set tmp4 (const 1))
2751 
     (sll tmp3 qlobit)
2752 
     (sll tmp4 qhibit)
2753 
     (and tmp1 tmp3)
2754 
     (and tmp2 tmp4)
2755 
     (set BI tmp1 tmp2)
2756 
     (set HI reghi8 tmp1)
2757 
     (set HI reg8 tmp2))
2758 
     ()
2759 
)
2760 
 
2761 
;movn direct bit
2762 
;BMOVN bitaddrZ.z,bitaddrQ.q
2763 
(dni bmovn "bit logical MOVN"
2764 
     ((PIPE OS) (IDOC ALU))
2765 
     "bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit"
2766 
     (+ OP1_3 OP2_10 reg8 reghi8 qhibit qlobit)
2767 
     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
2768 
     (set HI tmp1 reghi8)
2769 
     (set HI tmp2 reg8)
2770 
     (set tmp3 (const 1))
2771 
     (set tmp4 (const 1))
2772 
     (sll tmp3 qlobit)
2773 
     (sll tmp4 qhibit)
2774 
     (and tmp1 tmp3)
2775 
     (and tmp2 tmp4)
2776 
     (inv HI tmp2)
2777 
     (set BI tmp1 tmp2)
2778 
     (set HI reghi8 tmp1)
2779 
     (set HI reg8 tmp2))
2780 
     ()
2781 
)
2782 
 
2783 
;and direct bit
2784 
;BAND bitaddrZ.z,bitaddrQ.q
2785 
(dni band "bit logical AND"
2786 
     ((PIPE OS) (IDOC ALU))
2787 
     "band $reghi8$dot$qhibit,$reg8$dot$qlobit"
2788 
     (+ OP1_6 OP2_10 reg8 reghi8 qhibit qlobit)
2789 
     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
2790 
     (set HI tmp1 reghi8)
2791 
     (set HI tmp2 reg8)
2792 
     (set tmp3 (const 1))
2793 
     (set tmp4 (const 1))
2794 
     (sll tmp3 qlobit)
2795 
     (sll tmp4 qhibit)
2796 
     (and tmp1 tmp3)
2797 
     (and tmp2 tmp4)
2798 
     (set BI tmp1(and tmp1 tmp2))
2799 
     (set HI reghi8 tmp1)
2800 
     (set HI reg8 tmp2))
2801 
     ()
2802 
)
2803 
 
2804 
;or direct bit
2805 
;BOR bitaddrZ.z,bitaddrQ.q
2806 
(dni bor "bit logical OR"
2807 
     ((PIPE OS) (IDOC ALU))
2808 
     "bor $reghi8$dot$qhibit,$reg8$dot$qlobit"
2809 
     (+ OP1_5 OP2_10 reg8 reghi8 qhibit qlobit)
2810 
     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
2811 
     (set HI tmp1 reghi8)
2812 
     (set HI tmp2 reg8)
2813 
     (set tmp3 (const 1))
2814 
     (set tmp4 (const 1))
2815 
     (sll tmp3 qlobit)
2816 
     (sll tmp4 qhibit)
2817 
     (and tmp1 tmp3)
2818 
     (and tmp2 tmp4)
2819 
     (set BI tmp1(or tmp1 tmp2))
2820 
     (set HI reghi8 tmp1)
2821 
     (set HI reg8 tmp2))
2822 
     ()
2823 
)
2824 
 
2825 
;xor direct bit
2826 
;BXOR bitaddrZ.z,bitaddrQ.q
2827 
(dni bxor "bit logical XOR"
2828 
     ((PIPE OS) (IDOC ALU))
2829 
     "bxor $reghi8$dot$qhibit,$reg8$dot$qlobit"
2830 
     (+ OP1_7 OP2_10 reg8 reghi8 qhibit qlobit)
2831 
     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
2832 
     (set HI tmp1 reghi8)
2833 
     (set HI tmp2 reg8)
2834 
     (set tmp3 (const 1))
2835 
     (set tmp4 (const 1))
2836 
     (sll tmp3 qlobit)
2837 
     (sll tmp4 qhibit)
2838 
     (and tmp1 tmp3)
2839 
     (and tmp2 tmp4)
2840 
     (set BI tmp1(xor tmp1 tmp2))
2841 
     (set HI reghi8 tmp1)
2842 
     (set HI reg8 tmp2))
2843 
     ()
2844 
)
2845 
 
2846 
;cmp direct bit to bit
2847 
;BCMP bitaddrZ.z,bitaddrQ.q
2848 
(dni bcmp "bit to bit compare"
2849 
     ((PIPE OS) (IDOC ALU))
2850 
     "bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit"
2851 
     (+ OP1_2 OP2_10 reg8 reghi8 qhibit qlobit)
2852 
     (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4))
2853 
     (set HI tmp1 reghi8)
2854 
     (set HI tmp2 reg8)
2855 
     (set tmp3 (const 1))
2856 
     (set tmp4 (const 1))
2857 
     (sll tmp3 qlobit)
2858 
     (sll tmp4 qhibit)
2859 
     (and tmp1 tmp3)
2860 
     (and tmp2 tmp4)
2861 
     (set BI tmp1(xor tmp1 tmp2))
2862 
     (set HI reghi8 tmp1)
2863 
     (set HI reg8 tmp2))
2864 
     ()
2865 
)
2866 
 
2867 
;bit field low byte
2868 
;BFLDL op1,op2,op3
2869 
(dni bfldl "bit field low byte"
2870 
     ((PIPE OS) (IDOC MOVE))
2871 
     "bfldl $reg8,$hash$mask8,$hash$datahi8"
2872 
     (+ OP1_0 OP2_10 reg8 mask8 datahi8)
2873 
     (sequence ((HI tmp1) (QI tmp2) (QI tmp3))
2874 
     (set HI tmp1 reg8)
2875 
     (set QI tmp2 mask8)
2876 
     (set QI tmp3 datahi8)
2877 
     (inv QI tmp2)
2878 
     (set HI tmp1 (and tmp1 tmp2))
2879 
     (set HI tmp1 (or tmp1 tmp3))
2880 
     (set HI reg8 tmp1)
2881 
     )
2882 
     ()
2883 
)
2884 
 
2885 
;bit field high byte
2886 
;BFLDH op1,op2,op3
2887 
(dni bfldh "bit field high byte"
2888 
     ((PIPE OS) (IDOC MOVE))
2889 
     "bfldh $reg8,$hash$masklo8,$hash$data8"
2890 
     (+ OP1_1 OP2_10 reg8 masklo8 data8)
2891 
     (sequence ((HI tmp1) (HI tmp2) (HI tmp3))
2892 
             (set HI tmp1 reg8)
2893 
             (set QI tmp2 masklo8)
2894 
             (set HI tmp3 data8)
2895 
             (sll tmp2 (const 8))
2896 
             (inv HI tmp2)
2897 
             (sll tmp3 (const 8))
2898 
             (set HI tmp1 (and tmp1 tmp2))
2899 
             (set HI tmp1 (or tmp1 tmp3))
2900 
             (set HI reg8 tmp1)
2901 
     )
2902 
     ()
2903 
)
2904 
 
2905 
;/**********compare instructions******************
2906 
 
2907 
;Compare register
2908 
;CMP Rwn,Rwm
2909 
(dni cmpr "compare two registers"
2910 
     ((PIPE OS) (IDOC CMP))
2911 
     "cmp $src1,$src2"
2912 
     (+ OP1_4 OP2_0 src1 src2)
2913 
     (set condbit (lt HI src1 src2))
2914 
     ()
2915 
)
2916 
 
2917 
;Compare byte register
2918 
;CMPB Rbn,Rbm
2919 
(dni cmpbr "compare two byte registers"
2920 
     ((PIPE OS) (IDOC CMP))
2921 
     "cmpb $drb,$srb"
2922 
     (+ OP1_4 OP2_1 drb srb)
2923 
     (set condbit (lt QI drb srb))
2924 
     ()
2925 
)
2926 
 
2927 
(define-pmacro (cmp1 name insn opc1 opc2 op1 op2 mode)
2928 
  (dni name
2929 
       (.str name "compare" )
2930 
       ((PIPE OS) (IDOC CMP))
2931 
       (.str insn " $"op1 ",$hash$"op2)
2932 
       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
2933 
       (set condbit (lt mode op1 op2))
2934 
       ()
2935 
  )
2936 
)
2937 
(cmp1 cmpri cmp OP1_4 OP2_8 src1 uimm3 HI)
2938 
(cmp1 cmpbri cmpb OP1_4 OP2_9 drb uimm3 QI)
2939 
 
2940 
; CMP Rwn,#data16
2941 
(dni cmpi "compare"
2942 
     ((PIPE OS) (IDOC CMP))
2943 
     "cmp $reg8,$hash$uimm16"
2944 
     (+ OP1_4 OP2_6 reg8 uimm16)
2945 
     (set condbit (lt HI reg8 uimm16))
2946 
     ()
2947 
)
2948 
 
2949 
; CMPB reg,#data8
2950 
(dni cmpbi "compare"
2951 
     ((PIPE OS) (IDOC CMP))
2952 
     "cmpb $regb8,$hash$uimm8"
2953 
     (+ OP1_4 OP2_7 regb8 uimm8 (f-op-bit8 0))
2954 
     (set condbit (lt QI regb8 uimm8))
2955 
     ()
2956 
)
2957 
 
2958 
;compare reg and indirect memory
2959 
(define-pmacro (cmp2 name insn opc1 opc2 op1 op2 mode)
2960 
  (dni name
2961 
       (.str name "compare" )
2962 
       ((PIPE OS) (IDOC CMP))
2963 
       (.str insn " $"op1 ",[$"op2"]")
2964 
       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
2965 
       (set condbit (lt mode op1 op2))
2966 
       ()
2967 
  )
2968 
)
2969 
(cmp2 cmpr2 cmp OP1_4 OP2_8 dr sr2 HI)
2970 
(cmp2 cmpbr2 cmpb OP1_4 OP2_9 drb sr2 QI)
2971 
 
2972 
;compare register and indirect memory post increment
2973 
(define-pmacro (cmp3 name insn opc1 opc2 op1 op2 mode)
2974 
  (dni name
2975 
       (.str name "compare" )
2976 
       ((PIPE OS) (IDOC CMP))
2977 
       (.str insn " $"op1 ",[$"op2"+]")
2978 
       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
2979 
       (sequence ()
2980 
          (set condbit (lt mode op1 op2))
2981 
          (set HI op2 (add HI op2 (const 2)))
2982 
       )
2983 
       ()
2984 
  )
2985 
)
2986 
(cmp3 cmp2i cmp OP1_4 OP2_8 dr sr2 HI)
2987 
(cmp3 cmpb2i cmpb OP1_4 OP2_9 drb sr2 QI)
2988 
 
2989 
;compare register and direct memory
2990 
(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode)
2991 
  (dni name
2992 
       (.str name "compare" )
2993 
       ((PIPE OS) (IDOC CMP))
2994 
       (.str insn " $"op1 ",$pof$"op2)
2995 
       (+ opc1 opc2 op1 op2)
2996 
       (set condbit (lt HI op1 (mem HI op2)))
2997 
       ()
2998 
  )
2999 
)
3000 
(cmp4 cmp04 cmp OP1_4 OP2_2 reg8 upof16 HI)
3001 
(cmp4 cmpb4 cmpb OP1_4 OP2_3 regb8 upof16 QI)
3002 
 
3003 
;compare register and direct memory
3004 
(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode)
3005 
  (dni name
3006 
       (.str name "compare" )
3007 
       ((PIPE OS) (IDOC CMP))
3008 
       (.str insn " $"op1 ",$"op2)
3009 
       (+ opc1 opc2 op1 op2)
3010 
       (set condbit (lt HI op1 (mem HI op2)))
3011 
       ()
3012 
  )
3013 
)
3014 
(cmp4 cmp004 cmp OP1_4 OP2_2 regmem8 memgr8 HI)
3015 
(cmp4 cmp0004 cmp OP1_4 OP2_2 reg8 memory HI)
3016 
(cmp4 cmpb04 cmpb OP1_4 OP2_3 regbmem8 memgr8 QI)
3017 
(cmp4 cmpb004 cmpb OP1_4 OP2_3 regb8 memory QI)
3018 
 
3019 
;compare register and immediate
3020 
(define-pmacro (cmp5 name insn opc1 opc2 op1 op2 mode)
3021 
  (dni name
3022 
       (.str name "compare" )
3023 
       ((PIPE OS) (IDOC CMP))
3024 
       (.str insn " $"op1 ",$hash$"op2)
3025 
       (+ opc1 opc2 op2 op1)
3026 
       (sequence ()
3027 
            (set condbit (lt HI op1 op2))
3028 
            (set mode op1 (sub HI op1 (const 1)))
3029 
       )
3030 
       ()
3031 
  )
3032 
)
3033 
(cmp5 cmpd1ri cmpd1  OP1_10 OP2_0 sr uimm4 HI)
3034 
(cmp5 cmpd2ri cmpd2  OP1_11 OP2_0 sr uimm4 HI)
3035 
(cmp5 cmpi1ri cmpi1  OP1_8 OP2_0 sr uimm4 HI)
3036 
(cmp5 cmpi2ri cmpi2  OP1_9 OP2_0 sr uimm4 HI)
3037 
(cmp5 cmpd1rim cmpd1  OP1_10 OP2_6 reg8 uimm16 HI)
3038 
(cmp5 cmpd2rim cmpd2  OP1_11 OP2_6 reg8 uimm16 HI)
3039 
(cmp5 cmpi1rim cmpi1  OP1_8 OP2_6 reg8 uimm16 HI)
3040 
(cmp5 cmpi2rim cmpi2  OP1_9 OP2_6 reg8 uimm16 HI)
3041 
 
3042 
;compare register and direct memory
3043 
(define-pmacro (cmp6 name insn opc1 opc2 op1 op2 mode )
3044 
  (dni name
3045 
       (.str name "compare" )
3046 
       ((PIPE OS) (IDOC CMP))
3047 
       (.str insn " $"op1 ",$pof$"op2)
3048 
       (+ opc1 opc2 op1 op2)
3049 
       (sequence ()
3050 
            (set condbit (lt HI op1 (mem HI op2)))
3051 
            (set mode op1 (sub HI op1 (const 1)))
3052 
       )
3053 
       ()
3054 
  )
3055 
)
3056 
(cmp6 cmpd1rp cmpd1  OP1_10 OP2_2 reg8 upof16 HI )
3057 
(cmp6 cmpd2rp cmpd2  OP1_11 OP2_2 reg8 upof16 HI )
3058 
(cmp6 cmpi1rp cmpi1  OP1_8 OP2_2 reg8 upof16 HI )
3059 
(cmp6 cmpi2rp cmpi2  OP1_9 OP2_2 reg8 upof16 HI )
3060 
 
3061 
;compare register and direct memory
3062 
(define-pmacro (cmp7 name insn opc1 opc2 op1 op2 mode)
3063 
  (dni name
3064 
       (.str name "compare" )
3065 
       ((PIPE OS) (IDOC CMP))
3066 
       (.str insn " $"op1 ",$"op2)
3067 
       (+ opc1 opc2 op1 op2)
3068 
       (sequence ()
3069 
            (set condbit (lt HI op1 (mem HI op2)))
3070 
            (set mode op1 (sub HI op1 (const 1)))
3071 
       )
3072 
       ()
3073 
  )
3074 
)
3075 
(cmp7 cmpd1rm cmpd1  OP1_10 OP2_2 regmem8 memgr8 HI)
3076 
(cmp7 cmpd2rm cmpd2  OP1_11 OP2_2 regmem8 memgr8 HI)
3077 
(cmp7 cmpi1rm cmpi1  OP1_8 OP2_2 regmem8 memgr8 HI)
3078 
(cmp7 cmpi2rm cmpi2  OP1_9 OP2_2 regmem8 memgr8 HI)
3079 
(cmp7 cmpd1rmi cmpd1  OP1_10 OP2_2 reg8 memory HI)
3080 
(cmp7 cmpd2rmi cmpd2  OP1_11 OP2_2 reg8 memory HI)
3081 
(cmp7 cmpi1rmi cmpi1  OP1_8 OP2_2 reg8 memory HI)
3082 
(cmp7 cmpi2rmi cmpi2  OP1_9 OP2_2 reg8 memory HI)
3083 
 
3084 
 
3085 
;Shift and rotate insns
3086 
;****************************************************************
3087 
(define-pmacro (shift name insn insn1 opc1 opc2 op1 op2 mode)
3088 
  (dni name
3089 
       (.str name "shift" )
3090 
       ((PIPE OS) (IDOC ALU))
3091 
       (.str insn " $"op1 ",$"op2)
3092 
       (+ opc1 opc2 op1 op2)
3093 
       (set mode op1 (insn1 mode op1 op2))
3094 
       ()
3095 
  )
3096 
)
3097 
(shift shlr shl sll OP1_4 OP2_12 dr sr HI)
3098 
(shift shrr shr srl OP1_6 OP2_12 dr sr HI)
3099 
(shift rolr rol rol OP1_0 OP2_12 dr sr HI)
3100 
(shift rorr ror ror OP1_2 OP2_12 dr sr HI)
3101 
(shift ashrr ashr sra OP1_10 OP2_12 dr sr HI)
3102 
 
3103 
(define-pmacro (shift1 name insn insn1 opc1 opc2 op1 op2 mode)
3104 
  (dni name
3105 
       (.str name "shift" )
3106 
       ((PIPE OS) (IDOC ALU))
3107 
       (.str insn " $"op1 ",$hash$"op2)
3108 
       (+ opc1 opc2 op2 op1)
3109 
       (set mode op1 (insn1 mode op1 op2))
3110 
       ()
3111 
  )
3112 
)
3113 
(shift1 shlri shl sll OP1_5 OP2_12 sr uimm4 HI)
3114 
(shift1 shrri shr srl OP1_7 OP2_12 sr uimm4 HI)
3115 
(shift1 rolri rol rol OP1_1 OP2_12 sr uimm4 HI)
3116 
(shift1 rorri ror ror OP1_3 OP2_12 sr uimm4 HI)
3117 
(shift1 ashrri ashr sra OP1_11 OP2_12 sr uimm4 HI)

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