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jlechner |
/* tc-m32r.c -- Assembler for the Renesas M32R.
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
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2006, 2007 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#include "as.h"
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#include "safe-ctype.h"
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#include "subsegs.h"
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#include "symcat.h"
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#include "opcodes/m32r-desc.h"
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#include "opcodes/m32r-opc.h"
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#include "cgen.h"
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#include "elf/m32r.h"
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/* Linked list of symbols that are debugging symbols to be defined as the
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beginning of the current instruction. */
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typedef struct sym_link
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{
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struct sym_link *next;
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symbolS *symbol;
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} sym_linkS;
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static sym_linkS *debug_sym_link = (sym_linkS *) 0;
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/* Structure to hold all of the different components describing
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an individual instruction. */
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typedef struct
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{
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const CGEN_INSN *insn;
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const CGEN_INSN *orig_insn;
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CGEN_FIELDS fields;
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#if CGEN_INT_INSN_P
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CGEN_INSN_INT buffer[1];
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#define INSN_VALUE(buf) (*(buf))
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#else
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unsigned char buffer[CGEN_MAX_INSN_SIZE];
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#define INSN_VALUE(buf) (buf)
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#endif
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char *addr;
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fragS *frag;
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int num_fixups;
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fixS *fixups[GAS_CGEN_MAX_FIXUPS];
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int indices[MAX_OPERAND_INSTANCES];
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sym_linkS *debug_sym_link;
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}
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m32r_insn;
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/* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
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boundary (i.e. was the first of two 16 bit insns). */
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static m32r_insn prev_insn;
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/* Non-zero if we've seen a relaxable insn since the last 32 bit
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alignment request. */
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static int seen_relaxable_p = 0;
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/* Non-zero if we are generating PIC code. */
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int pic_code;
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/* Non-zero if -relax specified, in which case sufficient relocs are output
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for the linker to do relaxing.
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We do simple forms of relaxing internally, but they are always done.
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This flag does not apply to them. */
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static int m32r_relax;
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/* Non-zero if warn when a high/shigh reloc has no matching low reloc.
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Each high/shigh reloc must be paired with it's low cousin in order to
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properly calculate the addend in a relocatable link (since there is a
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potential carry from the low to the high/shigh).
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This option is off by default though for user-written assembler code it
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might make sense to make the default be on (i.e. have gcc pass a flag
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to turn it off). This warning must not be on for GCC created code as
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optimization may delete the low but not the high/shigh (at least we
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shouldn't assume or require it to). */
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static int warn_unmatched_high = 0;
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/* 1 if -m32rx has been specified, in which case support for
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the extended M32RX instruction set should be enabled.
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2 if -m32r2 has been specified, in which case support for
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the extended M32R2 instruction set should be enabled. */
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static int enable_m32rx = 0; /* Default to M32R. */
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/* Non-zero if -m32rx -hidden has been specified, in which case support for
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the special M32RX instruction set should be enabled. */
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static int enable_special = 0;
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/* Non-zero if -bitinst has been specified, in which case support
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for extended M32R bit-field instruction set should be enabled. */
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static int enable_special_m32r = 1;
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/* Non-zero if -float has been specified, in which case support for
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extended M32R floating point instruction set should be enabled. */
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static int enable_special_float = 0;
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/* Non-zero if the programmer should be warned when an explicit parallel
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instruction might have constraint violations. */
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static int warn_explicit_parallel_conflicts = 1;
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/* Non-zero if the programmer should not receive any messages about
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parallel instruction with potential or real constraint violations.
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The ability to suppress these messages is intended only for hardware
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vendors testing the chip. It superceedes
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warn_explicit_parallel_conflicts. */
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static int ignore_parallel_conflicts = 0;
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/* Non-zero if insns can be made parallel. */
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static int use_parallel = 0;
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/* Non-zero if optimizations should be performed. */
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static int optimize;
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/* m32r er_flags. */
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static int m32r_flags = 0;
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/* Stuff for .scomm symbols. */
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static segT sbss_section;
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static asection scom_section;
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static asymbol scom_symbol;
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const char comment_chars[] = ";";
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = "!";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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/* Relocations against symbols are done in two
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parts, with a HI relocation and a LO relocation. Each relocation
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has only 16 bits of space to store an addend. This means that in
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order for the linker to handle carries correctly, it must be able
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to locate both the HI and the LO relocation. This means that the
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relocations must appear in order in the relocation table.
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In order to implement this, we keep track of each unmatched HI
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relocation. We then sort them so that they immediately precede the
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corresponding LO relocation. */
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struct m32r_hi_fixup
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{
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/* Next HI fixup. */
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struct m32r_hi_fixup *next;
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/* This fixup. */
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fixS *fixp;
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/* The section this fixup is in. */
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segT seg;
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};
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/* The list of unmatched HI relocs. */
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static struct m32r_hi_fixup *m32r_hi_fixup_list;
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struct
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{
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enum bfd_architecture bfd_mach;
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int mach_flags;
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} mach_table[] =
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{
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{ bfd_mach_m32r, (1<<MACH_M32R) },
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{ bfd_mach_m32rx, (1<<MACH_M32RX) },
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{ bfd_mach_m32r2, (1<<MACH_M32R2) }
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};
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static void
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allow_m32rx (int on)
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{
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enable_m32rx = on;
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if (stdoutput != NULL)
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bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach);
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if (gas_cgen_cpu_desc != NULL)
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gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
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}
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#define M32R_SHORTOPTS "O::K:"
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const char *md_shortopts = M32R_SHORTOPTS;
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enum md_option_enums
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{
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OPTION_M32R = OPTION_MD_BASE,
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OPTION_M32RX,
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OPTION_M32R2,
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OPTION_BIG,
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OPTION_LITTLE,
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OPTION_PARALLEL,
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OPTION_NO_PARALLEL,
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OPTION_WARN_PARALLEL,
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OPTION_NO_WARN_PARALLEL,
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OPTION_IGNORE_PARALLEL,
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OPTION_NO_IGNORE_PARALLEL,
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OPTION_SPECIAL,
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OPTION_SPECIAL_M32R,
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OPTION_NO_SPECIAL_M32R,
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OPTION_SPECIAL_FLOAT,
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OPTION_WARN_UNMATCHED,
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OPTION_NO_WARN_UNMATCHED
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};
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struct option md_longopts[] =
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{
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{"m32r", no_argument, NULL, OPTION_M32R},
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{"m32rx", no_argument, NULL, OPTION_M32RX},
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{"m32r2", no_argument, NULL, OPTION_M32R2},
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{"big", no_argument, NULL, OPTION_BIG},
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{"little", no_argument, NULL, OPTION_LITTLE},
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{"EB", no_argument, NULL, OPTION_BIG},
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{"EL", no_argument, NULL, OPTION_LITTLE},
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{"parallel", no_argument, NULL, OPTION_PARALLEL},
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{"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},
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{"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
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228 |
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{"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
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{"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
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{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
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231 |
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{"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL},
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232 |
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{"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL},
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233 |
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{"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
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234 |
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{"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
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235 |
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{"hidden", no_argument, NULL, OPTION_SPECIAL},
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236 |
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{"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
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237 |
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{"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R},
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238 |
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{"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
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239 |
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/* Sigh. I guess all warnings must now have both variants. */
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240 |
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{"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
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241 |
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{"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
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242 |
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{"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
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243 |
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{"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
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244 |
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{NULL, no_argument, NULL, 0}
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245 |
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};
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246 |
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247 |
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size_t md_longopts_size = sizeof (md_longopts);
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248 |
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249 |
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static void
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250 |
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little (int on)
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251 |
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{
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252 |
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target_big_endian = ! on;
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253 |
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}
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254 |
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255 |
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/* Use parallel execution. */
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256 |
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257 |
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static int
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258 |
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parallel (void)
|
259 |
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{
|
260 |
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if (! enable_m32rx)
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261 |
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return 0;
|
262 |
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|
263 |
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if (use_parallel == 1)
|
264 |
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return 1;
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265 |
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|
266 |
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return 0;
|
267 |
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}
|
268 |
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|
269 |
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int
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270 |
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md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
|
271 |
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{
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272 |
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switch (c)
|
273 |
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{
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274 |
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case 'O':
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275 |
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optimize = 1;
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276 |
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use_parallel = 1;
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277 |
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break;
|
278 |
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|
279 |
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case OPTION_M32R:
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280 |
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allow_m32rx (0);
|
281 |
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break;
|
282 |
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|
283 |
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case OPTION_M32RX:
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284 |
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allow_m32rx (1);
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285 |
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break;
|
286 |
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|
287 |
|
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case OPTION_M32R2:
|
288 |
|
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allow_m32rx (2);
|
289 |
|
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enable_special = 1;
|
290 |
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enable_special_m32r = 1;
|
291 |
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break;
|
292 |
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|
|
293 |
|
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case OPTION_BIG:
|
294 |
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target_big_endian = 1;
|
295 |
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break;
|
296 |
|
|
|
297 |
|
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case OPTION_LITTLE:
|
298 |
|
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target_big_endian = 0;
|
299 |
|
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break;
|
300 |
|
|
|
301 |
|
|
case OPTION_PARALLEL:
|
302 |
|
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use_parallel = 1;
|
303 |
|
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break;
|
304 |
|
|
|
305 |
|
|
case OPTION_NO_PARALLEL:
|
306 |
|
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use_parallel = 0;
|
307 |
|
|
break;
|
308 |
|
|
|
309 |
|
|
case OPTION_WARN_PARALLEL:
|
310 |
|
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warn_explicit_parallel_conflicts = 1;
|
311 |
|
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break;
|
312 |
|
|
|
313 |
|
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case OPTION_NO_WARN_PARALLEL:
|
314 |
|
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warn_explicit_parallel_conflicts = 0;
|
315 |
|
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break;
|
316 |
|
|
|
317 |
|
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case OPTION_IGNORE_PARALLEL:
|
318 |
|
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ignore_parallel_conflicts = 1;
|
319 |
|
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break;
|
320 |
|
|
|
321 |
|
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case OPTION_NO_IGNORE_PARALLEL:
|
322 |
|
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ignore_parallel_conflicts = 0;
|
323 |
|
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break;
|
324 |
|
|
|
325 |
|
|
case OPTION_SPECIAL:
|
326 |
|
|
if (enable_m32rx)
|
327 |
|
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enable_special = 1;
|
328 |
|
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else
|
329 |
|
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{
|
330 |
|
|
/* Pretend that we do not recognise this option. */
|
331 |
|
|
as_bad (_("Unrecognised option: -hidden"));
|
332 |
|
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return 0;
|
333 |
|
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}
|
334 |
|
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break;
|
335 |
|
|
|
336 |
|
|
case OPTION_SPECIAL_M32R:
|
337 |
|
|
enable_special_m32r = 1;
|
338 |
|
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break;
|
339 |
|
|
|
340 |
|
|
case OPTION_NO_SPECIAL_M32R:
|
341 |
|
|
enable_special_m32r = 0;
|
342 |
|
|
break;
|
343 |
|
|
|
344 |
|
|
case OPTION_SPECIAL_FLOAT:
|
345 |
|
|
enable_special_float = 1;
|
346 |
|
|
break;
|
347 |
|
|
|
348 |
|
|
case OPTION_WARN_UNMATCHED:
|
349 |
|
|
warn_unmatched_high = 1;
|
350 |
|
|
break;
|
351 |
|
|
|
352 |
|
|
case OPTION_NO_WARN_UNMATCHED:
|
353 |
|
|
warn_unmatched_high = 0;
|
354 |
|
|
break;
|
355 |
|
|
|
356 |
|
|
case 'K':
|
357 |
|
|
if (strcmp (arg, "PIC") != 0)
|
358 |
|
|
as_warn (_("Unrecognized option following -K"));
|
359 |
|
|
else
|
360 |
|
|
pic_code = 1;
|
361 |
|
|
break;
|
362 |
|
|
|
363 |
|
|
default:
|
364 |
|
|
return 0;
|
365 |
|
|
}
|
366 |
|
|
|
367 |
|
|
return 1;
|
368 |
|
|
}
|
369 |
|
|
|
370 |
|
|
void
|
371 |
|
|
md_show_usage (FILE *stream)
|
372 |
|
|
{
|
373 |
|
|
fprintf (stream, _(" M32R specific command line options:\n"));
|
374 |
|
|
|
375 |
|
|
fprintf (stream, _("\
|
376 |
|
|
-m32r disable support for the m32rx instruction set\n"));
|
377 |
|
|
fprintf (stream, _("\
|
378 |
|
|
-m32rx support the extended m32rx instruction set\n"));
|
379 |
|
|
fprintf (stream, _("\
|
380 |
|
|
-m32r2 support the extended m32r2 instruction set\n"));
|
381 |
|
|
fprintf (stream, _("\
|
382 |
|
|
-EL,-little produce little endian code and data\n"));
|
383 |
|
|
fprintf (stream, _("\
|
384 |
|
|
-EB,-big produce big endian code and data\n"));
|
385 |
|
|
fprintf (stream, _("\
|
386 |
|
|
-parallel try to combine instructions in parallel\n"));
|
387 |
|
|
fprintf (stream, _("\
|
388 |
|
|
-no-parallel disable -parallel\n"));
|
389 |
|
|
fprintf (stream, _("\
|
390 |
|
|
-no-bitinst disallow the M32R2's extended bit-field instructions\n"));
|
391 |
|
|
fprintf (stream, _("\
|
392 |
|
|
-O try to optimize code. Implies -parallel\n"));
|
393 |
|
|
|
394 |
|
|
fprintf (stream, _("\
|
395 |
|
|
-warn-explicit-parallel-conflicts warn when parallel instructions\n"));
|
396 |
|
|
fprintf (stream, _("\
|
397 |
|
|
might violate contraints\n"));
|
398 |
|
|
fprintf (stream, _("\
|
399 |
|
|
-no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
|
400 |
|
|
fprintf (stream, _("\
|
401 |
|
|
instructions might violate contraints\n"));
|
402 |
|
|
fprintf (stream, _("\
|
403 |
|
|
-Wp synonym for -warn-explicit-parallel-conflicts\n"));
|
404 |
|
|
fprintf (stream, _("\
|
405 |
|
|
-Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
|
406 |
|
|
fprintf (stream, _("\
|
407 |
|
|
-ignore-parallel-conflicts do not check parallel instructions\n"));
|
408 |
|
|
fprintf (stream, _("\
|
409 |
|
|
fo contraint violations\n"));
|
410 |
|
|
fprintf (stream, _("\
|
411 |
|
|
-no-ignore-parallel-conflicts check parallel instructions for\n"));
|
412 |
|
|
fprintf (stream, _("\
|
413 |
|
|
contraint violations\n"));
|
414 |
|
|
fprintf (stream, _("\
|
415 |
|
|
-Ip synonym for -ignore-parallel-conflicts\n"));
|
416 |
|
|
fprintf (stream, _("\
|
417 |
|
|
-nIp synonym for -no-ignore-parallel-conflicts\n"));
|
418 |
|
|
|
419 |
|
|
fprintf (stream, _("\
|
420 |
|
|
-warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
|
421 |
|
|
fprintf (stream, _("\
|
422 |
|
|
-no-warn-unmatched-high do not warn about missing low relocs\n"));
|
423 |
|
|
fprintf (stream, _("\
|
424 |
|
|
-Wuh synonym for -warn-unmatched-high\n"));
|
425 |
|
|
fprintf (stream, _("\
|
426 |
|
|
-Wnuh synonym for -no-warn-unmatched-high\n"));
|
427 |
|
|
|
428 |
|
|
fprintf (stream, _("\
|
429 |
|
|
-KPIC generate PIC\n"));
|
430 |
|
|
}
|
431 |
|
|
|
432 |
|
|
/* Set by md_assemble for use by m32r_fill_insn. */
|
433 |
|
|
static subsegT prev_subseg;
|
434 |
|
|
static segT prev_seg;
|
435 |
|
|
|
436 |
|
|
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
|
437 |
|
|
symbolS * GOT_symbol;
|
438 |
|
|
|
439 |
|
|
static inline int
|
440 |
|
|
m32r_PIC_related_p (symbolS *sym)
|
441 |
|
|
{
|
442 |
|
|
expressionS *exp;
|
443 |
|
|
|
444 |
|
|
if (! sym)
|
445 |
|
|
return 0;
|
446 |
|
|
|
447 |
|
|
if (sym == GOT_symbol)
|
448 |
|
|
return 1;
|
449 |
|
|
|
450 |
|
|
exp = symbol_get_value_expression (sym);
|
451 |
|
|
|
452 |
|
|
return (exp->X_op == O_PIC_reloc
|
453 |
|
|
|| exp->X_md == BFD_RELOC_M32R_26_PLTREL
|
454 |
|
|
|| m32r_PIC_related_p (exp->X_add_symbol)
|
455 |
|
|
|| m32r_PIC_related_p (exp->X_op_symbol));
|
456 |
|
|
}
|
457 |
|
|
|
458 |
|
|
static inline int
|
459 |
|
|
m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
|
460 |
|
|
{
|
461 |
|
|
expressionS *exp = main_exp;
|
462 |
|
|
|
463 |
|
|
if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol))
|
464 |
|
|
return 1;
|
465 |
|
|
|
466 |
|
|
if (exp->X_op == O_symbol && exp->X_add_symbol)
|
467 |
|
|
{
|
468 |
|
|
if (exp->X_add_symbol == GOT_symbol)
|
469 |
|
|
{
|
470 |
|
|
*r_type_p = BFD_RELOC_M32R_GOTPC24;
|
471 |
|
|
return 0;
|
472 |
|
|
}
|
473 |
|
|
}
|
474 |
|
|
else if (exp->X_op == O_add)
|
475 |
|
|
{
|
476 |
|
|
exp = symbol_get_value_expression (exp->X_add_symbol);
|
477 |
|
|
if (! exp)
|
478 |
|
|
return 0;
|
479 |
|
|
}
|
480 |
|
|
|
481 |
|
|
if (exp->X_op == O_PIC_reloc)
|
482 |
|
|
{
|
483 |
|
|
*r_type_p = exp->X_md;
|
484 |
|
|
if (exp == main_exp)
|
485 |
|
|
exp->X_op = O_symbol;
|
486 |
|
|
else
|
487 |
|
|
{
|
488 |
|
|
main_exp->X_add_symbol = exp->X_add_symbol;
|
489 |
|
|
main_exp->X_add_number += exp->X_add_number;
|
490 |
|
|
}
|
491 |
|
|
}
|
492 |
|
|
else
|
493 |
|
|
return (m32r_PIC_related_p (exp->X_add_symbol)
|
494 |
|
|
|| m32r_PIC_related_p (exp->X_op_symbol));
|
495 |
|
|
|
496 |
|
|
return 0;
|
497 |
|
|
}
|
498 |
|
|
|
499 |
|
|
/* FIXME: Should be machine generated. */
|
500 |
|
|
#define NOP_INSN 0x7000
|
501 |
|
|
#define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
|
502 |
|
|
|
503 |
|
|
/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
|
504 |
|
|
of an rs_align_code fragment. */
|
505 |
|
|
|
506 |
|
|
void
|
507 |
|
|
m32r_handle_align (fragS *fragp)
|
508 |
|
|
{
|
509 |
|
|
static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
|
510 |
|
|
static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
|
511 |
|
|
|
512 |
|
|
int bytes, fix;
|
513 |
|
|
char *p;
|
514 |
|
|
|
515 |
|
|
if (fragp->fr_type != rs_align_code)
|
516 |
|
|
return;
|
517 |
|
|
|
518 |
|
|
bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
|
519 |
|
|
p = fragp->fr_literal + fragp->fr_fix;
|
520 |
|
|
fix = 0;
|
521 |
|
|
|
522 |
|
|
if (bytes & 1)
|
523 |
|
|
{
|
524 |
|
|
fix = 1;
|
525 |
|
|
*p++ = 0;
|
526 |
|
|
bytes--;
|
527 |
|
|
}
|
528 |
|
|
|
529 |
|
|
if (bytes & 2)
|
530 |
|
|
{
|
531 |
|
|
memcpy (p, nop_pattern, 2);
|
532 |
|
|
p += 2;
|
533 |
|
|
bytes -= 2;
|
534 |
|
|
fix += 2;
|
535 |
|
|
}
|
536 |
|
|
|
537 |
|
|
memcpy (p, multi_nop_pattern, 4);
|
538 |
|
|
|
539 |
|
|
fragp->fr_fix += fix;
|
540 |
|
|
fragp->fr_var = 4;
|
541 |
|
|
}
|
542 |
|
|
|
543 |
|
|
/* If the last instruction was the first of 2 16 bit insns,
|
544 |
|
|
output a nop to move the PC to a 32 bit boundary.
|
545 |
|
|
|
546 |
|
|
This is done via an alignment specification since branch relaxing
|
547 |
|
|
may make it unnecessary.
|
548 |
|
|
|
549 |
|
|
Internally, we need to output one of these each time a 32 bit insn is
|
550 |
|
|
seen after an insn that is relaxable. */
|
551 |
|
|
|
552 |
|
|
static void
|
553 |
|
|
fill_insn (int ignore ATTRIBUTE_UNUSED)
|
554 |
|
|
{
|
555 |
|
|
frag_align_code (2, 0);
|
556 |
|
|
prev_insn.insn = NULL;
|
557 |
|
|
seen_relaxable_p = 0;
|
558 |
|
|
}
|
559 |
|
|
|
560 |
|
|
/* Record the symbol so that when we output the insn, we can create
|
561 |
|
|
a symbol that is at the start of the instruction. This is used
|
562 |
|
|
to emit the label for the start of a breakpoint without causing
|
563 |
|
|
the assembler to emit a NOP if the previous instruction was a
|
564 |
|
|
16 bit instruction. */
|
565 |
|
|
|
566 |
|
|
static void
|
567 |
|
|
debug_sym (int ignore ATTRIBUTE_UNUSED)
|
568 |
|
|
{
|
569 |
|
|
char *name;
|
570 |
|
|
char delim;
|
571 |
|
|
char *end_name;
|
572 |
|
|
symbolS *symbolP;
|
573 |
|
|
sym_linkS *link;
|
574 |
|
|
|
575 |
|
|
name = input_line_pointer;
|
576 |
|
|
delim = get_symbol_end ();
|
577 |
|
|
end_name = input_line_pointer;
|
578 |
|
|
|
579 |
|
|
if ((symbolP = symbol_find (name)) == NULL
|
580 |
|
|
&& (symbolP = md_undefined_symbol (name)) == NULL)
|
581 |
|
|
symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
|
582 |
|
|
|
583 |
|
|
symbol_table_insert (symbolP);
|
584 |
|
|
if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
|
585 |
|
|
|| S_IS_EXTERNAL (symbolP)
|
586 |
|
|
|| S_IS_WEAK (symbolP)))
|
587 |
|
|
/* xgettext:c-format */
|
588 |
|
|
as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
|
589 |
|
|
|
590 |
|
|
else
|
591 |
|
|
{
|
592 |
|
|
link = (sym_linkS *) xmalloc (sizeof (sym_linkS));
|
593 |
|
|
link->symbol = symbolP;
|
594 |
|
|
link->next = debug_sym_link;
|
595 |
|
|
debug_sym_link = link;
|
596 |
|
|
symbol_get_obj (symbolP)->local = 1;
|
597 |
|
|
}
|
598 |
|
|
|
599 |
|
|
*end_name = delim;
|
600 |
|
|
demand_empty_rest_of_line ();
|
601 |
|
|
}
|
602 |
|
|
|
603 |
|
|
/* Second pass to expanding the debug symbols, go through linked
|
604 |
|
|
list of symbols and reassign the address. */
|
605 |
|
|
|
606 |
|
|
static void
|
607 |
|
|
expand_debug_syms (sym_linkS *syms, int align)
|
608 |
|
|
{
|
609 |
|
|
char *save_input_line = input_line_pointer;
|
610 |
|
|
sym_linkS *next_syms;
|
611 |
|
|
|
612 |
|
|
if (!syms)
|
613 |
|
|
return;
|
614 |
|
|
|
615 |
|
|
(void) frag_align_code (align, 0);
|
616 |
|
|
for (; syms != (sym_linkS *) 0; syms = next_syms)
|
617 |
|
|
{
|
618 |
|
|
symbolS *symbolP = syms->symbol;
|
619 |
|
|
next_syms = syms->next;
|
620 |
|
|
input_line_pointer = ".\n";
|
621 |
|
|
pseudo_set (symbolP);
|
622 |
|
|
free ((char *) syms);
|
623 |
|
|
}
|
624 |
|
|
|
625 |
|
|
input_line_pointer = save_input_line;
|
626 |
|
|
}
|
627 |
|
|
|
628 |
|
|
void
|
629 |
|
|
m32r_flush_pending_output (void)
|
630 |
|
|
{
|
631 |
|
|
if (debug_sym_link)
|
632 |
|
|
{
|
633 |
|
|
expand_debug_syms (debug_sym_link, 1);
|
634 |
|
|
debug_sym_link = (sym_linkS *) 0;
|
635 |
|
|
}
|
636 |
|
|
}
|
637 |
|
|
|
638 |
|
|
/* Cover function to fill_insn called after a label and at end of assembly.
|
639 |
|
|
The result is always 1: we're called in a conditional to see if the
|
640 |
|
|
current line is a label. */
|
641 |
|
|
|
642 |
|
|
int
|
643 |
|
|
m32r_fill_insn (int done)
|
644 |
|
|
{
|
645 |
|
|
if (prev_seg != NULL)
|
646 |
|
|
{
|
647 |
|
|
segT seg = now_seg;
|
648 |
|
|
subsegT subseg = now_subseg;
|
649 |
|
|
|
650 |
|
|
subseg_set (prev_seg, prev_subseg);
|
651 |
|
|
|
652 |
|
|
fill_insn (0);
|
653 |
|
|
|
654 |
|
|
subseg_set (seg, subseg);
|
655 |
|
|
}
|
656 |
|
|
|
657 |
|
|
if (done && debug_sym_link)
|
658 |
|
|
{
|
659 |
|
|
expand_debug_syms (debug_sym_link, 1);
|
660 |
|
|
debug_sym_link = (sym_linkS *) 0;
|
661 |
|
|
}
|
662 |
|
|
|
663 |
|
|
return 1;
|
664 |
|
|
}
|
665 |
|
|
|
666 |
|
|
/* The default target format to use. */
|
667 |
|
|
|
668 |
|
|
const char *
|
669 |
|
|
m32r_target_format (void)
|
670 |
|
|
{
|
671 |
|
|
#ifdef TE_LINUX
|
672 |
|
|
if (target_big_endian)
|
673 |
|
|
return "elf32-m32r-linux";
|
674 |
|
|
else
|
675 |
|
|
return "elf32-m32rle-linux";
|
676 |
|
|
#else
|
677 |
|
|
if (target_big_endian)
|
678 |
|
|
return "elf32-m32r";
|
679 |
|
|
else
|
680 |
|
|
return "elf32-m32rle";
|
681 |
|
|
#endif
|
682 |
|
|
}
|
683 |
|
|
|
684 |
|
|
void
|
685 |
|
|
md_begin (void)
|
686 |
|
|
{
|
687 |
|
|
flagword applicable;
|
688 |
|
|
segT seg;
|
689 |
|
|
subsegT subseg;
|
690 |
|
|
|
691 |
|
|
/* Initialize the `cgen' interface. */
|
692 |
|
|
|
693 |
|
|
/* Set the machine number and endian. */
|
694 |
|
|
gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
|
695 |
|
|
CGEN_CPU_OPEN_ENDIAN,
|
696 |
|
|
(target_big_endian ?
|
697 |
|
|
CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE),
|
698 |
|
|
CGEN_CPU_OPEN_END);
|
699 |
|
|
m32r_cgen_init_asm (gas_cgen_cpu_desc);
|
700 |
|
|
|
701 |
|
|
/* The operand instance table is used during optimization to determine
|
702 |
|
|
which insns can be executed in parallel. It is also used to give
|
703 |
|
|
warnings regarding operand interference in parallel insns. */
|
704 |
|
|
m32r_cgen_init_opinst_table (gas_cgen_cpu_desc);
|
705 |
|
|
|
706 |
|
|
/* This is a callback from cgen to gas to parse operands. */
|
707 |
|
|
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
|
708 |
|
|
|
709 |
|
|
/* Save the current subseg so we can restore it [it's the default one and
|
710 |
|
|
we don't want the initial section to be .sbss]. */
|
711 |
|
|
seg = now_seg;
|
712 |
|
|
subseg = now_subseg;
|
713 |
|
|
|
714 |
|
|
/* The sbss section is for local .scomm symbols. */
|
715 |
|
|
sbss_section = subseg_new (".sbss", 0);
|
716 |
|
|
seg_info (sbss_section)->bss = 1;
|
717 |
|
|
|
718 |
|
|
/* This is copied from perform_an_assembly_pass. */
|
719 |
|
|
applicable = bfd_applicable_section_flags (stdoutput);
|
720 |
|
|
bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
|
721 |
|
|
|
722 |
|
|
subseg_set (seg, subseg);
|
723 |
|
|
|
724 |
|
|
/* We must construct a fake section similar to bfd_com_section
|
725 |
|
|
but with the name .scommon. */
|
726 |
|
|
scom_section = bfd_com_section;
|
727 |
|
|
scom_section.name = ".scommon";
|
728 |
|
|
scom_section.output_section = & scom_section;
|
729 |
|
|
scom_section.symbol = & scom_symbol;
|
730 |
|
|
scom_section.symbol_ptr_ptr = & scom_section.symbol;
|
731 |
|
|
scom_symbol = * bfd_com_section.symbol;
|
732 |
|
|
scom_symbol.name = ".scommon";
|
733 |
|
|
scom_symbol.section = & scom_section;
|
734 |
|
|
|
735 |
|
|
allow_m32rx (enable_m32rx);
|
736 |
|
|
|
737 |
|
|
gas_cgen_initialize_saved_fixups_array ();
|
738 |
|
|
}
|
739 |
|
|
|
740 |
|
|
#define OPERAND_IS_COND_BIT(operand, indices, index) \
|
741 |
|
|
((operand)->hw_type == HW_H_COND \
|
742 |
|
|
|| ((operand)->hw_type == HW_H_PSW) \
|
743 |
|
|
|| ((operand)->hw_type == HW_H_CR \
|
744 |
|
|
&& (indices [index] == 0 || indices [index] == 1)))
|
745 |
|
|
|
746 |
|
|
/* Returns true if an output of instruction 'a' is referenced by an operand
|
747 |
|
|
of instruction 'b'. If 'check_outputs' is true then b's outputs are
|
748 |
|
|
checked, otherwise its inputs are examined. */
|
749 |
|
|
|
750 |
|
|
static int
|
751 |
|
|
first_writes_to_seconds_operands (m32r_insn *a,
|
752 |
|
|
m32r_insn *b,
|
753 |
|
|
const int check_outputs)
|
754 |
|
|
{
|
755 |
|
|
const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
|
756 |
|
|
const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
|
757 |
|
|
int a_index;
|
758 |
|
|
|
759 |
|
|
if (ignore_parallel_conflicts)
|
760 |
|
|
return 0;
|
761 |
|
|
|
762 |
|
|
/* If at least one of the instructions takes no operands, then there is
|
763 |
|
|
nothing to check. There really are instructions without operands,
|
764 |
|
|
eg 'nop'. */
|
765 |
|
|
if (a_operands == NULL || b_ops == NULL)
|
766 |
|
|
return 0;
|
767 |
|
|
|
768 |
|
|
/* Scan the operand list of 'a' looking for an output operand. */
|
769 |
|
|
for (a_index = 0;
|
770 |
|
|
a_operands->type != CGEN_OPINST_END;
|
771 |
|
|
a_index ++, a_operands ++)
|
772 |
|
|
{
|
773 |
|
|
if (a_operands->type == CGEN_OPINST_OUTPUT)
|
774 |
|
|
{
|
775 |
|
|
int b_index;
|
776 |
|
|
const CGEN_OPINST *b_operands = b_ops;
|
777 |
|
|
|
778 |
|
|
/* Special Case:
|
779 |
|
|
The Condition bit 'C' is a shadow of the CBR register (control
|
780 |
|
|
register 1) and also a shadow of bit 31 of the program status
|
781 |
|
|
word (control register 0). For now this is handled here, rather
|
782 |
|
|
than by cgen.... */
|
783 |
|
|
|
784 |
|
|
if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
|
785 |
|
|
{
|
786 |
|
|
/* Scan operand list of 'b' looking for another reference to the
|
787 |
|
|
condition bit, which goes in the right direction. */
|
788 |
|
|
for (b_index = 0;
|
789 |
|
|
b_operands->type != CGEN_OPINST_END;
|
790 |
|
|
b_index++, b_operands++)
|
791 |
|
|
{
|
792 |
|
|
if ((b_operands->type
|
793 |
|
|
== (check_outputs
|
794 |
|
|
? CGEN_OPINST_OUTPUT
|
795 |
|
|
: CGEN_OPINST_INPUT))
|
796 |
|
|
&& OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
|
797 |
|
|
return 1;
|
798 |
|
|
}
|
799 |
|
|
}
|
800 |
|
|
else
|
801 |
|
|
{
|
802 |
|
|
/* Scan operand list of 'b' looking for an operand that
|
803 |
|
|
references the same hardware element, and which goes in the
|
804 |
|
|
right direction. */
|
805 |
|
|
for (b_index = 0;
|
806 |
|
|
b_operands->type != CGEN_OPINST_END;
|
807 |
|
|
b_index++, b_operands++)
|
808 |
|
|
{
|
809 |
|
|
if ((b_operands->type
|
810 |
|
|
== (check_outputs
|
811 |
|
|
? CGEN_OPINST_OUTPUT
|
812 |
|
|
: CGEN_OPINST_INPUT))
|
813 |
|
|
&& (b_operands->hw_type == a_operands->hw_type)
|
814 |
|
|
&& (a->indices[a_index] == b->indices[b_index]))
|
815 |
|
|
return 1;
|
816 |
|
|
}
|
817 |
|
|
}
|
818 |
|
|
}
|
819 |
|
|
}
|
820 |
|
|
|
821 |
|
|
return 0;
|
822 |
|
|
}
|
823 |
|
|
|
824 |
|
|
/* Returns true if the insn can (potentially) alter the program counter. */
|
825 |
|
|
|
826 |
|
|
static int
|
827 |
|
|
writes_to_pc (m32r_insn *a)
|
828 |
|
|
{
|
829 |
|
|
if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
|
830 |
|
|
|| CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
|
831 |
|
|
return 1;
|
832 |
|
|
return 0;
|
833 |
|
|
}
|
834 |
|
|
|
835 |
|
|
/* Return NULL if the two 16 bit insns can be executed in parallel.
|
836 |
|
|
Otherwise return a pointer to an error message explaining why not. */
|
837 |
|
|
|
838 |
|
|
static const char *
|
839 |
|
|
can_make_parallel (m32r_insn *a, m32r_insn *b)
|
840 |
|
|
{
|
841 |
|
|
PIPE_ATTR a_pipe;
|
842 |
|
|
PIPE_ATTR b_pipe;
|
843 |
|
|
|
844 |
|
|
/* Make sure the instructions are the right length. */
|
845 |
|
|
if (CGEN_FIELDS_BITSIZE (&a->fields) != 16
|
846 |
|
|
|| CGEN_FIELDS_BITSIZE (&b->fields) != 16)
|
847 |
|
|
abort ();
|
848 |
|
|
|
849 |
|
|
if (first_writes_to_seconds_operands (a, b, TRUE))
|
850 |
|
|
return _("instructions write to the same destination register.");
|
851 |
|
|
|
852 |
|
|
a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
|
853 |
|
|
b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
|
854 |
|
|
|
855 |
|
|
/* Make sure that the instructions use the correct execution pipelines. */
|
856 |
|
|
if (a_pipe == PIPE_NONE
|
857 |
|
|
|| b_pipe == PIPE_NONE)
|
858 |
|
|
return _("Instructions do not use parallel execution pipelines.");
|
859 |
|
|
|
860 |
|
|
/* Leave this test for last, since it is the only test that can
|
861 |
|
|
go away if the instructions are swapped, and we want to make
|
862 |
|
|
sure that any other errors are detected before this happens. */
|
863 |
|
|
if (a_pipe == PIPE_S
|
864 |
|
|
|| b_pipe == PIPE_O
|
865 |
|
|
|| (b_pipe == PIPE_O_OS && (enable_m32rx != 2)))
|
866 |
|
|
return _("Instructions share the same execution pipeline");
|
867 |
|
|
|
868 |
|
|
return NULL;
|
869 |
|
|
}
|
870 |
|
|
|
871 |
|
|
/* Force the top bit of the second 16-bit insn to be set. */
|
872 |
|
|
|
873 |
|
|
static void
|
874 |
|
|
make_parallel (CGEN_INSN_BYTES_PTR buffer)
|
875 |
|
|
{
|
876 |
|
|
#if CGEN_INT_INSN_P
|
877 |
|
|
*buffer |= 0x8000;
|
878 |
|
|
#else
|
879 |
|
|
buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|
880 |
|
|
|= 0x80;
|
881 |
|
|
#endif
|
882 |
|
|
}
|
883 |
|
|
|
884 |
|
|
/* Same as make_parallel except buffer contains the bytes in target order. */
|
885 |
|
|
|
886 |
|
|
static void
|
887 |
|
|
target_make_parallel (char *buffer)
|
888 |
|
|
{
|
889 |
|
|
buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|
890 |
|
|
|= 0x80;
|
891 |
|
|
}
|
892 |
|
|
|
893 |
|
|
/* Assemble two instructions with an explicit parallel operation (||) or
|
894 |
|
|
sequential operation (->). */
|
895 |
|
|
|
896 |
|
|
static void
|
897 |
|
|
assemble_two_insns (char *str1, char *str2, int parallel_p)
|
898 |
|
|
{
|
899 |
|
|
char *str3;
|
900 |
|
|
m32r_insn first;
|
901 |
|
|
m32r_insn second;
|
902 |
|
|
char *errmsg;
|
903 |
|
|
char save_str2 = *str2;
|
904 |
|
|
|
905 |
|
|
/* Separate the two instructions. */
|
906 |
|
|
*str2 = 0;
|
907 |
|
|
|
908 |
|
|
/* Make sure the two insns begin on a 32 bit boundary.
|
909 |
|
|
This is also done for the serial case (foo -> bar), relaxing doesn't
|
910 |
|
|
affect insns written like this.
|
911 |
|
|
Note that we must always do this as we can't assume anything about
|
912 |
|
|
whether we're currently on a 32 bit boundary or not. Relaxing may
|
913 |
|
|
change this. */
|
914 |
|
|
fill_insn (0);
|
915 |
|
|
|
916 |
|
|
first.debug_sym_link = debug_sym_link;
|
917 |
|
|
debug_sym_link = (sym_linkS *) 0;
|
918 |
|
|
|
919 |
|
|
/* Parse the first instruction. */
|
920 |
|
|
if (! (first.insn = m32r_cgen_assemble_insn
|
921 |
|
|
(gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg)))
|
922 |
|
|
{
|
923 |
|
|
as_bad (errmsg);
|
924 |
|
|
return;
|
925 |
|
|
}
|
926 |
|
|
|
927 |
|
|
/* Check it. */
|
928 |
|
|
if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
|
929 |
|
|
{
|
930 |
|
|
/* xgettext:c-format */
|
931 |
|
|
as_bad (_("not a 16 bit instruction '%s'"), str1);
|
932 |
|
|
return;
|
933 |
|
|
}
|
934 |
|
|
#ifdef E_M32R2_ARCH
|
935 |
|
|
else if ((enable_m32rx == 1)
|
936 |
|
|
/* FIXME: Need standard macro to perform this test. */
|
937 |
|
|
&& ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
938 |
|
|
& (1 << MACH_M32R2))
|
939 |
|
|
&& !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
940 |
|
|
& (1 << MACH_M32RX)))))
|
941 |
|
|
{
|
942 |
|
|
/* xgettext:c-format */
|
943 |
|
|
as_bad (_("instruction '%s' is for the M32R2 only"), str1);
|
944 |
|
|
return;
|
945 |
|
|
}
|
946 |
|
|
else if ((! enable_special
|
947 |
|
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
|
948 |
|
|
|| (! enable_special_m32r
|
949 |
|
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)))
|
950 |
|
|
#else
|
951 |
|
|
else if (! enable_special
|
952 |
|
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
|
953 |
|
|
#endif
|
954 |
|
|
{
|
955 |
|
|
/* xgettext:c-format */
|
956 |
|
|
as_bad (_("unknown instruction '%s'"), str1);
|
957 |
|
|
return;
|
958 |
|
|
}
|
959 |
|
|
else if (! enable_m32rx
|
960 |
|
|
/* FIXME: Need standard macro to perform this test. */
|
961 |
|
|
&& (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
962 |
|
|
== (1 << MACH_M32RX)))
|
963 |
|
|
{
|
964 |
|
|
/* xgettext:c-format */
|
965 |
|
|
as_bad (_("instruction '%s' is for the M32RX only"), str1);
|
966 |
|
|
return;
|
967 |
|
|
}
|
968 |
|
|
|
969 |
|
|
/* Check to see if this is an allowable parallel insn. */
|
970 |
|
|
if (parallel_p
|
971 |
|
|
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
|
972 |
|
|
{
|
973 |
|
|
/* xgettext:c-format */
|
974 |
|
|
as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
|
975 |
|
|
return;
|
976 |
|
|
}
|
977 |
|
|
|
978 |
|
|
/* Restore the original assembly text, just in case it is needed. */
|
979 |
|
|
*str2 = save_str2;
|
980 |
|
|
|
981 |
|
|
/* Save the original string pointer. */
|
982 |
|
|
str3 = str1;
|
983 |
|
|
|
984 |
|
|
/* Advanced past the parsed string. */
|
985 |
|
|
str1 = str2 + 2;
|
986 |
|
|
|
987 |
|
|
/* Remember the entire string in case it is needed for error
|
988 |
|
|
messages. */
|
989 |
|
|
str2 = str3;
|
990 |
|
|
|
991 |
|
|
/* Convert the opcode to lower case. */
|
992 |
|
|
{
|
993 |
|
|
char *s2 = str1;
|
994 |
|
|
|
995 |
|
|
while (ISSPACE (*s2++))
|
996 |
|
|
continue;
|
997 |
|
|
|
998 |
|
|
--s2;
|
999 |
|
|
|
1000 |
|
|
while (ISALNUM (*s2))
|
1001 |
|
|
{
|
1002 |
|
|
*s2 = TOLOWER (*s2);
|
1003 |
|
|
s2++;
|
1004 |
|
|
}
|
1005 |
|
|
}
|
1006 |
|
|
|
1007 |
|
|
/* Preserve any fixups that have been generated and reset the list
|
1008 |
|
|
to empty. */
|
1009 |
|
|
gas_cgen_save_fixups (0);
|
1010 |
|
|
|
1011 |
|
|
/* Get the indices of the operands of the instruction. */
|
1012 |
|
|
/* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
|
1013 |
|
|
doesn't seem right. Perhaps allow passing fields like we do insn. */
|
1014 |
|
|
/* FIXME: ALIAS insns do not have operands, so we use this function
|
1015 |
|
|
to find the equivalent insn and overwrite the value stored in our
|
1016 |
|
|
structure. We still need the original insn, however, since this
|
1017 |
|
|
may have certain attributes that are not present in the unaliased
|
1018 |
|
|
version (eg relaxability). When aliases behave differently this
|
1019 |
|
|
may have to change. */
|
1020 |
|
|
first.orig_insn = first.insn;
|
1021 |
|
|
{
|
1022 |
|
|
CGEN_FIELDS tmp_fields;
|
1023 |
|
|
first.insn = cgen_lookup_get_insn_operands
|
1024 |
|
|
(gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
|
1025 |
|
|
first.indices, &tmp_fields);
|
1026 |
|
|
}
|
1027 |
|
|
|
1028 |
|
|
if (first.insn == NULL)
|
1029 |
|
|
as_fatal (_("internal error: lookup/get operands failed"));
|
1030 |
|
|
|
1031 |
|
|
second.debug_sym_link = NULL;
|
1032 |
|
|
|
1033 |
|
|
/* Parse the second instruction. */
|
1034 |
|
|
if (! (second.insn = m32r_cgen_assemble_insn
|
1035 |
|
|
(gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg)))
|
1036 |
|
|
{
|
1037 |
|
|
as_bad (errmsg);
|
1038 |
|
|
return;
|
1039 |
|
|
}
|
1040 |
|
|
|
1041 |
|
|
/* Check it. */
|
1042 |
|
|
if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
|
1043 |
|
|
{
|
1044 |
|
|
/* xgettext:c-format */
|
1045 |
|
|
as_bad (_("not a 16 bit instruction '%s'"), str1);
|
1046 |
|
|
return;
|
1047 |
|
|
}
|
1048 |
|
|
#ifdef E_M32R2_ARCH
|
1049 |
|
|
else if ((enable_m32rx == 1)
|
1050 |
|
|
/* FIXME: Need standard macro to perform this test. */
|
1051 |
|
|
&& ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
1052 |
|
|
& (1 << MACH_M32R2))
|
1053 |
|
|
&& !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
|
1054 |
|
|
& (1 << MACH_M32RX)))))
|
1055 |
|
|
{
|
1056 |
|
|
/* xgettext:c-format */
|
1057 |
|
|
as_bad (_("instruction '%s' is for the M32R2 only"), str1);
|
1058 |
|
|
return;
|
1059 |
|
|
}
|
1060 |
|
|
else if ((! enable_special
|
1061 |
|
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
1062 |
|
|
|| (! enable_special_m32r
|
1063 |
|
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)))
|
1064 |
|
|
#else
|
1065 |
|
|
else if (! enable_special
|
1066 |
|
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
1067 |
|
|
#endif
|
1068 |
|
|
{
|
1069 |
|
|
/* xgettext:c-format */
|
1070 |
|
|
as_bad (_("unknown instruction '%s'"), str1);
|
1071 |
|
|
return;
|
1072 |
|
|
}
|
1073 |
|
|
else if (! enable_m32rx
|
1074 |
|
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
|
1075 |
|
|
{
|
1076 |
|
|
/* xgettext:c-format */
|
1077 |
|
|
as_bad (_("instruction '%s' is for the M32RX only"), str1);
|
1078 |
|
|
return;
|
1079 |
|
|
}
|
1080 |
|
|
|
1081 |
|
|
/* Check to see if this is an allowable parallel insn. */
|
1082 |
|
|
if (parallel_p
|
1083 |
|
|
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
|
1084 |
|
|
{
|
1085 |
|
|
/* xgettext:c-format */
|
1086 |
|
|
as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
|
1087 |
|
|
return;
|
1088 |
|
|
}
|
1089 |
|
|
|
1090 |
|
|
if (parallel_p && ! enable_m32rx)
|
1091 |
|
|
{
|
1092 |
|
|
if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
|
1093 |
|
|
&& CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
|
1094 |
|
|
{
|
1095 |
|
|
/* xgettext:c-format */
|
1096 |
|
|
as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
|
1097 |
|
|
return;
|
1098 |
|
|
}
|
1099 |
|
|
}
|
1100 |
|
|
|
1101 |
|
|
/* Get the indices of the operands of the instruction. */
|
1102 |
|
|
second.orig_insn = second.insn;
|
1103 |
|
|
{
|
1104 |
|
|
CGEN_FIELDS tmp_fields;
|
1105 |
|
|
second.insn = cgen_lookup_get_insn_operands
|
1106 |
|
|
(gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
|
1107 |
|
|
second.indices, &tmp_fields);
|
1108 |
|
|
}
|
1109 |
|
|
|
1110 |
|
|
if (second.insn == NULL)
|
1111 |
|
|
as_fatal (_("internal error: lookup/get operands failed"));
|
1112 |
|
|
|
1113 |
|
|
/* We assume that if the first instruction writes to a register that is
|
1114 |
|
|
read by the second instruction it is because the programmer intended
|
1115 |
|
|
this to happen, (after all they have explicitly requested that these
|
1116 |
|
|
two instructions be executed in parallel). Although if the global
|
1117 |
|
|
variable warn_explicit_parallel_conflicts is true then we do generate
|
1118 |
|
|
a warning message. Similarly we assume that parallel branch and jump
|
1119 |
|
|
instructions are deliberate and should not produce errors. */
|
1120 |
|
|
|
1121 |
|
|
if (parallel_p && warn_explicit_parallel_conflicts)
|
1122 |
|
|
{
|
1123 |
|
|
if (first_writes_to_seconds_operands (&first, &second, FALSE))
|
1124 |
|
|
/* xgettext:c-format */
|
1125 |
|
|
as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
|
1126 |
|
|
|
1127 |
|
|
if (first_writes_to_seconds_operands (&second, &first, FALSE))
|
1128 |
|
|
/* xgettext:c-format */
|
1129 |
|
|
as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
|
1130 |
|
|
}
|
1131 |
|
|
|
1132 |
|
|
if (!parallel_p
|
1133 |
|
|
|| (errmsg = (char *) can_make_parallel (&first, &second)) == NULL)
|
1134 |
|
|
{
|
1135 |
|
|
/* Get the fixups for the first instruction. */
|
1136 |
|
|
gas_cgen_swap_fixups (0);
|
1137 |
|
|
|
1138 |
|
|
/* Write it out. */
|
1139 |
|
|
expand_debug_syms (first.debug_sym_link, 1);
|
1140 |
|
|
gas_cgen_finish_insn (first.orig_insn, first.buffer,
|
1141 |
|
|
CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
|
1142 |
|
|
|
1143 |
|
|
/* Force the top bit of the second insn to be set. */
|
1144 |
|
|
if (parallel_p)
|
1145 |
|
|
make_parallel (second.buffer);
|
1146 |
|
|
|
1147 |
|
|
/* Get its fixups. */
|
1148 |
|
|
gas_cgen_restore_fixups (0);
|
1149 |
|
|
|
1150 |
|
|
/* Write it out. */
|
1151 |
|
|
expand_debug_syms (second.debug_sym_link, 1);
|
1152 |
|
|
gas_cgen_finish_insn (second.orig_insn, second.buffer,
|
1153 |
|
|
CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
|
1154 |
|
|
}
|
1155 |
|
|
/* Try swapping the instructions to see if they work that way. */
|
1156 |
|
|
else if (can_make_parallel (&second, &first) == NULL)
|
1157 |
|
|
{
|
1158 |
|
|
/* Write out the second instruction first. */
|
1159 |
|
|
expand_debug_syms (second.debug_sym_link, 1);
|
1160 |
|
|
gas_cgen_finish_insn (second.orig_insn, second.buffer,
|
1161 |
|
|
CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
|
1162 |
|
|
|
1163 |
|
|
/* Force the top bit of the first instruction to be set. */
|
1164 |
|
|
make_parallel (first.buffer);
|
1165 |
|
|
|
1166 |
|
|
/* Get the fixups for the first instruction. */
|
1167 |
|
|
gas_cgen_restore_fixups (0);
|
1168 |
|
|
|
1169 |
|
|
/* Write out the first instruction. */
|
1170 |
|
|
expand_debug_syms (first.debug_sym_link, 1);
|
1171 |
|
|
gas_cgen_finish_insn (first.orig_insn, first.buffer,
|
1172 |
|
|
CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
|
1173 |
|
|
}
|
1174 |
|
|
else
|
1175 |
|
|
{
|
1176 |
|
|
as_bad ("'%s': %s", str2, errmsg);
|
1177 |
|
|
return;
|
1178 |
|
|
}
|
1179 |
|
|
|
1180 |
|
|
if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)
|
1181 |
|
|
|| CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
1182 |
|
|
m32r_flags |= E_M32R_HAS_HIDDEN_INST;
|
1183 |
|
|
if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)
|
1184 |
|
|
|| CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))
|
1185 |
|
|
m32r_flags |= E_M32R_HAS_BIT_INST;
|
1186 |
|
|
if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)
|
1187 |
|
|
|| CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))
|
1188 |
|
|
m32r_flags |= E_M32R_HAS_FLOAT_INST;
|
1189 |
|
|
|
1190 |
|
|
/* Set these so m32r_fill_insn can use them. */
|
1191 |
|
|
prev_seg = now_seg;
|
1192 |
|
|
prev_subseg = now_subseg;
|
1193 |
|
|
}
|
1194 |
|
|
|
1195 |
|
|
void
|
1196 |
|
|
md_assemble (char *str)
|
1197 |
|
|
{
|
1198 |
|
|
m32r_insn insn;
|
1199 |
|
|
char *errmsg;
|
1200 |
|
|
char *str2 = NULL;
|
1201 |
|
|
|
1202 |
|
|
/* Initialize GAS's cgen interface for a new instruction. */
|
1203 |
|
|
gas_cgen_init_parse ();
|
1204 |
|
|
|
1205 |
|
|
/* Look for a parallel instruction separator. */
|
1206 |
|
|
if ((str2 = strstr (str, "||")) != NULL)
|
1207 |
|
|
{
|
1208 |
|
|
assemble_two_insns (str, str2, 1);
|
1209 |
|
|
m32r_flags |= E_M32R_HAS_PARALLEL;
|
1210 |
|
|
return;
|
1211 |
|
|
}
|
1212 |
|
|
|
1213 |
|
|
/* Also look for a sequential instruction separator. */
|
1214 |
|
|
if ((str2 = strstr (str, "->")) != NULL)
|
1215 |
|
|
{
|
1216 |
|
|
assemble_two_insns (str, str2, 0);
|
1217 |
|
|
return;
|
1218 |
|
|
}
|
1219 |
|
|
|
1220 |
|
|
insn.debug_sym_link = debug_sym_link;
|
1221 |
|
|
debug_sym_link = (sym_linkS *) 0;
|
1222 |
|
|
|
1223 |
|
|
insn.insn = m32r_cgen_assemble_insn
|
1224 |
|
|
(gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg);
|
1225 |
|
|
|
1226 |
|
|
if (!insn.insn)
|
1227 |
|
|
{
|
1228 |
|
|
as_bad (errmsg);
|
1229 |
|
|
return;
|
1230 |
|
|
}
|
1231 |
|
|
|
1232 |
|
|
#ifdef E_M32R2_ARCH
|
1233 |
|
|
if ((enable_m32rx == 1)
|
1234 |
|
|
/* FIXME: Need standard macro to perform this test. */
|
1235 |
|
|
&& ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
|
1236 |
|
|
& (1 << MACH_M32R2))
|
1237 |
|
|
&& !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
|
1238 |
|
|
& (1 << MACH_M32RX)))))
|
1239 |
|
|
{
|
1240 |
|
|
/* xgettext:c-format */
|
1241 |
|
|
as_bad (_("instruction '%s' is for the M32R2 only"), str);
|
1242 |
|
|
return;
|
1243 |
|
|
}
|
1244 |
|
|
else if ((! enable_special
|
1245 |
|
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
1246 |
|
|
|| (! enable_special_m32r
|
1247 |
|
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))
|
1248 |
|
|
#else
|
1249 |
|
|
if (! enable_special
|
1250 |
|
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
1251 |
|
|
#endif
|
1252 |
|
|
{
|
1253 |
|
|
/* xgettext:c-format */
|
1254 |
|
|
as_bad (_("unknown instruction '%s'"), str);
|
1255 |
|
|
return;
|
1256 |
|
|
}
|
1257 |
|
|
else if (! enable_m32rx
|
1258 |
|
|
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
|
1259 |
|
|
{
|
1260 |
|
|
/* xgettext:c-format */
|
1261 |
|
|
as_bad (_("instruction '%s' is for the M32RX only"), str);
|
1262 |
|
|
return;
|
1263 |
|
|
}
|
1264 |
|
|
|
1265 |
|
|
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
1266 |
|
|
m32r_flags |= E_M32R_HAS_HIDDEN_INST;
|
1267 |
|
|
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))
|
1268 |
|
|
m32r_flags |= E_M32R_HAS_BIT_INST;
|
1269 |
|
|
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))
|
1270 |
|
|
m32r_flags |= E_M32R_HAS_FLOAT_INST;
|
1271 |
|
|
|
1272 |
|
|
if (CGEN_INSN_BITSIZE (insn.insn) == 32)
|
1273 |
|
|
{
|
1274 |
|
|
/* 32 bit insns must live on 32 bit boundaries. */
|
1275 |
|
|
if (prev_insn.insn || seen_relaxable_p)
|
1276 |
|
|
{
|
1277 |
|
|
/* ??? If calling fill_insn too many times turns us into a memory
|
1278 |
|
|
pig, can we call a fn to assemble a nop instead of
|
1279 |
|
|
!seen_relaxable_p? */
|
1280 |
|
|
fill_insn (0);
|
1281 |
|
|
}
|
1282 |
|
|
|
1283 |
|
|
expand_debug_syms (insn.debug_sym_link, 2);
|
1284 |
|
|
|
1285 |
|
|
/* Doesn't really matter what we pass for RELAX_P here. */
|
1286 |
|
|
gas_cgen_finish_insn (insn.insn, insn.buffer,
|
1287 |
|
|
CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL);
|
1288 |
|
|
}
|
1289 |
|
|
else
|
1290 |
|
|
{
|
1291 |
|
|
int on_32bit_boundary_p;
|
1292 |
|
|
int swap = FALSE;
|
1293 |
|
|
|
1294 |
|
|
if (CGEN_INSN_BITSIZE (insn.insn) != 16)
|
1295 |
|
|
abort ();
|
1296 |
|
|
|
1297 |
|
|
insn.orig_insn = insn.insn;
|
1298 |
|
|
|
1299 |
|
|
/* If the previous insn was relaxable, then it may be expanded
|
1300 |
|
|
to fill the current 16 bit slot. Emit a NOP here to occupy
|
1301 |
|
|
this slot, so that we can start at optimizing at a 32 bit
|
1302 |
|
|
boundary. */
|
1303 |
|
|
if (prev_insn.insn && seen_relaxable_p && optimize)
|
1304 |
|
|
fill_insn (0);
|
1305 |
|
|
|
1306 |
|
|
if (enable_m32rx)
|
1307 |
|
|
{
|
1308 |
|
|
/* Get the indices of the operands of the instruction.
|
1309 |
|
|
FIXME: See assemble_parallel for notes on orig_insn. */
|
1310 |
|
|
{
|
1311 |
|
|
CGEN_FIELDS tmp_fields;
|
1312 |
|
|
insn.insn = cgen_lookup_get_insn_operands
|
1313 |
|
|
(gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
|
1314 |
|
|
16, insn.indices, &tmp_fields);
|
1315 |
|
|
}
|
1316 |
|
|
|
1317 |
|
|
if (insn.insn == NULL)
|
1318 |
|
|
as_fatal (_("internal error: lookup/get operands failed"));
|
1319 |
|
|
}
|
1320 |
|
|
|
1321 |
|
|
/* Compute whether we're on a 32 bit boundary or not.
|
1322 |
|
|
prev_insn.insn is NULL when we're on a 32 bit boundary. */
|
1323 |
|
|
on_32bit_boundary_p = prev_insn.insn == NULL;
|
1324 |
|
|
|
1325 |
|
|
/* Change a frag to, if each insn to swap is in a different frag.
|
1326 |
|
|
It must keep only one instruction in a frag. */
|
1327 |
|
|
if (parallel() && on_32bit_boundary_p)
|
1328 |
|
|
{
|
1329 |
|
|
frag_wane (frag_now);
|
1330 |
|
|
frag_new (0);
|
1331 |
|
|
}
|
1332 |
|
|
|
1333 |
|
|
/* Look to see if this instruction can be combined with the
|
1334 |
|
|
previous instruction to make one, parallel, 32 bit instruction.
|
1335 |
|
|
If the previous instruction (potentially) changed the flow of
|
1336 |
|
|
program control, then it cannot be combined with the current
|
1337 |
|
|
instruction. If the current instruction is relaxable, then it
|
1338 |
|
|
might be replaced with a longer version, so we cannot combine it.
|
1339 |
|
|
Also if the output of the previous instruction is used as an
|
1340 |
|
|
input to the current instruction then it cannot be combined.
|
1341 |
|
|
Otherwise call can_make_parallel() with both orderings of the
|
1342 |
|
|
instructions to see if they can be combined. */
|
1343 |
|
|
if (! on_32bit_boundary_p
|
1344 |
|
|
&& parallel ()
|
1345 |
|
|
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
|
1346 |
|
|
&& ! writes_to_pc (&prev_insn)
|
1347 |
|
|
&& ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
|
1348 |
|
|
{
|
1349 |
|
|
if (can_make_parallel (&prev_insn, &insn) == NULL)
|
1350 |
|
|
make_parallel (insn.buffer);
|
1351 |
|
|
else if (can_make_parallel (&insn, &prev_insn) == NULL)
|
1352 |
|
|
swap = TRUE;
|
1353 |
|
|
}
|
1354 |
|
|
|
1355 |
|
|
expand_debug_syms (insn.debug_sym_link, 1);
|
1356 |
|
|
|
1357 |
|
|
{
|
1358 |
|
|
int i;
|
1359 |
|
|
finished_insnS fi;
|
1360 |
|
|
|
1361 |
|
|
/* Ensure each pair of 16 bit insns is in the same frag. */
|
1362 |
|
|
frag_grow (4);
|
1363 |
|
|
|
1364 |
|
|
gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
|
1365 |
|
|
CGEN_FIELDS_BITSIZE (&insn.fields),
|
1366 |
|
|
1 /* relax_p */, &fi);
|
1367 |
|
|
insn.addr = fi.addr;
|
1368 |
|
|
insn.frag = fi.frag;
|
1369 |
|
|
insn.num_fixups = fi.num_fixups;
|
1370 |
|
|
for (i = 0; i < fi.num_fixups; ++i)
|
1371 |
|
|
insn.fixups[i] = fi.fixups[i];
|
1372 |
|
|
}
|
1373 |
|
|
|
1374 |
|
|
if (swap)
|
1375 |
|
|
{
|
1376 |
|
|
int i, tmp;
|
1377 |
|
|
|
1378 |
|
|
#define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
|
1379 |
|
|
|
1380 |
|
|
/* Swap the two insns */
|
1381 |
|
|
SWAP_BYTES (prev_insn.addr[0], insn.addr[0]);
|
1382 |
|
|
SWAP_BYTES (prev_insn.addr[1], insn.addr[1]);
|
1383 |
|
|
|
1384 |
|
|
target_make_parallel (insn.addr);
|
1385 |
|
|
|
1386 |
|
|
/* Swap any relaxable frags recorded for the two insns. */
|
1387 |
|
|
/* FIXME: Clarify. relaxation precludes parallel insns */
|
1388 |
|
|
if (prev_insn.frag->fr_opcode == prev_insn.addr)
|
1389 |
|
|
prev_insn.frag->fr_opcode = insn.addr;
|
1390 |
|
|
else if (insn.frag->fr_opcode == insn.addr)
|
1391 |
|
|
insn.frag->fr_opcode = prev_insn.addr;
|
1392 |
|
|
|
1393 |
|
|
/* Change a frag to, if each insn is in a different frag.
|
1394 |
|
|
It must keep only one instruction in a frag. */
|
1395 |
|
|
if (prev_insn.frag != insn.frag)
|
1396 |
|
|
{
|
1397 |
|
|
for (i = 0; i < prev_insn.num_fixups; ++i)
|
1398 |
|
|
prev_insn.fixups[i]->fx_frag = insn.frag;
|
1399 |
|
|
for (i = 0; i < insn.num_fixups; ++i)
|
1400 |
|
|
insn.fixups[i]->fx_frag = prev_insn.frag;
|
1401 |
|
|
}
|
1402 |
|
|
else
|
1403 |
|
|
{
|
1404 |
|
|
/* Update the addresses in any fixups.
|
1405 |
|
|
Note that we don't have to handle the case where each insn is in
|
1406 |
|
|
a different frag as we ensure they're in the same frag above. */
|
1407 |
|
|
for (i = 0; i < prev_insn.num_fixups; ++i)
|
1408 |
|
|
prev_insn.fixups[i]->fx_where += 2;
|
1409 |
|
|
for (i = 0; i < insn.num_fixups; ++i)
|
1410 |
|
|
insn.fixups[i]->fx_where -= 2;
|
1411 |
|
|
}
|
1412 |
|
|
}
|
1413 |
|
|
|
1414 |
|
|
/* Keep track of whether we've seen a pair of 16 bit insns.
|
1415 |
|
|
prev_insn.insn is NULL when we're on a 32 bit boundary. */
|
1416 |
|
|
if (on_32bit_boundary_p)
|
1417 |
|
|
prev_insn = insn;
|
1418 |
|
|
else
|
1419 |
|
|
prev_insn.insn = NULL;
|
1420 |
|
|
|
1421 |
|
|
/* If the insn needs the following one to be on a 32 bit boundary
|
1422 |
|
|
(e.g. subroutine calls), fill this insn's slot. */
|
1423 |
|
|
if (on_32bit_boundary_p
|
1424 |
|
|
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
|
1425 |
|
|
fill_insn (0);
|
1426 |
|
|
|
1427 |
|
|
/* If this is a relaxable insn (can be replaced with a larger version)
|
1428 |
|
|
mark the fact so that we can emit an alignment directive for a
|
1429 |
|
|
following 32 bit insn if we see one. */
|
1430 |
|
|
if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
|
1431 |
|
|
seen_relaxable_p = 1;
|
1432 |
|
|
}
|
1433 |
|
|
|
1434 |
|
|
/* Set these so m32r_fill_insn can use them. */
|
1435 |
|
|
prev_seg = now_seg;
|
1436 |
|
|
prev_subseg = now_subseg;
|
1437 |
|
|
}
|
1438 |
|
|
|
1439 |
|
|
/* The syntax in the manual says constants begin with '#'.
|
1440 |
|
|
We just ignore it. */
|
1441 |
|
|
|
1442 |
|
|
void
|
1443 |
|
|
md_operand (expressionS *expressionP)
|
1444 |
|
|
{
|
1445 |
|
|
if (*input_line_pointer == '#')
|
1446 |
|
|
{
|
1447 |
|
|
input_line_pointer++;
|
1448 |
|
|
expression (expressionP);
|
1449 |
|
|
}
|
1450 |
|
|
}
|
1451 |
|
|
|
1452 |
|
|
valueT
|
1453 |
|
|
md_section_align (segT segment, valueT size)
|
1454 |
|
|
{
|
1455 |
|
|
int align = bfd_get_section_alignment (stdoutput, segment);
|
1456 |
|
|
|
1457 |
|
|
return ((size + (1 << align) - 1) & (-1 << align));
|
1458 |
|
|
}
|
1459 |
|
|
|
1460 |
|
|
symbolS *
|
1461 |
|
|
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
|
1462 |
|
|
{
|
1463 |
|
|
return 0;
|
1464 |
|
|
}
|
1465 |
|
|
|
1466 |
|
|
/* .scomm pseudo-op handler.
|
1467 |
|
|
|
1468 |
|
|
This is a new pseudo-op to handle putting objects in .scommon.
|
1469 |
|
|
By doing this the linker won't need to do any work,
|
1470 |
|
|
and more importantly it removes the implicit -G arg necessary to
|
1471 |
|
|
correctly link the object file. */
|
1472 |
|
|
|
1473 |
|
|
static void
|
1474 |
|
|
m32r_scomm (int ignore ATTRIBUTE_UNUSED)
|
1475 |
|
|
{
|
1476 |
|
|
char *name;
|
1477 |
|
|
char c;
|
1478 |
|
|
char *p;
|
1479 |
|
|
offsetT size;
|
1480 |
|
|
symbolS *symbolP;
|
1481 |
|
|
offsetT align;
|
1482 |
|
|
int align2;
|
1483 |
|
|
|
1484 |
|
|
name = input_line_pointer;
|
1485 |
|
|
c = get_symbol_end ();
|
1486 |
|
|
|
1487 |
|
|
/* Just after name is now '\0'. */
|
1488 |
|
|
p = input_line_pointer;
|
1489 |
|
|
*p = c;
|
1490 |
|
|
SKIP_WHITESPACE ();
|
1491 |
|
|
if (*input_line_pointer != ',')
|
1492 |
|
|
{
|
1493 |
|
|
as_bad (_("Expected comma after symbol-name: rest of line ignored."));
|
1494 |
|
|
ignore_rest_of_line ();
|
1495 |
|
|
return;
|
1496 |
|
|
}
|
1497 |
|
|
|
1498 |
|
|
/* Skip ','. */
|
1499 |
|
|
input_line_pointer++;
|
1500 |
|
|
if ((size = get_absolute_expression ()) < 0)
|
1501 |
|
|
{
|
1502 |
|
|
/* xgettext:c-format */
|
1503 |
|
|
as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
|
1504 |
|
|
ignore_rest_of_line ();
|
1505 |
|
|
return;
|
1506 |
|
|
}
|
1507 |
|
|
|
1508 |
|
|
/* The third argument to .scomm is the alignment. */
|
1509 |
|
|
if (*input_line_pointer != ',')
|
1510 |
|
|
align = 8;
|
1511 |
|
|
else
|
1512 |
|
|
{
|
1513 |
|
|
++input_line_pointer;
|
1514 |
|
|
align = get_absolute_expression ();
|
1515 |
|
|
if (align <= 0)
|
1516 |
|
|
{
|
1517 |
|
|
as_warn (_("ignoring bad alignment"));
|
1518 |
|
|
align = 8;
|
1519 |
|
|
}
|
1520 |
|
|
}
|
1521 |
|
|
|
1522 |
|
|
/* Convert to a power of 2 alignment. */
|
1523 |
|
|
if (align)
|
1524 |
|
|
{
|
1525 |
|
|
for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
|
1526 |
|
|
continue;
|
1527 |
|
|
if (align != 1)
|
1528 |
|
|
{
|
1529 |
|
|
as_bad (_("Common alignment not a power of 2"));
|
1530 |
|
|
ignore_rest_of_line ();
|
1531 |
|
|
return;
|
1532 |
|
|
}
|
1533 |
|
|
}
|
1534 |
|
|
else
|
1535 |
|
|
align2 = 0;
|
1536 |
|
|
|
1537 |
|
|
*p = 0;
|
1538 |
|
|
symbolP = symbol_find_or_make (name);
|
1539 |
|
|
*p = c;
|
1540 |
|
|
|
1541 |
|
|
if (S_IS_DEFINED (symbolP))
|
1542 |
|
|
{
|
1543 |
|
|
/* xgettext:c-format */
|
1544 |
|
|
as_bad (_("Ignoring attempt to re-define symbol `%s'."),
|
1545 |
|
|
S_GET_NAME (symbolP));
|
1546 |
|
|
ignore_rest_of_line ();
|
1547 |
|
|
return;
|
1548 |
|
|
}
|
1549 |
|
|
|
1550 |
|
|
if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
|
1551 |
|
|
{
|
1552 |
|
|
/* xgettext:c-format */
|
1553 |
|
|
as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
|
1554 |
|
|
S_GET_NAME (symbolP),
|
1555 |
|
|
(long) S_GET_VALUE (symbolP),
|
1556 |
|
|
(long) size);
|
1557 |
|
|
|
1558 |
|
|
ignore_rest_of_line ();
|
1559 |
|
|
return;
|
1560 |
|
|
}
|
1561 |
|
|
|
1562 |
|
|
if (symbol_get_obj (symbolP)->local)
|
1563 |
|
|
{
|
1564 |
|
|
segT old_sec = now_seg;
|
1565 |
|
|
int old_subsec = now_subseg;
|
1566 |
|
|
char *pfrag;
|
1567 |
|
|
|
1568 |
|
|
record_alignment (sbss_section, align2);
|
1569 |
|
|
subseg_set (sbss_section, 0);
|
1570 |
|
|
|
1571 |
|
|
if (align2)
|
1572 |
|
|
frag_align (align2, 0, 0);
|
1573 |
|
|
|
1574 |
|
|
if (S_GET_SEGMENT (symbolP) == sbss_section)
|
1575 |
|
|
symbol_get_frag (symbolP)->fr_symbol = 0;
|
1576 |
|
|
|
1577 |
|
|
symbol_set_frag (symbolP, frag_now);
|
1578 |
|
|
|
1579 |
|
|
pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
|
1580 |
|
|
(char *) 0);
|
1581 |
|
|
*pfrag = 0;
|
1582 |
|
|
S_SET_SIZE (symbolP, size);
|
1583 |
|
|
S_SET_SEGMENT (symbolP, sbss_section);
|
1584 |
|
|
S_CLEAR_EXTERNAL (symbolP);
|
1585 |
|
|
subseg_set (old_sec, old_subsec);
|
1586 |
|
|
}
|
1587 |
|
|
else
|
1588 |
|
|
{
|
1589 |
|
|
S_SET_VALUE (symbolP, (valueT) size);
|
1590 |
|
|
S_SET_ALIGN (symbolP, align2);
|
1591 |
|
|
S_SET_EXTERNAL (symbolP);
|
1592 |
|
|
S_SET_SEGMENT (symbolP, &scom_section);
|
1593 |
|
|
}
|
1594 |
|
|
|
1595 |
|
|
demand_empty_rest_of_line ();
|
1596 |
|
|
}
|
1597 |
|
|
|
1598 |
|
|
/* The target specific pseudo-ops which we support. */
|
1599 |
|
|
const pseudo_typeS md_pseudo_table[] =
|
1600 |
|
|
{
|
1601 |
|
|
{ "word", cons, 4 },
|
1602 |
|
|
{ "fillinsn", fill_insn, 0 },
|
1603 |
|
|
{ "scomm", m32r_scomm, 0 },
|
1604 |
|
|
{ "debugsym", debug_sym, 0 },
|
1605 |
|
|
{ "m32r", allow_m32rx, 0 },
|
1606 |
|
|
{ "m32rx", allow_m32rx, 1 },
|
1607 |
|
|
{ "m32r2", allow_m32rx, 2 },
|
1608 |
|
|
{ "little", little, 1 },
|
1609 |
|
|
{ "big", little, 0 },
|
1610 |
|
|
{ NULL, NULL, 0 }
|
1611 |
|
|
};
|
1612 |
|
|
|
1613 |
|
|
/* Interface to relax_segment. */
|
1614 |
|
|
|
1615 |
|
|
/* FIXME: Build table by hand, get it working, then machine generate. */
|
1616 |
|
|
|
1617 |
|
|
const relax_typeS md_relax_table[] =
|
1618 |
|
|
{
|
1619 |
|
|
/* The fields are:
|
1620 |
|
|
1) most positive reach of this state,
|
1621 |
|
|
2) most negative reach of this state,
|
1622 |
|
|
3) how many bytes this mode will add to the size of the current frag
|
1623 |
|
|
4) which index into the table to try if we can't fit into this one. */
|
1624 |
|
|
|
1625 |
|
|
/* The first entry must be unused because an `rlx_more' value of zero ends
|
1626 |
|
|
each list. */
|
1627 |
|
|
{1, 1, 0, 0},
|
1628 |
|
|
|
1629 |
|
|
/* The displacement used by GAS is from the end of the 2 byte insn,
|
1630 |
|
|
so we subtract 2 from the following. */
|
1631 |
|
|
/* 16 bit insn, 8 bit disp -> 10 bit range.
|
1632 |
|
|
This doesn't handle a branch in the right slot at the border:
|
1633 |
|
|
the "& -4" isn't taken into account. It's not important enough to
|
1634 |
|
|
complicate things over it, so we subtract an extra 2 (or + 2 in -ve
|
1635 |
|
|
case). */
|
1636 |
|
|
{511 - 2 - 2, -512 - 2 + 2, 0, 2 },
|
1637 |
|
|
/* 32 bit insn, 24 bit disp -> 26 bit range. */
|
1638 |
|
|
{0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
|
1639 |
|
|
/* Same thing, but with leading nop for alignment. */
|
1640 |
|
|
{0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
|
1641 |
|
|
};
|
1642 |
|
|
|
1643 |
|
|
long
|
1644 |
|
|
m32r_relax_frag (segT segment, fragS *fragP, long stretch)
|
1645 |
|
|
{
|
1646 |
|
|
/* Address of branch insn. */
|
1647 |
|
|
long address = fragP->fr_address + fragP->fr_fix - 2;
|
1648 |
|
|
long growth = 0;
|
1649 |
|
|
|
1650 |
|
|
/* Keep 32 bit insns aligned on 32 bit boundaries. */
|
1651 |
|
|
if (fragP->fr_subtype == 2)
|
1652 |
|
|
{
|
1653 |
|
|
if ((address & 3) != 0)
|
1654 |
|
|
{
|
1655 |
|
|
fragP->fr_subtype = 3;
|
1656 |
|
|
growth = 2;
|
1657 |
|
|
}
|
1658 |
|
|
}
|
1659 |
|
|
else if (fragP->fr_subtype == 3)
|
1660 |
|
|
{
|
1661 |
|
|
if ((address & 3) == 0)
|
1662 |
|
|
{
|
1663 |
|
|
fragP->fr_subtype = 2;
|
1664 |
|
|
growth = -2;
|
1665 |
|
|
}
|
1666 |
|
|
}
|
1667 |
|
|
else
|
1668 |
|
|
{
|
1669 |
|
|
growth = relax_frag (segment, fragP, stretch);
|
1670 |
|
|
|
1671 |
|
|
/* Long jump on odd halfword boundary? */
|
1672 |
|
|
if (fragP->fr_subtype == 2 && (address & 3) != 0)
|
1673 |
|
|
{
|
1674 |
|
|
fragP->fr_subtype = 3;
|
1675 |
|
|
growth += 2;
|
1676 |
|
|
}
|
1677 |
|
|
}
|
1678 |
|
|
|
1679 |
|
|
return growth;
|
1680 |
|
|
}
|
1681 |
|
|
|
1682 |
|
|
/* Return an initial guess of the length by which a fragment must grow to
|
1683 |
|
|
hold a branch to reach its destination.
|
1684 |
|
|
Also updates fr_type/fr_subtype as necessary.
|
1685 |
|
|
|
1686 |
|
|
Called just before doing relaxation.
|
1687 |
|
|
Any symbol that is now undefined will not become defined.
|
1688 |
|
|
The guess for fr_var is ACTUALLY the growth beyond fr_fix.
|
1689 |
|
|
Whatever we do to grow fr_fix or fr_var contributes to our returned value.
|
1690 |
|
|
Although it may not be explicit in the frag, pretend fr_var starts
|
1691 |
|
|
with a 0 value. */
|
1692 |
|
|
|
1693 |
|
|
int
|
1694 |
|
|
md_estimate_size_before_relax (fragS *fragP, segT segment)
|
1695 |
|
|
{
|
1696 |
|
|
/* The only thing we have to handle here are symbols outside of the
|
1697 |
|
|
current segment. They may be undefined or in a different segment in
|
1698 |
|
|
which case linker scripts may place them anywhere.
|
1699 |
|
|
However, we can't finish the fragment here and emit the reloc as insn
|
1700 |
|
|
alignment requirements may move the insn about. */
|
1701 |
|
|
if (S_GET_SEGMENT (fragP->fr_symbol) != segment
|
1702 |
|
|
|| S_IS_EXTERNAL (fragP->fr_symbol)
|
1703 |
|
|
|| S_IS_WEAK (fragP->fr_symbol))
|
1704 |
|
|
{
|
1705 |
|
|
/* The symbol is undefined in this segment.
|
1706 |
|
|
Change the relaxation subtype to the max allowable and leave
|
1707 |
|
|
all further handling to md_convert_frag. */
|
1708 |
|
|
fragP->fr_subtype = 2;
|
1709 |
|
|
|
1710 |
|
|
{
|
1711 |
|
|
const CGEN_INSN *insn;
|
1712 |
|
|
int i;
|
1713 |
|
|
|
1714 |
|
|
/* Update the recorded insn.
|
1715 |
|
|
Fortunately we don't have to look very far.
|
1716 |
|
|
FIXME: Change this to record in the instruction the next higher
|
1717 |
|
|
relaxable insn to use. */
|
1718 |
|
|
for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
|
1719 |
|
|
{
|
1720 |
|
|
if ((strcmp (CGEN_INSN_MNEMONIC (insn),
|
1721 |
|
|
CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
|
1722 |
|
|
== 0)
|
1723 |
|
|
&& CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
|
1724 |
|
|
break;
|
1725 |
|
|
}
|
1726 |
|
|
if (i == 4)
|
1727 |
|
|
abort ();
|
1728 |
|
|
|
1729 |
|
|
fragP->fr_cgen.insn = insn;
|
1730 |
|
|
return 2;
|
1731 |
|
|
}
|
1732 |
|
|
}
|
1733 |
|
|
|
1734 |
|
|
return md_relax_table[fragP->fr_subtype].rlx_length;
|
1735 |
|
|
}
|
1736 |
|
|
|
1737 |
|
|
/* *FRAGP has been relaxed to its final size, and now needs to have
|
1738 |
|
|
the bytes inside it modified to conform to the new size.
|
1739 |
|
|
|
1740 |
|
|
Called after relaxation is finished.
|
1741 |
|
|
fragP->fr_type == rs_machine_dependent.
|
1742 |
|
|
fragP->fr_subtype is the subtype of what the address relaxed to. */
|
1743 |
|
|
|
1744 |
|
|
void
|
1745 |
|
|
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
|
1746 |
|
|
segT sec,
|
1747 |
|
|
fragS *fragP)
|
1748 |
|
|
{
|
1749 |
|
|
char *opcode;
|
1750 |
|
|
char *displacement;
|
1751 |
|
|
int target_address;
|
1752 |
|
|
int opcode_address;
|
1753 |
|
|
int extension;
|
1754 |
|
|
int addend;
|
1755 |
|
|
|
1756 |
|
|
opcode = fragP->fr_opcode;
|
1757 |
|
|
|
1758 |
|
|
/* Address opcode resides at in file space. */
|
1759 |
|
|
opcode_address = fragP->fr_address + fragP->fr_fix - 2;
|
1760 |
|
|
|
1761 |
|
|
switch (fragP->fr_subtype)
|
1762 |
|
|
{
|
1763 |
|
|
case 1:
|
1764 |
|
|
extension = 0;
|
1765 |
|
|
displacement = &opcode[1];
|
1766 |
|
|
break;
|
1767 |
|
|
case 2:
|
1768 |
|
|
opcode[0] |= 0x80;
|
1769 |
|
|
extension = 2;
|
1770 |
|
|
displacement = &opcode[1];
|
1771 |
|
|
break;
|
1772 |
|
|
case 3:
|
1773 |
|
|
opcode[2] = opcode[0] | 0x80;
|
1774 |
|
|
md_number_to_chars (opcode, PAR_NOP_INSN, 2);
|
1775 |
|
|
opcode_address += 2;
|
1776 |
|
|
extension = 4;
|
1777 |
|
|
displacement = &opcode[3];
|
1778 |
|
|
break;
|
1779 |
|
|
default:
|
1780 |
|
|
abort ();
|
1781 |
|
|
}
|
1782 |
|
|
|
1783 |
|
|
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|
1784 |
|
|
|| S_IS_EXTERNAL (fragP->fr_symbol)
|
1785 |
|
|
|| S_IS_WEAK (fragP->fr_symbol))
|
1786 |
|
|
{
|
1787 |
|
|
/* Symbol must be resolved by linker. */
|
1788 |
|
|
if (fragP->fr_offset & 3)
|
1789 |
|
|
as_warn (_("Addend to unresolved symbol not on word boundary."));
|
1790 |
|
|
#ifdef USE_M32R_OLD_RELOC
|
1791 |
|
|
addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */
|
1792 |
|
|
#else
|
1793 |
|
|
addend = 0;
|
1794 |
|
|
#endif
|
1795 |
|
|
}
|
1796 |
|
|
else
|
1797 |
|
|
{
|
1798 |
|
|
/* Address we want to reach in file space. */
|
1799 |
|
|
target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
|
1800 |
|
|
addend = (target_address - (opcode_address & -4)) >> 2;
|
1801 |
|
|
}
|
1802 |
|
|
|
1803 |
|
|
/* Create a relocation for symbols that must be resolved by the linker.
|
1804 |
|
|
Otherwise output the completed insn. */
|
1805 |
|
|
|
1806 |
|
|
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|
1807 |
|
|
|| S_IS_EXTERNAL (fragP->fr_symbol)
|
1808 |
|
|
|| S_IS_WEAK (fragP->fr_symbol))
|
1809 |
|
|
{
|
1810 |
|
|
fixS *fixP;
|
1811 |
|
|
|
1812 |
|
|
assert (fragP->fr_subtype != 1);
|
1813 |
|
|
assert (fragP->fr_cgen.insn != 0);
|
1814 |
|
|
|
1815 |
|
|
fixP = gas_cgen_record_fixup (fragP,
|
1816 |
|
|
/* Offset of branch insn in frag. */
|
1817 |
|
|
fragP->fr_fix + extension - 4,
|
1818 |
|
|
fragP->fr_cgen.insn,
|
1819 |
|
|
4 /* Length. */,
|
1820 |
|
|
/* FIXME: quick hack. */
|
1821 |
|
|
cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
|
1822 |
|
|
M32R_OPERAND_DISP24),
|
1823 |
|
|
fragP->fr_cgen.opinfo,
|
1824 |
|
|
fragP->fr_symbol, fragP->fr_offset);
|
1825 |
|
|
if (fragP->fr_cgen.opinfo)
|
1826 |
|
|
fixP->fx_r_type = fragP->fr_cgen.opinfo;
|
1827 |
|
|
}
|
1828 |
|
|
|
1829 |
|
|
#define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
|
1830 |
|
|
|
1831 |
|
|
md_number_to_chars (displacement, (valueT) addend,
|
1832 |
|
|
SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
|
1833 |
|
|
|
1834 |
|
|
fragP->fr_fix += extension;
|
1835 |
|
|
}
|
1836 |
|
|
|
1837 |
|
|
/* Functions concerning relocs. */
|
1838 |
|
|
|
1839 |
|
|
/* The location from which a PC relative jump should be calculated,
|
1840 |
|
|
given a PC relative reloc. */
|
1841 |
|
|
|
1842 |
|
|
long
|
1843 |
|
|
md_pcrel_from_section (fixS *fixP, segT sec)
|
1844 |
|
|
{
|
1845 |
|
|
if (fixP->fx_addsy != (symbolS *) NULL
|
1846 |
|
|
&& (! S_IS_DEFINED (fixP->fx_addsy)
|
1847 |
|
|
|| S_GET_SEGMENT (fixP->fx_addsy) != sec
|
1848 |
|
|
|| S_IS_EXTERNAL (fixP->fx_addsy)
|
1849 |
|
|
|| S_IS_WEAK (fixP->fx_addsy)))
|
1850 |
|
|
{
|
1851 |
|
|
if (S_GET_SEGMENT (fixP->fx_addsy) != sec
|
1852 |
|
|
&& S_IS_DEFINED (fixP->fx_addsy)
|
1853 |
|
|
&& ! S_IS_EXTERNAL (fixP->fx_addsy)
|
1854 |
|
|
&& ! S_IS_WEAK (fixP->fx_addsy))
|
1855 |
|
|
return fixP->fx_offset;
|
1856 |
|
|
|
1857 |
|
|
/* The symbol is undefined (or is defined but not in this section).
|
1858 |
|
|
Let the linker figure it out. */
|
1859 |
|
|
return 0;
|
1860 |
|
|
}
|
1861 |
|
|
|
1862 |
|
|
return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
|
1863 |
|
|
}
|
1864 |
|
|
|
1865 |
|
|
/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
|
1866 |
|
|
Returns BFD_RELOC_NONE if no reloc type can be found.
|
1867 |
|
|
*FIXP may be modified if desired. */
|
1868 |
|
|
|
1869 |
|
|
bfd_reloc_code_real_type
|
1870 |
|
|
md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
|
1871 |
|
|
const CGEN_OPERAND *operand,
|
1872 |
|
|
fixS *fixP)
|
1873 |
|
|
{
|
1874 |
|
|
switch (operand->type)
|
1875 |
|
|
{
|
1876 |
|
|
case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL;
|
1877 |
|
|
case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL;
|
1878 |
|
|
case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL;
|
1879 |
|
|
case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24;
|
1880 |
|
|
case M32R_OPERAND_HI16:
|
1881 |
|
|
case M32R_OPERAND_SLO16:
|
1882 |
|
|
case M32R_OPERAND_ULO16:
|
1883 |
|
|
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
|
1884 |
|
|
if (fixP->fx_cgen.opinfo != 0)
|
1885 |
|
|
return fixP->fx_cgen.opinfo;
|
1886 |
|
|
break;
|
1887 |
|
|
default:
|
1888 |
|
|
/* Avoid -Wall warning. */
|
1889 |
|
|
break;
|
1890 |
|
|
}
|
1891 |
|
|
return BFD_RELOC_NONE;
|
1892 |
|
|
}
|
1893 |
|
|
|
1894 |
|
|
/* Record a HI16 reloc for later matching with its LO16 cousin. */
|
1895 |
|
|
|
1896 |
|
|
static void
|
1897 |
|
|
m32r_record_hi16 (int reloc_type,
|
1898 |
|
|
fixS *fixP,
|
1899 |
|
|
segT seg ATTRIBUTE_UNUSED)
|
1900 |
|
|
{
|
1901 |
|
|
struct m32r_hi_fixup *hi_fixup;
|
1902 |
|
|
|
1903 |
|
|
assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
|
1904 |
|
|
|| reloc_type == BFD_RELOC_M32R_HI16_ULO);
|
1905 |
|
|
|
1906 |
|
|
hi_fixup = xmalloc (sizeof (* hi_fixup));
|
1907 |
|
|
hi_fixup->fixp = fixP;
|
1908 |
|
|
hi_fixup->seg = now_seg;
|
1909 |
|
|
hi_fixup->next = m32r_hi_fixup_list;
|
1910 |
|
|
|
1911 |
|
|
m32r_hi_fixup_list = hi_fixup;
|
1912 |
|
|
}
|
1913 |
|
|
|
1914 |
|
|
/* Called while parsing an instruction to create a fixup.
|
1915 |
|
|
We need to check for HI16 relocs and queue them up for later sorting. */
|
1916 |
|
|
|
1917 |
|
|
fixS *
|
1918 |
|
|
m32r_cgen_record_fixup_exp (fragS *frag,
|
1919 |
|
|
int where,
|
1920 |
|
|
const CGEN_INSN *insn,
|
1921 |
|
|
int length,
|
1922 |
|
|
const CGEN_OPERAND *operand,
|
1923 |
|
|
int opinfo,
|
1924 |
|
|
expressionS *exp)
|
1925 |
|
|
{
|
1926 |
|
|
fixS *fixP;
|
1927 |
|
|
bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
|
1928 |
|
|
|
1929 |
|
|
if (m32r_check_fixup (exp, &r_type))
|
1930 |
|
|
as_bad (_("Invalid PIC expression."));
|
1931 |
|
|
|
1932 |
|
|
fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
|
1933 |
|
|
operand, opinfo, exp);
|
1934 |
|
|
|
1935 |
|
|
switch (operand->type)
|
1936 |
|
|
{
|
1937 |
|
|
case M32R_OPERAND_HI16:
|
1938 |
|
|
/* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
|
1939 |
|
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
|
1940 |
|
|
|| fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
1941 |
|
|
m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
|
1942 |
|
|
break;
|
1943 |
|
|
|
1944 |
|
|
default:
|
1945 |
|
|
/* Avoid -Wall warning. */
|
1946 |
|
|
break;
|
1947 |
|
|
}
|
1948 |
|
|
|
1949 |
|
|
switch (r_type)
|
1950 |
|
|
{
|
1951 |
|
|
case BFD_RELOC_UNUSED:
|
1952 |
|
|
default:
|
1953 |
|
|
return fixP;
|
1954 |
|
|
|
1955 |
|
|
case BFD_RELOC_M32R_GOTPC24:
|
1956 |
|
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
|
1957 |
|
|
r_type = BFD_RELOC_M32R_GOTPC_HI_SLO;
|
1958 |
|
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
1959 |
|
|
r_type = BFD_RELOC_M32R_GOTPC_HI_ULO;
|
1960 |
|
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
|
1961 |
|
|
r_type = BFD_RELOC_M32R_GOTPC_LO;
|
1962 |
|
|
break;
|
1963 |
|
|
|
1964 |
|
|
case BFD_RELOC_M32R_GOT24:
|
1965 |
|
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
|
1966 |
|
|
r_type = BFD_RELOC_M32R_GOT16_HI_SLO;
|
1967 |
|
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
1968 |
|
|
r_type = BFD_RELOC_M32R_GOT16_HI_ULO;
|
1969 |
|
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
|
1970 |
|
|
r_type = BFD_RELOC_M32R_GOT16_LO;
|
1971 |
|
|
break;
|
1972 |
|
|
|
1973 |
|
|
case BFD_RELOC_M32R_GOTOFF:
|
1974 |
|
|
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
|
1975 |
|
|
r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO;
|
1976 |
|
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
|
1977 |
|
|
r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO;
|
1978 |
|
|
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
|
1979 |
|
|
r_type = BFD_RELOC_M32R_GOTOFF_LO;
|
1980 |
|
|
break;
|
1981 |
|
|
|
1982 |
|
|
case BFD_RELOC_M32R_26_PLTREL:
|
1983 |
|
|
as_bad (_("Invalid PIC expression."));
|
1984 |
|
|
break;
|
1985 |
|
|
}
|
1986 |
|
|
|
1987 |
|
|
fixP->fx_r_type = r_type;
|
1988 |
|
|
|
1989 |
|
|
return fixP;
|
1990 |
|
|
}
|
1991 |
|
|
|
1992 |
|
|
/* Return BFD reloc type from opinfo field in a fixS.
|
1993 |
|
|
It's tricky using fx_r_type in m32r_frob_file because the values
|
1994 |
|
|
are BFD_RELOC_UNUSED + operand number. */
|
1995 |
|
|
#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
|
1996 |
|
|
|
1997 |
|
|
/* Sort any unmatched HI16 relocs so that they immediately precede
|
1998 |
|
|
the corresponding LO16 reloc. This is called before md_apply_fix and
|
1999 |
|
|
tc_gen_reloc. */
|
2000 |
|
|
|
2001 |
|
|
void
|
2002 |
|
|
m32r_frob_file (void)
|
2003 |
|
|
{
|
2004 |
|
|
struct m32r_hi_fixup *l;
|
2005 |
|
|
|
2006 |
|
|
for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
|
2007 |
|
|
{
|
2008 |
|
|
segment_info_type *seginfo;
|
2009 |
|
|
int pass;
|
2010 |
|
|
|
2011 |
|
|
assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
|
2012 |
|
|
|| FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
|
2013 |
|
|
|
2014 |
|
|
/* Check quickly whether the next fixup happens to be a matching low. */
|
2015 |
|
|
if (l->fixp->fx_next != NULL
|
2016 |
|
|
&& FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
|
2017 |
|
|
&& l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
|
2018 |
|
|
&& l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
|
2019 |
|
|
continue;
|
2020 |
|
|
|
2021 |
|
|
/* Look through the fixups for this segment for a matching `low'.
|
2022 |
|
|
When we find one, move the high/shigh just in front of it. We do
|
2023 |
|
|
this in two passes. In the first pass, we try to find a
|
2024 |
|
|
unique `low'. In the second pass, we permit multiple high's
|
2025 |
|
|
relocs for a single `low'. */
|
2026 |
|
|
seginfo = seg_info (l->seg);
|
2027 |
|
|
for (pass = 0; pass < 2; pass++)
|
2028 |
|
|
{
|
2029 |
|
|
fixS *f;
|
2030 |
|
|
fixS *prev;
|
2031 |
|
|
|
2032 |
|
|
prev = NULL;
|
2033 |
|
|
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
2034 |
|
|
{
|
2035 |
|
|
/* Check whether this is a `low' fixup which matches l->fixp. */
|
2036 |
|
|
if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
|
2037 |
|
|
&& f->fx_addsy == l->fixp->fx_addsy
|
2038 |
|
|
&& f->fx_offset == l->fixp->fx_offset
|
2039 |
|
|
&& (pass == 1
|
2040 |
|
|
|| prev == NULL
|
2041 |
|
|
|| (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
|
2042 |
|
|
&& FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
|
2043 |
|
|
|| prev->fx_addsy != f->fx_addsy
|
2044 |
|
|
|| prev->fx_offset != f->fx_offset))
|
2045 |
|
|
{
|
2046 |
|
|
fixS **pf;
|
2047 |
|
|
|
2048 |
|
|
/* Move l->fixp before f. */
|
2049 |
|
|
for (pf = &seginfo->fix_root;
|
2050 |
|
|
*pf != l->fixp;
|
2051 |
|
|
pf = & (*pf)->fx_next)
|
2052 |
|
|
assert (*pf != NULL);
|
2053 |
|
|
|
2054 |
|
|
*pf = l->fixp->fx_next;
|
2055 |
|
|
|
2056 |
|
|
l->fixp->fx_next = f;
|
2057 |
|
|
if (prev == NULL)
|
2058 |
|
|
seginfo->fix_root = l->fixp;
|
2059 |
|
|
else
|
2060 |
|
|
prev->fx_next = l->fixp;
|
2061 |
|
|
|
2062 |
|
|
break;
|
2063 |
|
|
}
|
2064 |
|
|
|
2065 |
|
|
prev = f;
|
2066 |
|
|
}
|
2067 |
|
|
|
2068 |
|
|
if (f != NULL)
|
2069 |
|
|
break;
|
2070 |
|
|
|
2071 |
|
|
if (pass == 1
|
2072 |
|
|
&& warn_unmatched_high)
|
2073 |
|
|
as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
|
2074 |
|
|
_("Unmatched high/shigh reloc"));
|
2075 |
|
|
}
|
2076 |
|
|
}
|
2077 |
|
|
}
|
2078 |
|
|
|
2079 |
|
|
/* See whether we need to force a relocation into the output file.
|
2080 |
|
|
This is used to force out switch and PC relative relocations when
|
2081 |
|
|
relaxing. */
|
2082 |
|
|
|
2083 |
|
|
int
|
2084 |
|
|
m32r_force_relocation (fixS *fix)
|
2085 |
|
|
{
|
2086 |
|
|
if (generic_force_reloc (fix))
|
2087 |
|
|
return 1;
|
2088 |
|
|
|
2089 |
|
|
if (! m32r_relax)
|
2090 |
|
|
return 0;
|
2091 |
|
|
|
2092 |
|
|
return fix->fx_pcrel;
|
2093 |
|
|
}
|
2094 |
|
|
|
2095 |
|
|
/* Write a value out to the object file, using the appropriate endianness. */
|
2096 |
|
|
|
2097 |
|
|
void
|
2098 |
|
|
md_number_to_chars (char *buf, valueT val, int n)
|
2099 |
|
|
{
|
2100 |
|
|
if (target_big_endian)
|
2101 |
|
|
number_to_chars_bigendian (buf, val, n);
|
2102 |
|
|
else
|
2103 |
|
|
number_to_chars_littleendian (buf, val, n);
|
2104 |
|
|
}
|
2105 |
|
|
|
2106 |
|
|
/* Turn a string in input_line_pointer into a floating point constant
|
2107 |
|
|
of type TYPE, and store the appropriate bytes in *LITP. The number
|
2108 |
|
|
of LITTLENUMS emitted is stored in *SIZEP. An error message is
|
2109 |
|
|
returned, or NULL on OK. */
|
2110 |
|
|
|
2111 |
|
|
/* Equal to MAX_PRECISION in atof-ieee.c. */
|
2112 |
|
|
#define MAX_LITTLENUMS 6
|
2113 |
|
|
|
2114 |
|
|
char *
|
2115 |
|
|
md_atof (int type, char *litP, int *sizeP)
|
2116 |
|
|
{
|
2117 |
|
|
return ieee_md_atof (type, litP, sizeP, target_big_endian);
|
2118 |
|
|
}
|
2119 |
|
|
|
2120 |
|
|
void
|
2121 |
|
|
m32r_elf_section_change_hook (void)
|
2122 |
|
|
{
|
2123 |
|
|
/* If we have reached the end of a section and we have just emitted a
|
2124 |
|
|
16 bit insn, then emit a nop to make sure that the section ends on
|
2125 |
|
|
a 32 bit boundary. */
|
2126 |
|
|
|
2127 |
|
|
if (prev_insn.insn || seen_relaxable_p)
|
2128 |
|
|
(void) m32r_fill_insn (0);
|
2129 |
|
|
}
|
2130 |
|
|
|
2131 |
|
|
/* Return true if can adjust the reloc to be relative to its section
|
2132 |
|
|
(such as .data) instead of relative to some symbol. */
|
2133 |
|
|
|
2134 |
|
|
bfd_boolean
|
2135 |
|
|
m32r_fix_adjustable (fixS *fixP)
|
2136 |
|
|
{
|
2137 |
|
|
bfd_reloc_code_real_type reloc_type;
|
2138 |
|
|
|
2139 |
|
|
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
|
2140 |
|
|
{
|
2141 |
|
|
const CGEN_INSN *insn = NULL;
|
2142 |
|
|
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
|
2143 |
|
|
const CGEN_OPERAND *operand =
|
2144 |
|
|
cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
|
2145 |
|
|
|
2146 |
|
|
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
|
2147 |
|
|
}
|
2148 |
|
|
else
|
2149 |
|
|
reloc_type = fixP->fx_r_type;
|
2150 |
|
|
|
2151 |
|
|
if (fixP->fx_addsy == NULL)
|
2152 |
|
|
return 1;
|
2153 |
|
|
|
2154 |
|
|
/* Prevent all adjustments to global symbols. */
|
2155 |
|
|
if (S_IS_EXTERNAL (fixP->fx_addsy))
|
2156 |
|
|
return 0;
|
2157 |
|
|
if (S_IS_WEAK (fixP->fx_addsy))
|
2158 |
|
|
return 0;
|
2159 |
|
|
|
2160 |
|
|
if (pic_code
|
2161 |
|
|
&& (reloc_type == BFD_RELOC_M32R_24
|
2162 |
|
|
|| reloc_type == BFD_RELOC_M32R_26_PCREL
|
2163 |
|
|
|| reloc_type == BFD_RELOC_M32R_HI16_SLO
|
2164 |
|
|
|| reloc_type == BFD_RELOC_M32R_HI16_ULO
|
2165 |
|
|
|| reloc_type == BFD_RELOC_M32R_LO16))
|
2166 |
|
|
return 0;
|
2167 |
|
|
|
2168 |
|
|
if (reloc_type == BFD_RELOC_M32R_GOT24
|
2169 |
|
|
|| reloc_type == BFD_RELOC_M32R_26_PLTREL
|
2170 |
|
|
|| reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO
|
2171 |
|
|
|| reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO
|
2172 |
|
|
|| reloc_type == BFD_RELOC_M32R_GOTPC_LO
|
2173 |
|
|
|| reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO
|
2174 |
|
|
|| reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO
|
2175 |
|
|
|| reloc_type == BFD_RELOC_M32R_GOT16_LO)
|
2176 |
|
|
return 0;
|
2177 |
|
|
|
2178 |
|
|
/* We need the symbol name for the VTABLE entries. */
|
2179 |
|
|
if (reloc_type == BFD_RELOC_VTABLE_INHERIT
|
2180 |
|
|
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
|
2181 |
|
|
return 0;
|
2182 |
|
|
|
2183 |
|
|
return 1;
|
2184 |
|
|
}
|
2185 |
|
|
|
2186 |
|
|
void
|
2187 |
|
|
m32r_elf_final_processing (void)
|
2188 |
|
|
{
|
2189 |
|
|
if (use_parallel)
|
2190 |
|
|
m32r_flags |= E_M32R_HAS_PARALLEL;
|
2191 |
|
|
elf_elfheader (stdoutput)->e_flags |= m32r_flags;
|
2192 |
|
|
}
|
2193 |
|
|
|
2194 |
|
|
/* Translate internal representation of relocation info to BFD target
|
2195 |
|
|
format. */
|
2196 |
|
|
|
2197 |
|
|
arelent *
|
2198 |
|
|
tc_gen_reloc (asection * section, fixS * fixP)
|
2199 |
|
|
{
|
2200 |
|
|
arelent * reloc;
|
2201 |
|
|
bfd_reloc_code_real_type code;
|
2202 |
|
|
|
2203 |
|
|
reloc = xmalloc (sizeof (* reloc));
|
2204 |
|
|
|
2205 |
|
|
reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
|
2206 |
|
|
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
|
2207 |
|
|
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
|
2208 |
|
|
|
2209 |
|
|
if (fixP->fx_pcrel)
|
2210 |
|
|
{
|
2211 |
|
|
if (fixP->fx_r_type == BFD_RELOC_32)
|
2212 |
|
|
fixP->fx_r_type = BFD_RELOC_32_PCREL;
|
2213 |
|
|
else if (fixP->fx_r_type == BFD_RELOC_16)
|
2214 |
|
|
{
|
2215 |
|
|
fixP->fx_r_type = BFD_RELOC_16_PCREL;
|
2216 |
|
|
bfd_set_error (bfd_error_bad_value);
|
2217 |
|
|
}
|
2218 |
|
|
}
|
2219 |
|
|
|
2220 |
|
|
code = fixP->fx_r_type;
|
2221 |
|
|
if (pic_code)
|
2222 |
|
|
{
|
2223 |
|
|
#ifdef DEBUG_PIC
|
2224 |
|
|
printf("%s",bfd_get_reloc_code_name(code));
|
2225 |
|
|
#endif
|
2226 |
|
|
switch (code)
|
2227 |
|
|
{
|
2228 |
|
|
case BFD_RELOC_M32R_26_PCREL:
|
2229 |
|
|
code = BFD_RELOC_M32R_26_PLTREL;
|
2230 |
|
|
break;
|
2231 |
|
|
|
2232 |
|
|
case BFD_RELOC_M32R_24:
|
2233 |
|
|
if (fixP->fx_addsy != NULL
|
2234 |
|
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
2235 |
|
|
code = BFD_RELOC_M32R_GOTPC24;
|
2236 |
|
|
else
|
2237 |
|
|
code = BFD_RELOC_M32R_GOT24;
|
2238 |
|
|
break;
|
2239 |
|
|
|
2240 |
|
|
case BFD_RELOC_M32R_HI16_ULO:
|
2241 |
|
|
if (fixP->fx_addsy != NULL
|
2242 |
|
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
2243 |
|
|
code = BFD_RELOC_M32R_GOTPC_HI_ULO;
|
2244 |
|
|
else
|
2245 |
|
|
code = BFD_RELOC_M32R_GOT16_HI_ULO;
|
2246 |
|
|
break;
|
2247 |
|
|
|
2248 |
|
|
case BFD_RELOC_M32R_HI16_SLO:
|
2249 |
|
|
if (fixP->fx_addsy != NULL
|
2250 |
|
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
2251 |
|
|
code = BFD_RELOC_M32R_GOTPC_HI_SLO;
|
2252 |
|
|
else
|
2253 |
|
|
code = BFD_RELOC_M32R_GOT16_HI_SLO;
|
2254 |
|
|
break;
|
2255 |
|
|
|
2256 |
|
|
case BFD_RELOC_M32R_LO16:
|
2257 |
|
|
if (fixP->fx_addsy != NULL
|
2258 |
|
|
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
|
2259 |
|
|
code = BFD_RELOC_M32R_GOTPC_LO;
|
2260 |
|
|
else
|
2261 |
|
|
code = BFD_RELOC_M32R_GOT16_LO;
|
2262 |
|
|
break;
|
2263 |
|
|
|
2264 |
|
|
default:
|
2265 |
|
|
break;
|
2266 |
|
|
}
|
2267 |
|
|
#ifdef DEBUG_PIC
|
2268 |
|
|
printf(" => %s",bfd_get_reloc_code_name(code));
|
2269 |
|
|
#endif
|
2270 |
|
|
}
|
2271 |
|
|
|
2272 |
|
|
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
|
2273 |
|
|
|
2274 |
|
|
#ifdef DEBUG_PIC
|
2275 |
|
|
printf(" => %s\n",reloc->howto->name);
|
2276 |
|
|
#endif
|
2277 |
|
|
|
2278 |
|
|
if (reloc->howto == (reloc_howto_type *) NULL)
|
2279 |
|
|
{
|
2280 |
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
2281 |
|
|
_("internal error: can't export reloc type %d (`%s')"),
|
2282 |
|
|
fixP->fx_r_type, bfd_get_reloc_code_name (code));
|
2283 |
|
|
return NULL;
|
2284 |
|
|
}
|
2285 |
|
|
|
2286 |
|
|
/* Use fx_offset for these cases. */
|
2287 |
|
|
if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
|
2288 |
|
|
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
2289 |
|
|
|| fixP->fx_r_type == BFD_RELOC_32_PCREL)
|
2290 |
|
|
reloc->addend = fixP->fx_offset;
|
2291 |
|
|
else if ((!pic_code
|
2292 |
|
|
&& code != BFD_RELOC_M32R_26_PLTREL)
|
2293 |
|
|
&& fixP->fx_pcrel
|
2294 |
|
|
&& fixP->fx_addsy != NULL
|
2295 |
|
|
&& (S_GET_SEGMENT(fixP->fx_addsy) != section)
|
2296 |
|
|
&& S_IS_DEFINED (fixP->fx_addsy)
|
2297 |
|
|
&& ! S_IS_EXTERNAL(fixP->fx_addsy)
|
2298 |
|
|
&& ! S_IS_WEAK(fixP->fx_addsy))
|
2299 |
|
|
/* Already used fx_offset in the opcode field itseld. */
|
2300 |
|
|
reloc->addend = fixP->fx_offset;
|
2301 |
|
|
else
|
2302 |
|
|
reloc->addend = fixP->fx_addnumber;
|
2303 |
|
|
|
2304 |
|
|
return reloc;
|
2305 |
|
|
}
|
2306 |
|
|
|
2307 |
|
|
inline static char *
|
2308 |
|
|
m32r_end_of_match (char *cont, char *what)
|
2309 |
|
|
{
|
2310 |
|
|
int len = strlen (what);
|
2311 |
|
|
|
2312 |
|
|
if (strncasecmp (cont, what, strlen (what)) == 0
|
2313 |
|
|
&& ! is_part_of_name (cont[len]))
|
2314 |
|
|
return cont + len;
|
2315 |
|
|
|
2316 |
|
|
return NULL;
|
2317 |
|
|
}
|
2318 |
|
|
|
2319 |
|
|
int
|
2320 |
|
|
m32r_parse_name (char const *name,
|
2321 |
|
|
expressionS *exprP,
|
2322 |
|
|
enum expr_mode mode,
|
2323 |
|
|
char *nextcharP)
|
2324 |
|
|
{
|
2325 |
|
|
char *next = input_line_pointer;
|
2326 |
|
|
char *next_end;
|
2327 |
|
|
int reloc_type;
|
2328 |
|
|
operatorT op_type;
|
2329 |
|
|
segT segment;
|
2330 |
|
|
|
2331 |
|
|
exprP->X_op_symbol = NULL;
|
2332 |
|
|
exprP->X_md = BFD_RELOC_UNUSED;
|
2333 |
|
|
|
2334 |
|
|
if (strcmp (name, GOT_NAME) == 0)
|
2335 |
|
|
{
|
2336 |
|
|
if (! GOT_symbol)
|
2337 |
|
|
GOT_symbol = symbol_find_or_make (name);
|
2338 |
|
|
|
2339 |
|
|
exprP->X_add_symbol = GOT_symbol;
|
2340 |
|
|
no_suffix:
|
2341 |
|
|
/* If we have an absolute symbol or a
|
2342 |
|
|
reg, then we know its value now. */
|
2343 |
|
|
segment = S_GET_SEGMENT (exprP->X_add_symbol);
|
2344 |
|
|
if (mode != expr_defer && segment == absolute_section)
|
2345 |
|
|
{
|
2346 |
|
|
exprP->X_op = O_constant;
|
2347 |
|
|
exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
|
2348 |
|
|
exprP->X_add_symbol = NULL;
|
2349 |
|
|
}
|
2350 |
|
|
else if (mode != expr_defer && segment == reg_section)
|
2351 |
|
|
{
|
2352 |
|
|
exprP->X_op = O_register;
|
2353 |
|
|
exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
|
2354 |
|
|
exprP->X_add_symbol = NULL;
|
2355 |
|
|
}
|
2356 |
|
|
else
|
2357 |
|
|
{
|
2358 |
|
|
exprP->X_op = O_symbol;
|
2359 |
|
|
exprP->X_add_number = 0;
|
2360 |
|
|
}
|
2361 |
|
|
|
2362 |
|
|
return 1;
|
2363 |
|
|
}
|
2364 |
|
|
|
2365 |
|
|
exprP->X_add_symbol = symbol_find_or_make (name);
|
2366 |
|
|
|
2367 |
|
|
if (*nextcharP != '@')
|
2368 |
|
|
goto no_suffix;
|
2369 |
|
|
else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF")))
|
2370 |
|
|
{
|
2371 |
|
|
reloc_type = BFD_RELOC_M32R_GOTOFF;
|
2372 |
|
|
op_type = O_PIC_reloc;
|
2373 |
|
|
}
|
2374 |
|
|
else if ((next_end = m32r_end_of_match (next + 1, "GOT")))
|
2375 |
|
|
{
|
2376 |
|
|
reloc_type = BFD_RELOC_M32R_GOT24;
|
2377 |
|
|
op_type = O_PIC_reloc;
|
2378 |
|
|
}
|
2379 |
|
|
else if ((next_end = m32r_end_of_match (next + 1, "PLT")))
|
2380 |
|
|
{
|
2381 |
|
|
reloc_type = BFD_RELOC_M32R_26_PLTREL;
|
2382 |
|
|
op_type = O_PIC_reloc;
|
2383 |
|
|
}
|
2384 |
|
|
else
|
2385 |
|
|
goto no_suffix;
|
2386 |
|
|
|
2387 |
|
|
*input_line_pointer = *nextcharP;
|
2388 |
|
|
input_line_pointer = next_end;
|
2389 |
|
|
*nextcharP = *input_line_pointer;
|
2390 |
|
|
*input_line_pointer = '\0';
|
2391 |
|
|
|
2392 |
|
|
exprP->X_op = op_type;
|
2393 |
|
|
exprP->X_add_number = 0;
|
2394 |
|
|
exprP->X_md = reloc_type;
|
2395 |
|
|
|
2396 |
|
|
return 1;
|
2397 |
|
|
}
|
2398 |
|
|
|
2399 |
|
|
int
|
2400 |
|
|
m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp)
|
2401 |
|
|
{
|
2402 |
|
|
if (exp->X_op == O_PIC_reloc
|
2403 |
|
|
&& exp->X_md == BFD_RELOC_M32R_26_PLTREL)
|
2404 |
|
|
{
|
2405 |
|
|
exp->X_op = O_symbol;
|
2406 |
|
|
opinfo = exp->X_md;
|
2407 |
|
|
}
|
2408 |
|
|
|
2409 |
|
|
return opinfo;
|
2410 |
|
|
}
|