1 |
12 |
jlechner |
;; Scheduling description for Alpha EV6.
|
2 |
|
|
;; Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc.
|
3 |
|
|
;;
|
4 |
|
|
;; This file is part of GCC.
|
5 |
|
|
;;
|
6 |
|
|
;; GCC is free software; you can redistribute it and/or modify
|
7 |
|
|
;; it under the terms of the GNU General Public License as published by
|
8 |
|
|
;; the Free Software Foundation; either version 2, or (at your option)
|
9 |
|
|
;; any later version.
|
10 |
|
|
;;
|
11 |
|
|
;; GCC is distributed in the hope that it will be useful,
|
12 |
|
|
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
|
|
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
14 |
|
|
;; GNU General Public License for more details.
|
15 |
|
|
;;
|
16 |
|
|
;; You should have received a copy of the GNU General Public License
|
17 |
|
|
;; along with GCC; see the file COPYING. If not, write to
|
18 |
|
|
;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
|
19 |
|
|
;; Boston, MA 02110-1301, USA.
|
20 |
|
|
|
21 |
|
|
; EV6 can issue 4 insns per clock. It's out-of-order, so this isn't
|
22 |
|
|
; expected to help over-much, but a precise description can be important
|
23 |
|
|
; for software pipelining.
|
24 |
|
|
;
|
25 |
|
|
; EV6 has two symmetric pairs ("clusters") of two asymmetric integer
|
26 |
|
|
; units ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
|
27 |
|
|
;
|
28 |
|
|
; ??? The clusters have independent register files that are re-synced
|
29 |
|
|
; every cycle. Thus there is one additional cycle of latency between
|
30 |
|
|
; insns issued on different clusters. Possibly model that by duplicating
|
31 |
|
|
; all EBOX insn_reservations that can issue to either cluster, increasing
|
32 |
|
|
; all latencies by one, and adding bypasses within the cluster.
|
33 |
|
|
;
|
34 |
|
|
; ??? In addition, instruction order affects cluster issue.
|
35 |
|
|
|
36 |
|
|
(define_automaton "ev6_0,ev6_1")
|
37 |
|
|
(define_cpu_unit "ev6_u0,ev6_u1,ev6_l0,ev6_l1" "ev6_0")
|
38 |
|
|
(define_reservation "ev6_u" "ev6_u0|ev6_u1")
|
39 |
|
|
(define_reservation "ev6_l" "ev6_l0|ev6_l1")
|
40 |
|
|
(define_reservation "ev6_ebox" "ev6_u|ev6_l")
|
41 |
|
|
|
42 |
|
|
(define_cpu_unit "ev6_fa" "ev6_1")
|
43 |
|
|
(define_cpu_unit "ev6_fm,ev6_fst0,ev6_fst1" "ev6_0")
|
44 |
|
|
(define_reservation "ev6_fst" "ev6_fst0|ev6_fst1")
|
45 |
|
|
|
46 |
|
|
; Assume type "multi" single issues.
|
47 |
|
|
(define_insn_reservation "ev6_multi" 1
|
48 |
|
|
(and (eq_attr "tune" "ev6")
|
49 |
|
|
(eq_attr "type" "multi"))
|
50 |
|
|
"ev6_u0+ev6_u1+ev6_l0+ev6_l1+ev6_fa+ev6_fm+ev6_fst0+ev6_fst1")
|
51 |
|
|
|
52 |
|
|
; Integer loads take at least 3 clocks, and only issue to lower units.
|
53 |
|
|
; adjust_cost still factors in user-specified memory latency, so return 1 here.
|
54 |
|
|
(define_insn_reservation "ev6_ild" 1
|
55 |
|
|
(and (eq_attr "tune" "ev6")
|
56 |
|
|
(eq_attr "type" "ild,ldsym,ld_l"))
|
57 |
|
|
"ev6_l")
|
58 |
|
|
|
59 |
|
|
(define_insn_reservation "ev6_ist" 1
|
60 |
|
|
(and (eq_attr "tune" "ev6")
|
61 |
|
|
(eq_attr "type" "ist,st_c"))
|
62 |
|
|
"ev6_l")
|
63 |
|
|
|
64 |
|
|
(define_insn_reservation "ev6_mb" 1
|
65 |
|
|
(and (eq_attr "tune" "ev6")
|
66 |
|
|
(eq_attr "type" "mb"))
|
67 |
|
|
"ev6_l1")
|
68 |
|
|
|
69 |
|
|
; FP loads take at least 4 clocks. adjust_cost still factors
|
70 |
|
|
; in user-specified memory latency, so return 2 here.
|
71 |
|
|
(define_insn_reservation "ev6_fld" 2
|
72 |
|
|
(and (eq_attr "tune" "ev6")
|
73 |
|
|
(eq_attr "type" "fld"))
|
74 |
|
|
"ev6_l")
|
75 |
|
|
|
76 |
|
|
; The FPU communicates with memory and the integer register file
|
77 |
|
|
; via two fp store units. We need a slot in the fst immediately, and
|
78 |
|
|
; a slot in LOW after the operand data is ready. At which point the
|
79 |
|
|
; data may be moved either to the store queue or the integer register
|
80 |
|
|
; file and the insn retired.
|
81 |
|
|
|
82 |
|
|
(define_insn_reservation "ev6_fst" 3
|
83 |
|
|
(and (eq_attr "tune" "ev6")
|
84 |
|
|
(eq_attr "type" "fst"))
|
85 |
|
|
"ev6_fst,nothing,ev6_l")
|
86 |
|
|
|
87 |
|
|
; Arithmetic goes anywhere.
|
88 |
|
|
(define_insn_reservation "ev6_arith" 1
|
89 |
|
|
(and (eq_attr "tune" "ev6")
|
90 |
|
|
(eq_attr "type" "iadd,ilog,icmp"))
|
91 |
|
|
"ev6_ebox")
|
92 |
|
|
|
93 |
|
|
; Motion video insns also issue only to U0, and take three ticks.
|
94 |
|
|
(define_insn_reservation "ev6_mvi" 3
|
95 |
|
|
(and (eq_attr "tune" "ev6")
|
96 |
|
|
(eq_attr "type" "mvi"))
|
97 |
|
|
"ev6_u0")
|
98 |
|
|
|
99 |
|
|
; Shifts issue to upper units.
|
100 |
|
|
(define_insn_reservation "ev6_shift" 1
|
101 |
|
|
(and (eq_attr "tune" "ev6")
|
102 |
|
|
(eq_attr "type" "shift"))
|
103 |
|
|
"ev6_u")
|
104 |
|
|
|
105 |
|
|
; Multiplies issue only to U1, and all take 7 ticks.
|
106 |
|
|
(define_insn_reservation "ev6_imul" 7
|
107 |
|
|
(and (eq_attr "tune" "ev6")
|
108 |
|
|
(eq_attr "type" "imul"))
|
109 |
|
|
"ev6_u1")
|
110 |
|
|
|
111 |
|
|
; Conditional moves decompose into two independent primitives, each taking
|
112 |
|
|
; one cycle. Since ev6 is out-of-order, we can't see anything but two cycles.
|
113 |
|
|
(define_insn_reservation "ev6_icmov" 2
|
114 |
|
|
(and (eq_attr "tune" "ev6")
|
115 |
|
|
(eq_attr "type" "icmov"))
|
116 |
|
|
"ev6_ebox,ev6_ebox")
|
117 |
|
|
|
118 |
|
|
; Integer branches issue to upper units
|
119 |
|
|
(define_insn_reservation "ev6_ibr" 1
|
120 |
|
|
(and (eq_attr "tune" "ev6")
|
121 |
|
|
(eq_attr "type" "ibr,callpal"))
|
122 |
|
|
"ev6_u")
|
123 |
|
|
|
124 |
|
|
; Calls only issue to L0.
|
125 |
|
|
(define_insn_reservation "ev6_jsr" 1
|
126 |
|
|
(and (eq_attr "tune" "ev6")
|
127 |
|
|
(eq_attr "type" "jsr"))
|
128 |
|
|
"ev6_l0")
|
129 |
|
|
|
130 |
|
|
; Ftoi/itof only issue to lower pipes.
|
131 |
|
|
(define_insn_reservation "ev6_itof" 3
|
132 |
|
|
(and (eq_attr "tune" "ev6")
|
133 |
|
|
(eq_attr "type" "itof"))
|
134 |
|
|
"ev6_l")
|
135 |
|
|
|
136 |
|
|
(define_insn_reservation "ev6_ftoi" 3
|
137 |
|
|
(and (eq_attr "tune" "ev6")
|
138 |
|
|
(eq_attr "type" "ftoi"))
|
139 |
|
|
"ev6_fst,nothing,ev6_l")
|
140 |
|
|
|
141 |
|
|
(define_insn_reservation "ev6_fmul" 4
|
142 |
|
|
(and (eq_attr "tune" "ev6")
|
143 |
|
|
(eq_attr "type" "fmul"))
|
144 |
|
|
"ev6_fm")
|
145 |
|
|
|
146 |
|
|
(define_insn_reservation "ev6_fadd" 4
|
147 |
|
|
(and (eq_attr "tune" "ev6")
|
148 |
|
|
(eq_attr "type" "fadd,fcpys,fbr"))
|
149 |
|
|
"ev6_fa")
|
150 |
|
|
|
151 |
|
|
(define_insn_reservation "ev6_fcmov" 8
|
152 |
|
|
(and (eq_attr "tune" "ev6")
|
153 |
|
|
(eq_attr "type" "fcmov"))
|
154 |
|
|
"ev6_fa,nothing*3,ev6_fa")
|
155 |
|
|
|
156 |
|
|
(define_insn_reservation "ev6_fdivsf" 12
|
157 |
|
|
(and (eq_attr "tune" "ev6")
|
158 |
|
|
(and (eq_attr "type" "fdiv")
|
159 |
|
|
(eq_attr "opsize" "si")))
|
160 |
|
|
"ev6_fa*9")
|
161 |
|
|
|
162 |
|
|
(define_insn_reservation "ev6_fdivdf" 15
|
163 |
|
|
(and (eq_attr "tune" "ev6")
|
164 |
|
|
(and (eq_attr "type" "fdiv")
|
165 |
|
|
(eq_attr "opsize" "di")))
|
166 |
|
|
"ev6_fa*12")
|
167 |
|
|
|
168 |
|
|
(define_insn_reservation "ev6_sqrtsf" 18
|
169 |
|
|
(and (eq_attr "tune" "ev6")
|
170 |
|
|
(and (eq_attr "type" "fsqrt")
|
171 |
|
|
(eq_attr "opsize" "si")))
|
172 |
|
|
"ev6_fa*15")
|
173 |
|
|
|
174 |
|
|
(define_insn_reservation "ev6_sqrtdf" 33
|
175 |
|
|
(and (eq_attr "tune" "ev6")
|
176 |
|
|
(and (eq_attr "type" "fsqrt")
|
177 |
|
|
(eq_attr "opsize" "di")))
|
178 |
|
|
"ev6_fa*30")
|