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jlechner |
;; ARM 1026EJ-S Pipeline Description
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;; Copyright (C) 2003 Free Software Foundation, Inc.
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;; Written by CodeSourcery, LLC.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to the Free
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;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
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;; 02110-1301, USA. */
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;; These descriptions are based on the information contained in the
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;; ARM1026EJ-S Technical Reference Manual, Copyright (c) 2003 ARM
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;; Limited.
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;;
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;; This automaton provides a pipeline description for the ARM
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;; 1026EJ-S core.
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;;
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;; The model given here assumes that the condition for all conditional
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;; instructions is "true", i.e., that all of the instructions are
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;; actually executed.
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(define_automaton "arm1026ejs")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Pipelines
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; There are two pipelines:
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;;
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;; - An Arithmetic Logic Unit (ALU) pipeline.
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;;
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;; The ALU pipeline has fetch, issue, decode, execute, memory, and
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;; write stages. We only need to model the execute, memory and write
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;; stages.
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;;
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;; - A Load-Store Unit (LSU) pipeline.
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;;
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;; The LSU pipeline has decode, execute, memory, and write stages.
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;; We only model the execute, memory and write stages.
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(define_cpu_unit "a_e,a_m,a_w" "arm1026ejs")
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(define_cpu_unit "l_e,l_m,l_w" "arm1026ejs")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU instructions require three cycles to execute, and use the ALU
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;; pipeline in each of the three stages. The results are available
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;; after the execute stage stage has finished.
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;;
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;; If the destination register is the PC, the pipelines are stalled
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;; for several cycles. That case is not modeled here.
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;; ALU operations with no shifted operand
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(define_insn_reservation "alu_op" 1
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "alu"))
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"a_e,a_m,a_w")
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;; ALU operations with a shift-by-constant operand
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(define_insn_reservation "alu_shift_op" 1
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "alu_shift"))
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"a_e,a_m,a_w")
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;; ALU operations with a shift-by-register operand
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;; These really stall in the decoder, in order to read
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;; the shift value in a second cycle. Pretend we take two cycles in
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;; the execute stage.
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(define_insn_reservation "alu_shift_reg_op" 2
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "alu_shift_reg"))
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"a_e*2,a_m,a_w")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Multiplication Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Multiplication instructions loop in the execute stage until the
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;; instruction has been passed through the multiplier array enough
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;; times.
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;; The result of the "smul" and "smulw" instructions is not available
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;; until after the memory stage.
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(define_insn_reservation "mult1" 2
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "insn" "smulxy,smulwy"))
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"a_e,a_m,a_w")
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;; The "smlaxy" and "smlawx" instructions require two iterations through
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;; the execute stage; the result is available immediately following
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;; the execute stage.
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(define_insn_reservation "mult2" 2
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "insn" "smlaxy,smlalxy,smlawx"))
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"a_e*2,a_m,a_w")
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;; The "smlalxy", "mul", and "mla" instructions require two iterations
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;; through the execute stage; the result is not available until after
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;; the memory stage.
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(define_insn_reservation "mult3" 3
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "insn" "smlalxy,mul,mla"))
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"a_e*2,a_m,a_w")
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;; The "muls" and "mlas" instructions loop in the execute stage for
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;; four iterations in order to set the flags. The value result is
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;; available after three iterations.
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(define_insn_reservation "mult4" 3
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "insn" "muls,mlas"))
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"a_e*4,a_m,a_w")
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;; Long multiply instructions that produce two registers of
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;; output (such as umull) make their results available in two cycles;
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;; the least significant word is available before the most significant
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;; word. That fact is not modeled; instead, the instructions are
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;; described.as if the entire result was available at the end of the
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;; cycle in which both words are available.
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;; The "umull", "umlal", "smull", and "smlal" instructions all take
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;; three iterations through the execute cycle, and make their results
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;; available after the memory cycle.
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(define_insn_reservation "mult5" 4
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "insn" "umull,umlal,smull,smlal"))
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"a_e*3,a_m,a_w")
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;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
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;; the execute stage for five iterations in order to set the flags.
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;; The value result is available after four iterations.
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(define_insn_reservation "mult6" 4
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "insn" "umulls,umlals,smulls,smlals"))
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"a_e*5,a_m,a_w")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Load/Store Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The models for load/store instructions do not accurately describe
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;; the difference between operations with a base register writeback
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;; (such as "ldm!"). These models assume that all memory references
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;; hit in dcache.
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;; LSU instructions require six cycles to execute. They use the ALU
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;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
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;; three through six.
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;; Loads and stores which use a scaled register offset or scaled
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;; register pre-indexed addressing mode take three cycles EXCEPT for
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;; those that are base + offset with LSL of 0 or 2, or base - offset
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;; with LSL of zero. The remainder take 1 cycle to execute.
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;; For 4byte loads there is a bypass from the load stage
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(define_insn_reservation "load1_op" 2
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "load_byte,load1"))
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"a_e+l_e,l_m,a_w+l_w")
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(define_insn_reservation "store1_op" 0
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "store1"))
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"a_e+l_e,l_m,a_w+l_w")
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;; A load's result can be stored by an immediately following store
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(define_bypass 1 "load1_op" "store1_op" "arm_no_early_store_addr_dep")
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;; On a LDM/STM operation, the LSU pipeline iterates until all of the
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;; registers have been processed.
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;;
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;; The time it takes to load the data depends on whether or not the
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;; base address is 64-bit aligned; if it is not, an additional cycle
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;; is required. This model assumes that the address is always 64-bit
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;; aligned. Because the processor can load two registers per cycle,
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;; that assumption means that we use the same instruction reservations
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;; for loading 2k and 2k - 1 registers.
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;;
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;; The ALU pipeline is stalled until the completion of the last memory
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;; stage in the LSU pipeline. That is modeled by keeping the ALU
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;; execute stage busy until that point.
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;;
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;; As with ALU operations, if one of the destination registers is the
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;; PC, there are additional stalls; that is not modeled.
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(define_insn_reservation "load2_op" 2
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "load2"))
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"a_e+l_e,l_m,a_w+l_w")
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(define_insn_reservation "store2_op" 0
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "store2"))
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"a_e+l_e,l_m,a_w+l_w")
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(define_insn_reservation "load34_op" 3
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "load3,load4"))
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"a_e+l_e,a_e+l_e+l_m,a_e+l_m,a_w+l_w")
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(define_insn_reservation "store34_op" 0
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "store3,store4"))
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"a_e+l_e,a_e+l_e+l_m,a_e+l_m,a_w+l_w")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branch and Call Instructions
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branch instructions are difficult to model accurately. The ARM
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;; core can predict most branches. If the branch is predicted
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;; correctly, and predicted early enough, the branch can be completely
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;; eliminated from the instruction stream. Some branches can
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;; therefore appear to require zero cycles to execute. We assume that
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;; all branches are predicted correctly, and that the latency is
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;; therefore the minimum value.
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(define_insn_reservation "branch_op" 0
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "branch"))
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"nothing")
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;; The latency for a call is not predictable. Therefore, we use 32 as
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;; roughly equivalent to positive infinity.
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(define_insn_reservation "call_op" 32
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(and (eq_attr "tune" "arm1026ejs")
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(eq_attr "type" "call"))
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"nothing")
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