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jlechner |
;; Itanium2 DFA descriptions for insn scheduling and bundling.
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;; Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc.
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;; Contributed by Vladimir Makarov .
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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;; Boston, MA 02110-1301, USA. */
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;;
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/* This is description of pipeline hazards based on DFA. The
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following constructions can be used for this:
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o define_cpu_unit string [string]) describes a cpu functional unit
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(separated by comma).
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1st operand: Names of cpu function units.
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2nd operand: Name of automaton (see comments for
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DEFINE_AUTOMATON).
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All define_reservations and define_cpu_units should have unique
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names which cannot be "nothing".
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o (exclusion_set string string) means that each CPU function unit
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in the first string cannot be reserved simultaneously with each
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unit whose name is in the second string and vise versa. CPU
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units in the string are separated by commas. For example, it is
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useful for description CPU with fully pipelined floating point
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functional unit which can execute simultaneously only single
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floating point insns or only double floating point insns.
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o (presence_set string string) means that each CPU function unit in
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the first string cannot be reserved unless at least one of
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pattern of units whose names are in the second string is
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reserved. This is an asymmetric relation. CPU units or unit
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patterns in the strings are separated by commas. Pattern is one
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unit name or unit names separated by white-spaces.
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For example, it is useful for description that slot1 is reserved
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after slot0 reservation for a VLIW processor. We could describe
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it by the following construction
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(presence_set "slot1" "slot0")
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Or slot1 is reserved only after slot0 and unit b0 reservation.
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In this case we could write
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(presence_set "slot1" "slot0 b0")
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All CPU functional units in a set should belong to the same
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automaton.
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o (final_presence_set string string) is analogous to
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`presence_set'. The difference between them is when checking is
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done. When an instruction is issued in given automaton state
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reflecting all current and planned unit reservations, the
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automaton state is changed. The first state is a source state,
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the second one is a result state. Checking for `presence_set' is
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done on the source state reservation, checking for
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`final_presence_set' is done on the result reservation. This
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construction is useful to describe a reservation which is
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actually two subsequent reservations. For example, if we use
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(presence_set "slot1" "slot0")
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the following insn will be never issued (because slot1 requires
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slot0 which is absent in the source state).
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(define_reservation "insn_and_nop" "slot0 + slot1")
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but it can be issued if we use analogous `final_presence_set'.
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o (absence_set string string) means that each CPU function unit in
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the first string can be reserved only if each pattern of units
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whose names are in the second string is not reserved. This is an
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asymmetric relation (actually exclusion set is analogous to this
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one but it is symmetric). CPU units or unit patterns in the
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string are separated by commas. Pattern is one unit name or unit
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names separated by white-spaces.
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For example, it is useful for description that slot0 cannot be
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reserved after slot1 or slot2 reservation for a VLIW processor.
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We could describe it by the following construction
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(absence_set "slot2" "slot0, slot1")
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Or slot2 cannot be reserved if slot0 and unit b0 are reserved or
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slot1 and unit b1 are reserved . In this case we could write
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(absence_set "slot2" "slot0 b0, slot1 b1")
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All CPU functional units in a set should to belong the same
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automaton.
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o (final_absence_set string string) is analogous to `absence_set' but
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checking is done on the result (state) reservation. See comments
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for final_presence_set.
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o (define_bypass number out_insn_names in_insn_names) names bypass with
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given latency (the first number) from insns given by the first
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string (see define_insn_reservation) into insns given by the
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second string. Insn names in the strings are separated by
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commas.
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o (define_automaton string) describes names of an automaton
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generated and used for pipeline hazards recognition. The names
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are separated by comma. Actually it is possibly to generate the
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single automaton but unfortunately it can be very large. If we
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use more one automata, the summary size of the automata usually
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is less than the single one. The automaton name is used in
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define_cpu_unit. All automata should have unique names.
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o (automata_option string) describes option for generation of
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automata. Currently there are the following options:
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o "no-minimization" which makes no minimization of automata.
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This is only worth to do when we are debugging the description
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and need to look more accurately at reservations of states.
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o "ndfa" which makes automata with nondetermenistic reservation
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by insns.
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o (define_reservation string string) names reservation (the first
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string) of cpu functional units (the 2nd string). Sometimes unit
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reservations for different insns contain common parts. In such
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case, you describe common part and use one its name (the 1st
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parameter) in regular expression in define_insn_reservation. All
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define_reservations, define results and define_cpu_units should
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have unique names which cannot be "nothing".
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o (define_insn_reservation name default_latency condition regexpr)
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describes reservation of cpu functional units (the 3nd operand)
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for instruction which is selected by the condition (the 2nd
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parameter). The first parameter is used for output of debugging
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information. The reservations are described by a regular
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expression according the following syntax:
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regexp = regexp "," oneof
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| oneof
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oneof = oneof "|" allof
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| allof
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allof = allof "+" repeat
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| repeat
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repeat = element "*" number
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| element
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element = cpu_function_name
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| reservation_name
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| result_name
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| "nothing"
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| "(" regexp ")"
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1. "," is used for describing start of the next cycle in
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reservation.
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2. "|" is used for describing the reservation described by the
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first regular expression *or* the reservation described by
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the second regular expression *or* etc.
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3. "+" is used for describing the reservation described by the
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first regular expression *and* the reservation described by
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the second regular expression *and* etc.
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4. "*" is used for convenience and simply means sequence in
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which the regular expression are repeated NUMBER times with
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cycle advancing (see ",").
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5. cpu function unit name which means reservation.
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6. reservation name -- see define_reservation.
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7. string "nothing" means no units reservation.
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*/
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(define_automaton "two")
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;; All possible combinations of bundles/syllables
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(define_cpu_unit "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
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2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" "two")
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(define_cpu_unit "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\
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2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." "two")
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(define_cpu_unit "2_0mii., 2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\
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2_0mib., 2_0mmb., 2_0mfb." "two")
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(define_cpu_unit "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\
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2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" "two")
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(define_cpu_unit "2_1mi.i, 2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\
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2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx." "two")
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(define_cpu_unit "2_1mii., 2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\
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2_1mib., 2_1mmb., 2_1mfb." "two")
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;; Slot 1
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(exclusion_set "2_0m.ii" "2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
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2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
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(exclusion_set "2_0m.mi" "2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib,\
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2_0m.mb, 2_0m.fb, 2_0m.lx")
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(exclusion_set "2_0m.fi" "2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb,\
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2_0m.fb, 2_0m.lx")
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(exclusion_set "2_0m.mf" "2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb,\
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2_0m.lx")
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(exclusion_set "2_0b.bb" "2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
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(exclusion_set "2_0m.bb" "2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
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(exclusion_set "2_0m.ib" "2_0m.mb, 2_0m.fb, 2_0m.lx")
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(exclusion_set "2_0m.mb" "2_0m.fb, 2_0m.lx")
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(exclusion_set "2_0m.fb" "2_0m.lx")
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;; Slot 2
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(exclusion_set "2_0mi.i" "2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\
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2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
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(exclusion_set "2_0mm.i" "2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\
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2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
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(exclusion_set "2_0mf.i" "2_0mm.f, 2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b,\
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2_0mf.b, 2_0mlx.")
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(exclusion_set "2_0mm.f" "2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b,\
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2_0mlx.")
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(exclusion_set "2_0bb.b" "2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
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(exclusion_set "2_0mb.b" "2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
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(exclusion_set "2_0mi.b" "2_0mm.b, 2_0mf.b, 2_0mlx.")
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(exclusion_set "2_0mm.b" "2_0mf.b, 2_0mlx.")
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(exclusion_set "2_0mf.b" "2_0mlx.")
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;; Slot 3
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(exclusion_set "2_0mii." "2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\
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2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.")
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(exclusion_set "2_0mmi." "2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\
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2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.")
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(exclusion_set "2_0mfi." "2_0mmf., 2_0bbb., 2_0mbb., 2_0mib., 2_0mmb.,\
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2_0mfb., 2_0mlx.")
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(exclusion_set "2_0mmf." "2_0bbb., 2_0mbb., 2_0mib., 2_0mmb., 2_0mfb.,\
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2_0mlx.")
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(exclusion_set "2_0bbb." "2_0mbb., 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.")
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(exclusion_set "2_0mbb." "2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.")
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(exclusion_set "2_0mib." "2_0mmb., 2_0mfb., 2_0mlx.")
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(exclusion_set "2_0mmb." "2_0mfb., 2_0mlx.")
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(exclusion_set "2_0mfb." "2_0mlx.")
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;; Slot 4
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(exclusion_set "2_1m.ii" "2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\
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2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx")
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(exclusion_set "2_1m.mi" "2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib,\
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2_1m.mb, 2_1m.fb, 2_1m.lx")
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(exclusion_set "2_1m.fi" "2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb,\
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2_1m.fb, 2_1m.lx")
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(exclusion_set "2_1m.mf" "2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb,\
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2_1m.lx")
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(exclusion_set "2_1b.bb" "2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx")
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(exclusion_set "2_1m.bb" "2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx")
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(exclusion_set "2_1m.ib" "2_1m.mb, 2_1m.fb, 2_1m.lx")
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(exclusion_set "2_1m.mb" "2_1m.fb, 2_1m.lx")
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(exclusion_set "2_1m.fb" "2_1m.lx")
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;; Slot 5
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(exclusion_set "2_1mi.i" "2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\
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2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.")
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(exclusion_set "2_1mm.i" "2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\
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2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.")
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(exclusion_set "2_1mf.i" "2_1mm.f, 2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b,\
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2_1mf.b, 2_1mlx.")
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(exclusion_set "2_1mm.f" "2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b,\
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2_1mlx.")
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(exclusion_set "2_1bb.b" "2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.")
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|
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(exclusion_set "2_1mb.b" "2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.")
|
279 |
|
|
(exclusion_set "2_1mi.b" "2_1mm.b, 2_1mf.b, 2_1mlx.")
|
280 |
|
|
(exclusion_set "2_1mm.b" "2_1mf.b, 2_1mlx.")
|
281 |
|
|
(exclusion_set "2_1mf.b" "2_1mlx.")
|
282 |
|
|
|
283 |
|
|
;; Slot 6
|
284 |
|
|
(exclusion_set "2_1mii." "2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\
|
285 |
|
|
2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.")
|
286 |
|
|
(exclusion_set "2_1mmi." "2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\
|
287 |
|
|
2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.")
|
288 |
|
|
(exclusion_set "2_1mfi." "2_1mmf., 2_1bbb., 2_1mbb., 2_1mib., 2_1mmb.,\
|
289 |
|
|
2_1mfb., 2_1mlx.")
|
290 |
|
|
(exclusion_set "2_1mmf." "2_1bbb., 2_1mbb., 2_1mib., 2_1mmb., 2_1mfb.,\
|
291 |
|
|
2_1mlx.")
|
292 |
|
|
(exclusion_set "2_1bbb." "2_1mbb., 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.")
|
293 |
|
|
(exclusion_set "2_1mbb." "2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.")
|
294 |
|
|
(exclusion_set "2_1mib." "2_1mmb., 2_1mfb., 2_1mlx.")
|
295 |
|
|
(exclusion_set "2_1mmb." "2_1mfb., 2_1mlx.")
|
296 |
|
|
(exclusion_set "2_1mfb." "2_1mlx.")
|
297 |
|
|
|
298 |
|
|
(final_presence_set "2_0mi.i" "2_0m.ii")
|
299 |
|
|
(final_presence_set "2_0mii." "2_0mi.i")
|
300 |
|
|
(final_presence_set "2_1mi.i" "2_1m.ii")
|
301 |
|
|
(final_presence_set "2_1mii." "2_1mi.i")
|
302 |
|
|
|
303 |
|
|
(final_presence_set "2_0mm.i" "2_0m.mi")
|
304 |
|
|
(final_presence_set "2_0mmi." "2_0mm.i")
|
305 |
|
|
(final_presence_set "2_1mm.i" "2_1m.mi")
|
306 |
|
|
(final_presence_set "2_1mmi." "2_1mm.i")
|
307 |
|
|
|
308 |
|
|
(final_presence_set "2_0mf.i" "2_0m.fi")
|
309 |
|
|
(final_presence_set "2_0mfi." "2_0mf.i")
|
310 |
|
|
(final_presence_set "2_1mf.i" "2_1m.fi")
|
311 |
|
|
(final_presence_set "2_1mfi." "2_1mf.i")
|
312 |
|
|
|
313 |
|
|
(final_presence_set "2_0mm.f" "2_0m.mf")
|
314 |
|
|
(final_presence_set "2_0mmf." "2_0mm.f")
|
315 |
|
|
(final_presence_set "2_1mm.f" "2_1m.mf")
|
316 |
|
|
(final_presence_set "2_1mmf." "2_1mm.f")
|
317 |
|
|
|
318 |
|
|
(final_presence_set "2_0bb.b" "2_0b.bb")
|
319 |
|
|
(final_presence_set "2_0bbb." "2_0bb.b")
|
320 |
|
|
(final_presence_set "2_1bb.b" "2_1b.bb")
|
321 |
|
|
(final_presence_set "2_1bbb." "2_1bb.b")
|
322 |
|
|
|
323 |
|
|
(final_presence_set "2_0mb.b" "2_0m.bb")
|
324 |
|
|
(final_presence_set "2_0mbb." "2_0mb.b")
|
325 |
|
|
(final_presence_set "2_1mb.b" "2_1m.bb")
|
326 |
|
|
(final_presence_set "2_1mbb." "2_1mb.b")
|
327 |
|
|
|
328 |
|
|
(final_presence_set "2_0mi.b" "2_0m.ib")
|
329 |
|
|
(final_presence_set "2_0mib." "2_0mi.b")
|
330 |
|
|
(final_presence_set "2_1mi.b" "2_1m.ib")
|
331 |
|
|
(final_presence_set "2_1mib." "2_1mi.b")
|
332 |
|
|
|
333 |
|
|
(final_presence_set "2_0mm.b" "2_0m.mb")
|
334 |
|
|
(final_presence_set "2_0mmb." "2_0mm.b")
|
335 |
|
|
(final_presence_set "2_1mm.b" "2_1m.mb")
|
336 |
|
|
(final_presence_set "2_1mmb." "2_1mm.b")
|
337 |
|
|
|
338 |
|
|
(final_presence_set "2_0mf.b" "2_0m.fb")
|
339 |
|
|
(final_presence_set "2_0mfb." "2_0mf.b")
|
340 |
|
|
(final_presence_set "2_1mf.b" "2_1m.fb")
|
341 |
|
|
(final_presence_set "2_1mfb." "2_1mf.b")
|
342 |
|
|
|
343 |
|
|
(final_presence_set "2_0mlx." "2_0m.lx")
|
344 |
|
|
(final_presence_set "2_1mlx." "2_1m.lx")
|
345 |
|
|
|
346 |
|
|
;; The following reflects the dual issue bundle types table.
|
347 |
|
|
;; We could place all possible combinations here because impossible
|
348 |
|
|
;; combinations would go away by the subsequent constrains.
|
349 |
|
|
(final_presence_set
|
350 |
|
|
"2_1m.lx"
|
351 |
|
|
"2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.")
|
352 |
|
|
(final_presence_set "2_1b.bb" "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mlx.")
|
353 |
|
|
(final_presence_set
|
354 |
|
|
"2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1m.bb,2_1m.ib,2_1m.mb,2_1m.fb"
|
355 |
|
|
"2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.")
|
356 |
|
|
|
357 |
|
|
;; Ports/units (nb means nop.b insn issued into given port):
|
358 |
|
|
(define_cpu_unit
|
359 |
|
|
"2_um0, 2_um1, 2_um2, 2_um3, 2_ui0, 2_ui1, 2_uf0, 2_uf1,\
|
360 |
|
|
2_ub0, 2_ub1, 2_ub2, 2_unb0, 2_unb1, 2_unb2" "two")
|
361 |
|
|
|
362 |
|
|
(exclusion_set "2_ub0" "2_unb0")
|
363 |
|
|
(exclusion_set "2_ub1" "2_unb1")
|
364 |
|
|
(exclusion_set "2_ub2" "2_unb2")
|
365 |
|
|
|
366 |
|
|
;; The following rules are used to decrease number of alternatives.
|
367 |
|
|
;; They are consequences of Itanium2 microarchitecture. They also
|
368 |
|
|
;; describe the following rules mentioned in Itanium2
|
369 |
|
|
;; microarchitecture: rules mentioned in Itanium2 microarchitecture:
|
370 |
|
|
;; o "BBB/MBB: Always splits issue after either of these bundles".
|
371 |
|
|
;; o "MIB BBB: Split issue after the first bundle in this pair".
|
372 |
|
|
(exclusion_set
|
373 |
|
|
"2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb."
|
374 |
|
|
"2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1b.bb,2_1m.bb,\
|
375 |
|
|
2_1m.ib,2_1m.mb,2_1m.fb,2_1m.lx")
|
376 |
|
|
(exclusion_set "2_0m.ib,2_0mi.b,2_0mib." "2_1b.bb")
|
377 |
|
|
|
378 |
|
|
;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
|
379 |
|
|
;;; B-slot contains a nop.b or a brp instruction".
|
380 |
|
|
;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
|
381 |
|
|
;;; nop.b, otherwise it disperses to B2".
|
382 |
|
|
(final_absence_set
|
383 |
|
|
"2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\
|
384 |
|
|
2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx"
|
385 |
|
|
"2_0mib. 2_ub2, 2_0mfb. 2_ub2, 2_0mmb. 2_ub2")
|
386 |
|
|
|
387 |
|
|
;; This is necessary to start new processor cycle when we meet stop bit.
|
388 |
|
|
(define_cpu_unit "2_stop" "two")
|
389 |
|
|
(final_absence_set
|
390 |
|
|
"2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\
|
391 |
|
|
2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\
|
392 |
|
|
2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\
|
393 |
|
|
2_0m.lx,2_0mlx., \
|
394 |
|
|
2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\
|
395 |
|
|
2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\
|
396 |
|
|
2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\
|
397 |
|
|
2_1m.lx,2_1mlx."
|
398 |
|
|
"2_stop")
|
399 |
|
|
|
400 |
|
|
;; The issue logic can reorder M slot insns between different subtypes
|
401 |
|
|
;; but cannot reorder insn within the same subtypes. The following
|
402 |
|
|
;; constraint is enough to describe this.
|
403 |
|
|
(final_presence_set "2_um1" "2_um0")
|
404 |
|
|
(final_presence_set "2_um3" "2_um2")
|
405 |
|
|
|
406 |
|
|
;; The insn in the 1st I slot of the two bundle issue group will issue
|
407 |
|
|
;; to I0. The second I slot insn will issue to I1.
|
408 |
|
|
(final_presence_set "2_ui1" "2_ui0")
|
409 |
|
|
|
410 |
|
|
;; For exceptions of I insns:
|
411 |
|
|
(define_cpu_unit "2_only_ui0" "two")
|
412 |
|
|
(final_absence_set "2_only_ui0" "2_ui1")
|
413 |
|
|
|
414 |
|
|
;; Insns
|
415 |
|
|
|
416 |
|
|
(define_reservation "2_M0"
|
417 |
|
|
"(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
|
418 |
|
|
|2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
|
419 |
|
|
|2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
|
420 |
|
|
+(2_um0|2_um1|2_um2|2_um3)")
|
421 |
|
|
|
422 |
|
|
(define_reservation "2_M1"
|
423 |
|
|
"(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
|
424 |
|
|
|2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
|
425 |
|
|
+(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
|
426 |
|
|
+(2_um0|2_um1|2_um2|2_um3)")
|
427 |
|
|
|
428 |
|
|
(define_reservation "2_M" "2_M0|2_M1")
|
429 |
|
|
|
430 |
|
|
(define_reservation "2_M0_only_um0"
|
431 |
|
|
"(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
|
432 |
|
|
|2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
|
433 |
|
|
|2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
|
434 |
|
|
+2_um0")
|
435 |
|
|
|
436 |
|
|
(define_reservation "2_M1_only_um0"
|
437 |
|
|
"(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
|
438 |
|
|
|2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
|
439 |
|
|
+(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
|
440 |
|
|
+2_um0")
|
441 |
|
|
|
442 |
|
|
(define_reservation "2_M_only_um0" "2_M0_only_um0|2_M1_only_um0")
|
443 |
|
|
|
444 |
|
|
(define_reservation "2_M0_only_um2"
|
445 |
|
|
"(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
|
446 |
|
|
|2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
|
447 |
|
|
|2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
|
448 |
|
|
+2_um2")
|
449 |
|
|
|
450 |
|
|
(define_reservation "2_M1_only_um2"
|
451 |
|
|
"(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
|
452 |
|
|
|2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
|
453 |
|
|
+(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
|
454 |
|
|
+2_um2")
|
455 |
|
|
|
456 |
|
|
(define_reservation "2_M_only_um2" "2_M0_only_um2|2_M1_only_um2")
|
457 |
|
|
|
458 |
|
|
(define_reservation "2_M0_only_um23"
|
459 |
|
|
"(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
|
460 |
|
|
|2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
|
461 |
|
|
|2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
|
462 |
|
|
+(2_um2|2_um3)")
|
463 |
|
|
|
464 |
|
|
(define_reservation "2_M1_only_um23"
|
465 |
|
|
"(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
|
466 |
|
|
|2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
|
467 |
|
|
+(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
|
468 |
|
|
+(2_um2|2_um3)")
|
469 |
|
|
|
470 |
|
|
(define_reservation "2_M_only_um23" "2_M0_only_um23|2_M1_only_um23")
|
471 |
|
|
|
472 |
|
|
(define_reservation "2_M0_only_um01"
|
473 |
|
|
"(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
|
474 |
|
|
|2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
|
475 |
|
|
|2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
|
476 |
|
|
+(2_um0|2_um1)")
|
477 |
|
|
|
478 |
|
|
(define_reservation "2_M1_only_um01"
|
479 |
|
|
"(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
|
480 |
|
|
|2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
|
481 |
|
|
+(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
|
482 |
|
|
+(2_um0|2_um1)")
|
483 |
|
|
|
484 |
|
|
(define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01")
|
485 |
|
|
|
486 |
|
|
;; I instruction is dispersed to the lowest numbered I unit
|
487 |
|
|
;; not already in use. Remember about possible splitting.
|
488 |
|
|
(define_reservation "2_I0"
|
489 |
|
|
"2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\
|
490 |
|
|
|2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\
|
491 |
|
|
|(2_1mii.|2_1mmi.|2_1mfi.)+(2_ui0|2_ui1)")
|
492 |
|
|
|
493 |
|
|
(define_reservation "2_I1"
|
494 |
|
|
"2_0m.ii+(2_um0|2_um1|2_um2|2_um3)+2_0mi.i+2_ui0\
|
495 |
|
|
|2_0mm.i+(2_um0|2_um1|2_um2|2_um3)+2_0mmi.+2_ui0\
|
496 |
|
|
|2_0mf.i+2_uf0+2_0mfi.+2_ui0\
|
497 |
|
|
|2_0m.ib+(2_um0|2_um1|2_um2|2_um3)+2_0mi.b+2_ui0\
|
498 |
|
|
|(2_1m.ii+2_1mi.i|2_1m.ib+2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)+(2_ui0|2_ui1)\
|
499 |
|
|
|2_1mm.i+(2_um0|2_um1|2_um2|2_um3)+2_1mmi.+(2_ui0|2_ui1)\
|
500 |
|
|
|2_1mf.i+2_uf1+2_1mfi.+(2_ui0|2_ui1)")
|
501 |
|
|
|
502 |
|
|
(define_reservation "2_I" "2_I0|2_I1")
|
503 |
|
|
|
504 |
|
|
;; "An F slot in the 1st bundle disperses to F0".
|
505 |
|
|
;; "An F slot in the 2st bundle disperses to F1".
|
506 |
|
|
(define_reservation "2_F0"
|
507 |
|
|
"2_0mf.i+2_uf0|2_0mmf.+2_uf0|2_0mf.b+2_uf0\
|
508 |
|
|
|2_1mf.i+2_uf1|2_1mmf.+2_uf1|2_1mf.b+2_uf1")
|
509 |
|
|
|
510 |
|
|
(define_reservation "2_F1"
|
511 |
|
|
"(2_0m.fi+2_0mf.i|2_0mm.f+2_0mmf.|2_0m.fb+2_0mf.b)\
|
512 |
|
|
+(2_um0|2_um1|2_um2|2_um3)+2_uf0\
|
513 |
|
|
|(2_1m.fi+2_1mf.i|2_1mm.f+2_1mmf.|2_1m.fb+2_1mf.b)\
|
514 |
|
|
+(2_um0|2_um1|2_um2|2_um3)+2_uf1")
|
515 |
|
|
|
516 |
|
|
(define_reservation "2_F2"
|
517 |
|
|
"(2_0m.mf+2_0mm.f+2_0mmf.+2_uf0|2_1m.mf+2_1mm.f+2_1mmf.+2_uf1)\
|
518 |
|
|
+(2_um0|2_um1|2_um2|2_um3)+(2_um0|2_um1|2_um2|2_um3)\
|
519 |
|
|
|(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0\
|
520 |
|
|
|2_0mmf.+(2_um0|2_um1|2_um2|2_um3)\
|
521 |
|
|
|2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)\
|
522 |
|
|
+(2_1m.fi+2_1mf.i|2_1m.fb+2_1mf.b)+(2_um0|2_um1|2_um2|2_um3)+2_uf1")
|
523 |
|
|
|
524 |
|
|
(define_reservation "2_F" "2_F0|2_F1|2_F2")
|
525 |
|
|
|
526 |
|
|
;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
|
527 |
|
|
;;; unit. That is, a B slot in 1st position is dispersed to B0. In the
|
528 |
|
|
;;; 2nd position it is dispersed to B2".
|
529 |
|
|
(define_reservation "2_NB"
|
530 |
|
|
"2_0b.bb+2_unb0|2_0bb.b+2_unb1|2_0bbb.+2_unb2\
|
531 |
|
|
|2_0mb.b+2_unb1|2_0mbb.+2_unb2|2_0mib.+2_unb0\
|
532 |
|
|
|2_0mmb.+2_unb0|2_0mfb.+2_unb0\
|
533 |
|
|
|2_1b.bb+2_unb0|2_1bb.b+2_unb1
|
534 |
|
|
|2_1bbb.+2_unb2|2_1mb.b+2_unb1|2_1mbb.+2_unb2\
|
535 |
|
|
|2_1mib.+2_unb0|2_1mmb.+2_unb0|2_1mfb.+2_unb0")
|
536 |
|
|
|
537 |
|
|
(define_reservation "2_B0"
|
538 |
|
|
"2_0b.bb+2_ub0|2_0bb.b+2_ub1|2_0bbb.+2_ub2\
|
539 |
|
|
|2_0mb.b+2_ub1|2_0mbb.+2_ub2|2_0mib.+2_ub2\
|
540 |
|
|
|2_0mfb.+2_ub2|2_1b.bb+2_ub0|2_1bb.b+2_ub1\
|
541 |
|
|
|2_1bbb.+2_ub2|2_1mb.b+2_ub1\
|
542 |
|
|
|2_1mib.+2_ub2|2_1mmb.+2_ub2|2_1mfb.+2_ub2")
|
543 |
|
|
|
544 |
|
|
(define_reservation "2_B1"
|
545 |
|
|
"2_0m.bb+(2_um0|2_um1|2_um2|2_um3)+2_0mb.b+2_ub1\
|
546 |
|
|
|2_0mi.b+2_ui0+2_0mib.+2_ub2\
|
547 |
|
|
|2_0mm.b+(2_um0|2_um1|2_um2|2_um3)+2_0mmb.+2_ub2\
|
548 |
|
|
|2_0mf.b+2_uf0+2_0mfb.+2_ub2\
|
549 |
|
|
|(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0)\
|
550 |
|
|
+2_1b.bb+2_ub0\
|
551 |
|
|
|2_1m.bb+(2_um0|2_um1|2_um2|2_um3)+2_1mb.b+2_ub1\
|
552 |
|
|
|2_1mi.b+(2_ui0|2_ui1)+2_1mib.+2_ub2\
|
553 |
|
|
|2_1mm.b+(2_um0|2_um1|2_um2|2_um3)+2_1mmb.+2_ub2\
|
554 |
|
|
|2_1mf.b+2_uf1+2_1mfb.+2_ub2")
|
555 |
|
|
|
556 |
|
|
(define_reservation "2_B" "2_B0|2_B1")
|
557 |
|
|
|
558 |
|
|
;; MLX bunlde uses ports equivalent to MFI bundles.
|
559 |
|
|
|
560 |
|
|
;; For the MLI template, the I slot insn is always assigned to port I0
|
561 |
|
|
;; if it is in the first bundle or it is assigned to port I1 if it is in
|
562 |
|
|
;; the second bundle.
|
563 |
|
|
(define_reservation "2_L0" "2_0mlx.+2_ui0+2_uf0|2_1mlx.+2_ui1+2_uf1")
|
564 |
|
|
|
565 |
|
|
(define_reservation "2_L1"
|
566 |
|
|
"2_0m.lx+(2_um0|2_um1|2_um2|2_um3)+2_0mlx.+2_ui0+2_uf0\
|
567 |
|
|
|2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1")
|
568 |
|
|
|
569 |
|
|
(define_reservation "2_L2"
|
570 |
|
|
"(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
|
571 |
|
|
|2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)
|
572 |
|
|
+2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1")
|
573 |
|
|
|
574 |
|
|
(define_reservation "2_L" "2_L0|2_L1|2_L2")
|
575 |
|
|
|
576 |
|
|
;; Should we describe that A insn in I slot can be issued into M
|
577 |
|
|
;; ports? I think it is not necessary because of multipass
|
578 |
|
|
;; scheduling. For example, the multipass scheduling could use
|
579 |
|
|
;; MMI-MMI instead of MII-MII where the two last I slots contain A
|
580 |
|
|
;; insns (even if the case is complicated by use-def conflicts).
|
581 |
|
|
;;
|
582 |
|
|
;; In any case we could describe it as
|
583 |
|
|
;; (define_cpu_unit "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" "two")
|
584 |
|
|
;; (final_presence_set "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres"
|
585 |
|
|
;; "2_ui1")
|
586 |
|
|
;; (define_reservation "b_A"
|
587 |
|
|
;; "b_M|b_I\
|
588 |
|
|
;; |(2_1mi.i|2_1mii.|2_1mmi.|2_1mfi.|2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)\
|
589 |
|
|
;; +(2_ui1_0pres|2_ui1_1pres|2_ui1_2pres|2_ui1_3pres)")
|
590 |
|
|
|
591 |
|
|
(define_reservation "2_A" "2_M|2_I")
|
592 |
|
|
|
593 |
|
|
;; We assume that there is no insn issued on the same cycle as the
|
594 |
|
|
;; unknown insn.
|
595 |
|
|
(define_cpu_unit "2_empty" "two")
|
596 |
|
|
(exclusion_set "2_empty"
|
597 |
|
|
"2_0m.ii,2_0m.mi,2_0m.fi,2_0m.mf,2_0b.bb,2_0m.bb,2_0m.ib,2_0m.mb,2_0m.fb,\
|
598 |
|
|
2_0m.lx")
|
599 |
|
|
|
600 |
|
|
(define_cpu_unit
|
601 |
|
|
"2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs"
|
602 |
|
|
"two")
|
603 |
|
|
(define_cpu_unit
|
604 |
|
|
"2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs"
|
605 |
|
|
"two")
|
606 |
|
|
|
607 |
|
|
(define_cpu_unit "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont, 2_mb_cont,\
|
608 |
|
|
2_b_cont, 2_bb_cont" "two")
|
609 |
|
|
|
610 |
|
|
;; For stop in the middle of the bundles.
|
611 |
|
|
(define_cpu_unit "2_m_stop, 2_m0_stop, 2_m1_stop, 2_0mmi_cont" "two")
|
612 |
|
|
(define_cpu_unit "2_mi_stop, 2_mi0_stop, 2_mi1_stop, 2_0mii_cont" "two")
|
613 |
|
|
|
614 |
|
|
(final_presence_set "2_0m_bs"
|
615 |
|
|
"2_0m.ii, 2_0m.mi, 2_0m.mf, 2_0m.fi, 2_0m.bb,\
|
616 |
|
|
2_0m.ib, 2_0m.fb, 2_0m.mb, 2_0m.lx")
|
617 |
|
|
(final_presence_set "2_1m_bs"
|
618 |
|
|
"2_1m.ii, 2_1m.mi, 2_1m.mf, 2_1m.fi, 2_1m.bb,\
|
619 |
|
|
2_1m.ib, 2_1m.fb, 2_1m.mb, 2_1m.lx")
|
620 |
|
|
(final_presence_set "2_0mi_bs" "2_0mi.i, 2_0mi.i")
|
621 |
|
|
(final_presence_set "2_1mi_bs" "2_1mi.i, 2_1mi.i")
|
622 |
|
|
(final_presence_set "2_0mm_bs" "2_0mm.i, 2_0mm.f, 2_0mm.b")
|
623 |
|
|
(final_presence_set "2_1mm_bs" "2_1mm.i, 2_1mm.f, 2_1mm.b")
|
624 |
|
|
(final_presence_set "2_0mf_bs" "2_0mf.i, 2_0mf.b")
|
625 |
|
|
(final_presence_set "2_1mf_bs" "2_1mf.i, 2_1mf.b")
|
626 |
|
|
(final_presence_set "2_0b_bs" "2_0b.bb")
|
627 |
|
|
(final_presence_set "2_1b_bs" "2_1b.bb")
|
628 |
|
|
(final_presence_set "2_0bb_bs" "2_0bb.b")
|
629 |
|
|
(final_presence_set "2_1bb_bs" "2_1bb.b")
|
630 |
|
|
(final_presence_set "2_0mb_bs" "2_0mb.b")
|
631 |
|
|
(final_presence_set "2_1mb_bs" "2_1mb.b")
|
632 |
|
|
|
633 |
|
|
(exclusion_set "2_0m_bs"
|
634 |
|
|
"2_0mi.i, 2_0mm.i, 2_0mm.f, 2_0mf.i, 2_0mb.b,\
|
635 |
|
|
2_0mi.b, 2_0mf.b, 2_0mm.b, 2_0mlx., 2_m0_stop")
|
636 |
|
|
(exclusion_set "2_1m_bs"
|
637 |
|
|
"2_1mi.i, 2_1mm.i, 2_1mm.f, 2_1mf.i, 2_1mb.b,\
|
638 |
|
|
2_1mi.b, 2_1mf.b, 2_1mm.b, 2_1mlx., 2_m1_stop")
|
639 |
|
|
(exclusion_set "2_0mi_bs" "2_0mii., 2_0mib., 2_mi0_stop")
|
640 |
|
|
(exclusion_set "2_1mi_bs" "2_1mii., 2_1mib., 2_mi1_stop")
|
641 |
|
|
(exclusion_set "2_0mm_bs" "2_0mmi., 2_0mmf., 2_0mmb.")
|
642 |
|
|
(exclusion_set "2_1mm_bs" "2_1mmi., 2_1mmf., 2_1mmb.")
|
643 |
|
|
(exclusion_set "2_0mf_bs" "2_0mfi., 2_0mfb.")
|
644 |
|
|
(exclusion_set "2_1mf_bs" "2_1mfi., 2_1mfb.")
|
645 |
|
|
(exclusion_set "2_0b_bs" "2_0bb.b")
|
646 |
|
|
(exclusion_set "2_1b_bs" "2_1bb.b")
|
647 |
|
|
(exclusion_set "2_0bb_bs" "2_0bbb.")
|
648 |
|
|
(exclusion_set "2_1bb_bs" "2_1bbb.")
|
649 |
|
|
(exclusion_set "2_0mb_bs" "2_0mbb.")
|
650 |
|
|
(exclusion_set "2_1mb_bs" "2_1mbb.")
|
651 |
|
|
|
652 |
|
|
(exclusion_set
|
653 |
|
|
"2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs,
|
654 |
|
|
2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs"
|
655 |
|
|
"2_stop")
|
656 |
|
|
|
657 |
|
|
(final_presence_set
|
658 |
|
|
"2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\
|
659 |
|
|
2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx."
|
660 |
|
|
"2_m_cont")
|
661 |
|
|
(final_presence_set "2_0mii., 2_0mib." "2_mi_cont")
|
662 |
|
|
(final_presence_set "2_0mmi., 2_0mmf., 2_0mmb." "2_mm_cont")
|
663 |
|
|
(final_presence_set "2_0mfi., 2_0mfb." "2_mf_cont")
|
664 |
|
|
(final_presence_set "2_0bb.b" "2_b_cont")
|
665 |
|
|
(final_presence_set "2_0bbb." "2_bb_cont")
|
666 |
|
|
(final_presence_set "2_0mbb." "2_mb_cont")
|
667 |
|
|
|
668 |
|
|
(exclusion_set
|
669 |
|
|
"2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
|
670 |
|
|
2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx"
|
671 |
|
|
"2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont,\
|
672 |
|
|
2_mb_cont, 2_b_cont, 2_bb_cont")
|
673 |
|
|
|
674 |
|
|
(exclusion_set "2_empty"
|
675 |
|
|
"2_m_cont,2_mi_cont,2_mm_cont,2_mf_cont,\
|
676 |
|
|
2_mb_cont,2_b_cont,2_bb_cont")
|
677 |
|
|
|
678 |
|
|
;; For m;mi bundle
|
679 |
|
|
(final_presence_set "2_m0_stop" "2_0m.mi")
|
680 |
|
|
(final_presence_set "2_0mm.i" "2_0mmi_cont")
|
681 |
|
|
(exclusion_set "2_0mmi_cont"
|
682 |
|
|
"2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
|
683 |
|
|
2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
|
684 |
|
|
(exclusion_set "2_m0_stop" "2_0mm.i")
|
685 |
|
|
(final_presence_set "2_m1_stop" "2_1m.mi")
|
686 |
|
|
(exclusion_set "2_m1_stop" "2_1mm.i")
|
687 |
|
|
(final_presence_set "2_m_stop" "2_m0_stop, 2_m1_stop")
|
688 |
|
|
|
689 |
|
|
;; For mi;i bundle
|
690 |
|
|
(final_presence_set "2_mi0_stop" "2_0mi.i")
|
691 |
|
|
(final_presence_set "2_0mii." "2_0mii_cont")
|
692 |
|
|
(exclusion_set "2_0mii_cont"
|
693 |
|
|
"2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
|
694 |
|
|
2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
|
695 |
|
|
(exclusion_set "2_mi0_stop" "2_0mii.")
|
696 |
|
|
(final_presence_set "2_mi1_stop" "2_1mi.i")
|
697 |
|
|
(exclusion_set "2_mi1_stop" "2_1mii.")
|
698 |
|
|
(final_presence_set "2_mi_stop" "2_mi0_stop, 2_mi1_stop")
|
699 |
|
|
|
700 |
|
|
(final_absence_set
|
701 |
|
|
"2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\
|
702 |
|
|
2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\
|
703 |
|
|
2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\
|
704 |
|
|
2_0m.lx,2_0mlx., \
|
705 |
|
|
2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\
|
706 |
|
|
2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\
|
707 |
|
|
2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\
|
708 |
|
|
2_1m.lx,2_1mlx."
|
709 |
|
|
"2_m0_stop,2_m1_stop,2_mi0_stop,2_mi1_stop")
|
710 |
|
|
|
711 |
|
|
(define_insn_reservation "2_stop_bit" 0
|
712 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
713 |
|
|
(eq_attr "itanium_class" "stop_bit"))
|
714 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
715 |
|
|
"2_stop|2_m0_stop|2_m1_stop|2_mi0_stop|2_mi1_stop")
|
716 |
|
|
|
717 |
|
|
(define_insn_reservation "2_br" 0
|
718 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
719 |
|
|
(eq_attr "itanium_class" "br"))
|
720 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_B")
|
721 |
|
|
(define_insn_reservation "2_scall" 0
|
722 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
723 |
|
|
(eq_attr "itanium_class" "scall"))
|
724 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_B")
|
725 |
|
|
(define_insn_reservation "2_fcmp" 2
|
726 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
727 |
|
|
(eq_attr "itanium_class" "fcmp"))
|
728 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
|
729 |
|
|
(define_insn_reservation "2_fcvtfx" 4
|
730 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
731 |
|
|
(eq_attr "itanium_class" "fcvtfx"))
|
732 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
|
733 |
|
|
(define_insn_reservation "2_fld" 6
|
734 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
735 |
|
|
(eq_attr "itanium_class" "fld"))
|
736 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_M")
|
737 |
|
|
(define_insn_reservation "2_fldp" 6
|
738 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
739 |
|
|
(eq_attr "itanium_class" "fldp"))
|
740 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
741 |
|
|
"2_M_only_um01")
|
742 |
|
|
(define_insn_reservation "2_fmac" 4
|
743 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
744 |
|
|
(eq_attr "itanium_class" "fmac"))
|
745 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
|
746 |
|
|
(define_insn_reservation "2_fmisc" 4
|
747 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
748 |
|
|
(eq_attr "itanium_class" "fmisc"))
|
749 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
|
750 |
|
|
|
751 |
|
|
;; There is only one insn `mov = ar.bsp' for frar_i:
|
752 |
|
|
;; Latency time ???
|
753 |
|
|
(define_insn_reservation "2_frar_i" 13
|
754 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
755 |
|
|
(eq_attr "itanium_class" "frar_i"))
|
756 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
757 |
|
|
"2_I+2_only_ui0")
|
758 |
|
|
;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m:
|
759 |
|
|
;; Latency time ???
|
760 |
|
|
(define_insn_reservation "2_frar_m" 6
|
761 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
762 |
|
|
(eq_attr "itanium_class" "frar_m"))
|
763 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
764 |
|
|
"2_M_only_um2")
|
765 |
|
|
(define_insn_reservation "2_frbr" 2
|
766 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
767 |
|
|
(eq_attr "itanium_class" "frbr"))
|
768 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
769 |
|
|
"2_I+2_only_ui0")
|
770 |
|
|
(define_insn_reservation "2_frfr" 5
|
771 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
772 |
|
|
(eq_attr "itanium_class" "frfr"))
|
773 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
774 |
|
|
"2_M_only_um2")
|
775 |
|
|
(define_insn_reservation "2_frpr" 2
|
776 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
777 |
|
|
(eq_attr "itanium_class" "frpr"))
|
778 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
779 |
|
|
"2_I+2_only_ui0")
|
780 |
|
|
|
781 |
|
|
(define_insn_reservation "2_ialu" 1
|
782 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
783 |
|
|
(eq_attr "itanium_class" "ialu"))
|
784 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
785 |
|
|
"2_A")
|
786 |
|
|
(define_insn_reservation "2_icmp" 1
|
787 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
788 |
|
|
(eq_attr "itanium_class" "icmp"))
|
789 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
|
790 |
|
|
(define_insn_reservation "2_ilog" 1
|
791 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
792 |
|
|
(eq_attr "itanium_class" "ilog"))
|
793 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
|
794 |
|
|
(define_insn_reservation "2_mmalua" 2
|
795 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
796 |
|
|
(eq_attr "itanium_class" "mmalua"))
|
797 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
|
798 |
|
|
;; Latency time ???
|
799 |
|
|
(define_insn_reservation "2_ishf" 1
|
800 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
801 |
|
|
(eq_attr "itanium_class" "ishf"))
|
802 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
803 |
|
|
"2_I+2_only_ui0")
|
804 |
|
|
(define_insn_reservation "2_ld" 1
|
805 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
806 |
|
|
(eq_attr "itanium_class" "ld"))
|
807 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
808 |
|
|
"2_M_only_um01")
|
809 |
|
|
(define_insn_reservation "2_long_i" 1
|
810 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
811 |
|
|
(eq_attr "itanium_class" "long_i"))
|
812 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_L")
|
813 |
|
|
|
814 |
|
|
(define_insn_reservation "2_mmmul" 2
|
815 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
816 |
|
|
(eq_attr "itanium_class" "mmmul"))
|
817 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
818 |
|
|
"2_I+2_only_ui0")
|
819 |
|
|
;; Latency time ???
|
820 |
|
|
(define_insn_reservation "2_mmshf" 2
|
821 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
822 |
|
|
(eq_attr "itanium_class" "mmshf"))
|
823 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_I")
|
824 |
|
|
;; Latency time ???
|
825 |
|
|
(define_insn_reservation "2_mmshfi" 1
|
826 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
827 |
|
|
(eq_attr "itanium_class" "mmshfi"))
|
828 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_I")
|
829 |
|
|
|
830 |
|
|
;; Now we have only one insn (flushrs) of such class. We assume that flushrs
|
831 |
|
|
;; is the 1st syllable of the bundle after stop bit.
|
832 |
|
|
(define_insn_reservation "2_rse_m" 0
|
833 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
834 |
|
|
(eq_attr "itanium_class" "rse_m"))
|
835 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
836 |
|
|
"(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb\
|
837 |
|
|
|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx)+2_um0")
|
838 |
|
|
(define_insn_reservation "2_sem" 0
|
839 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
840 |
|
|
(eq_attr "itanium_class" "sem"))
|
841 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
842 |
|
|
"2_M_only_um23")
|
843 |
|
|
|
844 |
|
|
(define_insn_reservation "2_stf" 1
|
845 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
846 |
|
|
(eq_attr "itanium_class" "stf"))
|
847 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
848 |
|
|
"2_M_only_um23")
|
849 |
|
|
(define_insn_reservation "2_st" 1
|
850 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
851 |
|
|
(eq_attr "itanium_class" "st"))
|
852 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
853 |
|
|
"2_M_only_um23")
|
854 |
|
|
(define_insn_reservation "2_syst_m0" 0
|
855 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
856 |
|
|
(eq_attr "itanium_class" "syst_m0"))
|
857 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
858 |
|
|
"2_M_only_um2")
|
859 |
|
|
(define_insn_reservation "2_syst_m" 0
|
860 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
861 |
|
|
(eq_attr "itanium_class" "syst_m"))
|
862 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
863 |
|
|
"2_M_only_um0")
|
864 |
|
|
;; Reservation???
|
865 |
|
|
(define_insn_reservation "2_tbit" 1
|
866 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
867 |
|
|
(eq_attr "itanium_class" "tbit"))
|
868 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
869 |
|
|
"2_I+2_only_ui0")
|
870 |
|
|
|
871 |
|
|
;; There is only ony insn `mov ar.pfs =' for toar_i:
|
872 |
|
|
(define_insn_reservation "2_toar_i" 0
|
873 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
874 |
|
|
(eq_attr "itanium_class" "toar_i"))
|
875 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
876 |
|
|
"2_I+2_only_ui0")
|
877 |
|
|
;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m:
|
878 |
|
|
;; Latency time ???
|
879 |
|
|
(define_insn_reservation "2_toar_m" 5
|
880 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
881 |
|
|
(eq_attr "itanium_class" "toar_m"))
|
882 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
883 |
|
|
"2_M_only_um2")
|
884 |
|
|
;; Latency time ???
|
885 |
|
|
(define_insn_reservation "2_tobr" 1
|
886 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
887 |
|
|
(eq_attr "itanium_class" "tobr"))
|
888 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
889 |
|
|
"2_I+2_only_ui0")
|
890 |
|
|
(define_insn_reservation "2_tofr" 5
|
891 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
892 |
|
|
(eq_attr "itanium_class" "tofr"))
|
893 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
894 |
|
|
"2_M_only_um23")
|
895 |
|
|
;; Latency time ???
|
896 |
|
|
(define_insn_reservation "2_topr" 1
|
897 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
898 |
|
|
(eq_attr "itanium_class" "topr"))
|
899 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
900 |
|
|
"2_I+2_only_ui0")
|
901 |
|
|
|
902 |
|
|
(define_insn_reservation "2_xmpy" 4
|
903 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
904 |
|
|
(eq_attr "itanium_class" "xmpy"))
|
905 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
|
906 |
|
|
;; Latency time ???
|
907 |
|
|
(define_insn_reservation "2_xtd" 1
|
908 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
909 |
|
|
(eq_attr "itanium_class" "xtd"))
|
910 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_I")
|
911 |
|
|
|
912 |
|
|
(define_insn_reservation "2_chk_s" 0
|
913 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
914 |
|
|
(eq_attr "itanium_class" "chk_s"))
|
915 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
916 |
|
|
"2_I|2_M_only_um23")
|
917 |
|
|
(define_insn_reservation "2_lfetch" 0
|
918 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
919 |
|
|
(eq_attr "itanium_class" "lfetch"))
|
920 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
921 |
|
|
"2_M_only_um01")
|
922 |
|
|
|
923 |
|
|
(define_insn_reservation "2_nop_m" 0
|
924 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
925 |
|
|
(eq_attr "itanium_class" "nop_m"))
|
926 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_M0")
|
927 |
|
|
(define_insn_reservation "2_nop_b" 0
|
928 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
929 |
|
|
(eq_attr "itanium_class" "nop_b"))
|
930 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_NB")
|
931 |
|
|
(define_insn_reservation "2_nop_i" 0
|
932 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
933 |
|
|
(eq_attr "itanium_class" "nop_i"))
|
934 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_I0")
|
935 |
|
|
(define_insn_reservation "2_nop_f" 0
|
936 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
937 |
|
|
(eq_attr "itanium_class" "nop_f"))
|
938 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_F0")
|
939 |
|
|
(define_insn_reservation "2_nop_x" 0
|
940 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
941 |
|
|
(eq_attr "itanium_class" "nop_x"))
|
942 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_L0")
|
943 |
|
|
|
944 |
|
|
(define_insn_reservation "2_unknown" 1
|
945 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
946 |
|
|
(eq_attr "itanium_class" "unknown"))
|
947 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "2_empty")
|
948 |
|
|
|
949 |
|
|
(define_insn_reservation "2_nop" 0
|
950 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
951 |
|
|
(eq_attr "itanium_class" "nop"))
|
952 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
953 |
|
|
"2_M0|2_NB|2_I0|2_F0")
|
954 |
|
|
|
955 |
|
|
(define_insn_reservation "2_ignore" 0
|
956 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
957 |
|
|
(eq_attr "itanium_class" "ignore"))
|
958 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0))) "nothing")
|
959 |
|
|
|
960 |
|
|
(define_cpu_unit "2_m_cont_only, 2_b_cont_only" "two")
|
961 |
|
|
(define_cpu_unit "2_mi_cont_only, 2_mm_cont_only, 2_mf_cont_only" "two")
|
962 |
|
|
(define_cpu_unit "2_mb_cont_only, 2_bb_cont_only" "two")
|
963 |
|
|
|
964 |
|
|
(final_presence_set "2_m_cont_only" "2_m_cont")
|
965 |
|
|
(exclusion_set "2_m_cont_only"
|
966 |
|
|
"2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\
|
967 |
|
|
2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
|
968 |
|
|
|
969 |
|
|
(final_presence_set "2_b_cont_only" "2_b_cont")
|
970 |
|
|
(exclusion_set "2_b_cont_only" "2_0bb.b")
|
971 |
|
|
|
972 |
|
|
(final_presence_set "2_mi_cont_only" "2_mi_cont")
|
973 |
|
|
(exclusion_set "2_mi_cont_only" "2_0mii., 2_0mib.")
|
974 |
|
|
|
975 |
|
|
(final_presence_set "2_mm_cont_only" "2_mm_cont")
|
976 |
|
|
(exclusion_set "2_mm_cont_only" "2_0mmi., 2_0mmf., 2_0mmb.")
|
977 |
|
|
|
978 |
|
|
(final_presence_set "2_mf_cont_only" "2_mf_cont")
|
979 |
|
|
(exclusion_set "2_mf_cont_only" "2_0mfi., 2_0mfb.")
|
980 |
|
|
|
981 |
|
|
(final_presence_set "2_mb_cont_only" "2_mb_cont")
|
982 |
|
|
(exclusion_set "2_mb_cont_only" "2_0mbb.")
|
983 |
|
|
|
984 |
|
|
(final_presence_set "2_bb_cont_only" "2_bb_cont")
|
985 |
|
|
(exclusion_set "2_bb_cont_only" "2_0bbb.")
|
986 |
|
|
|
987 |
|
|
(define_insn_reservation "2_pre_cycle" 0
|
988 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
989 |
|
|
(eq_attr "itanium_class" "pre_cycle"))
|
990 |
|
|
(eq (symbol_ref "bundling_p") (const_int 0)))
|
991 |
|
|
"nothing")
|
992 |
|
|
|
993 |
|
|
;;(define_insn_reservation "2_pre_cycle" 0
|
994 |
|
|
;; (and (and (eq_attr "cpu" "itanium2")
|
995 |
|
|
;; (eq_attr "itanium_class" "pre_cycle"))
|
996 |
|
|
;; (eq (symbol_ref "bundling_p") (const_int 0)))
|
997 |
|
|
;; "(2_0m_bs, 2_m_cont) \
|
998 |
|
|
;; | (2_0mi_bs, (2_mi_cont|nothing)) \
|
999 |
|
|
;; | (2_0mm_bs, 2_mm_cont) \
|
1000 |
|
|
;; | (2_0mf_bs, (2_mf_cont|nothing)) \
|
1001 |
|
|
;; | (2_0b_bs, (2_b_cont|nothing)) \
|
1002 |
|
|
;; | (2_0bb_bs, (2_bb_cont|nothing)) \
|
1003 |
|
|
;; | (2_0mb_bs, (2_mb_cont|nothing)) \
|
1004 |
|
|
;; | (2_1m_bs, 2_m_cont) \
|
1005 |
|
|
;; | (2_1mi_bs, (2_mi_cont|nothing)) \
|
1006 |
|
|
;; | (2_1mm_bs, 2_mm_cont) \
|
1007 |
|
|
;; | (2_1mf_bs, (2_mf_cont|nothing)) \
|
1008 |
|
|
;; | (2_1b_bs, (2_b_cont|nothing)) \
|
1009 |
|
|
;; | (2_1bb_bs, (2_bb_cont|nothing)) \
|
1010 |
|
|
;; | (2_1mb_bs, (2_mb_cont|nothing)) \
|
1011 |
|
|
;; | (2_m_cont_only, (2_m_cont|nothing)) \
|
1012 |
|
|
;; | (2_b_cont_only, (2_b_cont|nothing)) \
|
1013 |
|
|
;; | (2_mi_cont_only, (2_mi_cont|nothing)) \
|
1014 |
|
|
;; | (2_mm_cont_only, (2_mm_cont|nothing)) \
|
1015 |
|
|
;; | (2_mf_cont_only, (2_mf_cont|nothing)) \
|
1016 |
|
|
;; | (2_mb_cont_only, (2_mb_cont|nothing)) \
|
1017 |
|
|
;; | (2_bb_cont_only, (2_bb_cont|nothing)) \
|
1018 |
|
|
;; | (2_m_stop, (2_0mmi_cont|nothing)) \
|
1019 |
|
|
;; | (2_mi_stop, (2_0mii_cont|nothing))")
|
1020 |
|
|
|
1021 |
|
|
;; Bypasses:
|
1022 |
|
|
|
1023 |
|
|
(define_bypass 1 "2_fcmp" "2_br,2_scall")
|
1024 |
|
|
(define_bypass 0 "2_icmp" "2_br,2_scall")
|
1025 |
|
|
(define_bypass 0 "2_tbit" "2_br,2_scall")
|
1026 |
|
|
(define_bypass 2 "2_ld" "2_ld" "ia64_ld_address_bypass_p")
|
1027 |
|
|
(define_bypass 2 "2_ld" "2_st" "ia64_st_address_bypass_p")
|
1028 |
|
|
(define_bypass 2 "2_ld" "2_mmalua,2_mmmul,2_mmshf")
|
1029 |
|
|
(define_bypass 3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf")
|
1030 |
|
|
(define_bypass 3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf")
|
1031 |
|
|
(define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld")
|
1032 |
|
|
(define_bypass 6 "2_tofr" "2_frfr,2_stf")
|
1033 |
|
|
(define_bypass 7 "2_fmac" "2_frfr,2_stf")
|
1034 |
|
|
|
1035 |
|
|
;; We don't use here fcmp because scall may be predicated.
|
1036 |
|
|
(define_bypass 0 "2_fcvtfx,2_fld,2_fmac,2_fmisc,2_frar_i,2_frar_m,\
|
1037 |
|
|
2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_long_i,\
|
1038 |
|
|
2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,\
|
1039 |
|
|
2_xmpy,2_xtd"
|
1040 |
|
|
"2_scall")
|
1041 |
|
|
|
1042 |
|
|
(define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,\
|
1043 |
|
|
2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\
|
1044 |
|
|
2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_chk_s,2_long_i,\
|
1045 |
|
|
2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\
|
1046 |
|
|
2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\
|
1047 |
|
|
2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\
|
1048 |
|
|
2_topr,2_xmpy,2_xtd,2_lfetch" "2_ignore")
|
1049 |
|
|
|
1050 |
|
|
|
1051 |
|
|
|
1052 |
|
|
;; Bundling
|
1053 |
|
|
|
1054 |
|
|
(define_automaton "twob")
|
1055 |
|
|
|
1056 |
|
|
;; Pseudo units for quicker searching for position in two packet window. */
|
1057 |
|
|
(define_query_cpu_unit "2_1,2_2,2_3,2_4,2_5,2_6" "twob")
|
1058 |
|
|
|
1059 |
|
|
;; All possible combinations of bundles/syllables
|
1060 |
|
|
(define_cpu_unit
|
1061 |
|
|
"2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
|
1062 |
|
|
2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" "twob")
|
1063 |
|
|
(define_cpu_unit
|
1064 |
|
|
"2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\
|
1065 |
|
|
2b_0mi.b, 2b_0mm.b, 2b_0mf.b" "twob")
|
1066 |
|
|
(define_query_cpu_unit
|
1067 |
|
|
"2b_0mii., 2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\
|
1068 |
|
|
2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx." "twob")
|
1069 |
|
|
|
1070 |
|
|
(define_cpu_unit
|
1071 |
|
|
"2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\
|
1072 |
|
|
2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" "twob")
|
1073 |
|
|
(define_cpu_unit
|
1074 |
|
|
"2b_1mi.i, 2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\
|
1075 |
|
|
2b_1mi.b, 2b_1mm.b, 2b_1mf.b" "twob")
|
1076 |
|
|
(define_query_cpu_unit
|
1077 |
|
|
"2b_1mii., 2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\
|
1078 |
|
|
2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx." "twob")
|
1079 |
|
|
|
1080 |
|
|
;; Slot 1
|
1081 |
|
|
(exclusion_set "2b_0m.ii"
|
1082 |
|
|
"2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
|
1083 |
|
|
2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
|
1084 |
|
|
(exclusion_set "2b_0m.mi"
|
1085 |
|
|
"2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib,\
|
1086 |
|
|
2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
|
1087 |
|
|
(exclusion_set "2b_0m.fi"
|
1088 |
|
|
"2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
|
1089 |
|
|
(exclusion_set "2b_0m.mf"
|
1090 |
|
|
"2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
|
1091 |
|
|
(exclusion_set "2b_0b.bb" "2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
|
1092 |
|
|
(exclusion_set "2b_0m.bb" "2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
|
1093 |
|
|
(exclusion_set "2b_0m.ib" "2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
|
1094 |
|
|
(exclusion_set "2b_0m.mb" "2b_0m.fb, 2b_0m.lx")
|
1095 |
|
|
(exclusion_set "2b_0m.fb" "2b_0m.lx")
|
1096 |
|
|
|
1097 |
|
|
;; Slot 2
|
1098 |
|
|
(exclusion_set "2b_0mi.i"
|
1099 |
|
|
"2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\
|
1100 |
|
|
2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
|
1101 |
|
|
(exclusion_set "2b_0mm.i"
|
1102 |
|
|
"2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\
|
1103 |
|
|
2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
|
1104 |
|
|
(exclusion_set "2b_0mf.i"
|
1105 |
|
|
"2b_0mm.f, 2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
|
1106 |
|
|
(exclusion_set "2b_0mm.f"
|
1107 |
|
|
"2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
|
1108 |
|
|
(exclusion_set "2b_0bb.b" "2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
|
1109 |
|
|
(exclusion_set "2b_0mb.b" "2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
|
1110 |
|
|
(exclusion_set "2b_0mi.b" "2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
|
1111 |
|
|
(exclusion_set "2b_0mm.b" "2b_0mf.b, 2b_0mlx.")
|
1112 |
|
|
(exclusion_set "2b_0mf.b" "2b_0mlx.")
|
1113 |
|
|
|
1114 |
|
|
;; Slot 3
|
1115 |
|
|
(exclusion_set "2b_0mii."
|
1116 |
|
|
"2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\
|
1117 |
|
|
2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
|
1118 |
|
|
(exclusion_set "2b_0mmi."
|
1119 |
|
|
"2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\
|
1120 |
|
|
2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
|
1121 |
|
|
(exclusion_set "2b_0mfi."
|
1122 |
|
|
"2b_0mmf., 2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
|
1123 |
|
|
(exclusion_set "2b_0mmf."
|
1124 |
|
|
"2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
|
1125 |
|
|
(exclusion_set "2b_0bbb." "2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
|
1126 |
|
|
(exclusion_set "2b_0mbb." "2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
|
1127 |
|
|
(exclusion_set "2b_0mib." "2b_0mmb., 2b_0mfb., 2b_0mlx.")
|
1128 |
|
|
(exclusion_set "2b_0mmb." "2b_0mfb., 2b_0mlx.")
|
1129 |
|
|
(exclusion_set "2b_0mfb." "2b_0mlx.")
|
1130 |
|
|
|
1131 |
|
|
;; Slot 4
|
1132 |
|
|
(exclusion_set "2b_1m.ii"
|
1133 |
|
|
"2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\
|
1134 |
|
|
2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
|
1135 |
|
|
(exclusion_set "2b_1m.mi"
|
1136 |
|
|
"2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib,\
|
1137 |
|
|
2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
|
1138 |
|
|
(exclusion_set "2b_1m.fi"
|
1139 |
|
|
"2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
|
1140 |
|
|
(exclusion_set "2b_1m.mf"
|
1141 |
|
|
"2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
|
1142 |
|
|
(exclusion_set "2b_1b.bb" "2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
|
1143 |
|
|
(exclusion_set "2b_1m.bb" "2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
|
1144 |
|
|
(exclusion_set "2b_1m.ib" "2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
|
1145 |
|
|
(exclusion_set "2b_1m.mb" "2b_1m.fb, 2b_1m.lx")
|
1146 |
|
|
(exclusion_set "2b_1m.fb" "2b_1m.lx")
|
1147 |
|
|
|
1148 |
|
|
;; Slot 5
|
1149 |
|
|
(exclusion_set "2b_1mi.i"
|
1150 |
|
|
"2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\
|
1151 |
|
|
2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
|
1152 |
|
|
(exclusion_set "2b_1mm.i"
|
1153 |
|
|
"2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\
|
1154 |
|
|
2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
|
1155 |
|
|
(exclusion_set "2b_1mf.i"
|
1156 |
|
|
"2b_1mm.f, 2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
|
1157 |
|
|
(exclusion_set "2b_1mm.f"
|
1158 |
|
|
"2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
|
1159 |
|
|
(exclusion_set "2b_1bb.b" "2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
|
1160 |
|
|
(exclusion_set "2b_1mb.b" "2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
|
1161 |
|
|
(exclusion_set "2b_1mi.b" "2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
|
1162 |
|
|
(exclusion_set "2b_1mm.b" "2b_1mf.b, 2b_1mlx.")
|
1163 |
|
|
(exclusion_set "2b_1mf.b" "2b_1mlx.")
|
1164 |
|
|
|
1165 |
|
|
;; Slot 6
|
1166 |
|
|
(exclusion_set "2b_1mii."
|
1167 |
|
|
"2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\
|
1168 |
|
|
2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
|
1169 |
|
|
(exclusion_set "2b_1mmi."
|
1170 |
|
|
"2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\
|
1171 |
|
|
2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
|
1172 |
|
|
(exclusion_set "2b_1mfi."
|
1173 |
|
|
"2b_1mmf., 2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
|
1174 |
|
|
(exclusion_set "2b_1mmf."
|
1175 |
|
|
"2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
|
1176 |
|
|
(exclusion_set "2b_1bbb." "2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
|
1177 |
|
|
(exclusion_set "2b_1mbb." "2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
|
1178 |
|
|
(exclusion_set "2b_1mib." "2b_1mmb., 2b_1mfb., 2b_1mlx.")
|
1179 |
|
|
(exclusion_set "2b_1mmb." "2b_1mfb., 2b_1mlx.")
|
1180 |
|
|
(exclusion_set "2b_1mfb." "2b_1mlx.")
|
1181 |
|
|
|
1182 |
|
|
(final_presence_set "2b_0mi.i" "2b_0m.ii")
|
1183 |
|
|
(final_presence_set "2b_0mii." "2b_0mi.i")
|
1184 |
|
|
(final_presence_set "2b_1mi.i" "2b_1m.ii")
|
1185 |
|
|
(final_presence_set "2b_1mii." "2b_1mi.i")
|
1186 |
|
|
|
1187 |
|
|
(final_presence_set "2b_0mm.i" "2b_0m.mi")
|
1188 |
|
|
(final_presence_set "2b_0mmi." "2b_0mm.i")
|
1189 |
|
|
(final_presence_set "2b_1mm.i" "2b_1m.mi")
|
1190 |
|
|
(final_presence_set "2b_1mmi." "2b_1mm.i")
|
1191 |
|
|
|
1192 |
|
|
(final_presence_set "2b_0mf.i" "2b_0m.fi")
|
1193 |
|
|
(final_presence_set "2b_0mfi." "2b_0mf.i")
|
1194 |
|
|
(final_presence_set "2b_1mf.i" "2b_1m.fi")
|
1195 |
|
|
(final_presence_set "2b_1mfi." "2b_1mf.i")
|
1196 |
|
|
|
1197 |
|
|
(final_presence_set "2b_0mm.f" "2b_0m.mf")
|
1198 |
|
|
(final_presence_set "2b_0mmf." "2b_0mm.f")
|
1199 |
|
|
(final_presence_set "2b_1mm.f" "2b_1m.mf")
|
1200 |
|
|
(final_presence_set "2b_1mmf." "2b_1mm.f")
|
1201 |
|
|
|
1202 |
|
|
(final_presence_set "2b_0bb.b" "2b_0b.bb")
|
1203 |
|
|
(final_presence_set "2b_0bbb." "2b_0bb.b")
|
1204 |
|
|
(final_presence_set "2b_1bb.b" "2b_1b.bb")
|
1205 |
|
|
(final_presence_set "2b_1bbb." "2b_1bb.b")
|
1206 |
|
|
|
1207 |
|
|
(final_presence_set "2b_0mb.b" "2b_0m.bb")
|
1208 |
|
|
(final_presence_set "2b_0mbb." "2b_0mb.b")
|
1209 |
|
|
(final_presence_set "2b_1mb.b" "2b_1m.bb")
|
1210 |
|
|
(final_presence_set "2b_1mbb." "2b_1mb.b")
|
1211 |
|
|
|
1212 |
|
|
(final_presence_set "2b_0mi.b" "2b_0m.ib")
|
1213 |
|
|
(final_presence_set "2b_0mib." "2b_0mi.b")
|
1214 |
|
|
(final_presence_set "2b_1mi.b" "2b_1m.ib")
|
1215 |
|
|
(final_presence_set "2b_1mib." "2b_1mi.b")
|
1216 |
|
|
|
1217 |
|
|
(final_presence_set "2b_0mm.b" "2b_0m.mb")
|
1218 |
|
|
(final_presence_set "2b_0mmb." "2b_0mm.b")
|
1219 |
|
|
(final_presence_set "2b_1mm.b" "2b_1m.mb")
|
1220 |
|
|
(final_presence_set "2b_1mmb." "2b_1mm.b")
|
1221 |
|
|
|
1222 |
|
|
(final_presence_set "2b_0mf.b" "2b_0m.fb")
|
1223 |
|
|
(final_presence_set "2b_0mfb." "2b_0mf.b")
|
1224 |
|
|
(final_presence_set "2b_1mf.b" "2b_1m.fb")
|
1225 |
|
|
(final_presence_set "2b_1mfb." "2b_1mf.b")
|
1226 |
|
|
|
1227 |
|
|
(final_presence_set "2b_0mlx." "2b_0m.lx")
|
1228 |
|
|
(final_presence_set "2b_1mlx." "2b_1m.lx")
|
1229 |
|
|
|
1230 |
|
|
;; See the corresponding comment in non-bundling section above.
|
1231 |
|
|
(final_presence_set
|
1232 |
|
|
"2b_1m.lx"
|
1233 |
|
|
"2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.")
|
1234 |
|
|
(final_presence_set "2b_1b.bb" "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mlx.")
|
1235 |
|
|
(final_presence_set
|
1236 |
|
|
"2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1m.bb,2b_1m.ib,2b_1m.mb,2b_1m.fb"
|
1237 |
|
|
"2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.")
|
1238 |
|
|
|
1239 |
|
|
;; Ports/units (nb means nop.b insn issued into given port):
|
1240 |
|
|
(define_cpu_unit
|
1241 |
|
|
"2b_um0, 2b_um1, 2b_um2, 2b_um3, 2b_ui0, 2b_ui1, 2b_uf0, 2b_uf1,\
|
1242 |
|
|
2b_ub0, 2b_ub1, 2b_ub2, 2b_unb0, 2b_unb1, 2b_unb2" "twob")
|
1243 |
|
|
|
1244 |
|
|
(exclusion_set "2b_ub0" "2b_unb0")
|
1245 |
|
|
(exclusion_set "2b_ub1" "2b_unb1")
|
1246 |
|
|
(exclusion_set "2b_ub2" "2b_unb2")
|
1247 |
|
|
|
1248 |
|
|
;; The following rules are used to decrease number of alternatives.
|
1249 |
|
|
;; They are consequences of Itanium2 microarchitecture. They also
|
1250 |
|
|
;; describe the following rules mentioned in Itanium2
|
1251 |
|
|
;; microarchitecture: rules mentioned in Itanium2 microarchitecture:
|
1252 |
|
|
;; o "BBB/MBB: Always splits issue after either of these bundles".
|
1253 |
|
|
;; o "MIB BBB: Split issue after the first bundle in this pair".
|
1254 |
|
|
(exclusion_set
|
1255 |
|
|
"2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb."
|
1256 |
|
|
"2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1b.bb,2b_1m.bb,\
|
1257 |
|
|
2b_1m.ib,2b_1m.mb,2b_1m.fb,2b_1m.lx")
|
1258 |
|
|
(exclusion_set "2b_0m.ib,2b_0mi.b,2b_0mib." "2b_1b.bb")
|
1259 |
|
|
|
1260 |
|
|
;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
|
1261 |
|
|
;;; B-slot contains a nop.b or a brp instruction".
|
1262 |
|
|
;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
|
1263 |
|
|
;;; nop.b, otherwise it disperses to B2".
|
1264 |
|
|
(final_absence_set
|
1265 |
|
|
"2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\
|
1266 |
|
|
2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx"
|
1267 |
|
|
"2b_0mib. 2b_ub2, 2b_0mfb. 2b_ub2, 2b_0mmb. 2b_ub2")
|
1268 |
|
|
|
1269 |
|
|
;; This is necessary to start new processor cycle when we meet stop bit.
|
1270 |
|
|
(define_cpu_unit "2b_stop" "twob")
|
1271 |
|
|
(final_absence_set
|
1272 |
|
|
"2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\
|
1273 |
|
|
2b_0m.fi,2b_0mf.i,2b_0mfi.,\
|
1274 |
|
|
2b_0m.mf,2b_0mm.f,2b_0mmf.,2b_0b.bb,2b_0bb.b,2b_0bbb.,\
|
1275 |
|
|
2b_0m.bb,2b_0mb.b,2b_0mbb.,\
|
1276 |
|
|
2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\
|
1277 |
|
|
2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \
|
1278 |
|
|
2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\
|
1279 |
|
|
2b_1m.fi,2b_1mf.i,2b_1mfi.,\
|
1280 |
|
|
2b_1m.mf,2b_1mm.f,2b_1mmf.,2b_1b.bb,2b_1bb.b,2b_1bbb.,\
|
1281 |
|
|
2b_1m.bb,2b_1mb.b,2b_1mbb.,\
|
1282 |
|
|
2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\
|
1283 |
|
|
2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx."
|
1284 |
|
|
"2b_stop")
|
1285 |
|
|
|
1286 |
|
|
;; The issue logic can reorder M slot insns between different subtypes
|
1287 |
|
|
;; but cannot reorder insn within the same subtypes. The following
|
1288 |
|
|
;; constraint is enough to describe this.
|
1289 |
|
|
(final_presence_set "2b_um1" "2b_um0")
|
1290 |
|
|
(final_presence_set "2b_um3" "2b_um2")
|
1291 |
|
|
|
1292 |
|
|
;; The insn in the 1st I slot of the two bundle issue group will issue
|
1293 |
|
|
;; to I0. The second I slot insn will issue to I1.
|
1294 |
|
|
(final_presence_set "2b_ui1" "2b_ui0")
|
1295 |
|
|
|
1296 |
|
|
;; For exceptions of I insns:
|
1297 |
|
|
(define_cpu_unit "2b_only_ui0" "twob")
|
1298 |
|
|
(final_absence_set "2b_only_ui0" "2b_ui1")
|
1299 |
|
|
|
1300 |
|
|
;; Insns
|
1301 |
|
|
|
1302 |
|
|
(define_reservation "2b_M"
|
1303 |
|
|
"((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
|
1304 |
|
|
|2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
|
1305 |
|
|
|(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
|
1306 |
|
|
|2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
|
1307 |
|
|
|(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
|
1308 |
|
|
|(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
|
1309 |
|
|
+(2b_um0|2b_um1|2b_um2|2b_um3)")
|
1310 |
|
|
|
1311 |
|
|
(define_reservation "2b_M_only_um0"
|
1312 |
|
|
"((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
|
1313 |
|
|
|2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
|
1314 |
|
|
|(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
|
1315 |
|
|
|2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
|
1316 |
|
|
|(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
|
1317 |
|
|
|(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
|
1318 |
|
|
+2b_um0")
|
1319 |
|
|
|
1320 |
|
|
(define_reservation "2b_M_only_um2"
|
1321 |
|
|
"((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
|
1322 |
|
|
|2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
|
1323 |
|
|
|(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
|
1324 |
|
|
|2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
|
1325 |
|
|
|(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
|
1326 |
|
|
|(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
|
1327 |
|
|
+2b_um2")
|
1328 |
|
|
|
1329 |
|
|
(define_reservation "2b_M_only_um01"
|
1330 |
|
|
"((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
|
1331 |
|
|
|2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
|
1332 |
|
|
|(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
|
1333 |
|
|
|2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
|
1334 |
|
|
|(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
|
1335 |
|
|
|(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
|
1336 |
|
|
+(2b_um0|2b_um1)")
|
1337 |
|
|
|
1338 |
|
|
(define_reservation "2b_M_only_um23"
|
1339 |
|
|
"((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
|
1340 |
|
|
|2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
|
1341 |
|
|
|(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
|
1342 |
|
|
|2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
|
1343 |
|
|
|(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
|
1344 |
|
|
|(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
|
1345 |
|
|
+(2b_um2|2b_um3)")
|
1346 |
|
|
|
1347 |
|
|
;; I instruction is dispersed to the lowest numbered I unit
|
1348 |
|
|
;; not already in use. Remember about possible splitting.
|
1349 |
|
|
(define_reservation "2b_I"
|
1350 |
|
|
"2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\
|
1351 |
|
|
|2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\
|
1352 |
|
|
|(2b_1mi.i+2_5|2b_1mi.b+2_5)+(2b_ui0|2b_ui1)\
|
1353 |
|
|
|(2b_1mii.|2b_1mmi.|2b_1mfi.)+2_6+(2b_ui0|2b_ui1)")
|
1354 |
|
|
|
1355 |
|
|
;; "An F slot in the 1st bundle disperses to F0".
|
1356 |
|
|
;; "An F slot in the 2st bundle disperses to F1".
|
1357 |
|
|
(define_reservation "2b_F"
|
1358 |
|
|
"2b_0mf.i+2_2+2b_uf0|2b_0mmf.+2_3+2b_uf0|2b_0mf.b+2_2+2b_uf0\
|
1359 |
|
|
|2b_1mf.i+2_5+2b_uf1|2b_1mmf.+2_6+2b_uf1|2b_1mf.b+2_5+2b_uf1")
|
1360 |
|
|
|
1361 |
|
|
;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
|
1362 |
|
|
;;; unit. That is, a B slot in 1st position is dispersed to B0. In the
|
1363 |
|
|
;;; 2nd position it is dispersed to B2".
|
1364 |
|
|
(define_reservation "2b_NB"
|
1365 |
|
|
"2b_0b.bb+2_1+2b_unb0|2b_0bb.b+2_2+2b_unb1|2b_0bbb.+2_3+2b_unb2\
|
1366 |
|
|
|2b_0mb.b+2_2+2b_unb1|2b_0mbb.+2_3+2b_unb2\
|
1367 |
|
|
|2b_0mib.+2_3+2b_unb0|2b_0mmb.+2_3+2b_unb0|2b_0mfb.+2_3+2b_unb0\
|
1368 |
|
|
|2b_1b.bb+2_4+2b_unb0|2b_1bb.b+2_5+2b_unb1\
|
1369 |
|
|
|2b_1bbb.+2_6+2b_unb2|2b_1mb.b+2_5+2b_unb1|2b_1mbb.+2_6+2b_unb2\
|
1370 |
|
|
|2b_1mib.+2_6+2b_unb0|2b_1mmb.+2_6+2b_unb0|2b_1mfb.+2_6+2b_unb0")
|
1371 |
|
|
|
1372 |
|
|
(define_reservation "2b_B"
|
1373 |
|
|
"2b_0b.bb+2_1+2b_ub0|2b_0bb.b+2_2+2b_ub1|2b_0bbb.+2_3+2b_ub2\
|
1374 |
|
|
|2b_0mb.b+2_2+2b_ub1|2b_0mbb.+2_3+2b_ub2|2b_0mib.+2_3+2b_ub2\
|
1375 |
|
|
|2b_0mfb.+2_3+2b_ub2|2b_1b.bb+2_4+2b_ub0|2b_1bb.b+2_5+2b_ub1\
|
1376 |
|
|
|2b_1bbb.+2_6+2b_ub2|2b_1mb.b+2_5+2b_ub1\
|
1377 |
|
|
|2b_1mib.+2_6+2b_ub2|2b_1mmb.+2_6+2b_ub2|2b_1mfb.+2_6+2b_ub2")
|
1378 |
|
|
|
1379 |
|
|
;; For the MLI template, the I slot insn is always assigned to port I0
|
1380 |
|
|
;; if it is in the first bundle or it is assigned to port I1 if it is in
|
1381 |
|
|
;; the second bundle.
|
1382 |
|
|
(define_reservation "2b_L"
|
1383 |
|
|
"2b_0mlx.+2_3+2b_ui0+2b_uf0|2b_1mlx.+2_6+2b_ui1+2b_uf1")
|
1384 |
|
|
|
1385 |
|
|
;; Should we describe that A insn in I slot can be issued into M
|
1386 |
|
|
;; ports? I think it is not necessary because of multipass
|
1387 |
|
|
;; scheduling. For example, the multipass scheduling could use
|
1388 |
|
|
;; MMI-MMI instead of MII-MII where the two last I slots contain A
|
1389 |
|
|
;; insns (even if the case is complicated by use-def conflicts).
|
1390 |
|
|
;;
|
1391 |
|
|
;; In any case we could describe it as
|
1392 |
|
|
;; (define_cpu_unit "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres"
|
1393 |
|
|
;; "twob")
|
1394 |
|
|
;; (final_presence_set "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres"
|
1395 |
|
|
;; "2b_ui1")
|
1396 |
|
|
;; (define_reservation "b_A"
|
1397 |
|
|
;; "b_M|b_I\
|
1398 |
|
|
;; |(2b_1mi.i+2_5|2b_1mii.+2_6|2b_1mmi.+2_6|2b_1mfi.+2_6|2b_1mi.b+2_5)\
|
1399 |
|
|
;; +(2b_um0|2b_um1|2b_um2|2b_um3)\
|
1400 |
|
|
;; +(2b_ui1_0pres|2b_ui1_1pres|2b_ui1_2pres|2b_ui1_3pres)")
|
1401 |
|
|
|
1402 |
|
|
(define_reservation "2b_A" "2b_M|2b_I")
|
1403 |
|
|
|
1404 |
|
|
;; We assume that there is no insn issued on the same cycle as the
|
1405 |
|
|
;; unknown insn.
|
1406 |
|
|
(define_cpu_unit "2b_empty" "twob")
|
1407 |
|
|
(exclusion_set "2b_empty"
|
1408 |
|
|
"2b_0m.ii,2b_0m.mi,2b_0m.fi,2b_0m.mf,2b_0b.bb,2b_0m.bb,\
|
1409 |
|
|
2b_0m.ib,2b_0m.mb,2b_0m.fb,2b_0m.lx,2b_0mm.i")
|
1410 |
|
|
|
1411 |
|
|
(define_cpu_unit
|
1412 |
|
|
"2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs"
|
1413 |
|
|
"twob")
|
1414 |
|
|
(define_cpu_unit
|
1415 |
|
|
"2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs"
|
1416 |
|
|
"twob")
|
1417 |
|
|
|
1418 |
|
|
(define_cpu_unit "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont, 2b_mb_cont,\
|
1419 |
|
|
2b_b_cont, 2b_bb_cont" "twob")
|
1420 |
|
|
|
1421 |
|
|
;; For stop in the middle of the bundles.
|
1422 |
|
|
(define_cpu_unit "2b_m_stop, 2b_m0_stop, 2b_m1_stop, 2b_0mmi_cont" "twob")
|
1423 |
|
|
(define_cpu_unit "2b_mi_stop, 2b_mi0_stop, 2b_mi1_stop, 2b_0mii_cont" "twob")
|
1424 |
|
|
|
1425 |
|
|
(final_presence_set "2b_0m_bs"
|
1426 |
|
|
"2b_0m.ii, 2b_0m.mi, 2b_0m.mf, 2b_0m.fi, 2b_0m.bb,\
|
1427 |
|
|
2b_0m.ib, 2b_0m.fb, 2b_0m.mb, 2b_0m.lx")
|
1428 |
|
|
(final_presence_set "2b_1m_bs"
|
1429 |
|
|
"2b_1m.ii, 2b_1m.mi, 2b_1m.mf, 2b_1m.fi, 2b_1m.bb,\
|
1430 |
|
|
2b_1m.ib, 2b_1m.fb, 2b_1m.mb, 2b_1m.lx")
|
1431 |
|
|
(final_presence_set "2b_0mi_bs" "2b_0mi.i, 2b_0mi.i")
|
1432 |
|
|
(final_presence_set "2b_1mi_bs" "2b_1mi.i, 2b_1mi.i")
|
1433 |
|
|
(final_presence_set "2b_0mm_bs" "2b_0mm.i, 2b_0mm.f, 2b_0mm.b")
|
1434 |
|
|
(final_presence_set "2b_1mm_bs" "2b_1mm.i, 2b_1mm.f, 2b_1mm.b")
|
1435 |
|
|
(final_presence_set "2b_0mf_bs" "2b_0mf.i, 2b_0mf.b")
|
1436 |
|
|
(final_presence_set "2b_1mf_bs" "2b_1mf.i, 2b_1mf.b")
|
1437 |
|
|
(final_presence_set "2b_0b_bs" "2b_0b.bb")
|
1438 |
|
|
(final_presence_set "2b_1b_bs" "2b_1b.bb")
|
1439 |
|
|
(final_presence_set "2b_0bb_bs" "2b_0bb.b")
|
1440 |
|
|
(final_presence_set "2b_1bb_bs" "2b_1bb.b")
|
1441 |
|
|
(final_presence_set "2b_0mb_bs" "2b_0mb.b")
|
1442 |
|
|
(final_presence_set "2b_1mb_bs" "2b_1mb.b")
|
1443 |
|
|
|
1444 |
|
|
(exclusion_set "2b_0m_bs"
|
1445 |
|
|
"2b_0mi.i, 2b_0mm.i, 2b_0mm.f, 2b_0mf.i, 2b_0mb.b,\
|
1446 |
|
|
2b_0mi.b, 2b_0mf.b, 2b_0mm.b, 2b_0mlx., 2b_m0_stop")
|
1447 |
|
|
(exclusion_set "2b_1m_bs"
|
1448 |
|
|
"2b_1mi.i, 2b_1mm.i, 2b_1mm.f, 2b_1mf.i, 2b_1mb.b,\
|
1449 |
|
|
2b_1mi.b, 2b_1mf.b, 2b_1mm.b, 2b_1mlx., 2b_m1_stop")
|
1450 |
|
|
(exclusion_set "2b_0mi_bs" "2b_0mii., 2b_0mib., 2b_mi0_stop")
|
1451 |
|
|
(exclusion_set "2b_1mi_bs" "2b_1mii., 2b_1mib., 2b_mi1_stop")
|
1452 |
|
|
(exclusion_set "2b_0mm_bs" "2b_0mmi., 2b_0mmf., 2b_0mmb.")
|
1453 |
|
|
(exclusion_set "2b_1mm_bs" "2b_1mmi., 2b_1mmf., 2b_1mmb.")
|
1454 |
|
|
(exclusion_set "2b_0mf_bs" "2b_0mfi., 2b_0mfb.")
|
1455 |
|
|
(exclusion_set "2b_1mf_bs" "2b_1mfi., 2b_1mfb.")
|
1456 |
|
|
(exclusion_set "2b_0b_bs" "2b_0bb.b")
|
1457 |
|
|
(exclusion_set "2b_1b_bs" "2b_1bb.b")
|
1458 |
|
|
(exclusion_set "2b_0bb_bs" "2b_0bbb.")
|
1459 |
|
|
(exclusion_set "2b_1bb_bs" "2b_1bbb.")
|
1460 |
|
|
(exclusion_set "2b_0mb_bs" "2b_0mbb.")
|
1461 |
|
|
(exclusion_set "2b_1mb_bs" "2b_1mbb.")
|
1462 |
|
|
|
1463 |
|
|
(exclusion_set
|
1464 |
|
|
"2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs,
|
1465 |
|
|
2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs"
|
1466 |
|
|
"2b_stop")
|
1467 |
|
|
|
1468 |
|
|
(final_presence_set
|
1469 |
|
|
"2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0mb.b,\
|
1470 |
|
|
2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx."
|
1471 |
|
|
"2b_m_cont")
|
1472 |
|
|
(final_presence_set "2b_0mii., 2b_0mib." "2b_mi_cont")
|
1473 |
|
|
(final_presence_set "2b_0mmi., 2b_0mmf., 2b_0mmb." "2b_mm_cont")
|
1474 |
|
|
(final_presence_set "2b_0mfi., 2b_0mfb." "2b_mf_cont")
|
1475 |
|
|
(final_presence_set "2b_0bb.b" "2b_b_cont")
|
1476 |
|
|
(final_presence_set "2b_0bbb." "2b_bb_cont")
|
1477 |
|
|
(final_presence_set "2b_0mbb." "2b_mb_cont")
|
1478 |
|
|
|
1479 |
|
|
(exclusion_set
|
1480 |
|
|
"2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
|
1481 |
|
|
2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx"
|
1482 |
|
|
"2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont,\
|
1483 |
|
|
2b_mb_cont, 2b_b_cont, 2b_bb_cont")
|
1484 |
|
|
|
1485 |
|
|
(exclusion_set "2b_empty"
|
1486 |
|
|
"2b_m_cont,2b_mi_cont,2b_mm_cont,2b_mf_cont,\
|
1487 |
|
|
2b_mb_cont,2b_b_cont,2b_bb_cont")
|
1488 |
|
|
|
1489 |
|
|
;; For m;mi bundle
|
1490 |
|
|
(final_presence_set "2b_m0_stop" "2b_0m.mi")
|
1491 |
|
|
(final_presence_set "2b_0mm.i" "2b_0mmi_cont")
|
1492 |
|
|
(exclusion_set "2b_0mmi_cont"
|
1493 |
|
|
"2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
|
1494 |
|
|
2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
|
1495 |
|
|
(exclusion_set "2b_m0_stop" "2b_0mm.i")
|
1496 |
|
|
(final_presence_set "2b_m1_stop" "2b_1m.mi")
|
1497 |
|
|
(exclusion_set "2b_m1_stop" "2b_1mm.i")
|
1498 |
|
|
(final_presence_set "2b_m_stop" "2b_m0_stop, 2b_m1_stop")
|
1499 |
|
|
|
1500 |
|
|
;; For mi;i bundle
|
1501 |
|
|
(final_presence_set "2b_mi0_stop" "2b_0mi.i")
|
1502 |
|
|
(final_presence_set "2b_0mii." "2b_0mii_cont")
|
1503 |
|
|
(exclusion_set "2b_0mii_cont"
|
1504 |
|
|
"2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
|
1505 |
|
|
2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
|
1506 |
|
|
(exclusion_set "2b_mi0_stop" "2b_0mii.")
|
1507 |
|
|
(final_presence_set "2b_mi1_stop" "2b_1mi.i")
|
1508 |
|
|
(exclusion_set "2b_mi1_stop" "2b_1mii.")
|
1509 |
|
|
(final_presence_set "2b_mi_stop" "2b_mi0_stop, 2b_mi1_stop")
|
1510 |
|
|
|
1511 |
|
|
(final_absence_set
|
1512 |
|
|
"2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\
|
1513 |
|
|
2b_0m.fi,2b_0mf.i,2b_0mfi.,2b_0m.mf,2b_0mm.f,2b_0mmf.,\
|
1514 |
|
|
2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb.,\
|
1515 |
|
|
2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\
|
1516 |
|
|
2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \
|
1517 |
|
|
2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\
|
1518 |
|
|
2b_1m.fi,2b_1mf.i,2b_1mfi.,2b_1m.mf,2b_1mm.f,2b_1mmf.,\
|
1519 |
|
|
2b_1b.bb,2b_1bb.b,2b_1bbb.,2b_1m.bb,2b_1mb.b,2b_1mbb.,\
|
1520 |
|
|
2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\
|
1521 |
|
|
2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx."
|
1522 |
|
|
"2b_m0_stop,2b_m1_stop,2b_mi0_stop,2b_mi1_stop")
|
1523 |
|
|
|
1524 |
|
|
(define_insn_reservation "2b_stop_bit" 0
|
1525 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1526 |
|
|
(eq_attr "itanium_class" "stop_bit"))
|
1527 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1528 |
|
|
"2b_stop|2b_m0_stop|2b_m1_stop|2b_mi0_stop|2b_mi1_stop")
|
1529 |
|
|
(define_insn_reservation "2b_br" 0
|
1530 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1531 |
|
|
(eq_attr "itanium_class" "br"))
|
1532 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_B")
|
1533 |
|
|
(define_insn_reservation "2b_scall" 0
|
1534 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1535 |
|
|
(eq_attr "itanium_class" "scall"))
|
1536 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_B")
|
1537 |
|
|
(define_insn_reservation "2b_fcmp" 2
|
1538 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1539 |
|
|
(eq_attr "itanium_class" "fcmp"))
|
1540 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
|
1541 |
|
|
(define_insn_reservation "2b_fcvtfx" 4
|
1542 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1543 |
|
|
(eq_attr "itanium_class" "fcvtfx"))
|
1544 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
|
1545 |
|
|
(define_insn_reservation "2b_fld" 6
|
1546 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1547 |
|
|
(eq_attr "itanium_class" "fld"))
|
1548 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_M")
|
1549 |
|
|
(define_insn_reservation "2b_fldp" 6
|
1550 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1551 |
|
|
(eq_attr "itanium_class" "fldp"))
|
1552 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1553 |
|
|
"2b_M_only_um01")
|
1554 |
|
|
(define_insn_reservation "2b_fmac" 4
|
1555 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1556 |
|
|
(eq_attr "itanium_class" "fmac"))
|
1557 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
|
1558 |
|
|
(define_insn_reservation "2b_fmisc" 4
|
1559 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1560 |
|
|
(eq_attr "itanium_class" "fmisc"))
|
1561 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
|
1562 |
|
|
|
1563 |
|
|
;; Latency time ???
|
1564 |
|
|
(define_insn_reservation "2b_frar_i" 13
|
1565 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1566 |
|
|
(eq_attr "itanium_class" "frar_i"))
|
1567 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1568 |
|
|
"2b_I+2b_only_ui0")
|
1569 |
|
|
;; Latency time ???
|
1570 |
|
|
(define_insn_reservation "2b_frar_m" 6
|
1571 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1572 |
|
|
(eq_attr "itanium_class" "frar_m"))
|
1573 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1574 |
|
|
"2b_M_only_um2")
|
1575 |
|
|
(define_insn_reservation "2b_frbr" 2
|
1576 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1577 |
|
|
(eq_attr "itanium_class" "frbr"))
|
1578 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1579 |
|
|
"2b_I+2b_only_ui0")
|
1580 |
|
|
(define_insn_reservation "2b_frfr" 5
|
1581 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1582 |
|
|
(eq_attr "itanium_class" "frfr"))
|
1583 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1584 |
|
|
"2b_M_only_um2")
|
1585 |
|
|
(define_insn_reservation "2b_frpr" 2
|
1586 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1587 |
|
|
(eq_attr "itanium_class" "frpr"))
|
1588 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1589 |
|
|
"2b_I+2b_only_ui0")
|
1590 |
|
|
|
1591 |
|
|
(define_insn_reservation "2b_ialu" 1
|
1592 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1593 |
|
|
(eq_attr "itanium_class" "ialu"))
|
1594 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1595 |
|
|
"2b_A")
|
1596 |
|
|
(define_insn_reservation "2b_icmp" 1
|
1597 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1598 |
|
|
(eq_attr "itanium_class" "icmp"))
|
1599 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
|
1600 |
|
|
(define_insn_reservation "2b_ilog" 1
|
1601 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1602 |
|
|
(eq_attr "itanium_class" "ilog"))
|
1603 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
|
1604 |
|
|
(define_insn_reservation "2b_mmalua" 2
|
1605 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1606 |
|
|
(eq_attr "itanium_class" "mmalua"))
|
1607 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
|
1608 |
|
|
;; Latency time ???
|
1609 |
|
|
(define_insn_reservation "2b_ishf" 1
|
1610 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1611 |
|
|
(eq_attr "itanium_class" "ishf"))
|
1612 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1613 |
|
|
"2b_I+2b_only_ui0")
|
1614 |
|
|
(define_insn_reservation "2b_ld" 1
|
1615 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1616 |
|
|
(eq_attr "itanium_class" "ld"))
|
1617 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1618 |
|
|
"2b_M_only_um01")
|
1619 |
|
|
(define_insn_reservation "2b_long_i" 1
|
1620 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1621 |
|
|
(eq_attr "itanium_class" "long_i"))
|
1622 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_L")
|
1623 |
|
|
|
1624 |
|
|
;; Latency time ???
|
1625 |
|
|
(define_insn_reservation "2b_mmmul" 2
|
1626 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1627 |
|
|
(eq_attr "itanium_class" "mmmul"))
|
1628 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1629 |
|
|
"2b_I+2b_only_ui0")
|
1630 |
|
|
;; Latency time ???
|
1631 |
|
|
(define_insn_reservation "2b_mmshf" 2
|
1632 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1633 |
|
|
(eq_attr "itanium_class" "mmshf"))
|
1634 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_I")
|
1635 |
|
|
;; Latency time ???
|
1636 |
|
|
(define_insn_reservation "2b_mmshfi" 1
|
1637 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1638 |
|
|
(eq_attr "itanium_class" "mmshfi"))
|
1639 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_I")
|
1640 |
|
|
|
1641 |
|
|
(define_insn_reservation "2b_rse_m" 0
|
1642 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1643 |
|
|
(eq_attr "itanium_class" "rse_m"))
|
1644 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1645 |
|
|
"(2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
|
1646 |
|
|
|2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1+2b_um0")
|
1647 |
|
|
(define_insn_reservation "2b_sem" 0
|
1648 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1649 |
|
|
(eq_attr "itanium_class" "sem"))
|
1650 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1651 |
|
|
"2b_M_only_um23")
|
1652 |
|
|
|
1653 |
|
|
(define_insn_reservation "2b_stf" 1
|
1654 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1655 |
|
|
(eq_attr "itanium_class" "stf"))
|
1656 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1657 |
|
|
"2b_M_only_um23")
|
1658 |
|
|
(define_insn_reservation "2b_st" 1
|
1659 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1660 |
|
|
(eq_attr "itanium_class" "st"))
|
1661 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1662 |
|
|
"2b_M_only_um23")
|
1663 |
|
|
(define_insn_reservation "2b_syst_m0" 0
|
1664 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1665 |
|
|
(eq_attr "itanium_class" "syst_m0"))
|
1666 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1667 |
|
|
"2b_M_only_um2")
|
1668 |
|
|
(define_insn_reservation "2b_syst_m" 0
|
1669 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1670 |
|
|
(eq_attr "itanium_class" "syst_m"))
|
1671 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1672 |
|
|
"2b_M_only_um0")
|
1673 |
|
|
;; Reservation???
|
1674 |
|
|
(define_insn_reservation "2b_tbit" 1
|
1675 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1676 |
|
|
(eq_attr "itanium_class" "tbit"))
|
1677 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1678 |
|
|
"2b_I+2b_only_ui0")
|
1679 |
|
|
(define_insn_reservation "2b_toar_i" 0
|
1680 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1681 |
|
|
(eq_attr "itanium_class" "toar_i"))
|
1682 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1683 |
|
|
"2b_I+2b_only_ui0")
|
1684 |
|
|
;; Latency time ???
|
1685 |
|
|
(define_insn_reservation "2b_toar_m" 5
|
1686 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1687 |
|
|
(eq_attr "itanium_class" "toar_m"))
|
1688 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1689 |
|
|
"2b_M_only_um2")
|
1690 |
|
|
;; Latency time ???
|
1691 |
|
|
(define_insn_reservation "2b_tobr" 1
|
1692 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1693 |
|
|
(eq_attr "itanium_class" "tobr"))
|
1694 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1695 |
|
|
"2b_I+2b_only_ui0")
|
1696 |
|
|
(define_insn_reservation "2b_tofr" 5
|
1697 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1698 |
|
|
(eq_attr "itanium_class" "tofr"))
|
1699 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1700 |
|
|
"2b_M_only_um23")
|
1701 |
|
|
;; Latency time ???
|
1702 |
|
|
(define_insn_reservation "2b_topr" 1
|
1703 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1704 |
|
|
(eq_attr "itanium_class" "topr"))
|
1705 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1706 |
|
|
"2b_I+2b_only_ui0")
|
1707 |
|
|
|
1708 |
|
|
(define_insn_reservation "2b_xmpy" 4
|
1709 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1710 |
|
|
(eq_attr "itanium_class" "xmpy"))
|
1711 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
|
1712 |
|
|
;; Latency time ???
|
1713 |
|
|
(define_insn_reservation "2b_xtd" 1
|
1714 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1715 |
|
|
(eq_attr "itanium_class" "xtd"))
|
1716 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_I")
|
1717 |
|
|
(define_insn_reservation "2b_chk_s" 0
|
1718 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1719 |
|
|
(eq_attr "itanium_class" "chk_s"))
|
1720 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1721 |
|
|
"2b_I|2b_M_only_um23")
|
1722 |
|
|
(define_insn_reservation "2b_lfetch" 0
|
1723 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1724 |
|
|
(eq_attr "itanium_class" "lfetch"))
|
1725 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1726 |
|
|
"2b_M_only_um01")
|
1727 |
|
|
(define_insn_reservation "2b_nop_m" 0
|
1728 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1729 |
|
|
(eq_attr "itanium_class" "nop_m"))
|
1730 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_M")
|
1731 |
|
|
(define_insn_reservation "2b_nop_b" 0
|
1732 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1733 |
|
|
(eq_attr "itanium_class" "nop_b"))
|
1734 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_NB")
|
1735 |
|
|
(define_insn_reservation "2b_nop_i" 0
|
1736 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1737 |
|
|
(eq_attr "itanium_class" "nop_i"))
|
1738 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_I")
|
1739 |
|
|
(define_insn_reservation "2b_nop_f" 0
|
1740 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1741 |
|
|
(eq_attr "itanium_class" "nop_f"))
|
1742 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
|
1743 |
|
|
(define_insn_reservation "2b_nop_x" 0
|
1744 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1745 |
|
|
(eq_attr "itanium_class" "nop_x"))
|
1746 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_L")
|
1747 |
|
|
(define_insn_reservation "2b_unknown" 1
|
1748 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1749 |
|
|
(eq_attr "itanium_class" "unknown"))
|
1750 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_empty")
|
1751 |
|
|
(define_insn_reservation "2b_nop" 0
|
1752 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1753 |
|
|
(eq_attr "itanium_class" "nop"))
|
1754 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1755 |
|
|
"2b_M|2b_NB|2b_I|2b_F")
|
1756 |
|
|
(define_insn_reservation "2b_ignore" 0
|
1757 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1758 |
|
|
(eq_attr "itanium_class" "ignore"))
|
1759 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0))) "nothing")
|
1760 |
|
|
|
1761 |
|
|
(define_insn_reservation "2b_pre_cycle" 0
|
1762 |
|
|
(and (and (eq_attr "cpu" "itanium2")
|
1763 |
|
|
(eq_attr "itanium_class" "pre_cycle"))
|
1764 |
|
|
(ne (symbol_ref "bundling_p") (const_int 0)))
|
1765 |
|
|
"(2b_0m_bs, 2b_m_cont) \
|
1766 |
|
|
| (2b_0mi_bs, 2b_mi_cont) \
|
1767 |
|
|
| (2b_0mm_bs, 2b_mm_cont) \
|
1768 |
|
|
| (2b_0mf_bs, 2b_mf_cont) \
|
1769 |
|
|
| (2b_0b_bs, 2b_b_cont) \
|
1770 |
|
|
| (2b_0bb_bs, 2b_bb_cont) \
|
1771 |
|
|
| (2b_0mb_bs, 2b_mb_cont) \
|
1772 |
|
|
| (2b_1m_bs, 2b_m_cont) \
|
1773 |
|
|
| (2b_1mi_bs, 2b_mi_cont) \
|
1774 |
|
|
| (2b_1mm_bs, 2b_mm_cont) \
|
1775 |
|
|
| (2b_1mf_bs, 2b_mf_cont) \
|
1776 |
|
|
| (2b_1b_bs, 2b_b_cont) \
|
1777 |
|
|
| (2b_1bb_bs, 2b_bb_cont) \
|
1778 |
|
|
| (2b_1mb_bs, 2b_mb_cont) \
|
1779 |
|
|
| (2b_m_stop, 2b_0mmi_cont) \
|
1780 |
|
|
| (2b_mi_stop, 2b_0mii_cont)")
|
1781 |
|
|
|