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[/] [scarts/] [trunk/] [toolchain/] [scarts-gcc/] [gcc-4.1.1/] [gcc/] [config/] [iq2000/] [iq2000.h] - Blame information for rev 12

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1 12 jlechner
/* Definitions of target machine for GNU compiler.
2
   Vitesse IQ2000 processors
3
   Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
4
 
5
   This file is part of GCC.
6
 
7
   GCC is free software; you can redistribute it and/or modify it
8
   under the terms of the GNU General Public License as published
9
   by the Free Software Foundation; either version 2, or (at your
10
   option) any later version.
11
 
12
   GCC is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GCC; see the file COPYING.  If not, write to the Free
19
   Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
20
   02110-1301, USA.  */
21
 
22
/* Driver configuration.  */
23
 
24
#undef  SWITCH_TAKES_ARG
25
#define SWITCH_TAKES_ARG(CHAR)                                          \
26
  (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
27
 
28
/* The svr4.h LIB_SPEC with -leval and --*group tacked on */
29
#undef  LIB_SPEC
30
#define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
31
 
32
#undef STARTFILE_SPEC
33
#undef ENDFILE_SPEC
34
 
35
 
36
/* Run-time target specifications.  */
37
 
38
#define TARGET_CPU_CPP_BUILTINS()               \
39
  do                                            \
40
    {                                           \
41
      builtin_define ("__iq2000__");            \
42
      builtin_assert ("cpu=iq2000");            \
43
      builtin_assert ("machine=iq2000");        \
44
    }                                           \
45
  while (0)
46
 
47
/* Macros used in the machine description to test the flags.  */
48
 
49
#define TARGET_STATS            0
50
 
51
#define TARGET_DEBUG_MODE       0
52
#define TARGET_DEBUG_A_MODE     0
53
#define TARGET_DEBUG_B_MODE     0
54
#define TARGET_DEBUG_C_MODE     0
55
#define TARGET_DEBUG_D_MODE     0
56
 
57
#ifndef IQ2000_ISA_DEFAULT
58
#define IQ2000_ISA_DEFAULT 1
59
#endif
60
 
61
#define IQ2000_VERSION "[1.0]"
62
 
63
#ifndef MACHINE_TYPE
64
#define MACHINE_TYPE "IQ2000"
65
#endif
66
 
67
#ifndef TARGET_VERSION_INTERNAL
68
#define TARGET_VERSION_INTERNAL(STREAM)                                 \
69
  fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
70
#endif
71
 
72
#ifndef TARGET_VERSION
73
#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
74
#endif
75
 
76
#define OVERRIDE_OPTIONS override_options ()
77
 
78
#define CAN_DEBUG_WITHOUT_FP
79
 
80
/* Storage Layout.  */
81
 
82
#define BITS_BIG_ENDIAN                 0
83
#define BYTES_BIG_ENDIAN                1 
84
#define WORDS_BIG_ENDIAN                1
85
#define LIBGCC2_WORDS_BIG_ENDIAN        1
86
#define BITS_PER_WORD                   32
87
#define MAX_BITS_PER_WORD               64
88
#define UNITS_PER_WORD                  4
89
#define MIN_UNITS_PER_WORD              4
90
#define POINTER_SIZE                    32
91
 
92
/* Define this macro if it is advisable to hold scalars in registers
93
   in a wider mode than that declared by the program.  In such cases,
94
   the value is constrained to be within the bounds of the declared
95
   type, but kept valid in the wider mode.  The signedness of the
96
   extension may differ from that of the type.
97
 
98
   We promote any value smaller than SImode up to SImode.  */
99
 
100
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
101
  if (GET_MODE_CLASS (MODE) == MODE_INT         \
102
      && GET_MODE_SIZE (MODE) < 4)              \
103
    (MODE) = SImode;
104
 
105
#define PARM_BOUNDARY 32
106
 
107
#define STACK_BOUNDARY 64
108
 
109
#define FUNCTION_BOUNDARY 32
110
 
111
#define BIGGEST_ALIGNMENT 64
112
 
113
#undef  DATA_ALIGNMENT
114
#define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
115
  ((((ALIGN) < BITS_PER_WORD)                                           \
116
    && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
117
        || TREE_CODE (TYPE) == UNION_TYPE                               \
118
        || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
119
 
120
#define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
121
  ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
122
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
123
 
124
#define EMPTY_FIELD_BOUNDARY 32
125
 
126
#define STRUCTURE_SIZE_BOUNDARY 8
127
 
128
#define STRICT_ALIGNMENT 1
129
 
130
#define PCC_BITFIELD_TYPE_MATTERS 1
131
 
132
#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
133
 
134
 
135
/* Layout of Source Language Data Types.  */
136
 
137
#define INT_TYPE_SIZE           32
138
#define SHORT_TYPE_SIZE         16
139
#define LONG_TYPE_SIZE          32
140
#define LONG_LONG_TYPE_SIZE     64
141
#define CHAR_TYPE_SIZE          BITS_PER_UNIT
142
#define FLOAT_TYPE_SIZE         32
143
#define DOUBLE_TYPE_SIZE        64
144
#define LONG_DOUBLE_TYPE_SIZE   64
145
#define DEFAULT_SIGNED_CHAR     1
146
 
147
 
148
/* Register Basics.  */
149
 
150
/* On the IQ2000, we have 32 integer registers.  */
151
#define FIRST_PSEUDO_REGISTER 33
152
 
153
#define FIXED_REGISTERS                                                 \
154
{                                                                       \
155
  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                     \
156
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                        \
157
}
158
 
159
#define CALL_USED_REGISTERS                                             \
160
{                                                                       \
161
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
162
  0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                      \
163
}
164
 
165
 
166
/* Order of allocation of registers.  */
167
 
168
#define REG_ALLOC_ORDER                                                 \
169
{  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,        \
170
  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
171
}
172
 
173
 
174
/* How Values Fit in Registers.  */
175
 
176
#define HARD_REGNO_NREGS(REGNO, MODE)   \
177
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
178
 
179
#define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
180
 ((REGNO_REG_CLASS (REGNO) == GR_REGS)                          \
181
  ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4      \
182
  : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
183
 
184
#define MODES_TIEABLE_P(MODE1, MODE2)                           \
185
  ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
186
    GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
187
   == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
188
       GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
189
 
190
#define AVOID_CCMODE_COPIES
191
 
192
 
193
/* Register Classes.  */
194
 
195
enum reg_class
196
{
197
  NO_REGS,                      /* No registers in set.  */
198
  GR_REGS,                      /* Integer registers.  */
199
  ALL_REGS,                     /* All registers.  */
200
  LIM_REG_CLASSES               /* Max value + 1.  */
201
};
202
 
203
#define GENERAL_REGS GR_REGS
204
 
205
#define N_REG_CLASSES (int) LIM_REG_CLASSES
206
 
207
#define REG_CLASS_NAMES                                         \
208
{                                                               \
209
  "NO_REGS",                                                    \
210
  "GR_REGS",                                                    \
211
  "ALL_REGS"                                                    \
212
}
213
 
214
#define REG_CLASS_CONTENTS                                      \
215
{                                                               \
216
  { 0x00000000, 0x00000000 },   /* No registers,  */            \
217
  { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
218
  { 0xffffffff, 0x00000001 }    /* All registers.  */           \
219
}
220
 
221
#define REGNO_REG_CLASS(REGNO) \
222
((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
223
 
224
#define BASE_REG_CLASS  (GR_REGS)
225
 
226
#define INDEX_REG_CLASS NO_REGS
227
 
228
#define REG_CLASS_FROM_LETTER(C) \
229
  ((C) == 'd' ? GR_REGS :        \
230
   (C) == 'b' ? ALL_REGS :       \
231
   (C) == 'y' ? GR_REGS :        \
232
   NO_REGS)
233
 
234
#define REGNO_OK_FOR_INDEX_P(regno)     0
235
 
236
#define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
237
  ((CLASS) != ALL_REGS                                          \
238
   ? (CLASS)                                                    \
239
   : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
240
       || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
241
      ? (GR_REGS)                                               \
242
      : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
243
          || GET_MODE (X) == VOIDmode)                          \
244
         ? (GR_REGS)                                            \
245
         : (CLASS))))
246
 
247
#define SMALL_REGISTER_CLASSES 0
248
 
249
#define CLASS_MAX_NREGS(CLASS, MODE)    \
250
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
251
 
252
/* For IQ2000:
253
 
254
   `I'  is used for the range of constants an arithmetic insn can
255
        actually contain (16 bits signed integers).
256
 
257
   `J'  is used for the range which is just zero (i.e., $r0).
258
 
259
   `K'  is used for the range of constants a logical insn can actually
260
        contain (16 bit zero-extended integers).
261
 
262
   `L'  is used for the range of constants that be loaded with lui
263
        (i.e., the bottom 16 bits are zero).
264
 
265
   `M'  is used for the range of constants that take two words to load
266
        (i.e., not matched by `I', `K', and `L').
267
 
268
   `N'  is used for constants 0xffffnnnn or 0xnnnnffff
269
 
270
   `O'  is a 5 bit zero-extended integer.  */
271
 
272
#define CONST_OK_FOR_LETTER_P(VALUE, C)                                 \
273
  ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
274
   : (C) == 'J' ? ((VALUE) == 0)                                 \
275
   : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)          \
276
   : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0                           \
277
                   && (((VALUE) & ~2147483647) == 0                      \
278
                       || ((VALUE) & ~2147483647) == ~2147483647))      \
279
   : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)                        \
280
                   && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)          \
281
                   && (((VALUE) & 0x0000ffff) != 0                       \
282
                       || (((VALUE) & ~2147483647) != 0                  \
283
                           && ((VALUE) & ~2147483647) != ~2147483647))) \
284
   : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff)                       \
285
                   || (((VALUE) & 0xffff0000) == 0xffff0000))           \
286
   : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40)    \
287
   : 0)
288
 
289
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)                          \
290
  ((C) == 'G'                                                           \
291
   && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
292
 
293
/* `R' is for memory references which take 1 word for the instruction.  */
294
 
295
#define EXTRA_CONSTRAINT(OP,CODE)                                       \
296
  (((CODE) == 'R')        ? simple_memory_operand (OP, GET_MODE (OP))   \
297
   : FALSE)
298
 
299
 
300
/* Basic Stack Layout.  */
301
 
302
#define STACK_GROWS_DOWNWARD
303
 
304
#define FRAME_GROWS_DOWNWARD 0
305
 
306
#define STARTING_FRAME_OFFSET                                           \
307
  (current_function_outgoing_args_size)
308
 
309
/* Use the default value zero.  */
310
/* #define STACK_POINTER_OFFSET 0 */
311
 
312
#define FIRST_PARM_OFFSET(FNDECL) 0
313
 
314
/* The return address for the current frame is in r31 if this is a leaf
315
   function.  Otherwise, it is on the stack.  It is at a variable offset
316
   from sp/fp/ap, so we define a fake hard register rap which is a
317
   pointer to the return address on the stack.  This always gets eliminated
318
   during reload to be either the frame pointer or the stack pointer plus
319
   an offset.  */
320
 
321
#define RETURN_ADDR_RTX(count, frame)                                   \
322
  (((count) == 0)                                                       \
323
   ? (leaf_function_p ()                                                \
324
      ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
325
      : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
326
                                         RETURN_ADDRESS_POINTER_REGNUM))) \
327
    : (rtx) 0)
328
 
329
/* Before the prologue, RA lives in r31.  */
330
#define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
331
 
332
 
333
/* Register That Address the Stack Frame.  */
334
 
335
#define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
336
#define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
337
#define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
338
#define ARG_POINTER_REGNUM              GP_REG_FIRST
339
#define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
340
#define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
341
 
342
 
343
/* Eliminating the Frame Pointer and the Arg Pointer.  */
344
 
345
#define FRAME_POINTER_REQUIRED 0
346
 
347
#define ELIMINABLE_REGS                                                 \
348
{{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
349
 { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
350
 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
351
 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
352
 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
353
 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
354
 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
355
 
356
 
357
/* We can always eliminate to the frame pointer.  We can eliminate to the
358
   stack pointer unless a frame pointer is needed.  */
359
 
360
#define CAN_ELIMINATE(FROM, TO)                                         \
361
  (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p ()    \
362
   || (TO == GP_REG_FIRST + 31 && leaf_function_p)))                    \
363
  || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM                           \
364
   && ((TO) == HARD_FRAME_POINTER_REGNUM                                \
365
   || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed))))
366
 
367
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
368
        (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
369
 
370
/* Passing Function Arguments on the Stack.  */
371
 
372
/* #define PUSH_ROUNDING(BYTES) 0 */
373
 
374
#define ACCUMULATE_OUTGOING_ARGS 1
375
 
376
#define REG_PARM_STACK_SPACE(FNDECL) 0
377
 
378
#define OUTGOING_REG_PARM_STACK_SPACE
379
 
380
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
381
 
382
 
383
/* Function Arguments in Registers.  */
384
 
385
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
386
  function_arg (& CUM, MODE, TYPE, NAMED)
387
 
388
#define MAX_ARGS_IN_REGISTERS 8
389
 
390
typedef struct iq2000_args
391
{
392
  int gp_reg_found;             /* Whether a gp register was found yet.  */
393
  unsigned int arg_number;      /* Argument number.  */
394
  unsigned int arg_words;       /* # total words the arguments take.  */
395
  unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
396
  int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
397
  int fp_code;                  /* Mode of FP arguments.  */
398
  unsigned int num_adjusts;     /* Number of adjustments made.  */
399
                                /* Adjustments made to args pass in regs.  */
400
  struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2];
401
} CUMULATIVE_ARGS;
402
 
403
/* Initialize a variable CUM of type CUMULATIVE_ARGS
404
   for a call to a function whose data type is FNTYPE.
405
   For a library call, FNTYPE is 0.  */
406
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
407
  init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
408
 
409
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)                    \
410
  function_arg_advance (& CUM, MODE, TYPE, NAMED)
411
 
412
#define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
413
  (! BYTES_BIG_ENDIAN                                                   \
414
   ? upward                                                             \
415
   : (((MODE) == BLKmode                                                \
416
       ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
417
          && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
418
       : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
419
          && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
420
      ? downward : upward))
421
 
422
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)                               \
423
  (((TYPE) != 0)                                                 \
424
        ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY)                          \
425
                ? PARM_BOUNDARY                                         \
426
                : TYPE_ALIGN(TYPE))                                     \
427
        : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)                  \
428
                ? PARM_BOUNDARY                                         \
429
                : GET_MODE_ALIGNMENT(MODE)))
430
 
431
#define FUNCTION_ARG_REGNO_P(N)                                         \
432
  (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
433
 
434
 
435
/* How Scalar Function Values are Returned.  */
436
 
437
#define FUNCTION_VALUE(VALTYPE, FUNC)   iq2000_function_value (VALTYPE, FUNC)
438
 
439
#define LIBCALL_VALUE(MODE)                             \
440
  gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT      \
441
                 || GET_MODE_SIZE (MODE) >= 4)          \
442
                ? (MODE)                                \
443
                : SImode),                              \
444
               GP_RETURN)
445
 
446
/* On the IQ2000, R2 and R3 are the only register thus used.  */
447
 
448
#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
449
 
450
 
451
/* How Large Values are Returned.  */
452
 
453
#define DEFAULT_PCC_STRUCT_RETURN 0
454
 
455
/* Function Entry and Exit.  */
456
 
457
#define EXIT_IGNORE_STACK 1
458
 
459
 
460
/* Generating Code for Profiling.  */
461
 
462
#define FUNCTION_PROFILER(FILE, LABELNO)                                \
463
{                                                                       \
464
  fprintf (FILE, "\t.set\tnoreorder\n");                                \
465
  fprintf (FILE, "\t.set\tnoat\n");                                     \
466
  fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
467
           reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
468
  fprintf (FILE, "\tjal\t_mcount\n");                                   \
469
  fprintf (FILE,                                                        \
470
           "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
471
           "subu",                                                      \
472
           reg_names[STACK_POINTER_REGNUM],                             \
473
           reg_names[STACK_POINTER_REGNUM],                             \
474
           Pmode == DImode ? 16 : 8);                                   \
475
  fprintf (FILE, "\t.set\treorder\n");                                  \
476
  fprintf (FILE, "\t.set\tat\n");                                       \
477
}
478
 
479
 
480
/* Implementing the Varargs Macros.  */
481
 
482
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
483
  iq2000_va_start (valist, nextarg)
484
 
485
 
486
/* Trampolines for Nested Functions.  */
487
 
488
/* A C statement to output, on the stream FILE, assembler code for a
489
   block of data that contains the constant parts of a trampoline.
490
   This code should not include a label--the label is taken care of
491
   automatically.  */
492
 
493
#define TRAMPOLINE_TEMPLATE(STREAM)                                      \
494
{                                                                        \
495
  fprintf (STREAM, "\t.word\t0x03e00821\t\t# move   $1,$31\n");         \
496
  fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");         \
497
  fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n");                   \
498
  if (Pmode == DImode)                                                  \
499
    {                                                                   \
500
      fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld     $3,20($31)\n"); \
501
      fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld     $2,28($31)\n"); \
502
    }                                                                   \
503
  else                                                                  \
504
    {                                                                   \
505
      fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw     $3,20($31)\n"); \
506
      fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw     $2,24($31)\n"); \
507
    }                                                                   \
508
  fprintf (STREAM, "\t.word\t0x0060c821\t\t# move   $25,$3 (abicalls)\n"); \
509
  fprintf (STREAM, "\t.word\t0x00600008\t\t# jr     $3\n");             \
510
  fprintf (STREAM, "\t.word\t0x0020f821\t\t# move   $31,$1\n");         \
511
  fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
512
  fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
513
}
514
 
515
#define TRAMPOLINE_SIZE (40)
516
 
517
#define TRAMPOLINE_ALIGNMENT 32
518
 
519
#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)                            \
520
{                                                                           \
521
  rtx addr = ADDR;                                                          \
522
    emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
523
    emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
524
}
525
 
526
 
527
/* Addressing Modes.  */
528
 
529
#define CONSTANT_ADDRESS_P(X)                                           \
530
  (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
531
    || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
532
    || (GET_CODE (X) == CONST)))
533
 
534
#define MAX_REGS_PER_ADDRESS 1
535
 
536
#ifdef REG_OK_STRICT
537
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)         \
538
  {                                                     \
539
    if (iq2000_legitimate_address_p (MODE, X, 1))       \
540
      goto ADDR;                                        \
541
  }
542
#else
543
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)         \
544
  {                                                     \
545
    if (iq2000_legitimate_address_p (MODE, X, 0))        \
546
      goto ADDR;                                        \
547
  }
548
#endif
549
 
550
#define REG_OK_FOR_INDEX_P(X) 0
551
 
552
 
553
/* For the IQ2000, transform:
554
 
555
        memory(X + <large int>)
556
   into:
557
        Y = <large int> & ~0x7fff;
558
        Z = X + Y
559
        memory (Z + (<large int> & 0x7fff));
560
*/
561
 
562
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)                             \
563
{                                                                       \
564
  rtx xinsn = (X);                                                      \
565
                                                                        \
566
  if (TARGET_DEBUG_B_MODE)                                              \
567
    {                                                                   \
568
      GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n");                  \
569
      GO_DEBUG_RTX (xinsn);                                             \
570
    }                                                                   \
571
                                                                        \
572
  if (iq2000_check_split (X, MODE))             \
573
    {                                                                   \
574
      X = gen_rtx_LO_SUM (Pmode,                                        \
575
                          copy_to_mode_reg (Pmode,                      \
576
                                            gen_rtx_HIGH (Pmode, X)),   \
577
                          X);                                           \
578
      goto WIN;                                                         \
579
    }                                                                   \
580
                                                                        \
581
  if (GET_CODE (xinsn) == PLUS)                                         \
582
    {                                                                   \
583
      rtx xplus0 = XEXP (xinsn, 0);                                      \
584
      rtx xplus1 = XEXP (xinsn, 1);                                     \
585
      enum rtx_code code0 = GET_CODE (xplus0);                          \
586
      enum rtx_code code1 = GET_CODE (xplus1);                          \
587
                                                                        \
588
      if (code0 != REG && code1 == REG)                                 \
589
        {                                                               \
590
          xplus0 = XEXP (xinsn, 1);                                     \
591
          xplus1 = XEXP (xinsn, 0);                                      \
592
          code0 = GET_CODE (xplus0);                                    \
593
          code1 = GET_CODE (xplus1);                                    \
594
        }                                                               \
595
                                                                        \
596
      if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)         \
597
          && code1 == CONST_INT && !SMALL_INT (xplus1))                 \
598
        {                                                               \
599
          rtx int_reg = gen_reg_rtx (Pmode);                            \
600
          rtx ptr_reg = gen_reg_rtx (Pmode);                            \
601
                                                                        \
602
          emit_move_insn (int_reg,                                      \
603
                          GEN_INT (INTVAL (xplus1) & ~ 0x7fff));        \
604
                                                                        \
605
          emit_insn (gen_rtx_SET (VOIDmode,                             \
606
                                  ptr_reg,                              \
607
                                  gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
608
                                                                        \
609
          X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff);        \
610
          goto WIN;                                                     \
611
        }                                                               \
612
    }                                                                   \
613
                                                                        \
614
  if (TARGET_DEBUG_B_MODE)                                              \
615
    GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n");                  \
616
}
617
 
618
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
619
 
620
#define LEGITIMATE_CONSTANT_P(X) (1)
621
 
622
 
623
/* Describing Relative Costs of Operations.  */
624
 
625
#define REGISTER_MOVE_COST(MODE, FROM, TO)      2
626
 
627
#define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
628
  (TO_P ? 2 : 16)
629
 
630
#define BRANCH_COST 2
631
 
632
#define SLOW_BYTE_ACCESS 1
633
 
634
#define NO_FUNCTION_CSE 1
635
 
636
#define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
637
  if (REG_NOTE_KIND (LINK) != 0)                                 \
638
    (COST) = 0; /* Anti or output dependence.  */
639
 
640
 
641
/* Dividing the output into sections.  */
642
 
643
#define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
644
 
645
#define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
646
 
647
 
648
/* The Overall Framework of an Assembler File.  */
649
 
650
#define ASM_COMMENT_START " #"
651
 
652
#define ASM_APP_ON "#APP\n"
653
 
654
#define ASM_APP_OFF "#NO_APP\n"
655
 
656
 
657
/* Output and Generation of Labels.  */
658
 
659
#undef ASM_GENERATE_INTERNAL_LABEL
660
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
661
  sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
662
 
663
#define GLOBAL_ASM_OP "\t.globl\t"
664
 
665
 
666
/* Output of Assembler Instructions.  */
667
 
668
#define REGISTER_NAMES                                                  \
669
{                                                                       \
670
 "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
671
 "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
672
 "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
673
 "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
674
};
675
 
676
#define ADDITIONAL_REGISTER_NAMES                                       \
677
{                                                                       \
678
  { "%0",        0 + GP_REG_FIRST },                                     \
679
  { "%1",        1 + GP_REG_FIRST },                                    \
680
  { "%2",        2 + GP_REG_FIRST },                                    \
681
  { "%3",        3 + GP_REG_FIRST },                                    \
682
  { "%4",        4 + GP_REG_FIRST },                                    \
683
  { "%5",        5 + GP_REG_FIRST },                                    \
684
  { "%6",        6 + GP_REG_FIRST },                                    \
685
  { "%7",        7 + GP_REG_FIRST },                                    \
686
  { "%8",        8 + GP_REG_FIRST },                                    \
687
  { "%9",        9 + GP_REG_FIRST },                                    \
688
  { "%10",      10 + GP_REG_FIRST },                                    \
689
  { "%11",      11 + GP_REG_FIRST },                                    \
690
  { "%12",      12 + GP_REG_FIRST },                                    \
691
  { "%13",      13 + GP_REG_FIRST },                                    \
692
  { "%14",      14 + GP_REG_FIRST },                                    \
693
  { "%15",      15 + GP_REG_FIRST },                                    \
694
  { "%16",      16 + GP_REG_FIRST },                                    \
695
  { "%17",      17 + GP_REG_FIRST },                                    \
696
  { "%18",      18 + GP_REG_FIRST },                                    \
697
  { "%19",      19 + GP_REG_FIRST },                                    \
698
  { "%20",      20 + GP_REG_FIRST },                                    \
699
  { "%21",      21 + GP_REG_FIRST },                                    \
700
  { "%22",      22 + GP_REG_FIRST },                                    \
701
  { "%23",      23 + GP_REG_FIRST },                                    \
702
  { "%24",      24 + GP_REG_FIRST },                                    \
703
  { "%25",      25 + GP_REG_FIRST },                                    \
704
  { "%26",      26 + GP_REG_FIRST },                                    \
705
  { "%27",      27 + GP_REG_FIRST },                                    \
706
  { "%28",      28 + GP_REG_FIRST },                                    \
707
  { "%29",      29 + GP_REG_FIRST },                                    \
708
  { "%30",      27 + GP_REG_FIRST },                                    \
709
  { "%31",      31 + GP_REG_FIRST },                                    \
710
  { "%rap",     32 + GP_REG_FIRST },                                    \
711
}
712
 
713
/* Check if the current insn needs a nop in front of it
714
   because of load delays, and also update the delay slot statistics.  */
715
 
716
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
717
  final_prescan_insn (INSN, OPVEC, NOPERANDS)
718
 
719
/* See iq2000.c for the IQ2000 specific codes.  */
720
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
721
 
722
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) iq2000_print_operand_punct[CODE]
723
 
724
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
725
 
726
#define DBR_OUTPUT_SEQEND(STREAM)                                       \
727
do                                                                      \
728
  {                                                                     \
729
    fputs ("\n", STREAM);                                               \
730
  }                                                                     \
731
while (0)
732
 
733
#define LOCAL_LABEL_PREFIX      "$"
734
 
735
#define USER_LABEL_PREFIX       ""
736
 
737
 
738
/* Output of dispatch tables.  */
739
 
740
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
741
  do                                                                    \
742
    {                                                                   \
743
      fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
744
               Pmode == DImode ? ".dword" : ".word",                    \
745
               LOCAL_LABEL_PREFIX, VALUE);                              \
746
    }                                                                   \
747
  while (0)
748
 
749
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
750
  fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
751
           Pmode == DImode ? ".dword" : ".word",                        \
752
           LOCAL_LABEL_PREFIX,                                          \
753
           VALUE)
754
 
755
 
756
/* Assembler Commands for Alignment.  */
757
 
758
#undef ASM_OUTPUT_SKIP
759
#define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
760
  fprintf (STREAM, "\t.space\t%u\n", (SIZE))
761
 
762
#define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
763
  if ((LOG) != 0)                                                \
764
    fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
765
 
766
 
767
/* Macros Affecting all Debug Formats.  */
768
 
769
#define DEBUGGER_AUTO_OFFSET(X)  \
770
  iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
771
 
772
#define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
773
  iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
774
 
775
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
776
 
777
#define DWARF2_DEBUGGING_INFO 1
778
 
779
 
780
/* Miscellaneous Parameters.  */
781
 
782
#define CASE_VECTOR_MODE SImode
783
 
784
#define WORD_REGISTER_OPERATIONS
785
 
786
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
787
 
788
#define MOVE_MAX 4
789
 
790
#define MAX_MOVE_MAX 8
791
 
792
#define SHIFT_COUNT_TRUNCATED 1
793
 
794
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
795
 
796
#define STORE_FLAG_VALUE 1
797
 
798
#define Pmode SImode
799
 
800
#define FUNCTION_MODE SImode
801
 
802
/* Standard GCC variables that we reference.  */
803
 
804
extern char     call_used_regs[];
805
 
806
/* IQ2000 external variables defined in iq2000.c.  */
807
 
808
/* Comparison type.  */
809
enum cmp_type
810
{
811
  CMP_SI,                               /* Compare four byte integers.  */
812
  CMP_DI,                               /* Compare eight byte integers.  */
813
  CMP_SF,                               /* Compare single precision floats.  */
814
  CMP_DF,                               /* Compare double precision floats.  */
815
  CMP_MAX                               /* Max comparison type.  */
816
};
817
 
818
/* Types of delay slot.  */
819
enum delay_type
820
{
821
  DELAY_NONE,                           /* No delay slot.  */
822
  DELAY_LOAD,                           /* Load from memory delay.  */
823
  DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
824
};
825
 
826
/* Which processor to schedule for.  */
827
 
828
enum processor_type
829
{
830
  PROCESSOR_DEFAULT,
831
  PROCESSOR_IQ2000,
832
  PROCESSOR_IQ10
833
};
834
 
835
/* Recast the cpu class to be the cpu attribute.  */
836
#define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
837
 
838
/* Functions to change what output section we are using.  */
839
extern void             rdata_section (void);
840
extern void             sdata_section (void);
841
extern void             sbss_section  (void);
842
 
843
#define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
844
#define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
845
 
846
 
847
#define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
848
 
849
/* Macros to decide whether certain features are available or not,
850
   depending on the instruction set architecture level.  */
851
 
852
#define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
853
 
854
/* ISA has branch likely instructions.  */
855
#define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
856
 
857
 
858
#undef ASM_SPEC
859
 
860
 
861
/* The mapping from gcc register number to DWARF 2 CFA column number.  */
862
#define DWARF_FRAME_REGNUM(REG)        (REG)
863
 
864
/* The DWARF 2 CFA column which tracks the return address.  */
865
#define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
866
 
867
/* Describe how we implement __builtin_eh_return.  */
868
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
869
 
870
/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
871
   location used to store the amount to adjust the stack.  This is
872
   usually a register that is available from end of the function's body
873
   to the end of the epilogue. Thus, this cannot be a register used as a
874
   temporary by the epilogue.
875
 
876
   This must be an integer register.  */
877
#define EH_RETURN_STACKADJ_REGNO        3
878
#define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
879
 
880
/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
881
   location used to store the address the processor should jump to
882
   catch exception.  This is usually a registers that is available from
883
   end of the function's body to the end of the epilogue. Thus, this
884
   cannot be a register used as a temporary by the epilogue.
885
 
886
   This must be an address register.  */
887
#define EH_RETURN_HANDLER_REGNO         26
888
#define EH_RETURN_HANDLER_RTX           \
889
        gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
890
 
891
/* Offsets recorded in opcodes are a multiple of this alignment factor.  */
892
#define DWARF_CIE_DATA_ALIGNMENT 4
893
 
894
/* For IQ2000, width of a floating point register.  */
895
#define UNITS_PER_FPREG 4
896
 
897
/* Force right-alignment for small varargs in 32 bit little_endian mode */
898
 
899
#define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
900
 
901
/* Internal macros to classify a register number as to whether it's a
902
   general purpose register, a floating point register, a
903
   multiply/divide register, or a status register.  */
904
 
905
#define GP_REG_FIRST 0
906
#define GP_REG_LAST  31
907
#define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
908
 
909
#define RAP_REG_NUM   32
910
#define AT_REGNUM       (GP_REG_FIRST + 1)
911
 
912
#define GP_REG_P(REGNO) \
913
  ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
914
 
915
/* IQ2000 registers used in prologue/epilogue code when the stack frame
916
   is larger than 32K bytes.  These registers must come from the
917
   scratch register set, and not used for passing and returning
918
   arguments and any other information used in the calling sequence.  */
919
 
920
#define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
921
#define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
922
 
923
/* This macro is used later on in the file.  */
924
#define GR_REG_CLASS_P(CLASS)                                           \
925
  ((CLASS) == GR_REGS)
926
 
927
#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
928
#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
929
 
930
/* Certain machines have the property that some registers cannot be
931
   copied to some other registers without using memory.  Define this
932
   macro on those machines to be a C expression that is nonzero if
933
   objects of mode MODE in registers of CLASS1 can only be copied to
934
   registers of class CLASS2 by storing a register of CLASS1 into
935
   memory and loading that memory location into a register of CLASS2.
936
 
937
   Do not define this macro if its value would always be zero.  */
938
 
939
/* Return the maximum number of consecutive registers
940
   needed to represent mode MODE in a register of class CLASS.  */
941
 
942
#define CLASS_UNITS(mode, size)                                         \
943
  ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
944
 
945
/* If defined, gives a class of registers that cannot be used as the
946
   operand of a SUBREG that changes the mode of the object illegally.  */
947
 
948
#define CLASS_CANNOT_CHANGE_MODE 0
949
 
950
/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
951
 
952
#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
953
  (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
954
 
955
/* Make sure 4 words are always allocated on the stack.  */
956
 
957
#ifndef STACK_ARGS_ADJUST
958
#define STACK_ARGS_ADJUST(SIZE)                                         \
959
  {                                                                     \
960
    if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
961
      SIZE.constant = 4 * UNITS_PER_WORD;                               \
962
  }
963
#endif
964
 
965
 
966
/* Symbolic macros for the registers used to return integer and floating
967
   point values.  */
968
 
969
#define GP_RETURN (GP_REG_FIRST + 2)
970
 
971
/* Symbolic macros for the first/last argument registers.  */
972
 
973
#define GP_ARG_FIRST (GP_REG_FIRST + 4)
974
#define GP_ARG_LAST  (GP_REG_FIRST + 11)
975
 
976
#define MAX_ARGS_IN_REGISTERS   8
977
 
978
 
979
/* Tell prologue and epilogue if register REGNO should be saved / restored.  */
980
 
981
#define MUST_SAVE_REGISTER(regno) \
982
 ((regs_ever_live[regno] && !call_used_regs[regno])                     \
983
  || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
984
  || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
985
 
986
/* ALIGN FRAMES on double word boundaries */
987
#ifndef IQ2000_STACK_ALIGN
988
#define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
989
#endif
990
 
991
 
992
/* These assume that REGNO is a hard or pseudo reg number.
993
   They give nonzero only if REGNO is a hard reg of the suitable class
994
   or a pseudo reg currently allocated to a suitable hard reg.
995
   These definitions are NOT overridden anywhere.  */
996
 
997
#define BASE_REG_P(regno, mode)                                 \
998
  (GP_REG_P (regno))
999
 
1000
#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
1001
  BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
1002
             (mode))
1003
 
1004
#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
1005
  (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
1006
 
1007
#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
1008
  GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
1009
 
1010
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1011
   and check its validity for a certain class.
1012
   We have two alternate definitions for each of them.
1013
   The usual definition accepts all pseudo regs; the other rejects them all.
1014
   The symbol REG_OK_STRICT causes the latter definition to be used.
1015
 
1016
   Most source files want to accept pseudo regs in the hope that
1017
   they will get allocated to the class that the insn wants them to be in.
1018
   Some source files that are used after register allocation
1019
   need to be strict.  */
1020
 
1021
#ifndef REG_OK_STRICT
1022
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1023
  iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
1024
#else
1025
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1026
  iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
1027
#endif
1028
 
1029
#if 1
1030
#define GO_PRINTF(x)    fprintf (stderr, (x))
1031
#define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
1032
#define GO_DEBUG_RTX(x) debug_rtx (x)
1033
 
1034
#else
1035
#define GO_PRINTF(x)
1036
#define GO_PRINTF2(x,y)
1037
#define GO_DEBUG_RTX(x)
1038
#endif
1039
 
1040
/* If defined, modifies the length assigned to instruction INSN as a
1041
   function of the context in which it is used.  LENGTH is an lvalue
1042
   that contains the initially computed length of the insn and should
1043
   be updated with the correct length of the insn.  */
1044
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1045
  ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
1046
 
1047
 
1048
 
1049
 
1050
/* How to tell the debugger about changes of source files.  */
1051
 
1052
#ifndef SET_FILE_NUMBER
1053
#define SET_FILE_NUMBER() ++ num_source_filenames
1054
#endif
1055
 
1056
/* This is how to output a note the debugger telling it the line number
1057
   to which the following sequence of instructions corresponds.  */
1058
 
1059
#ifndef LABEL_AFTER_LOC
1060
#define LABEL_AFTER_LOC(STREAM)
1061
#endif
1062
 
1063
 
1064
/* Default to -G 8 */
1065
#ifndef IQ2000_DEFAULT_GVALUE
1066
#define IQ2000_DEFAULT_GVALUE 8
1067
#endif
1068
 
1069
#define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
1070
 
1071
 
1072
/* List of all IQ2000 punctuation characters used by print_operand.  */
1073
extern char iq2000_print_operand_punct[256];
1074
 
1075
/* The target cpu for optimization and scheduling.  */
1076
extern enum processor_type iq2000_tune;
1077
 
1078
/* Which instruction set architecture to use.  */
1079
extern int iq2000_isa;
1080
 
1081
/* Cached operands, and operator to compare for use in set/branch/trap
1082
   on condition codes.  */
1083
extern rtx branch_cmp[2];
1084
 
1085
/* What type of branch to use.  */
1086
extern enum cmp_type branch_type;
1087
 
1088
enum iq2000_builtins
1089
{
1090
  IQ2000_BUILTIN_ADO16,
1091
  IQ2000_BUILTIN_CFC0,
1092
  IQ2000_BUILTIN_CFC1,
1093
  IQ2000_BUILTIN_CFC2,
1094
  IQ2000_BUILTIN_CFC3,
1095
  IQ2000_BUILTIN_CHKHDR,
1096
  IQ2000_BUILTIN_CTC0,
1097
  IQ2000_BUILTIN_CTC1,
1098
  IQ2000_BUILTIN_CTC2,
1099
  IQ2000_BUILTIN_CTC3,
1100
  IQ2000_BUILTIN_LU,
1101
  IQ2000_BUILTIN_LUC32L,
1102
  IQ2000_BUILTIN_LUC64,
1103
  IQ2000_BUILTIN_LUC64L,
1104
  IQ2000_BUILTIN_LUK,
1105
  IQ2000_BUILTIN_LULCK,
1106
  IQ2000_BUILTIN_LUM32,
1107
  IQ2000_BUILTIN_LUM32L,
1108
  IQ2000_BUILTIN_LUM64,
1109
  IQ2000_BUILTIN_LUM64L,
1110
  IQ2000_BUILTIN_LUR,
1111
  IQ2000_BUILTIN_LURL,
1112
  IQ2000_BUILTIN_MFC0,
1113
  IQ2000_BUILTIN_MFC1,
1114
  IQ2000_BUILTIN_MFC2,
1115
  IQ2000_BUILTIN_MFC3,
1116
  IQ2000_BUILTIN_MRGB,
1117
  IQ2000_BUILTIN_MTC0,
1118
  IQ2000_BUILTIN_MTC1,
1119
  IQ2000_BUILTIN_MTC2,
1120
  IQ2000_BUILTIN_MTC3,
1121
  IQ2000_BUILTIN_PKRL,
1122
  IQ2000_BUILTIN_RAM,
1123
  IQ2000_BUILTIN_RB,
1124
  IQ2000_BUILTIN_RX,
1125
  IQ2000_BUILTIN_SRRD,
1126
  IQ2000_BUILTIN_SRRDL,
1127
  IQ2000_BUILTIN_SRULC,
1128
  IQ2000_BUILTIN_SRULCK,
1129
  IQ2000_BUILTIN_SRWR,
1130
  IQ2000_BUILTIN_SRWRU,
1131
  IQ2000_BUILTIN_TRAPQF,
1132
  IQ2000_BUILTIN_TRAPQFL,
1133
  IQ2000_BUILTIN_TRAPQN,
1134
  IQ2000_BUILTIN_TRAPQNE,
1135
  IQ2000_BUILTIN_TRAPRE,
1136
  IQ2000_BUILTIN_TRAPREL,
1137
  IQ2000_BUILTIN_WB,
1138
  IQ2000_BUILTIN_WBR,
1139
  IQ2000_BUILTIN_WBU,
1140
  IQ2000_BUILTIN_WX,
1141
  IQ2000_BUILTIN_SYSCALL
1142
};

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