OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gcc/] [gcc-4.1.1/] [gcc/] [config/] [m32c/] [addsub.md] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 jlechner
;; Machine Descriptions for R8C/M16C/M32C
2
;; Copyright (C) 2005
3
;; Free Software Foundation, Inc.
4
;; Contributed by Red Hat.
5
;;
6
;; This file is part of GCC.
7
;;
8
;; GCC is free software; you can redistribute it and/or modify it
9
;; under the terms of the GNU General Public License as published
10
;; by the Free Software Foundation; either version 2, or (at your
11
;; option) any later version.
12
;;
13
;; GCC is distributed in the hope that it will be useful, but WITHOUT
14
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
;; License for more details.
17
;;
18
;; You should have received a copy of the GNU General Public License
19
;; along with GCC; see the file COPYING.  If not, write to the Free
20
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
21
;; 02110-1301, USA.
22
 
23
;; add, sub
24
 
25
(define_insn "addqi3"
26
  [(set (match_operand:QI 0 "mra_or_sp_operand"
27
                  "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm")
28
        (plus:QI (match_operand:QI 1 "mra_operand"
29
                  "%0,0,0,0, 0,0,0,0")
30
                 (match_operand:QI 2 "mrai_operand"
31
                  "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa")))]
32
  ""
33
  "add.b\t%2,%0"
34
  [(set_attr "flags" "oszc")]
35
  )
36
 
37
(define_insn "addhi3"
38
  [(set (match_operand:HI 0 "nonimmediate_operand"
39
                  "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, !Rsp")
40
        (plus:HI (match_operand:HI 1 "general_operand"
41
                  "%0,0,0,0, 0,0, Raw, 0")
42
                 (match_operand:HI 2 "general_operand"
43
                  "IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, i")))]
44
  ""
45
  "@
46
   add.w\t%2,%0
47
   add.w\t%2,%0
48
   add.w\t%2,%0
49
   add.w\t%2,%0
50
   sub.w\t%m2,%0
51
   sub.w\t%m2,%0
52
   mova\t%d2[%1],%0
53
   add.w\t%2,%0"
54
  [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,oszc,oszc")]
55
  )
56
 
57
(define_insn "addpsi3"
58
  [(set (match_operand:PSI 0 "nonimmediate_operand" "=SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi,Rhi,&Rhi")
59
        (plus:PSI (match_operand:PSI 1 "nonimmediate_operand" "0,0,0, Raa,Rad,!Rcl,Rhi")
60
                  (match_operand:PSI 2 "general_operand" "iSdRpi,?Rmm,i, i,IS2,i,!Rcl")))]
61
  "TARGET_A24"
62
  "@
63
   add.%&\t%2,%0
64
   add.%&\t%2,%0
65
   add.%&\t%2,%0
66
   mova\t%d2[%1],%0
67
   mova\t%D2[%1],%0
68
   #
69
   #"
70
  [(set_attr "flags" "oszc,oszc,oszc,*,*,oszc,oszc")]
71
  )
72
 
73
; This is needed for reloading large frames.
74
(define_split
75
  [(set (match_operand:PSI 0 "ra_operand" "")
76
        (plus:PSI (match_operand:PSI 1 "cr_operand" "")
77
                 (match_operand:PSI 2 "immediate_operand" "")))]
78
  ""
79
  [(set (match_dup 0) (match_dup 1))
80
   (set (match_dup 0)
81
        (plus:PSI (match_dup 0)
82
                 (match_dup 2)))]
83
  ""
84
  )
85
 
86
; This is needed for reloading large frames.
87
(define_split
88
  [(set (match_operand:PSI 0 "ra_operand" "")
89
        (plus:PSI (match_operand:PSI 1 "ra_operand" "")
90
                 (match_operand:PSI 2 "cr_operand" "")))]
91
  ""
92
  [(set (match_dup 0) (match_dup 2))
93
   (set (match_dup 0)
94
        (plus:PSI (match_dup 0)
95
                 (match_dup 1)))]
96
  ""
97
  )
98
 
99
(define_insn "subqi3"
100
  [(set (match_operand:QI 0 "mra_or_sp_operand"
101
                   "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp")
102
        (minus:QI (match_operand:QI 1 "mra_operand"
103
                   "0,0,0,0, 0,0,0,0, 0")
104
                  (match_operand:QI 2 "mrai_operand"
105
                   "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa, i")))]
106
  ""
107
  "sub.b\t%2,%0"
108
  [(set_attr "flags" "oszc")]
109
  )
110
 
111
(define_insn "subhi3"
112
  [(set (match_operand:HI 0 "mra_operand"
113
                   "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm")
114
        (minus:HI (match_operand:HI 1 "mras_operand"
115
                   "0,0,0,0, 0,0")
116
                  (match_operand:HI 2 "mrai_operand"
117
                   "IU2SdRhi,?Rmm,IU2SdRhi,?Rmm, IM2,IM2")))]
118
  ""
119
  "@
120
   sub.w\t%2,%0
121
   sub.w\t%2,%0
122
   sub.w\t%2,%0
123
   sub.w\t%2,%0
124
   add.w\t%m2,%0
125
   add.w\t%m2,%0"
126
  [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc")]
127
  )
128
 
129
(define_insn "subpsi3"
130
  [(set (match_operand:PSI 0 "mra_operand" "=RpiSd,RpiSd,??Rmm,??Rmm")
131
        (minus:PSI (match_operand:PSI 1 "mra_operand" "0,0,0,0")
132
                   (match_operand:PSI 2 "mrai_operand" "iRpiSd,?Rmm,iRpiSd,?Rmm")))]
133
  "TARGET_A24"
134
  "sub.%&\t%2,%0"
135
  [(set_attr "flags" "oszc")]
136
  )
137
 
138
(define_insn "negqi2"
139
  [(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm")
140
        (neg:QI (match_operand:QI 1 "mra_operand" "0,0")))]
141
  ""
142
  "neg.b\t%0"
143
  [(set_attr "flags" "oszc,oszc")]
144
  )
145
 
146
(define_insn "neghi2"
147
  [(set (match_operand:HI 0 "mra_operand" "=SdRhi,??Rmm")
148
        (neg:HI (match_operand:HI 1 "mra_operand" "0,0")))]
149
  ""
150
  "neg.w\t%0"
151
  [(set_attr "flags" "oszc,oszc")]
152
  )
153
 
154
; We can negate an SImode by operating on the subparts.  GCC deals
155
; with this itself for larger modes, but not SI.
156
(define_insn "negsi2"
157
  [(set (match_operand:SI 0 "mra_operand" "=SdR03,??Rmm")
158
        (neg:SI (match_operand:SI 1 "mra_operand" "0,0")))]
159
  ""
160
  "not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0"
161
  [(set_attr "flags" "oszc,oszc")]
162
  )
163
 
164
(define_insn "absqi2"
165
  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
166
        (abs:QI (match_operand:QI 1 "mra_operand" "0,0")))]
167
  ""
168
  "abs.b\t%0"
169
  [(set_attr "flags" "oszc")]
170
  )
171
 
172
(define_insn "abshi2"
173
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
174
        (abs:HI (match_operand:HI 1 "mra_operand" "0,0")))]
175
  ""
176
  "abs.w\t%0"
177
  [(set_attr "flags" "oszc")]
178
  )

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.