OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gcc/] [gcc-4.1.1/] [gcc/] [config/] [m32c/] [bitops.md] - Blame information for rev 20

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 jlechner
;; Machine Descriptions for R8C/M16C/M32C
2
;; Copyright (C) 2005
3
;; Free Software Foundation, Inc.
4
;; Contributed by Red Hat.
5
;;
6
;; This file is part of GCC.
7
;;
8
;; GCC is free software; you can redistribute it and/or modify it
9
;; under the terms of the GNU General Public License as published
10
;; by the Free Software Foundation; either version 2, or (at your
11
;; option) any later version.
12
;;
13
;; GCC is distributed in the hope that it will be useful, but WITHOUT
14
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
;; License for more details.
17
;;
18
;; You should have received a copy of the GNU General Public License
19
;; along with GCC; see the file COPYING.  If not, write to the Free
20
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
21
;; 02110-1301, USA.
22
 
23
;; Bit-wise operations (and, ior, xor, shift)
24
 
25
(define_insn "andqi3"
26
  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
27
        (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
28
                (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
29
  ""
30
  "and.b\t%x2,%0"
31
  [(set_attr "flags" "sz,sz,sz,sz")]
32
  )
33
 
34
(define_insn "andhi3"
35
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm,RhiSd,??Rmm")
36
        (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
37
                (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,?Rmm,iRhiSd")))]
38
  ""
39
  "and.w\t%X2,%0"
40
  [(set_attr "flags" "sz,sz,sz,sz")]
41
  )
42
 
43
(define_insn "iorqi3"
44
  [(set (match_operand:QI 0 "mra_operand" "=RqiSd,??Rmm,RqiSd,??Rmm")
45
        (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
46
                (match_operand:QI 2 "mrai_operand" "iRhlSd,iRhlSd,?Rmm,?Rmm")))]
47
  ""
48
  "or.b\t%x2,%0"
49
  [(set_attr "flags" "sz,sz,sz,sz")]
50
  )
51
 
52
(define_insn "iorhi3"
53
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
54
        (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
55
                (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
56
  ""
57
  "or.w\t%X2,%0"
58
  [(set_attr "flags" "sz,sz,sz,sz")]
59
  )
60
 
61
(define_insn "xorqi3"
62
  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
63
        (xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
64
                (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
65
  ""
66
  "xor.b\t%x2,%0"
67
  [(set_attr "flags" "sz,sz,sz,sz")]
68
  )
69
 
70
(define_insn "xorhi3"
71
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
72
        (xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
73
                (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
74
  ""
75
  "xor.w\t%X2,%0"
76
  [(set_attr "flags" "sz,sz,sz,sz")]
77
  )
78
 
79
(define_insn "one_cmplqi2"
80
  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
81
        (not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
82
  ""
83
  "not.b\t%0"
84
  [(set_attr "flags" "sz,sz")]
85
  )
86
 
87
(define_insn "one_cmplhi2"
88
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
89
        (not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
90
  ""
91
  "not.w\t%0"
92
  [(set_attr "flags" "sz,sz")]
93
  )

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.