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jlechner |
;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2005
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 2, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to the Free
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;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
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;; 02110-1301, USA.
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;; multiply and divide
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; Here is the pattern for the const_int.
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(define_insn "mulqihi3_c"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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(mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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(match_operand 2 "immediate_operand" "i,i")))]
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""
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"mul.b\t%2,%1"
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)
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; Here is the pattern for registers and such.
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(define_insn "mulqihi3_r"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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(mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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(sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
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""
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"mul.b\t%2,%1"
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)
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; Don't try to sign_extend a const_int. Same for all other multiplies.
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(define_expand "mulqihi3"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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(mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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(match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
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""
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"{ if (GET_MODE (operands[2]) != VOIDmode)
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operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
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)
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(define_insn "umulqihi3_c"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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(mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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(match_operand 2 "immediate_operand" "i,i")))]
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""
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"mulu.b\t%U2,%1"
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)
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(define_insn "umulqihi3_r"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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(mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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(zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
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""
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"mulu.b\t%U2,%1"
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)
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(define_expand "umulqihi3"
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[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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(mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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(match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
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""
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"{ if (GET_MODE (operands[2]) != VOIDmode)
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operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
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)
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(define_insn "mulhisi3_c"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm")
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(mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
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(match_operand 2 "immediate_operand" "i,i")))]
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""
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"mul.w\t%2,%1"
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)
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(define_insn "mulhisi3_r"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
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(sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
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""
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"mul.w\t%2,%1"
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)
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(define_expand "mulhisi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
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(match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
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""
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"{ if (GET_MODE (operands[2]) != VOIDmode)
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operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
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)
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(define_insn "umulhisi3_c"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm")
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(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
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(match_operand 2 "immediate_operand" "i,i")))]
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""
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"mulu.w\t%u2,%1"
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)
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(define_insn "umulhisi3_r"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
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(zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
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""
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"mulu.w\t%u2,%1"
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)
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(define_expand "umulhisi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
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(match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
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""
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"{ if (GET_MODE (operands[2]) != VOIDmode)
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operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
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)
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; GCC expects to be able to multiply pointer-sized integers too, but
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; fortunately it only multiplies by powers of two.
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(define_insn "mulpsi3"
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[(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
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(mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
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(match_operand 2 "const_int_operand" "Ilb")))]
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"TARGET_A24"
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"shl.l\t%b2,%0"
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[(set_attr "flags" "szc")]
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)
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(define_expand "divmodqi4"
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[(set (match_dup 4)
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(sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
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(parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
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(div:QI (match_dup 4)
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(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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(set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
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(mod:QI (match_dup 4) (match_dup 2)))
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])]
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"0"
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"operands[4] = gen_reg_rtx (HImode);"
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)
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(define_insn "divmodqi4_n"
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[(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
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(div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
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(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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(set (match_operand:QI 3 "register_operand" "=R0h,R0h")
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(mod:QI (match_dup 1) (match_dup 2)))
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]
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"0"
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"div.b\t%2"
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)
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(define_expand "udivmodqi4"
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[(set (match_dup 4)
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(zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
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(parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
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(udiv:QI (match_dup 4)
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(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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(set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
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(umod:QI (match_dup 4) (match_dup 2)))
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])]
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"0"
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"operands[4] = gen_reg_rtx (HImode);"
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)
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(define_insn "udivmodqi4_n"
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[(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
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(udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
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(match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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(set (match_operand:QI 3 "register_operand" "=R0h,R0h")
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(umod:QI (match_dup 1) (match_dup 2)))
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]
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"0"
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"divu.b\t%2"
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)
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(define_expand "divmodhi4"
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[(set (match_dup 4)
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(sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
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(parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
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(div:HI (match_dup 4)
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(match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
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(set (match_operand:HI 3 "register_operand" "=R2w,R2w")
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(mod:HI (match_dup 4) (match_dup 2)))
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])]
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""
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"operands[4] = gen_reg_rtx (SImode);"
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)
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(define_insn "divmodhi4_n"
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[(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
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(div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
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(match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
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(set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
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(mod:HI (match_dup 1) (match_dup 2)))
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]
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""
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"div.w\t%2"
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)
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(define_expand "udivmodhi4"
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[(set (match_dup 4)
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(zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
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(parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
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(udiv:HI (match_dup 4)
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(match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
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(set (match_operand:HI 3 "register_operand" "=R2w,R2w")
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(umod:HI (match_dup 4) (match_dup 2)))
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])]
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""
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"operands[4] = gen_reg_rtx (SImode);"
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)
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(define_insn "udivmodhi4_n"
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[(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
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(udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
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(match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
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(set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
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(umod:HI (match_dup 1) (match_dup 2)))
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]
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""
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"divu.w\t%2"
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)
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