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jlechner |
/* Definitions of target machine for GNU compiler, Renesas M32R cpu.
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Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
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2005 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 2, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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/* Things to do:
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- longlong.h?
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*/
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#undef SWITCH_TAKES_ARG
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#undef WORD_SWITCH_TAKES_ARG
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#undef HANDLE_SYSV_PRAGMA
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#undef SIZE_TYPE
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#undef PTRDIFF_TYPE
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#undef WCHAR_TYPE
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#undef WCHAR_TYPE_SIZE
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#undef TARGET_VERSION
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#undef CPP_SPEC
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#undef ASM_SPEC
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#undef LINK_SPEC
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#undef STARTFILE_SPEC
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#undef ENDFILE_SPEC
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#undef ASM_APP_ON
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#undef ASM_APP_OFF
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/* M32R/X overrides. */
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/* Print subsidiary information on the compiler version in use. */
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#define TARGET_VERSION fprintf (stderr, " (m32r/x/2)");
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/* Additional flags for the preprocessor. */
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#define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
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%{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
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%{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
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"
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/* Assembler switches. */
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#define ASM_CPU_SPEC \
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"%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
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/* Use m32rx specific crt0/crtinit/crtfini files. */
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#define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
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#define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
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/* Define this macro as a C expression for the initializer of an array of
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strings to tell the driver program which options are defaults for this
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target and thus do not need to be handled specially when using
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`MULTILIB_OPTIONS'. */
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#define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
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/* Number of additional registers the subtarget defines. */
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#define SUBTARGET_NUM_REGISTERS 1
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/* 1 for registers that cannot be allocated. */
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#define SUBTARGET_FIXED_REGISTERS , 1
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/* 1 for registers that are not available across function calls. */
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#define SUBTARGET_CALL_USED_REGISTERS , 1
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/* Order to allocate model specific registers. */
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#define SUBTARGET_REG_ALLOC_ORDER , 19
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/* Registers which are accumulators. */
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#define SUBTARGET_REG_CLASS_ACCUM 0x80000
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/* All registers added. */
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#define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
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/* Additional accumulator registers. */
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#define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
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/* Define additional register names. */
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#define SUBTARGET_REGISTER_NAMES , "a1"
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/* end M32R/X overrides. */
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/* Print subsidiary information on the compiler version in use. */
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#ifndef TARGET_VERSION
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#define TARGET_VERSION fprintf (stderr, " (m32r)")
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#endif
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/* Switch Recognition by gcc.c. Add -G xx support. */
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#undef SWITCH_TAKES_ARG
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#define SWITCH_TAKES_ARG(CHAR) \
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(DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
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/* Names to predefine in the preprocessor for this target machine. */
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/* __M32R__ is defined by the existing compiler so we use that. */
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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{ \
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builtin_define ("__M32R__"); \
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builtin_define ("__m32r__"); \
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builtin_assert ("cpu=m32r"); \
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builtin_assert ("machine=m32r"); \
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builtin_define (TARGET_BIG_ENDIAN \
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? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
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if (flag_pic) \
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{ \
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builtin_define ("__pic__"); \
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builtin_define ("__PIC__"); \
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} \
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} \
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while (0)
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/* This macro defines names of additional specifications to put in the specs
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that can be used in various specifications like CC1_SPEC. Its definition
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is an initializer with a subgrouping for each command option.
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Each subgrouping contains a string constant, that defines the
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specification name, and a string constant that used by the GCC driver
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program.
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Do not define this macro if it does not need to do anything. */
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#ifndef SUBTARGET_EXTRA_SPECS
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#define SUBTARGET_EXTRA_SPECS
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#endif
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#ifndef ASM_CPU_SPEC
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#define ASM_CPU_SPEC ""
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#endif
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#ifndef CPP_CPU_SPEC
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#define CPP_CPU_SPEC ""
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#endif
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#ifndef CC1_CPU_SPEC
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#define CC1_CPU_SPEC ""
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#endif
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#ifndef LINK_CPU_SPEC
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#define LINK_CPU_SPEC ""
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#endif
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#ifndef STARTFILE_CPU_SPEC
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#define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
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#endif
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#ifndef ENDFILE_CPU_SPEC
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#define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
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#endif
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#ifndef RELAX_SPEC
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#if 0 /* Not supported yet. */
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#define RELAX_SPEC "%{mrelax:-relax}"
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#else
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#define RELAX_SPEC ""
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#endif
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#endif
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#define EXTRA_SPECS \
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{ "asm_cpu", ASM_CPU_SPEC }, \
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{ "cpp_cpu", CPP_CPU_SPEC }, \
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{ "cc1_cpu", CC1_CPU_SPEC }, \
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{ "link_cpu", LINK_CPU_SPEC }, \
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{ "startfile_cpu", STARTFILE_CPU_SPEC }, \
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{ "endfile_cpu", ENDFILE_CPU_SPEC }, \
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{ "relax", RELAX_SPEC }, \
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SUBTARGET_EXTRA_SPECS
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#define CPP_SPEC "%(cpp_cpu)"
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#undef CC1_SPEC
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#define CC1_SPEC "%{G*} %(cc1_cpu)"
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/* Options to pass on to the assembler. */
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#undef ASM_SPEC
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#define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}"
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#define LINK_SPEC "%{v} %(link_cpu) %(relax)"
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#undef STARTFILE_SPEC
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#define STARTFILE_SPEC "%(startfile_cpu)"
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#undef ENDFILE_SPEC
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#define ENDFILE_SPEC "%(endfile_cpu)"
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#undef LIB_SPEC
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/* Run-time compilation parameters selecting different hardware subsets. */
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#define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
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#ifndef TARGET_LITTLE_ENDIAN
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#define TARGET_LITTLE_ENDIAN 0
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#endif
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#define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
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/* This defaults us to m32r. */
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#ifndef TARGET_CPU_DEFAULT
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#define TARGET_CPU_DEFAULT 0
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#endif
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/* Code Models
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Code models are used to select between two choices of two separate
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possibilities (address space size, call insn to use):
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small: addresses use 24 bits, use bl to make calls
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medium: addresses use 32 bits, use bl to make calls (*1)
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large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
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The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
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using this one doesn't make much sense.
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(*1) The linker may eventually be able to relax seth/add3 -> ld24.
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(*2) The linker may eventually be able to relax seth/add3/jl -> bl.
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Internally these are recorded as TARGET_ADDR{24,32} and
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TARGET_CALL{26,32}.
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The __model__ attribute can be used to select the code model to use when
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accessing particular objects. */
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enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
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extern enum m32r_model m32r_model;
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#define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
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#define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
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#define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
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#define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
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#define TARGET_ADDR32 (! TARGET_ADDR24)
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#define TARGET_CALL26 (! TARGET_CALL32)
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#define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
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/* The default is the small model. */
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#ifndef M32R_MODEL_DEFAULT
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#define M32R_MODEL_DEFAULT M32R_MODEL_SMALL
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#endif
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249 |
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/* Small Data Area
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251 |
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The SDA consists of sections .sdata, .sbss, and .scommon.
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.scommon isn't a real section, symbols in it have their section index
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set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
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Two switches control the SDA:
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-G NNN - specifies the maximum size of variable to go in the SDA
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-msdata=foo - specifies how such variables are handled
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-msdata=none - small data area is disabled
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263 |
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-msdata=sdata - small data goes in the SDA, special code isn't
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generated to use it, and special relocs aren't
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generated
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267 |
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-msdata=use - small data goes in the SDA, special code is generated
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to use the SDA and special relocs are generated
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The SDA is not multilib'd, it isn't necessary.
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MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
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libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
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-msdata=use will successfully link with them (references in header files
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will cause the compiler to emit code that refers to library objects in
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.data). ??? There can be a problem if the user passes a -G value greater
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than the default and a library object in a header file is that size.
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The default is 8 so this should be rare - if it occurs the user
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is required to rebuild the libraries or use a smaller value for -G. */
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279 |
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280 |
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/* Maximum size of variables that go in .sdata/.sbss.
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281 |
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The -msdata=foo switch also controls how small variables are handled. */
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282 |
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#ifndef SDATA_DEFAULT_SIZE
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283 |
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#define SDATA_DEFAULT_SIZE 8
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284 |
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#endif
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285 |
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286 |
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enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
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287 |
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288 |
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extern enum m32r_sdata m32r_sdata;
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289 |
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#define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
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290 |
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#define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
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291 |
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#define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
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292 |
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293 |
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/* Default is to disable the SDA
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294 |
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[for upward compatibility with previous toolchains]. */
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295 |
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#ifndef M32R_SDATA_DEFAULT
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296 |
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#define M32R_SDATA_DEFAULT M32R_SDATA_NONE
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297 |
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#endif
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298 |
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|
299 |
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/* Define this macro as a C expression for the initializer of an array of
|
300 |
|
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strings to tell the driver program which options are defaults for this
|
301 |
|
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target and thus do not need to be handled specially when using
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302 |
|
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`MULTILIB_OPTIONS'. */
|
303 |
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#ifndef SUBTARGET_MULTILIB_DEFAULTS
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304 |
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#define SUBTARGET_MULTILIB_DEFAULTS
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305 |
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#endif
|
306 |
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|
307 |
|
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#ifndef MULTILIB_DEFAULTS
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308 |
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#define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
|
309 |
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#endif
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310 |
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|
311 |
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/* Sometimes certain combinations of command options do not make
|
312 |
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sense on a particular target machine. You can define a macro
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313 |
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`OVERRIDE_OPTIONS' to take account of this. This macro, if
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defined, is executed once just after all the command options have
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been parsed.
|
316 |
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|
317 |
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Don't use this macro to turn on various extra optimizations for
|
318 |
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`-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
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319 |
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|
320 |
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#ifndef SUBTARGET_OVERRIDE_OPTIONS
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#define SUBTARGET_OVERRIDE_OPTIONS
|
322 |
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#endif
|
323 |
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|
324 |
|
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#define OVERRIDE_OPTIONS \
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325 |
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do \
|
326 |
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{ \
|
327 |
|
|
/* These need to be done at start up. \
|
328 |
|
|
It's convenient to do them here. */ \
|
329 |
|
|
m32r_init (); \
|
330 |
|
|
SUBTARGET_OVERRIDE_OPTIONS \
|
331 |
|
|
} \
|
332 |
|
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while (0)
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333 |
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|
334 |
|
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#ifndef SUBTARGET_OPTIMIZATION_OPTIONS
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335 |
|
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#define SUBTARGET_OPTIMIZATION_OPTIONS
|
336 |
|
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#endif
|
337 |
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|
338 |
|
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#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
|
339 |
|
|
do \
|
340 |
|
|
{ \
|
341 |
|
|
if (LEVEL == 1) \
|
342 |
|
|
flag_regmove = TRUE; \
|
343 |
|
|
\
|
344 |
|
|
if (SIZE) \
|
345 |
|
|
{ \
|
346 |
|
|
flag_omit_frame_pointer = TRUE; \
|
347 |
|
|
flag_strength_reduce = FALSE; \
|
348 |
|
|
} \
|
349 |
|
|
\
|
350 |
|
|
SUBTARGET_OPTIMIZATION_OPTIONS \
|
351 |
|
|
} \
|
352 |
|
|
while (0)
|
353 |
|
|
|
354 |
|
|
/* Define this macro if debugging can be performed even without a
|
355 |
|
|
frame pointer. If this macro is defined, GCC will turn on the
|
356 |
|
|
`-fomit-frame-pointer' option whenever `-O' is specified. */
|
357 |
|
|
#define CAN_DEBUG_WITHOUT_FP
|
358 |
|
|
|
359 |
|
|
/* Target machine storage layout. */
|
360 |
|
|
|
361 |
|
|
/* Define this if most significant bit is lowest numbered
|
362 |
|
|
in instructions that operate on numbered bit-fields. */
|
363 |
|
|
#define BITS_BIG_ENDIAN 1
|
364 |
|
|
|
365 |
|
|
/* Define this if most significant byte of a word is the lowest numbered. */
|
366 |
|
|
#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
|
367 |
|
|
|
368 |
|
|
/* Define this if most significant word of a multiword number is the lowest
|
369 |
|
|
numbered. */
|
370 |
|
|
#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
|
371 |
|
|
|
372 |
|
|
/* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
|
373 |
|
|
be a constant value with the same meaning as WORDS_BIG_ENDIAN,
|
374 |
|
|
which will be used only when compiling libgcc2.c. Typically the
|
375 |
|
|
value will be set based on preprocessor defines. */
|
376 |
|
|
/*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
|
377 |
|
|
|
378 |
|
|
/* Width of a word, in units (bytes). */
|
379 |
|
|
#define UNITS_PER_WORD 4
|
380 |
|
|
|
381 |
|
|
/* Define this macro if it is advisable to hold scalars in registers
|
382 |
|
|
in a wider mode than that declared by the program. In such cases,
|
383 |
|
|
the value is constrained to be within the bounds of the declared
|
384 |
|
|
type, but kept valid in the wider mode. The signedness of the
|
385 |
|
|
extension may differ from that of the type. */
|
386 |
|
|
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
|
387 |
|
|
if (GET_MODE_CLASS (MODE) == MODE_INT \
|
388 |
|
|
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
|
389 |
|
|
{ \
|
390 |
|
|
(MODE) = SImode; \
|
391 |
|
|
}
|
392 |
|
|
|
393 |
|
|
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
|
394 |
|
|
#define PARM_BOUNDARY 32
|
395 |
|
|
|
396 |
|
|
/* Boundary (in *bits*) on which stack pointer should be aligned. */
|
397 |
|
|
#define STACK_BOUNDARY 32
|
398 |
|
|
|
399 |
|
|
/* ALIGN FRAMES on word boundaries */
|
400 |
|
|
#define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
|
401 |
|
|
|
402 |
|
|
/* Allocation boundary (in *bits*) for the code of a function. */
|
403 |
|
|
#define FUNCTION_BOUNDARY 32
|
404 |
|
|
|
405 |
|
|
/* Alignment of field after `int : 0' in a structure. */
|
406 |
|
|
#define EMPTY_FIELD_BOUNDARY 32
|
407 |
|
|
|
408 |
|
|
/* Every structure's size must be a multiple of this. */
|
409 |
|
|
#define STRUCTURE_SIZE_BOUNDARY 8
|
410 |
|
|
|
411 |
|
|
/* A bit-field declared as `int' forces `int' alignment for the struct. */
|
412 |
|
|
#define PCC_BITFIELD_TYPE_MATTERS 1
|
413 |
|
|
|
414 |
|
|
/* No data type wants to be aligned rounder than this. */
|
415 |
|
|
#define BIGGEST_ALIGNMENT 32
|
416 |
|
|
|
417 |
|
|
/* The best alignment to use in cases where we have a choice. */
|
418 |
|
|
#define FASTEST_ALIGNMENT 32
|
419 |
|
|
|
420 |
|
|
/* Make strings word-aligned so strcpy from constants will be faster. */
|
421 |
|
|
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
|
422 |
|
|
((TREE_CODE (EXP) == STRING_CST \
|
423 |
|
|
&& (ALIGN) < FASTEST_ALIGNMENT) \
|
424 |
|
|
? FASTEST_ALIGNMENT : (ALIGN))
|
425 |
|
|
|
426 |
|
|
/* Make arrays of chars word-aligned for the same reasons. */
|
427 |
|
|
#define DATA_ALIGNMENT(TYPE, ALIGN) \
|
428 |
|
|
(TREE_CODE (TYPE) == ARRAY_TYPE \
|
429 |
|
|
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
|
430 |
|
|
&& (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
|
431 |
|
|
|
432 |
|
|
/* Set this nonzero if move instructions will actually fail to work
|
433 |
|
|
when given unaligned data. */
|
434 |
|
|
#define STRICT_ALIGNMENT 1
|
435 |
|
|
|
436 |
|
|
/* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
|
437 |
|
|
#define LABEL_ALIGN(insn) 2
|
438 |
|
|
|
439 |
|
|
/* Layout of source language data types. */
|
440 |
|
|
|
441 |
|
|
#define SHORT_TYPE_SIZE 16
|
442 |
|
|
#define INT_TYPE_SIZE 32
|
443 |
|
|
#define LONG_TYPE_SIZE 32
|
444 |
|
|
#define LONG_LONG_TYPE_SIZE 64
|
445 |
|
|
#define FLOAT_TYPE_SIZE 32
|
446 |
|
|
#define DOUBLE_TYPE_SIZE 64
|
447 |
|
|
#define LONG_DOUBLE_TYPE_SIZE 64
|
448 |
|
|
|
449 |
|
|
/* Define this as 1 if `char' should by default be signed; else as 0. */
|
450 |
|
|
#define DEFAULT_SIGNED_CHAR 1
|
451 |
|
|
|
452 |
|
|
#define SIZE_TYPE "long unsigned int"
|
453 |
|
|
#define PTRDIFF_TYPE "long int"
|
454 |
|
|
#define WCHAR_TYPE "short unsigned int"
|
455 |
|
|
#define WCHAR_TYPE_SIZE 16
|
456 |
|
|
|
457 |
|
|
/* Standard register usage. */
|
458 |
|
|
|
459 |
|
|
/* Number of actual hardware registers.
|
460 |
|
|
The hardware registers are assigned numbers for the compiler
|
461 |
|
|
from 0 to just below FIRST_PSEUDO_REGISTER.
|
462 |
|
|
All registers that the compiler knows about must be given numbers,
|
463 |
|
|
even those that are not normally considered general registers. */
|
464 |
|
|
|
465 |
|
|
#define M32R_NUM_REGISTERS 19
|
466 |
|
|
|
467 |
|
|
#ifndef SUBTARGET_NUM_REGISTERS
|
468 |
|
|
#define SUBTARGET_NUM_REGISTERS 0
|
469 |
|
|
#endif
|
470 |
|
|
|
471 |
|
|
#define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
|
472 |
|
|
|
473 |
|
|
/* 1 for registers that have pervasive standard uses
|
474 |
|
|
and are not available for the register allocator.
|
475 |
|
|
|
476 |
|
|
0-3 - arguments/results
|
477 |
|
|
4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
|
478 |
|
|
6 - call used, gptmp
|
479 |
|
|
7 - call used, static chain pointer
|
480 |
|
|
8-11 - call saved
|
481 |
|
|
12 - call saved [reserved for global pointer]
|
482 |
|
|
13 - frame pointer
|
483 |
|
|
14 - subroutine link register
|
484 |
|
|
15 - stack pointer
|
485 |
|
|
16 - arg pointer
|
486 |
|
|
17 - carry flag
|
487 |
|
|
18 - accumulator
|
488 |
|
|
19 - accumulator 1 in the m32r/x
|
489 |
|
|
By default, the extension registers are not available. */
|
490 |
|
|
|
491 |
|
|
#ifndef SUBTARGET_FIXED_REGISTERS
|
492 |
|
|
#define SUBTARGET_FIXED_REGISTERS
|
493 |
|
|
#endif
|
494 |
|
|
|
495 |
|
|
#define FIXED_REGISTERS \
|
496 |
|
|
{ \
|
497 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
498 |
|
|
0, 0, 0, 0, 0, 0, 0, 1, \
|
499 |
|
|
1, 1, 1 \
|
500 |
|
|
SUBTARGET_FIXED_REGISTERS \
|
501 |
|
|
}
|
502 |
|
|
|
503 |
|
|
/* 1 for registers not available across function calls.
|
504 |
|
|
These must include the FIXED_REGISTERS and also any
|
505 |
|
|
registers that can be used without being saved.
|
506 |
|
|
The latter must include the registers where values are returned
|
507 |
|
|
and the register where structure-value addresses are passed.
|
508 |
|
|
Aside from that, you can include as many other registers as you like. */
|
509 |
|
|
|
510 |
|
|
#ifndef SUBTARGET_CALL_USED_REGISTERS
|
511 |
|
|
#define SUBTARGET_CALL_USED_REGISTERS
|
512 |
|
|
#endif
|
513 |
|
|
|
514 |
|
|
#define CALL_USED_REGISTERS \
|
515 |
|
|
{ \
|
516 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, \
|
517 |
|
|
0, 0, 0, 0, 0, 0, 1, 1, \
|
518 |
|
|
1, 1, 1 \
|
519 |
|
|
SUBTARGET_CALL_USED_REGISTERS \
|
520 |
|
|
}
|
521 |
|
|
|
522 |
|
|
#define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
|
523 |
|
|
|
524 |
|
|
/* Zero or more C statements that may conditionally modify two variables
|
525 |
|
|
`fixed_regs' and `call_used_regs' (both of type `char []') after they
|
526 |
|
|
have been initialized from the two preceding macros.
|
527 |
|
|
|
528 |
|
|
This is necessary in case the fixed or call-clobbered registers depend
|
529 |
|
|
on target flags.
|
530 |
|
|
|
531 |
|
|
You need not define this macro if it has no work to do. */
|
532 |
|
|
|
533 |
|
|
#ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
|
534 |
|
|
#define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
|
535 |
|
|
#else
|
536 |
|
|
#define CONDITIONAL_REGISTER_USAGE \
|
537 |
|
|
do \
|
538 |
|
|
{ \
|
539 |
|
|
if (flag_pic) \
|
540 |
|
|
{ \
|
541 |
|
|
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
|
542 |
|
|
call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
|
543 |
|
|
} \
|
544 |
|
|
} \
|
545 |
|
|
while (0)
|
546 |
|
|
#endif
|
547 |
|
|
|
548 |
|
|
/* If defined, an initializer for a vector of integers, containing the
|
549 |
|
|
numbers of hard registers in the order in which GCC should
|
550 |
|
|
prefer to use them (from most preferred to least). */
|
551 |
|
|
|
552 |
|
|
#ifndef SUBTARGET_REG_ALLOC_ORDER
|
553 |
|
|
#define SUBTARGET_REG_ALLOC_ORDER
|
554 |
|
|
#endif
|
555 |
|
|
|
556 |
|
|
#if 1 /* Better for int code. */
|
557 |
|
|
#define REG_ALLOC_ORDER \
|
558 |
|
|
{ \
|
559 |
|
|
4, 5, 6, 7, 2, 3, 8, 9, 10, \
|
560 |
|
|
11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
|
561 |
|
|
SUBTARGET_REG_ALLOC_ORDER \
|
562 |
|
|
}
|
563 |
|
|
|
564 |
|
|
#else /* Better for fp code at expense of int code. */
|
565 |
|
|
#define REG_ALLOC_ORDER \
|
566 |
|
|
{ \
|
567 |
|
|
0, 1, 2, 3, 4, 5, 6, 7, 8, \
|
568 |
|
|
9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
|
569 |
|
|
SUBTARGET_REG_ALLOC_ORDER \
|
570 |
|
|
}
|
571 |
|
|
#endif
|
572 |
|
|
|
573 |
|
|
/* Return number of consecutive hard regs needed starting at reg REGNO
|
574 |
|
|
to hold something of mode MODE.
|
575 |
|
|
This is ordinarily the length in words of a value of mode MODE
|
576 |
|
|
but can be less for certain modes in special long registers. */
|
577 |
|
|
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
578 |
|
|
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
579 |
|
|
|
580 |
|
|
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
|
581 |
|
|
extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
|
582 |
|
|
extern unsigned int m32r_mode_class[];
|
583 |
|
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
|
584 |
|
|
((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
|
585 |
|
|
|
586 |
|
|
/* A C expression that is nonzero if it is desirable to choose
|
587 |
|
|
register allocation so as to avoid move instructions between a
|
588 |
|
|
value of mode MODE1 and a value of mode MODE2.
|
589 |
|
|
|
590 |
|
|
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
|
591 |
|
|
MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
|
592 |
|
|
MODE2)' must be zero. */
|
593 |
|
|
|
594 |
|
|
/* Tie QI/HI/SI modes together. */
|
595 |
|
|
#define MODES_TIEABLE_P(MODE1, MODE2) \
|
596 |
|
|
( GET_MODE_CLASS (MODE1) == MODE_INT \
|
597 |
|
|
&& GET_MODE_CLASS (MODE2) == MODE_INT \
|
598 |
|
|
&& GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
|
599 |
|
|
&& GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
|
600 |
|
|
|
601 |
|
|
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
|
602 |
|
|
m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
|
603 |
|
|
|
604 |
|
|
/* Register classes and constants. */
|
605 |
|
|
|
606 |
|
|
/* Define the classes of registers for register constraints in the
|
607 |
|
|
machine description. Also define ranges of constants.
|
608 |
|
|
|
609 |
|
|
One of the classes must always be named ALL_REGS and include all hard regs.
|
610 |
|
|
If there is more than one class, another class must be named NO_REGS
|
611 |
|
|
and contain no registers.
|
612 |
|
|
|
613 |
|
|
The name GENERAL_REGS must be the name of a class (or an alias for
|
614 |
|
|
another name such as ALL_REGS). This is the class of registers
|
615 |
|
|
that is allowed by "g" or "r" in a register constraint.
|
616 |
|
|
Also, registers outside this class are allocated only when
|
617 |
|
|
instructions express preferences for them.
|
618 |
|
|
|
619 |
|
|
The classes must be numbered in nondecreasing order; that is,
|
620 |
|
|
a larger-numbered class must never be contained completely
|
621 |
|
|
in a smaller-numbered class.
|
622 |
|
|
|
623 |
|
|
For any two classes, it is very desirable that there be another
|
624 |
|
|
class that represents their union.
|
625 |
|
|
|
626 |
|
|
It is important that any condition codes have class NO_REGS.
|
627 |
|
|
See `register_operand'. */
|
628 |
|
|
|
629 |
|
|
enum reg_class
|
630 |
|
|
{
|
631 |
|
|
NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
|
632 |
|
|
};
|
633 |
|
|
|
634 |
|
|
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
|
635 |
|
|
|
636 |
|
|
/* Give names of register classes as strings for dump file. */
|
637 |
|
|
#define REG_CLASS_NAMES \
|
638 |
|
|
{ "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
|
639 |
|
|
|
640 |
|
|
/* Define which registers fit in which classes.
|
641 |
|
|
This is an initializer for a vector of HARD_REG_SET
|
642 |
|
|
of length N_REG_CLASSES. */
|
643 |
|
|
|
644 |
|
|
#ifndef SUBTARGET_REG_CLASS_CARRY
|
645 |
|
|
#define SUBTARGET_REG_CLASS_CARRY 0
|
646 |
|
|
#endif
|
647 |
|
|
|
648 |
|
|
#ifndef SUBTARGET_REG_CLASS_ACCUM
|
649 |
|
|
#define SUBTARGET_REG_CLASS_ACCUM 0
|
650 |
|
|
#endif
|
651 |
|
|
|
652 |
|
|
#ifndef SUBTARGET_REG_CLASS_GENERAL
|
653 |
|
|
#define SUBTARGET_REG_CLASS_GENERAL 0
|
654 |
|
|
#endif
|
655 |
|
|
|
656 |
|
|
#ifndef SUBTARGET_REG_CLASS_ALL
|
657 |
|
|
#define SUBTARGET_REG_CLASS_ALL 0
|
658 |
|
|
#endif
|
659 |
|
|
|
660 |
|
|
#define REG_CLASS_CONTENTS \
|
661 |
|
|
{ \
|
662 |
|
|
{ 0x00000 }, \
|
663 |
|
|
{ 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
|
664 |
|
|
{ 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
|
665 |
|
|
{ 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
|
666 |
|
|
{ 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
|
667 |
|
|
}
|
668 |
|
|
|
669 |
|
|
/* The same information, inverted:
|
670 |
|
|
Return the class number of the smallest class containing
|
671 |
|
|
reg number REGNO. This could be a conditional expression
|
672 |
|
|
or could index an array. */
|
673 |
|
|
extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
|
674 |
|
|
#define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
|
675 |
|
|
|
676 |
|
|
/* The class value for index registers, and the one for base regs. */
|
677 |
|
|
#define INDEX_REG_CLASS GENERAL_REGS
|
678 |
|
|
#define BASE_REG_CLASS GENERAL_REGS
|
679 |
|
|
|
680 |
|
|
#define REG_CLASS_FROM_LETTER(C) \
|
681 |
|
|
( (C) == 'c' ? CARRY_REG \
|
682 |
|
|
: (C) == 'a' ? ACCUM_REGS \
|
683 |
|
|
: NO_REGS)
|
684 |
|
|
|
685 |
|
|
/* These assume that REGNO is a hard or pseudo reg number.
|
686 |
|
|
They give nonzero only if REGNO is a hard reg of the suitable class
|
687 |
|
|
or a pseudo reg currently allocated to a suitable hard reg.
|
688 |
|
|
Since they use reg_renumber, they are safe only once reg_renumber
|
689 |
|
|
has been allocated, which happens in local-alloc.c. */
|
690 |
|
|
#define REGNO_OK_FOR_BASE_P(REGNO) \
|
691 |
|
|
((REGNO) < FIRST_PSEUDO_REGISTER \
|
692 |
|
|
? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
|
693 |
|
|
: GPR_P (reg_renumber[REGNO]))
|
694 |
|
|
|
695 |
|
|
#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
|
696 |
|
|
|
697 |
|
|
/* Given an rtx X being reloaded into a reg required to be
|
698 |
|
|
in class CLASS, return the class of reg to actually use.
|
699 |
|
|
In general this is just CLASS; but on some machines
|
700 |
|
|
in some cases it is preferable to use a more restrictive class. */
|
701 |
|
|
#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
|
702 |
|
|
|
703 |
|
|
/* Return the maximum number of consecutive registers
|
704 |
|
|
needed to represent mode MODE in a register of class CLASS. */
|
705 |
|
|
#define CLASS_MAX_NREGS(CLASS, MODE) \
|
706 |
|
|
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
707 |
|
|
|
708 |
|
|
/* The letters I, J, K, L, M, N, O, P in a register constraint string
|
709 |
|
|
can be used to stand for particular ranges of immediate operands.
|
710 |
|
|
This macro defines what the ranges are.
|
711 |
|
|
C is the letter, and VALUE is a constant value.
|
712 |
|
|
Return 1 if VALUE is in the range specified by C. */
|
713 |
|
|
/* 'I' is used for 8 bit signed immediates.
|
714 |
|
|
'J' is used for 16 bit signed immediates.
|
715 |
|
|
'K' is used for 16 bit unsigned immediates.
|
716 |
|
|
'L' is used for 16 bit immediates left shifted by 16 (sign ???).
|
717 |
|
|
'M' is used for 24 bit unsigned immediates.
|
718 |
|
|
'N' is used for any 32 bit non-symbolic value.
|
719 |
|
|
'O' is used for 5 bit unsigned immediates (shift count).
|
720 |
|
|
'P' is used for 16 bit signed immediates for compares
|
721 |
|
|
(values in the range -32767 to +32768). */
|
722 |
|
|
|
723 |
|
|
/* Return true if a value is inside a range. */
|
724 |
|
|
#define IN_RANGE_P(VALUE, LOW, HIGH) \
|
725 |
|
|
(((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
|
726 |
|
|
<= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
|
727 |
|
|
|
728 |
|
|
/* Local to this file. */
|
729 |
|
|
#define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f)
|
730 |
|
|
#define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
|
731 |
|
|
#define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
|
732 |
|
|
#define UPPER16_P(X) (((X) & 0xffff) == 0 \
|
733 |
|
|
&& ((X) >> 16) >= - 0x8000 \
|
734 |
|
|
&& ((X) >> 16) <= 0x7fff)
|
735 |
|
|
#define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
|
736 |
|
|
#define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
|
737 |
|
|
#define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
|
738 |
|
|
#define UINT5_P(X) ((X) >= 0 && (X) < 32)
|
739 |
|
|
#define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
|
740 |
|
|
|
741 |
|
|
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
|
742 |
|
|
( (C) == 'I' ? INT8_P (VALUE) \
|
743 |
|
|
: (C) == 'J' ? INT16_P (VALUE) \
|
744 |
|
|
: (C) == 'K' ? UINT16_P (VALUE) \
|
745 |
|
|
: (C) == 'L' ? UPPER16_P (VALUE) \
|
746 |
|
|
: (C) == 'M' ? UINT24_P (VALUE) \
|
747 |
|
|
: (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \
|
748 |
|
|
: (C) == 'O' ? UINT5_P (VALUE) \
|
749 |
|
|
: (C) == 'P' ? CMP_INT16_P (VALUE) \
|
750 |
|
|
: 0)
|
751 |
|
|
|
752 |
|
|
/* Similar, but for floating constants, and defining letters G and H.
|
753 |
|
|
Here VALUE is the CONST_DOUBLE rtx itself.
|
754 |
|
|
For the m32r, handle a few constants inline.
|
755 |
|
|
??? We needn't treat DI and DF modes differently, but for now we do. */
|
756 |
|
|
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
|
757 |
|
|
( (C) == 'G' ? easy_di_const (VALUE) \
|
758 |
|
|
: (C) == 'H' ? easy_df_const (VALUE) \
|
759 |
|
|
: 0)
|
760 |
|
|
|
761 |
|
|
/* A C expression that defines the optional machine-dependent constraint
|
762 |
|
|
letters that can be used to segregate specific types of operands,
|
763 |
|
|
usually memory references, for the target machine. It should return 1 if
|
764 |
|
|
VALUE corresponds to the operand type represented by the constraint letter
|
765 |
|
|
C. If C is not defined as an extra constraint, the value returned should
|
766 |
|
|
be 0 regardless of VALUE. */
|
767 |
|
|
/* Q is for symbolic addresses loadable with ld24.
|
768 |
|
|
R is for symbolic addresses when ld24 can't be used.
|
769 |
|
|
S is for stores with pre {inc,dec}rement
|
770 |
|
|
T is for indirect of a pointer.
|
771 |
|
|
U is for loads with post increment. */
|
772 |
|
|
|
773 |
|
|
#define EXTRA_CONSTRAINT(VALUE, C) \
|
774 |
|
|
( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \
|
775 |
|
|
|| addr24_operand (VALUE, VOIDmode)) \
|
776 |
|
|
: (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \
|
777 |
|
|
|| addr32_operand (VALUE, VOIDmode)) \
|
778 |
|
|
: (C) == 'S' ? (GET_CODE (VALUE) == MEM \
|
779 |
|
|
&& STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
|
780 |
|
|
XEXP (VALUE, 0))) \
|
781 |
|
|
: (C) == 'T' ? (GET_CODE (VALUE) == MEM \
|
782 |
|
|
&& memreg_operand (VALUE, GET_MODE (VALUE))) \
|
783 |
|
|
: (C) == 'U' ? (GET_CODE (VALUE) == MEM \
|
784 |
|
|
&& LOAD_POSTINC_P (GET_MODE (VALUE), \
|
785 |
|
|
XEXP (VALUE, 0))) \
|
786 |
|
|
: 0)
|
787 |
|
|
|
788 |
|
|
/* Stack layout and stack pointer usage. */
|
789 |
|
|
|
790 |
|
|
/* Define this macro if pushing a word onto the stack moves the stack
|
791 |
|
|
pointer to a smaller address. */
|
792 |
|
|
#define STACK_GROWS_DOWNWARD
|
793 |
|
|
|
794 |
|
|
/* Offset from frame pointer to start allocating local variables at.
|
795 |
|
|
If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
|
796 |
|
|
first local allocated. Otherwise, it is the offset to the BEGINNING
|
797 |
|
|
of the first local allocated. */
|
798 |
|
|
/* The frame pointer points at the same place as the stack pointer, except if
|
799 |
|
|
alloca has been called. */
|
800 |
|
|
#define STARTING_FRAME_OFFSET \
|
801 |
|
|
M32R_STACK_ALIGN (current_function_outgoing_args_size)
|
802 |
|
|
|
803 |
|
|
/* Offset from the stack pointer register to the first location at which
|
804 |
|
|
outgoing arguments are placed. */
|
805 |
|
|
#define STACK_POINTER_OFFSET 0
|
806 |
|
|
|
807 |
|
|
/* Offset of first parameter from the argument pointer register value. */
|
808 |
|
|
#define FIRST_PARM_OFFSET(FNDECL) 0
|
809 |
|
|
|
810 |
|
|
/* Register to use for pushing function arguments. */
|
811 |
|
|
#define STACK_POINTER_REGNUM 15
|
812 |
|
|
|
813 |
|
|
/* Base register for access to local variables of the function. */
|
814 |
|
|
#define FRAME_POINTER_REGNUM 13
|
815 |
|
|
|
816 |
|
|
/* Base register for access to arguments of the function. */
|
817 |
|
|
#define ARG_POINTER_REGNUM 16
|
818 |
|
|
|
819 |
|
|
/* Register in which static-chain is passed to a function.
|
820 |
|
|
This must not be a register used by the prologue. */
|
821 |
|
|
#define STATIC_CHAIN_REGNUM 7
|
822 |
|
|
|
823 |
|
|
/* These aren't official macros. */
|
824 |
|
|
#define PROLOGUE_TMP_REGNUM 4
|
825 |
|
|
#define RETURN_ADDR_REGNUM 14
|
826 |
|
|
/* #define GP_REGNUM 12 */
|
827 |
|
|
#define CARRY_REGNUM 17
|
828 |
|
|
#define ACCUM_REGNUM 18
|
829 |
|
|
#define M32R_MAX_INT_REGS 16
|
830 |
|
|
|
831 |
|
|
#ifndef SUBTARGET_GPR_P
|
832 |
|
|
#define SUBTARGET_GPR_P(REGNO) 0
|
833 |
|
|
#endif
|
834 |
|
|
|
835 |
|
|
#ifndef SUBTARGET_ACCUM_P
|
836 |
|
|
#define SUBTARGET_ACCUM_P(REGNO) 0
|
837 |
|
|
#endif
|
838 |
|
|
|
839 |
|
|
#ifndef SUBTARGET_CARRY_P
|
840 |
|
|
#define SUBTARGET_CARRY_P(REGNO) 0
|
841 |
|
|
#endif
|
842 |
|
|
|
843 |
|
|
#define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
|
844 |
|
|
#define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
|
845 |
|
|
#define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
|
846 |
|
|
|
847 |
|
|
/* Eliminating the frame and arg pointers. */
|
848 |
|
|
|
849 |
|
|
/* A C expression which is nonzero if a function must have and use a
|
850 |
|
|
frame pointer. This expression is evaluated in the reload pass.
|
851 |
|
|
If its value is nonzero the function will have a frame pointer. */
|
852 |
|
|
#define FRAME_POINTER_REQUIRED current_function_calls_alloca
|
853 |
|
|
|
854 |
|
|
#if 0
|
855 |
|
|
/* C statement to store the difference between the frame pointer
|
856 |
|
|
and the stack pointer values immediately after the function prologue.
|
857 |
|
|
If `ELIMINABLE_REGS' is defined, this macro will be not be used and
|
858 |
|
|
need not be defined. */
|
859 |
|
|
#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
|
860 |
|
|
((VAR) = m32r_compute_frame_size (get_frame_size ()))
|
861 |
|
|
#endif
|
862 |
|
|
|
863 |
|
|
/* If defined, this macro specifies a table of register pairs used to
|
864 |
|
|
eliminate unneeded registers that point into the stack frame. If
|
865 |
|
|
it is not defined, the only elimination attempted by the compiler
|
866 |
|
|
is to replace references to the frame pointer with references to
|
867 |
|
|
the stack pointer.
|
868 |
|
|
|
869 |
|
|
Note that the elimination of the argument pointer with the stack
|
870 |
|
|
pointer is specified first since that is the preferred elimination. */
|
871 |
|
|
|
872 |
|
|
#define ELIMINABLE_REGS \
|
873 |
|
|
{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
874 |
|
|
{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
875 |
|
|
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
|
876 |
|
|
|
877 |
|
|
/* A C expression that returns nonzero if the compiler is allowed to
|
878 |
|
|
try to replace register number FROM-REG with register number
|
879 |
|
|
TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
|
880 |
|
|
defined, and will usually be the constant 1, since most of the
|
881 |
|
|
cases preventing register elimination are things that the compiler
|
882 |
|
|
already knows about. */
|
883 |
|
|
|
884 |
|
|
#define CAN_ELIMINATE(FROM, TO) \
|
885 |
|
|
((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
|
886 |
|
|
? ! frame_pointer_needed \
|
887 |
|
|
: 1)
|
888 |
|
|
|
889 |
|
|
/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
|
890 |
|
|
specifies the initial difference between the specified pair of
|
891 |
|
|
registers. This macro must be defined if `ELIMINABLE_REGS' is
|
892 |
|
|
defined. */
|
893 |
|
|
|
894 |
|
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
895 |
|
|
do \
|
896 |
|
|
{ \
|
897 |
|
|
int size = m32r_compute_frame_size (get_frame_size ()); \
|
898 |
|
|
\
|
899 |
|
|
if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
|
900 |
|
|
(OFFSET) = 0; \
|
901 |
|
|
else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
|
902 |
|
|
(OFFSET) = size - current_function_pretend_args_size; \
|
903 |
|
|
else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
|
904 |
|
|
(OFFSET) = size - current_function_pretend_args_size; \
|
905 |
|
|
else \
|
906 |
|
|
gcc_unreachable (); \
|
907 |
|
|
} \
|
908 |
|
|
while (0)
|
909 |
|
|
|
910 |
|
|
/* Function argument passing. */
|
911 |
|
|
|
912 |
|
|
/* If defined, the maximum amount of space required for outgoing
|
913 |
|
|
arguments will be computed and placed into the variable
|
914 |
|
|
`current_function_outgoing_args_size'. No space will be pushed
|
915 |
|
|
onto the stack for each call; instead, the function prologue should
|
916 |
|
|
increase the stack frame size by this amount. */
|
917 |
|
|
#define ACCUMULATE_OUTGOING_ARGS 1
|
918 |
|
|
|
919 |
|
|
/* Value is the number of bytes of arguments automatically
|
920 |
|
|
popped when returning from a subroutine call.
|
921 |
|
|
FUNDECL is the declaration node of the function (as a tree),
|
922 |
|
|
FUNTYPE is the data type of the function (as a tree),
|
923 |
|
|
or for a library call it is an identifier node for the subroutine name.
|
924 |
|
|
SIZE is the number of bytes of arguments passed on the stack. */
|
925 |
|
|
#define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
|
926 |
|
|
|
927 |
|
|
/* Define a data type for recording info about an argument list
|
928 |
|
|
during the scan of that argument list. This data type should
|
929 |
|
|
hold all necessary information about the function itself
|
930 |
|
|
and about the args processed so far, enough to enable macros
|
931 |
|
|
such as FUNCTION_ARG to determine where the next arg should go. */
|
932 |
|
|
#define CUMULATIVE_ARGS int
|
933 |
|
|
|
934 |
|
|
/* Initialize a variable CUM of type CUMULATIVE_ARGS
|
935 |
|
|
for a call to a function whose data type is FNTYPE.
|
936 |
|
|
For a library call, FNTYPE is 0. */
|
937 |
|
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
938 |
|
|
((CUM) = 0)
|
939 |
|
|
|
940 |
|
|
/* The number of registers used for parameter passing. Local to this file. */
|
941 |
|
|
#define M32R_MAX_PARM_REGS 4
|
942 |
|
|
|
943 |
|
|
/* 1 if N is a possible register number for function argument passing. */
|
944 |
|
|
#define FUNCTION_ARG_REGNO_P(N) \
|
945 |
|
|
((unsigned) (N) < M32R_MAX_PARM_REGS)
|
946 |
|
|
|
947 |
|
|
/* The ROUND_ADVANCE* macros are local to this file. */
|
948 |
|
|
/* Round SIZE up to a word boundary. */
|
949 |
|
|
#define ROUND_ADVANCE(SIZE) \
|
950 |
|
|
(((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
951 |
|
|
|
952 |
|
|
/* Round arg MODE/TYPE up to the next word boundary. */
|
953 |
|
|
#define ROUND_ADVANCE_ARG(MODE, TYPE) \
|
954 |
|
|
((MODE) == BLKmode \
|
955 |
|
|
? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
|
956 |
|
|
: ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
|
957 |
|
|
|
958 |
|
|
/* Round CUM up to the necessary point for argument MODE/TYPE. */
|
959 |
|
|
#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
|
960 |
|
|
|
961 |
|
|
/* Return boolean indicating arg of type TYPE and mode MODE will be passed in
|
962 |
|
|
a reg. This includes arguments that have to be passed by reference as the
|
963 |
|
|
pointer to them is passed in a reg if one is available (and that is what
|
964 |
|
|
we're given).
|
965 |
|
|
This macro is only used in this file. */
|
966 |
|
|
#define PASS_IN_REG_P(CUM, MODE, TYPE) \
|
967 |
|
|
(ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
|
968 |
|
|
|
969 |
|
|
/* Determine where to put an argument to a function.
|
970 |
|
|
Value is zero to push the argument on the stack,
|
971 |
|
|
or a hard register in which to store the argument.
|
972 |
|
|
|
973 |
|
|
MODE is the argument's machine mode.
|
974 |
|
|
TYPE is the data type of the argument (as a tree).
|
975 |
|
|
This is null for libcalls where that information may
|
976 |
|
|
not be available.
|
977 |
|
|
CUM is a variable of type CUMULATIVE_ARGS which gives info about
|
978 |
|
|
the preceding args and about the function being called.
|
979 |
|
|
NAMED is nonzero if this argument is a named parameter
|
980 |
|
|
(otherwise it is an extra parameter matching an ellipsis). */
|
981 |
|
|
/* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
|
982 |
|
|
and the rest are pushed. */
|
983 |
|
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
984 |
|
|
(PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
|
985 |
|
|
? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
|
986 |
|
|
: 0)
|
987 |
|
|
|
988 |
|
|
/* Update the data in CUM to advance over an argument
|
989 |
|
|
of mode MODE and data type TYPE.
|
990 |
|
|
(TYPE is null for libcalls where that information may not be available.) */
|
991 |
|
|
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
992 |
|
|
((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
|
993 |
|
|
+ ROUND_ADVANCE_ARG ((MODE), (TYPE))))
|
994 |
|
|
|
995 |
|
|
/* If defined, a C expression that gives the alignment boundary, in bits,
|
996 |
|
|
of an argument with the specified mode and type. If it is not defined,
|
997 |
|
|
PARM_BOUNDARY is used for all arguments. */
|
998 |
|
|
#if 0
|
999 |
|
|
/* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
|
1000 |
|
|
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
|
1001 |
|
|
(((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
|
1002 |
|
|
? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
|
1003 |
|
|
#endif
|
1004 |
|
|
|
1005 |
|
|
/* Function results. */
|
1006 |
|
|
|
1007 |
|
|
/* Define how to find the value returned by a function.
|
1008 |
|
|
VALTYPE is the data type of the value (as a tree).
|
1009 |
|
|
If the precise function being called is known, FUNC is its FUNCTION_DECL;
|
1010 |
|
|
otherwise, FUNC is 0. */
|
1011 |
|
|
#define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
|
1012 |
|
|
|
1013 |
|
|
/* Define how to find the value returned by a library function
|
1014 |
|
|
assuming the value has mode MODE. */
|
1015 |
|
|
#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
|
1016 |
|
|
|
1017 |
|
|
/* 1 if N is a possible register number for a function value
|
1018 |
|
|
as seen by the caller. */
|
1019 |
|
|
/* ??? What about r1 in DI/DF values. */
|
1020 |
|
|
#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
|
1021 |
|
|
|
1022 |
|
|
/* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
|
1023 |
|
|
#define DEFAULT_PCC_STRUCT_RETURN 0
|
1024 |
|
|
|
1025 |
|
|
/* Function entry and exit. */
|
1026 |
|
|
|
1027 |
|
|
/* Initialize data used by insn expanders. This is called from
|
1028 |
|
|
init_emit, once for each function, before code is generated. */
|
1029 |
|
|
#define INIT_EXPANDERS m32r_init_expanders ()
|
1030 |
|
|
|
1031 |
|
|
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
|
1032 |
|
|
the stack pointer does not matter. The value is tested only in
|
1033 |
|
|
functions that have frame pointers.
|
1034 |
|
|
No definition is equivalent to always zero. */
|
1035 |
|
|
#define EXIT_IGNORE_STACK 1
|
1036 |
|
|
|
1037 |
|
|
/* Output assembler code to FILE to increment profiler label # LABELNO
|
1038 |
|
|
for profiling a function entry. */
|
1039 |
|
|
#undef FUNCTION_PROFILER
|
1040 |
|
|
#define FUNCTION_PROFILER(FILE, LABELNO) \
|
1041 |
|
|
do \
|
1042 |
|
|
{ \
|
1043 |
|
|
if (flag_pic) \
|
1044 |
|
|
{ \
|
1045 |
|
|
fprintf (FILE, "\tld24 r14,#mcount\n"); \
|
1046 |
|
|
fprintf (FILE, "\tadd r14,r12\n"); \
|
1047 |
|
|
fprintf (FILE, "\tld r14,@r14\n"); \
|
1048 |
|
|
fprintf (FILE, "\tjl r14\n"); \
|
1049 |
|
|
} \
|
1050 |
|
|
else \
|
1051 |
|
|
{ \
|
1052 |
|
|
if (TARGET_ADDR24) \
|
1053 |
|
|
fprintf (FILE, "\tbl mcount\n"); \
|
1054 |
|
|
else \
|
1055 |
|
|
{ \
|
1056 |
|
|
fprintf (FILE, "\tseth r14,#high(mcount)\n"); \
|
1057 |
|
|
fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \
|
1058 |
|
|
fprintf (FILE, "\tjl r14\n"); \
|
1059 |
|
|
} \
|
1060 |
|
|
} \
|
1061 |
|
|
fprintf (FILE, "\taddi sp,#4\n"); \
|
1062 |
|
|
} \
|
1063 |
|
|
while (0)
|
1064 |
|
|
|
1065 |
|
|
/* Trampolines. */
|
1066 |
|
|
|
1067 |
|
|
/* On the M32R, the trampoline is:
|
1068 |
|
|
|
1069 |
|
|
mv r7, lr -> bl L1 ; 178e 7e01
|
1070 |
|
|
L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
|
1071 |
|
|
mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
|
1072 |
|
|
ld r6, @r6 -> jmp r6 ; 26c6 1fc6
|
1073 |
|
|
L2: .word STATIC
|
1074 |
|
|
.word FUNCTION */
|
1075 |
|
|
|
1076 |
|
|
#ifndef CACHE_FLUSH_FUNC
|
1077 |
|
|
#define CACHE_FLUSH_FUNC "_flush_cache"
|
1078 |
|
|
#endif
|
1079 |
|
|
#ifndef CACHE_FLUSH_TRAP
|
1080 |
|
|
#define CACHE_FLUSH_TRAP 12
|
1081 |
|
|
#endif
|
1082 |
|
|
|
1083 |
|
|
/* Length in bytes of the trampoline for entering a nested function. */
|
1084 |
|
|
#define TRAMPOLINE_SIZE 24
|
1085 |
|
|
|
1086 |
|
|
/* Emit RTL insns to initialize the variable parts of a trampoline.
|
1087 |
|
|
FNADDR is an RTX for the address of the function's pure code.
|
1088 |
|
|
CXT is an RTX for the static chain value for the function. */
|
1089 |
|
|
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
|
1090 |
|
|
do \
|
1091 |
|
|
{ \
|
1092 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
|
1093 |
|
|
GEN_INT \
|
1094 |
|
|
(TARGET_LITTLE_ENDIAN ? 0x017e8e17 : 0x178e7e01)); \
|
1095 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
|
1096 |
|
|
GEN_INT \
|
1097 |
|
|
(TARGET_LITTLE_ENDIAN ? 0x0c00ae86 : 0x86ae000c)); \
|
1098 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
|
1099 |
|
|
GEN_INT \
|
1100 |
|
|
(TARGET_LITTLE_ENDIAN ? 0xe627871e : 0x1e8727e6)); \
|
1101 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), \
|
1102 |
|
|
GEN_INT \
|
1103 |
|
|
(TARGET_LITTLE_ENDIAN ? 0xc616c626 : 0x26c61fc6)); \
|
1104 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), \
|
1105 |
|
|
(CXT)); \
|
1106 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)), \
|
1107 |
|
|
(FNADDR)); \
|
1108 |
|
|
if (m32r_cache_flush_trap >= 0) \
|
1109 |
|
|
emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\
|
1110 |
|
|
GEN_INT (m32r_cache_flush_trap) )); \
|
1111 |
|
|
else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) \
|
1112 |
|
|
emit_library_call (m32r_function_symbol (m32r_cache_flush_func), \
|
1113 |
|
|
0, VOIDmode, 3, TRAMP, Pmode, \
|
1114 |
|
|
GEN_INT (TRAMPOLINE_SIZE), SImode, \
|
1115 |
|
|
GEN_INT (3), SImode); \
|
1116 |
|
|
} \
|
1117 |
|
|
while (0)
|
1118 |
|
|
|
1119 |
|
|
#define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT)
|
1120 |
|
|
|
1121 |
|
|
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
|
1122 |
|
|
|
1123 |
|
|
/* Addressing modes, and classification of registers for them. */
|
1124 |
|
|
|
1125 |
|
|
/* Maximum number of registers that can appear in a valid memory address. */
|
1126 |
|
|
#define MAX_REGS_PER_ADDRESS 1
|
1127 |
|
|
|
1128 |
|
|
/* We have post-inc load and pre-dec,pre-inc store,
|
1129 |
|
|
but only for 4 byte vals. */
|
1130 |
|
|
#define HAVE_PRE_DECREMENT 1
|
1131 |
|
|
#define HAVE_PRE_INCREMENT 1
|
1132 |
|
|
#define HAVE_POST_INCREMENT 1
|
1133 |
|
|
|
1134 |
|
|
/* Recognize any constant value that is a valid address. */
|
1135 |
|
|
#define CONSTANT_ADDRESS_P(X) \
|
1136 |
|
|
( GET_CODE (X) == LABEL_REF \
|
1137 |
|
|
|| GET_CODE (X) == SYMBOL_REF \
|
1138 |
|
|
|| GET_CODE (X) == CONST_INT \
|
1139 |
|
|
|| (GET_CODE (X) == CONST \
|
1140 |
|
|
&& ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
|
1141 |
|
|
|
1142 |
|
|
/* Nonzero if the constant value X is a legitimate general operand.
|
1143 |
|
|
We don't allow (plus symbol large-constant) as the relocations can't
|
1144 |
|
|
describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
|
1145 |
|
|
We allow all CONST_DOUBLE's as the md file patterns will force the
|
1146 |
|
|
constant to memory if they can't handle them. */
|
1147 |
|
|
|
1148 |
|
|
#define LEGITIMATE_CONSTANT_P(X) \
|
1149 |
|
|
(! (GET_CODE (X) == CONST \
|
1150 |
|
|
&& GET_CODE (XEXP (X, 0)) == PLUS \
|
1151 |
|
|
&& GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
|
1152 |
|
|
&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
|
1153 |
|
|
&& (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
|
1154 |
|
|
|
1155 |
|
|
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
1156 |
|
|
and check its validity for a certain class.
|
1157 |
|
|
We have two alternate definitions for each of them.
|
1158 |
|
|
The usual definition accepts all pseudo regs; the other rejects
|
1159 |
|
|
them unless they have been allocated suitable hard regs.
|
1160 |
|
|
The symbol REG_OK_STRICT causes the latter definition to be used.
|
1161 |
|
|
|
1162 |
|
|
Most source files want to accept pseudo regs in the hope that
|
1163 |
|
|
they will get allocated to the class that the insn wants them to be in.
|
1164 |
|
|
Source files for reload pass need to be strict.
|
1165 |
|
|
After reload, it makes no difference, since pseudo regs have
|
1166 |
|
|
been eliminated by then. */
|
1167 |
|
|
|
1168 |
|
|
#ifdef REG_OK_STRICT
|
1169 |
|
|
|
1170 |
|
|
/* Nonzero if X is a hard reg that can be used as a base reg. */
|
1171 |
|
|
#define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
|
1172 |
|
|
/* Nonzero if X is a hard reg that can be used as an index. */
|
1173 |
|
|
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
|
1174 |
|
|
|
1175 |
|
|
#else
|
1176 |
|
|
|
1177 |
|
|
/* Nonzero if X is a hard reg that can be used as a base reg
|
1178 |
|
|
or if it is a pseudo reg. */
|
1179 |
|
|
#define REG_OK_FOR_BASE_P(X) \
|
1180 |
|
|
(GPR_P (REGNO (X)) \
|
1181 |
|
|
|| (REGNO (X)) == ARG_POINTER_REGNUM \
|
1182 |
|
|
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
|
1183 |
|
|
/* Nonzero if X is a hard reg that can be used as an index
|
1184 |
|
|
or if it is a pseudo reg. */
|
1185 |
|
|
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
|
1186 |
|
|
|
1187 |
|
|
#endif
|
1188 |
|
|
|
1189 |
|
|
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
|
1190 |
|
|
that is a valid memory address for an instruction.
|
1191 |
|
|
The MODE argument is the machine mode for the MEM expression
|
1192 |
|
|
that wants to use this address. */
|
1193 |
|
|
|
1194 |
|
|
/* Local to this file. */
|
1195 |
|
|
#define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
|
1196 |
|
|
|
1197 |
|
|
/* Local to this file. */
|
1198 |
|
|
#define RTX_OK_FOR_OFFSET_P(X) \
|
1199 |
|
|
(GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
|
1200 |
|
|
|
1201 |
|
|
/* Local to this file. */
|
1202 |
|
|
#define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
|
1203 |
|
|
(GET_CODE (X) == PLUS \
|
1204 |
|
|
&& RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
|
1205 |
|
|
&& RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
|
1206 |
|
|
|
1207 |
|
|
/* Local to this file. */
|
1208 |
|
|
/* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
|
1209 |
|
|
since more than one instruction will be required. */
|
1210 |
|
|
#define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
|
1211 |
|
|
(GET_CODE (X) == LO_SUM \
|
1212 |
|
|
&& (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
|
1213 |
|
|
&& RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
|
1214 |
|
|
&& CONSTANT_P (XEXP (X, 1)))
|
1215 |
|
|
|
1216 |
|
|
/* Local to this file. */
|
1217 |
|
|
/* Is this a load and increment operation. */
|
1218 |
|
|
#define LOAD_POSTINC_P(MODE, X) \
|
1219 |
|
|
(((MODE) == SImode || (MODE) == SFmode) \
|
1220 |
|
|
&& GET_CODE (X) == POST_INC \
|
1221 |
|
|
&& GET_CODE (XEXP (X, 0)) == REG \
|
1222 |
|
|
&& RTX_OK_FOR_BASE_P (XEXP (X, 0)))
|
1223 |
|
|
|
1224 |
|
|
/* Local to this file. */
|
1225 |
|
|
/* Is this an increment/decrement and store operation. */
|
1226 |
|
|
#define STORE_PREINC_PREDEC_P(MODE, X) \
|
1227 |
|
|
(((MODE) == SImode || (MODE) == SFmode) \
|
1228 |
|
|
&& (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
|
1229 |
|
|
&& GET_CODE (XEXP (X, 0)) == REG \
|
1230 |
|
|
&& RTX_OK_FOR_BASE_P (XEXP (X, 0)))
|
1231 |
|
|
|
1232 |
|
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
1233 |
|
|
do \
|
1234 |
|
|
{ \
|
1235 |
|
|
if (RTX_OK_FOR_BASE_P (X)) \
|
1236 |
|
|
goto ADDR; \
|
1237 |
|
|
if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
|
1238 |
|
|
goto ADDR; \
|
1239 |
|
|
if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
|
1240 |
|
|
goto ADDR; \
|
1241 |
|
|
if (LOAD_POSTINC_P ((MODE), (X))) \
|
1242 |
|
|
goto ADDR; \
|
1243 |
|
|
if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
|
1244 |
|
|
goto ADDR; \
|
1245 |
|
|
} \
|
1246 |
|
|
while (0)
|
1247 |
|
|
|
1248 |
|
|
/* Try machine-dependent ways of modifying an illegitimate address
|
1249 |
|
|
to be legitimate. If we find one, return the new, valid address.
|
1250 |
|
|
This macro is used in only one place: `memory_address' in explow.c.
|
1251 |
|
|
|
1252 |
|
|
OLDX is the address as it was before break_out_memory_refs was called.
|
1253 |
|
|
In some cases it is useful to look at this to decide what needs to be done.
|
1254 |
|
|
|
1255 |
|
|
MODE and WIN are passed so that this macro can use
|
1256 |
|
|
GO_IF_LEGITIMATE_ADDRESS.
|
1257 |
|
|
|
1258 |
|
|
It is always safe for this macro to do nothing. It exists to recognize
|
1259 |
|
|
opportunities to optimize the output. */
|
1260 |
|
|
|
1261 |
|
|
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
|
1262 |
|
|
do \
|
1263 |
|
|
{ \
|
1264 |
|
|
if (flag_pic) \
|
1265 |
|
|
(X) = m32r_legitimize_pic_address (X, NULL_RTX); \
|
1266 |
|
|
if (memory_address_p (MODE, X)) \
|
1267 |
|
|
goto WIN; \
|
1268 |
|
|
} \
|
1269 |
|
|
while (0)
|
1270 |
|
|
|
1271 |
|
|
/* Go to LABEL if ADDR (a legitimate address expression)
|
1272 |
|
|
has an effect that depends on the machine mode it is used for. */
|
1273 |
|
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
|
1274 |
|
|
do \
|
1275 |
|
|
{ \
|
1276 |
|
|
if ( GET_CODE (ADDR) == PRE_DEC \
|
1277 |
|
|
|| GET_CODE (ADDR) == PRE_INC \
|
1278 |
|
|
|| GET_CODE (ADDR) == POST_INC \
|
1279 |
|
|
|| GET_CODE (ADDR) == LO_SUM) \
|
1280 |
|
|
goto LABEL; \
|
1281 |
|
|
} \
|
1282 |
|
|
while (0)
|
1283 |
|
|
|
1284 |
|
|
/* Condition code usage. */
|
1285 |
|
|
|
1286 |
|
|
/* Return nonzero if SELECT_CC_MODE will never return MODE for a
|
1287 |
|
|
floating point inequality comparison. */
|
1288 |
|
|
#define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
|
1289 |
|
|
|
1290 |
|
|
/* Costs. */
|
1291 |
|
|
|
1292 |
|
|
/* Compute extra cost of moving data between one register class
|
1293 |
|
|
and another. */
|
1294 |
|
|
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
|
1295 |
|
|
|
1296 |
|
|
/* Compute the cost of moving data between registers and memory. */
|
1297 |
|
|
/* Memory is 3 times as expensive as registers.
|
1298 |
|
|
??? Is that the right way to look at it? */
|
1299 |
|
|
#define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
|
1300 |
|
|
(GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
|
1301 |
|
|
|
1302 |
|
|
/* The cost of a branch insn. */
|
1303 |
|
|
/* A value of 2 here causes GCC to avoid using branches in comparisons like
|
1304 |
|
|
while (a < N && a). Branches aren't that expensive on the M32R so
|
1305 |
|
|
we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
|
1306 |
|
|
#define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
|
1307 |
|
|
|
1308 |
|
|
/* Nonzero if access to memory by bytes is slow and undesirable.
|
1309 |
|
|
For RISC chips, it means that access to memory by bytes is no
|
1310 |
|
|
better than access by words when possible, so grab a whole word
|
1311 |
|
|
and maybe make use of that. */
|
1312 |
|
|
#define SLOW_BYTE_ACCESS 1
|
1313 |
|
|
|
1314 |
|
|
/* Define this macro if it is as good or better to call a constant
|
1315 |
|
|
function address than to call an address kept in a register. */
|
1316 |
|
|
#define NO_FUNCTION_CSE
|
1317 |
|
|
|
1318 |
|
|
/* Section selection. */
|
1319 |
|
|
|
1320 |
|
|
#define TEXT_SECTION_ASM_OP "\t.section .text"
|
1321 |
|
|
#define DATA_SECTION_ASM_OP "\t.section .data"
|
1322 |
|
|
#define BSS_SECTION_ASM_OP "\t.section .bss"
|
1323 |
|
|
|
1324 |
|
|
/* Define this macro if jump tables (for tablejump insns) should be
|
1325 |
|
|
output in the text section, along with the assembler instructions.
|
1326 |
|
|
Otherwise, the readonly data section is used.
|
1327 |
|
|
This macro is irrelevant if there is no separate readonly data section. */
|
1328 |
|
|
#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
|
1329 |
|
|
|
1330 |
|
|
/* Position Independent Code. */
|
1331 |
|
|
|
1332 |
|
|
/* The register number of the register used to address a table of static
|
1333 |
|
|
data addresses in memory. In some cases this register is defined by a
|
1334 |
|
|
processor's ``application binary interface'' (ABI). When this macro
|
1335 |
|
|
is defined, RTL is generated for this register once, as with the stack
|
1336 |
|
|
pointer and frame pointer registers. If this macro is not defined, it
|
1337 |
|
|
is up to the machine-dependent files to allocate such a register (if
|
1338 |
|
|
necessary). */
|
1339 |
|
|
#define PIC_OFFSET_TABLE_REGNUM 12
|
1340 |
|
|
|
1341 |
|
|
/* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
|
1342 |
|
|
clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
|
1343 |
|
|
is not defined. */
|
1344 |
|
|
/* This register is call-saved on the M32R. */
|
1345 |
|
|
/*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
|
1346 |
|
|
|
1347 |
|
|
/* A C expression that is nonzero if X is a legitimate immediate
|
1348 |
|
|
operand on the target machine when generating position independent code.
|
1349 |
|
|
You can assume that X satisfies CONSTANT_P, so you need not
|
1350 |
|
|
check this. You can also assume `flag_pic' is true, so you need not
|
1351 |
|
|
check it either. You need not define this macro if all constants
|
1352 |
|
|
(including SYMBOL_REF) can be immediate operands when generating
|
1353 |
|
|
position independent code. */
|
1354 |
|
|
#define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
|
1355 |
|
|
|
1356 |
|
|
/* Control the assembler format that we output. */
|
1357 |
|
|
|
1358 |
|
|
/* A C string constant describing how to begin a comment in the target
|
1359 |
|
|
assembler language. The compiler assumes that the comment will
|
1360 |
|
|
end at the end of the line. */
|
1361 |
|
|
#define ASM_COMMENT_START ";"
|
1362 |
|
|
|
1363 |
|
|
/* Output to assembler file text saying following lines
|
1364 |
|
|
may contain character constants, extra white space, comments, etc. */
|
1365 |
|
|
#define ASM_APP_ON ""
|
1366 |
|
|
|
1367 |
|
|
/* Output to assembler file text saying following lines
|
1368 |
|
|
no longer contain unusual constructs. */
|
1369 |
|
|
#define ASM_APP_OFF ""
|
1370 |
|
|
|
1371 |
|
|
/* Globalizing directive for a label. */
|
1372 |
|
|
#define GLOBAL_ASM_OP "\t.global\t"
|
1373 |
|
|
|
1374 |
|
|
/* We do not use DBX_LINES_FUNCTION_RELATIVE or
|
1375 |
|
|
dbxout_stab_value_internal_label_diff here because
|
1376 |
|
|
we need to use .debugsym for the line label. */
|
1377 |
|
|
|
1378 |
|
|
#define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \
|
1379 |
|
|
do \
|
1380 |
|
|
{ \
|
1381 |
|
|
rtx begin_label = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);\
|
1382 |
|
|
char label[64]; \
|
1383 |
|
|
ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \
|
1384 |
|
|
\
|
1385 |
|
|
dbxout_begin_stabn_sline (line); \
|
1386 |
|
|
assemble_name (file, label); \
|
1387 |
|
|
putc ('-', file); \
|
1388 |
|
|
assemble_name (file, begin_label); \
|
1389 |
|
|
fputs ("\n\t.debugsym ", file); \
|
1390 |
|
|
assemble_name (file, label); \
|
1391 |
|
|
putc ('\n', file); \
|
1392 |
|
|
counter += 1; \
|
1393 |
|
|
} \
|
1394 |
|
|
while (0)
|
1395 |
|
|
|
1396 |
|
|
/* How to refer to registers in assembler output.
|
1397 |
|
|
This sequence is indexed by compiler's hard-register-number (see above). */
|
1398 |
|
|
#ifndef SUBTARGET_REGISTER_NAMES
|
1399 |
|
|
#define SUBTARGET_REGISTER_NAMES
|
1400 |
|
|
#endif
|
1401 |
|
|
|
1402 |
|
|
#define REGISTER_NAMES \
|
1403 |
|
|
{ \
|
1404 |
|
|
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
|
1405 |
|
|
"r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
|
1406 |
|
|
"ap", "cbit", "a0" \
|
1407 |
|
|
SUBTARGET_REGISTER_NAMES \
|
1408 |
|
|
}
|
1409 |
|
|
|
1410 |
|
|
/* If defined, a C initializer for an array of structures containing
|
1411 |
|
|
a name and a register number. This macro defines additional names
|
1412 |
|
|
for hard registers, thus allowing the `asm' option in declarations
|
1413 |
|
|
to refer to registers using alternate names. */
|
1414 |
|
|
#ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
|
1415 |
|
|
#define SUBTARGET_ADDITIONAL_REGISTER_NAMES
|
1416 |
|
|
#endif
|
1417 |
|
|
|
1418 |
|
|
#define ADDITIONAL_REGISTER_NAMES \
|
1419 |
|
|
{ \
|
1420 |
|
|
/*{ "gp", GP_REGNUM },*/ \
|
1421 |
|
|
{ "r13", FRAME_POINTER_REGNUM }, \
|
1422 |
|
|
{ "r14", RETURN_ADDR_REGNUM }, \
|
1423 |
|
|
{ "r15", STACK_POINTER_REGNUM }, \
|
1424 |
|
|
SUBTARGET_ADDITIONAL_REGISTER_NAMES \
|
1425 |
|
|
}
|
1426 |
|
|
|
1427 |
|
|
/* A C expression which evaluates to true if CODE is a valid
|
1428 |
|
|
punctuation character for use in the `PRINT_OPERAND' macro. */
|
1429 |
|
|
extern char m32r_punct_chars[256];
|
1430 |
|
|
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
|
1431 |
|
|
m32r_punct_chars[(unsigned char) (CHAR)]
|
1432 |
|
|
|
1433 |
|
|
/* Print operand X (an rtx) in assembler syntax to file FILE.
|
1434 |
|
|
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
|
1435 |
|
|
For `%' followed by punctuation, CODE is the punctuation and X is null. */
|
1436 |
|
|
#define PRINT_OPERAND(FILE, X, CODE) \
|
1437 |
|
|
m32r_print_operand (FILE, X, CODE)
|
1438 |
|
|
|
1439 |
|
|
/* A C compound statement to output to stdio stream STREAM the
|
1440 |
|
|
assembler syntax for an instruction operand that is a memory
|
1441 |
|
|
reference whose address is ADDR. ADDR is an RTL expression. */
|
1442 |
|
|
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
|
1443 |
|
|
m32r_print_operand_address (FILE, ADDR)
|
1444 |
|
|
|
1445 |
|
|
/* If defined, C string expressions to be used for the `%R', `%L',
|
1446 |
|
|
`%U', and `%I' options of `asm_fprintf' (see `final.c'). These
|
1447 |
|
|
are useful when a single `md' file must support multiple assembler
|
1448 |
|
|
formats. In that case, the various `tm.h' files can define these
|
1449 |
|
|
macros differently. */
|
1450 |
|
|
#define REGISTER_PREFIX ""
|
1451 |
|
|
#define LOCAL_LABEL_PREFIX ".L"
|
1452 |
|
|
#define USER_LABEL_PREFIX ""
|
1453 |
|
|
#define IMMEDIATE_PREFIX "#"
|
1454 |
|
|
|
1455 |
|
|
/* This is how to output an element of a case-vector that is absolute. */
|
1456 |
|
|
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
1457 |
|
|
do \
|
1458 |
|
|
{ \
|
1459 |
|
|
char label[30]; \
|
1460 |
|
|
ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
|
1461 |
|
|
fprintf (FILE, "\t.word\t"); \
|
1462 |
|
|
assemble_name (FILE, label); \
|
1463 |
|
|
fprintf (FILE, "\n"); \
|
1464 |
|
|
} \
|
1465 |
|
|
while (0)
|
1466 |
|
|
|
1467 |
|
|
/* This is how to output an element of a case-vector that is relative. */
|
1468 |
|
|
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
|
1469 |
|
|
do \
|
1470 |
|
|
{ \
|
1471 |
|
|
char label[30]; \
|
1472 |
|
|
ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
|
1473 |
|
|
fprintf (FILE, "\t.word\t"); \
|
1474 |
|
|
assemble_name (FILE, label); \
|
1475 |
|
|
fprintf (FILE, "-"); \
|
1476 |
|
|
ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
|
1477 |
|
|
assemble_name (FILE, label); \
|
1478 |
|
|
fprintf (FILE, "\n"); \
|
1479 |
|
|
} \
|
1480 |
|
|
while (0)
|
1481 |
|
|
|
1482 |
|
|
/* The desired alignment for the location counter at the beginning
|
1483 |
|
|
of a loop. */
|
1484 |
|
|
/* On the M32R, align loops to 32 byte boundaries (cache line size)
|
1485 |
|
|
if -malign-loops. */
|
1486 |
|
|
#define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
|
1487 |
|
|
|
1488 |
|
|
/* Define this to be the maximum number of insns to move around when moving
|
1489 |
|
|
a loop test from the top of a loop to the bottom
|
1490 |
|
|
and seeing whether to duplicate it. The default is thirty.
|
1491 |
|
|
|
1492 |
|
|
Loop unrolling currently doesn't like this optimization, so
|
1493 |
|
|
disable doing if we are unrolling loops and saving space. */
|
1494 |
|
|
#define LOOP_TEST_THRESHOLD (optimize_size \
|
1495 |
|
|
&& !flag_unroll_loops \
|
1496 |
|
|
&& !flag_unroll_all_loops ? 2 : 30)
|
1497 |
|
|
|
1498 |
|
|
/* This is how to output an assembler line
|
1499 |
|
|
that says to advance the location counter
|
1500 |
|
|
to a multiple of 2**LOG bytes. */
|
1501 |
|
|
/* .balign is used to avoid confusion. */
|
1502 |
|
|
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
|
1503 |
|
|
do \
|
1504 |
|
|
{ \
|
1505 |
|
|
if ((LOG) != 0) \
|
1506 |
|
|
fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
|
1507 |
|
|
} \
|
1508 |
|
|
while (0)
|
1509 |
|
|
|
1510 |
|
|
/* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
|
1511 |
|
|
separate, explicit argument. If you define this macro, it is used in
|
1512 |
|
|
place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
|
1513 |
|
|
handling the required alignment of the variable. The alignment is
|
1514 |
|
|
specified as the number of bits. */
|
1515 |
|
|
|
1516 |
|
|
#define SCOMMON_ASM_OP "\t.scomm\t"
|
1517 |
|
|
|
1518 |
|
|
#undef ASM_OUTPUT_ALIGNED_COMMON
|
1519 |
|
|
#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
|
1520 |
|
|
do \
|
1521 |
|
|
{ \
|
1522 |
|
|
if (! TARGET_SDATA_NONE \
|
1523 |
|
|
&& (SIZE) > 0 && (SIZE) <= g_switch_value) \
|
1524 |
|
|
fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
|
1525 |
|
|
else \
|
1526 |
|
|
fprintf ((FILE), "%s", COMMON_ASM_OP); \
|
1527 |
|
|
assemble_name ((FILE), (NAME)); \
|
1528 |
|
|
fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
|
1529 |
|
|
} \
|
1530 |
|
|
while (0)
|
1531 |
|
|
|
1532 |
|
|
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
|
1533 |
|
|
do \
|
1534 |
|
|
{ \
|
1535 |
|
|
if (! TARGET_SDATA_NONE \
|
1536 |
|
|
&& (SIZE) > 0 && (SIZE) <= g_switch_value) \
|
1537 |
|
|
named_section (0, ".sbss", 0); \
|
1538 |
|
|
else \
|
1539 |
|
|
bss_section (); \
|
1540 |
|
|
ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
|
1541 |
|
|
last_assemble_variable_decl = DECL; \
|
1542 |
|
|
ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
|
1543 |
|
|
ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
|
1544 |
|
|
} \
|
1545 |
|
|
while (0)
|
1546 |
|
|
|
1547 |
|
|
/* Debugging information. */
|
1548 |
|
|
|
1549 |
|
|
/* Generate DBX and DWARF debugging information. */
|
1550 |
|
|
#define DBX_DEBUGGING_INFO 1
|
1551 |
|
|
#define DWARF2_DEBUGGING_INFO 1
|
1552 |
|
|
|
1553 |
|
|
/* Use DWARF2 debugging info by default. */
|
1554 |
|
|
#undef PREFERRED_DEBUGGING_TYPE
|
1555 |
|
|
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
1556 |
|
|
|
1557 |
|
|
/* Turn off splitting of long stabs. */
|
1558 |
|
|
#define DBX_CONTIN_LENGTH 0
|
1559 |
|
|
|
1560 |
|
|
/* Miscellaneous. */
|
1561 |
|
|
|
1562 |
|
|
/* Specify the machine mode that this machine uses
|
1563 |
|
|
for the index in the tablejump instruction. */
|
1564 |
|
|
#define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
|
1565 |
|
|
|
1566 |
|
|
/* Define if operations between registers always perform the operation
|
1567 |
|
|
on the full register even if a narrower mode is specified. */
|
1568 |
|
|
#define WORD_REGISTER_OPERATIONS
|
1569 |
|
|
|
1570 |
|
|
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
|
1571 |
|
|
will either zero-extend or sign-extend. The value of this macro should
|
1572 |
|
|
be the code that says which one of the two operations is implicitly
|
1573 |
|
|
done, UNKNOWN if none. */
|
1574 |
|
|
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
|
1575 |
|
|
|
1576 |
|
|
/* Max number of bytes we can move from memory
|
1577 |
|
|
to memory in one reasonably fast instruction. */
|
1578 |
|
|
#define MOVE_MAX 4
|
1579 |
|
|
|
1580 |
|
|
/* Define this to be nonzero if shift instructions ignore all but the low-order
|
1581 |
|
|
few bits. */
|
1582 |
|
|
#define SHIFT_COUNT_TRUNCATED 1
|
1583 |
|
|
|
1584 |
|
|
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
|
1585 |
|
|
is done just by pretending it is already truncated. */
|
1586 |
|
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
1587 |
|
|
|
1588 |
|
|
/* Specify the machine mode that pointers have.
|
1589 |
|
|
After generation of rtl, the compiler makes no further distinction
|
1590 |
|
|
between pointers and any other objects of this machine mode. */
|
1591 |
|
|
/* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
|
1592 |
|
|
its own problems (you have to add extendpsisi2 and truncsipsi2).
|
1593 |
|
|
Try to avoid it. */
|
1594 |
|
|
#define Pmode SImode
|
1595 |
|
|
|
1596 |
|
|
/* A function address in a call instruction. */
|
1597 |
|
|
#define FUNCTION_MODE SImode
|
1598 |
|
|
|
1599 |
|
|
/* Define the information needed to generate branch and scc insns. This is
|
1600 |
|
|
stored from the compare operation. Note that we can't use "rtx" here
|
1601 |
|
|
since it hasn't been defined! */
|
1602 |
|
|
extern struct rtx_def * m32r_compare_op0;
|
1603 |
|
|
extern struct rtx_def * m32r_compare_op1;
|
1604 |
|
|
|
1605 |
|
|
/* M32R function types. */
|
1606 |
|
|
enum m32r_function_type
|
1607 |
|
|
{
|
1608 |
|
|
M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
|
1609 |
|
|
};
|
1610 |
|
|
|
1611 |
|
|
#define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
|
1612 |
|
|
|
1613 |
|
|
/* The maximum number of bytes to copy using pairs of load/store instructions.
|
1614 |
|
|
If a block is larger than this then a loop will be generated to copy
|
1615 |
|
|
MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
|
1616 |
|
|
A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
|
1617 |
|
|
string copy in it. */
|
1618 |
|
|
#define MAX_MOVE_BYTES 32
|