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jlechner |
/* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
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Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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/* We need to have MOTOROLA always defined (either 0 or 1) because we use
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if-statements and ?: on it. This way we have compile-time error checking
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for both the MOTOROLA and MIT code paths. We do rely on the host compiler
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to optimize away all constant tests. */
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#ifdef MOTOROLA
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# undef MOTOROLA
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# define MOTOROLA 1 /* Use the Motorola assembly syntax. */
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# define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
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#else
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# define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
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# define MOTOROLA 0 /* Use the MIT assembly syntax. */
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#endif
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/* Note that some other tm.h files include this one and then override
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many of the definitions that relate to assembler syntax. */
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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{ \
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builtin_define ("__m68k__"); \
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builtin_define_std ("mc68000"); \
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if (TARGET_68040_ONLY) \
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{ \
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if (TARGET_68060) \
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builtin_define_std ("mc68060"); \
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else \
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builtin_define_std ("mc68040"); \
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} \
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else if (TARGET_68060) /* -m68020-60 */ \
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{ \
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builtin_define_std ("mc68060"); \
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builtin_define_std ("mc68040"); \
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builtin_define_std ("mc68030"); \
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builtin_define_std ("mc68020"); \
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} \
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else if (TARGET_68040) /* -m68020-40 */ \
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{ \
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builtin_define_std ("mc68040"); \
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builtin_define_std ("mc68030"); \
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builtin_define_std ("mc68020"); \
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} \
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else if (TARGET_68030) \
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builtin_define_std ("mc68030"); \
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else if (TARGET_68020) \
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builtin_define_std ("mc68020"); \
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if (TARGET_68881) \
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builtin_define ("__HAVE_68881__"); \
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if (TARGET_CPU32) \
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{ \
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builtin_define_std ("mc68332"); \
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builtin_define_std ("mcpu32"); \
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} \
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if (TARGET_COLDFIRE) \
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builtin_define ("__mcoldfire__"); \
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if (TARGET_5200) \
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builtin_define ("__mcf5200__"); \
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if (TARGET_528x) \
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{ \
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builtin_define ("__mcf528x__"); \
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builtin_define ("__mcf5200__"); \
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} \
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if (TARGET_CFV3) \
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{ \
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builtin_define ("__mcf5300__"); \
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builtin_define ("__mcf5307__"); \
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} \
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if (TARGET_CFV4) \
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{ \
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builtin_define ("__mcf5400__"); \
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builtin_define ("__mcf5407__"); \
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} \
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if (TARGET_CF_HWDIV) \
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builtin_define ("__mcfhwdiv__"); \
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if (flag_pic) \
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{ \
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builtin_define ("__pic__"); \
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if (flag_pic > 1) \
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builtin_define ("__PIC__"); \
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} \
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builtin_assert ("cpu=m68k"); \
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builtin_assert ("machine=m68k"); \
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} \
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while (0)
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/* Classify the groups of pseudo-ops used to assemble QI, HI and SI
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quantities. */
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#define INT_OP_STANDARD 0 /* .byte, .short, .long */
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#define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
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#define INT_OP_NO_DOT 2 /* byte, short, long */
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#define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
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/* Set the default. */
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#define INT_OP_GROUP INT_OP_DOT_WORD
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/* Compile for a CPU32. A 68020 without bitfields is a good
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heuristic for a CPU32. */
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#define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
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/* Is the target a ColdFire? */
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#define MASK_COLDFIRE (MASK_5200 | MASK_528x | MASK_CFV3 | MASK_CFV4)
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#define TARGET_COLDFIRE ((target_flags & MASK_COLDFIRE) != 0)
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#define OVERRIDE_OPTIONS override_options()
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/* These are meant to be redefined in the host dependent files */
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#define SUBTARGET_OVERRIDE_OPTIONS
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/* target machine storage layout */
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#define LONG_DOUBLE_TYPE_SIZE 80
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/* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
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instructions, we get proper intermediate rounding, otherwise we
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get extended precision results. */
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#define TARGET_FLT_EVAL_METHOD ((TARGET_68040_ONLY || ! TARGET_68881) ? 0 : 2)
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#define BITS_BIG_ENDIAN 1
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#define BYTES_BIG_ENDIAN 1
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#define WORDS_BIG_ENDIAN 1
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#define UNITS_PER_WORD 4
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#define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
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#define STACK_BOUNDARY 16
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#define FUNCTION_BOUNDARY 16
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#define EMPTY_FIELD_BOUNDARY 16
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/* No data type wants to be aligned rounder than this.
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Most published ABIs say that ints should be aligned on 16 bit
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boundaries, but CPUs with 32-bit busses get better performance
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aligned on 32-bit boundaries. ColdFires without a misalignment
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module require 32-bit alignment. */
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#define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
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#define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
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#define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
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/* Define these to avoid dependence on meaning of `int'. */
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#define WCHAR_TYPE "long int"
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#define WCHAR_TYPE_SIZE 32
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/* Maximum number of library IDs we permit with -mid-shared-library. */
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#define MAX_LIBRARY_ID 255
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/* Standard register usage. */
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/* For the m68k, we give the data registers numbers 0-7,
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the address registers numbers 010-017 (8-15),
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and the 68881 floating point registers numbers 020-027 (16-24).
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We also have a fake `arg-pointer' register 030 (25) used for
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register elimination. */
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#define FIRST_PSEUDO_REGISTER 25
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/* All m68k targets (except AmigaOS) use %a5 as the PIC register */
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#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
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/* 1 for registers that have pervasive standard uses
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and are not available for the register allocator.
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On the m68k, only the stack pointer is such.
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Our fake arg-pointer is obviously fixed as well. */
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#define FIXED_REGISTERS \
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{/* Data registers. */ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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\
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/* Address registers. */ \
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0, 0, 0, 0, 0, 0, 0, 1, \
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\
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/* Floating point registers \
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(if available). */ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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\
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/* Arg pointer. */ \
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1 }
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/* 1 for registers not available across function calls.
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These must include the FIXED_REGISTERS and also any
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registers that can be used without being saved.
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The latter must include the registers where values are returned
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and the register where structure-value addresses are passed.
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Aside from that, you can include as many other registers as you like. */
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#define CALL_USED_REGISTERS \
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{/* Data registers. */ \
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1, 1, 0, 0, 0, 0, 0, 0, \
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\
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/* Address registers. */ \
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1, 1, 0, 0, 0, 0, 0, 1, \
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\
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/* Floating point registers \
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(if available). */ \
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1, 1, 0, 0, 0, 0, 0, 0, \
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\
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/* Arg pointer. */ \
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1 }
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#define REG_ALLOC_ORDER \
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{ /* d0/d1/a0/a1 */ \
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0, 1, 8, 9, \
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/* d2-d7 */ \
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2, 3, 4, 5, 6, 7, \
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/* a2-a7/arg */ \
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10, 11, 12, 13, 14, 15, 24, \
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/* fp0-fp7 */ \
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16, 17, 18, 19, 20, 21, 22, 23\
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}
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/* Make sure everything's fine if we *don't* have a given processor.
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This assumes that putting a register in fixed_regs will keep the
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compiler's mitts completely off it. We don't bother to zero it out
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of register classes. */
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#define CONDITIONAL_REGISTER_USAGE \
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{ \
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int i; \
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HARD_REG_SET x; \
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if (! TARGET_68881) \
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{ \
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COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
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if (TEST_HARD_REG_BIT (x, i)) \
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fixed_regs[i] = call_used_regs[i] = 1; \
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} \
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if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
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fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
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= call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
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}
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/* On the m68k, ordinary registers hold 32 bits worth;
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for the 68881 registers, a single register is always enough for
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anything that can be stored in them at all. */
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
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: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
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/* A C expression that is nonzero if hard register NEW_REG can be
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considered for use as a rename register for OLD_REG register. */
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#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
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m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
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/* Value is true if hard register REGNO can hold a value of machine-mode MODE.
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On the 68000, the cpu registers can hold any mode except bytes in
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address registers, the 68881 registers can hold only SFmode or DFmode. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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m68k_regno_mode_ok ((REGNO), (MODE))
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| 270 |
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#define MODES_TIEABLE_P(MODE1, MODE2) \
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(! TARGET_68881 \
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|| ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
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|| GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
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== (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
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|| GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
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/* Specify the registers used for certain standard purposes.
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The values of these macros are register numbers. */
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| 279 |
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| 280 |
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#define STACK_POINTER_REGNUM 15
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| 282 |
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/* Most m68k targets use %a6 as a frame pointer. The AmigaOS
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ABI uses %a6 for shared library calls, therefore the frame
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pointer is shifted to %a5 on this target. */
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| 285 |
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#define FRAME_POINTER_REGNUM 14
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| 286 |
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| 287 |
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#define FRAME_POINTER_REQUIRED 0
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| 288 |
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| 289 |
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/* Base register for access to arguments of the function.
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| 290 |
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* This isn't a hardware register. It will be eliminated to the
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| 291 |
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* stack pointer or frame pointer.
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| 292 |
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*/
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| 293 |
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#define ARG_POINTER_REGNUM 24
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| 295 |
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#define STATIC_CHAIN_REGNUM 8
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| 297 |
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/* Register in which address to store a structure value
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| 298 |
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is passed to a function. */
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| 299 |
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#define M68K_STRUCT_VALUE_REGNUM 9
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| 301 |
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| 302 |
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| 303 |
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/* The m68k has three kinds of registers, so eight classes would be
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a complete set. One of them is not needed. */
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enum reg_class {
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NO_REGS, DATA_REGS,
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ADDR_REGS, FP_REGS,
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GENERAL_REGS, DATA_OR_FP_REGS,
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ADDR_OR_FP_REGS, ALL_REGS,
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LIM_REG_CLASSES };
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| 311 |
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| 312 |
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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| 314 |
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#define REG_CLASS_NAMES \
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{ "NO_REGS", "DATA_REGS", \
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"ADDR_REGS", "FP_REGS", \
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| 317 |
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"GENERAL_REGS", "DATA_OR_FP_REGS", \
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| 318 |
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"ADDR_OR_FP_REGS", "ALL_REGS" }
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| 319 |
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| 320 |
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#define REG_CLASS_CONTENTS \
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{ \
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| 322 |
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{0x00000000}, /* NO_REGS */ \
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{0x000000ff}, /* DATA_REGS */ \
|
| 324 |
|
|
{0x0100ff00}, /* ADDR_REGS */ \
|
| 325 |
|
|
{0x00ff0000}, /* FP_REGS */ \
|
| 326 |
|
|
{0x0100ffff}, /* GENERAL_REGS */ \
|
| 327 |
|
|
{0x00ff00ff}, /* DATA_OR_FP_REGS */ \
|
| 328 |
|
|
{0x01ffff00}, /* ADDR_OR_FP_REGS */ \
|
| 329 |
|
|
{0x01ffffff}, /* ALL_REGS */ \
|
| 330 |
|
|
}
|
| 331 |
|
|
|
| 332 |
|
|
extern enum reg_class regno_reg_class[];
|
| 333 |
|
|
#define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
|
| 334 |
|
|
#define INDEX_REG_CLASS GENERAL_REGS
|
| 335 |
|
|
#define BASE_REG_CLASS ADDR_REGS
|
| 336 |
|
|
|
| 337 |
|
|
/* We do a trick here to modify the effective constraints on the
|
| 338 |
|
|
machine description; we zorch the constraint letters that aren't
|
| 339 |
|
|
appropriate for a specific target. This allows us to guarantee
|
| 340 |
|
|
that a specific kind of register will not be used for a given target
|
| 341 |
|
|
without fiddling with the register classes above. */
|
| 342 |
|
|
#define REG_CLASS_FROM_LETTER(C) \
|
| 343 |
|
|
((C) == 'a' ? ADDR_REGS : \
|
| 344 |
|
|
((C) == 'd' ? DATA_REGS : \
|
| 345 |
|
|
((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
|
| 346 |
|
|
NO_REGS) : \
|
| 347 |
|
|
NO_REGS)))
|
| 348 |
|
|
|
| 349 |
|
|
/* For the m68k, `I' is used for the range 1 to 8
|
| 350 |
|
|
allowed as immediate shift counts and in addq.
|
| 351 |
|
|
`J' is used for the range of signed numbers that fit in 16 bits.
|
| 352 |
|
|
`K' is for numbers that moveq can't handle.
|
| 353 |
|
|
`L' is for range -8 to -1, range of values that can be added with subq.
|
| 354 |
|
|
`M' is for numbers that moveq+notb can't handle.
|
| 355 |
|
|
'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
|
| 356 |
|
|
'O' is for 16 (for rotate using swap).
|
| 357 |
|
|
'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
|
| 358 |
|
|
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
|
| 359 |
|
|
((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
|
| 360 |
|
|
(C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
|
| 361 |
|
|
(C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
|
| 362 |
|
|
(C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
|
| 363 |
|
|
(C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
|
| 364 |
|
|
(C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
|
| 365 |
|
|
(C) == 'O' ? (VALUE) == 16 : \
|
| 366 |
|
|
(C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
|
| 367 |
|
|
|
| 368 |
|
|
/* "G" defines all of the floating constants that are *NOT* 68881
|
| 369 |
|
|
constants. This is so 68881 constants get reloaded and the
|
| 370 |
|
|
fpmovecr is used. */
|
| 371 |
|
|
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
|
| 372 |
|
|
((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
|
| 373 |
|
|
|
| 374 |
|
|
/* `Q' means address register indirect addressing mode.
|
| 375 |
|
|
`S' is for operands that satisfy 'm' when -mpcrel is in effect.
|
| 376 |
|
|
`T' is for operands that satisfy 's' when -mpcrel is not in effect.
|
| 377 |
|
|
`U' is for register offset addressing. */
|
| 378 |
|
|
#define EXTRA_CONSTRAINT(OP,CODE) \
|
| 379 |
|
|
(((CODE) == 'S') \
|
| 380 |
|
|
? (TARGET_PCREL \
|
| 381 |
|
|
&& GET_CODE (OP) == MEM \
|
| 382 |
|
|
&& (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
|
| 383 |
|
|
|| GET_CODE (XEXP (OP, 0)) == LABEL_REF \
|
| 384 |
|
|
|| GET_CODE (XEXP (OP, 0)) == CONST)) \
|
| 385 |
|
|
: \
|
| 386 |
|
|
(((CODE) == 'T') \
|
| 387 |
|
|
? ( !TARGET_PCREL \
|
| 388 |
|
|
&& (GET_CODE (OP) == SYMBOL_REF \
|
| 389 |
|
|
|| GET_CODE (OP) == LABEL_REF \
|
| 390 |
|
|
|| GET_CODE (OP) == CONST)) \
|
| 391 |
|
|
: \
|
| 392 |
|
|
(((CODE) == 'Q') \
|
| 393 |
|
|
? (GET_CODE (OP) == MEM \
|
| 394 |
|
|
&& GET_CODE (XEXP (OP, 0)) == REG) \
|
| 395 |
|
|
: \
|
| 396 |
|
|
(((CODE) == 'U') \
|
| 397 |
|
|
? (GET_CODE (OP) == MEM \
|
| 398 |
|
|
&& GET_CODE (XEXP (OP, 0)) == PLUS \
|
| 399 |
|
|
&& GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
|
| 400 |
|
|
&& GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
|
| 401 |
|
|
: \
|
| 402 |
|
|
0))))
|
| 403 |
|
|
|
| 404 |
|
|
/* On the m68k, use a data reg if possible when the
|
| 405 |
|
|
value is a constant in the range where moveq could be used
|
| 406 |
|
|
and we ensure that QImodes are reloaded into data regs. */
|
| 407 |
|
|
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
|
| 408 |
|
|
((GET_CODE (X) == CONST_INT \
|
| 409 |
|
|
&& (unsigned) (INTVAL (X) + 0x80) < 0x100 \
|
| 410 |
|
|
&& (CLASS) != ADDR_REGS) \
|
| 411 |
|
|
? DATA_REGS \
|
| 412 |
|
|
: (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
|
| 413 |
|
|
? DATA_REGS \
|
| 414 |
|
|
: (GET_CODE (X) == CONST_DOUBLE \
|
| 415 |
|
|
&& GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
|
| 416 |
|
|
? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
|
| 417 |
|
|
? FP_REGS : NO_REGS) \
|
| 418 |
|
|
: (TARGET_PCREL \
|
| 419 |
|
|
&& (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
|
| 420 |
|
|
|| GET_CODE (X) == LABEL_REF)) \
|
| 421 |
|
|
? ADDR_REGS \
|
| 422 |
|
|
: (CLASS))
|
| 423 |
|
|
|
| 424 |
|
|
/* Force QImode output reloads from subregs to be allocated to data regs,
|
| 425 |
|
|
since QImode stores from address regs are not supported. We make the
|
| 426 |
|
|
assumption that if the class is not ADDR_REGS, then it must be a superset
|
| 427 |
|
|
of DATA_REGS. */
|
| 428 |
|
|
#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
|
| 429 |
|
|
(((MODE) == QImode && (CLASS) != ADDR_REGS) \
|
| 430 |
|
|
? DATA_REGS \
|
| 431 |
|
|
: (CLASS))
|
| 432 |
|
|
|
| 433 |
|
|
/* On the m68k, this is the size of MODE in words,
|
| 434 |
|
|
except in the FP regs, where a single reg is always enough. */
|
| 435 |
|
|
#define CLASS_MAX_NREGS(CLASS, MODE) \
|
| 436 |
|
|
((CLASS) == FP_REGS ? 1 \
|
| 437 |
|
|
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
|
| 438 |
|
|
|
| 439 |
|
|
/* Moves between fp regs and other regs are two insns. */
|
| 440 |
|
|
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
|
| 441 |
|
|
(((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
|
| 442 |
|
|
|| ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
|
| 443 |
|
|
? 4 : 2)
|
| 444 |
|
|
|
| 445 |
|
|
/* Stack layout; function entry, exit and calling. */
|
| 446 |
|
|
|
| 447 |
|
|
#define STACK_GROWS_DOWNWARD
|
| 448 |
|
|
#define FRAME_GROWS_DOWNWARD 1
|
| 449 |
|
|
#define STARTING_FRAME_OFFSET 0
|
| 450 |
|
|
|
| 451 |
|
|
/* On the 680x0, sp@- in a byte insn really pushes a word.
|
| 452 |
|
|
On the ColdFire, sp@- in a byte insn pushes just a byte. */
|
| 453 |
|
|
#define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
|
| 454 |
|
|
|
| 455 |
|
|
#define FIRST_PARM_OFFSET(FNDECL) 8
|
| 456 |
|
|
|
| 457 |
|
|
/* On the 68000, the RTS insn cannot pop anything.
|
| 458 |
|
|
On the 68010, the RTD insn may be used to pop them if the number
|
| 459 |
|
|
of args is fixed, but if the number is variable then the caller
|
| 460 |
|
|
must pop them all. RTD can't be used for library calls now
|
| 461 |
|
|
because the library is compiled with the Unix compiler.
|
| 462 |
|
|
Use of RTD is a selectable option, since it is incompatible with
|
| 463 |
|
|
standard Unix calling sequences. If the option is not selected,
|
| 464 |
|
|
the caller must always pop the args. */
|
| 465 |
|
|
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
|
| 466 |
|
|
((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
|
| 467 |
|
|
&& (TYPE_ARG_TYPES (FUNTYPE) == 0 \
|
| 468 |
|
|
|| (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
|
| 469 |
|
|
== void_type_node))) \
|
| 470 |
|
|
? (SIZE) : 0)
|
| 471 |
|
|
|
| 472 |
|
|
/* On the m68k the return value is always in D0. */
|
| 473 |
|
|
#define FUNCTION_VALUE(VALTYPE, FUNC) \
|
| 474 |
|
|
gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
|
| 475 |
|
|
|
| 476 |
|
|
/* On the m68k the return value is always in D0. */
|
| 477 |
|
|
#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
|
| 478 |
|
|
|
| 479 |
|
|
/* On the m68k, D0 is the only register used. */
|
| 480 |
|
|
#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
|
| 481 |
|
|
|
| 482 |
|
|
/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
|
| 483 |
|
|
more than one register.
|
| 484 |
|
|
XXX This macro is m68k specific and used only for m68kemb.h. */
|
| 485 |
|
|
#define NEEDS_UNTYPED_CALL 0
|
| 486 |
|
|
|
| 487 |
|
|
#define PCC_STATIC_STRUCT_RETURN
|
| 488 |
|
|
|
| 489 |
|
|
/* On the m68k, all arguments are usually pushed on the stack. */
|
| 490 |
|
|
#define FUNCTION_ARG_REGNO_P(N) 0
|
| 491 |
|
|
|
| 492 |
|
|
/* On the m68k, this is a single integer, which is a number of bytes
|
| 493 |
|
|
of arguments scanned so far. */
|
| 494 |
|
|
#define CUMULATIVE_ARGS int
|
| 495 |
|
|
|
| 496 |
|
|
/* On the m68k, the offset starts at 0. */
|
| 497 |
|
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
| 498 |
|
|
((CUM) = 0)
|
| 499 |
|
|
|
| 500 |
|
|
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
| 501 |
|
|
((CUM) += ((MODE) != BLKmode \
|
| 502 |
|
|
? (GET_MODE_SIZE (MODE) + 3) & ~3 \
|
| 503 |
|
|
: (int_size_in_bytes (TYPE) + 3) & ~3))
|
| 504 |
|
|
|
| 505 |
|
|
/* On the m68k all args are always pushed. */
|
| 506 |
|
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
|
| 507 |
|
|
|
| 508 |
|
|
#define FUNCTION_PROFILER(FILE, LABELNO) \
|
| 509 |
|
|
asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
|
| 510 |
|
|
|
| 511 |
|
|
#define EXIT_IGNORE_STACK 1
|
| 512 |
|
|
|
| 513 |
|
|
/* Determine if the epilogue should be output as RTL.
|
| 514 |
|
|
You should override this if you define FUNCTION_EXTRA_EPILOGUE.
|
| 515 |
|
|
|
| 516 |
|
|
XXX This macro is m68k-specific and only used in m68k.md. */
|
| 517 |
|
|
#define USE_RETURN_INSN use_return_insn ()
|
| 518 |
|
|
|
| 519 |
|
|
/* Output assembler code for a block containing the constant parts
|
| 520 |
|
|
of a trampoline, leaving space for the variable parts.
|
| 521 |
|
|
|
| 522 |
|
|
On the m68k, the trampoline looks like this:
|
| 523 |
|
|
movl #STATIC,a0
|
| 524 |
|
|
jmp FUNCTION
|
| 525 |
|
|
|
| 526 |
|
|
WARNING: Targets that may run on 68040+ cpus must arrange for
|
| 527 |
|
|
the instruction cache to be flushed. Previous incarnations of
|
| 528 |
|
|
the m68k trampoline code attempted to get around this by either
|
| 529 |
|
|
using an out-of-line transfer function or pc-relative data, but
|
| 530 |
|
|
the fact remains that the code to jump to the transfer function
|
| 531 |
|
|
or the code to load the pc-relative data needs to be flushed
|
| 532 |
|
|
just as much as the "variable" portion of the trampoline.
|
| 533 |
|
|
Recognizing that a cache flush is going to be required anyway,
|
| 534 |
|
|
dispense with such notions and build a smaller trampoline.
|
| 535 |
|
|
|
| 536 |
|
|
Since more instructions are required to move a template into
|
| 537 |
|
|
place than to create it on the spot, don't use a template. */
|
| 538 |
|
|
|
| 539 |
|
|
#define TRAMPOLINE_SIZE 12
|
| 540 |
|
|
#define TRAMPOLINE_ALIGNMENT 16
|
| 541 |
|
|
|
| 542 |
|
|
/* Targets redefine this to invoke code to either flush the cache,
|
| 543 |
|
|
or enable stack execution (or both). */
|
| 544 |
|
|
#ifndef FINALIZE_TRAMPOLINE
|
| 545 |
|
|
#define FINALIZE_TRAMPOLINE(TRAMP)
|
| 546 |
|
|
#endif
|
| 547 |
|
|
|
| 548 |
|
|
/* We generate a two-instructions program at address TRAMP :
|
| 549 |
|
|
movea.l &CXT,%a0
|
| 550 |
|
|
jmp FNADDR */
|
| 551 |
|
|
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
|
| 552 |
|
|
{ \
|
| 553 |
|
|
emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
|
| 554 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
|
| 555 |
|
|
emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
|
| 556 |
|
|
GEN_INT(0x4EF9)); \
|
| 557 |
|
|
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
|
| 558 |
|
|
FINALIZE_TRAMPOLINE(TRAMP); \
|
| 559 |
|
|
}
|
| 560 |
|
|
|
| 561 |
|
|
/* This is the library routine that is used to transfer control from the
|
| 562 |
|
|
trampoline to the actual nested function. It is defined for backward
|
| 563 |
|
|
compatibility, for linking with object code that used the old trampoline
|
| 564 |
|
|
definition.
|
| 565 |
|
|
|
| 566 |
|
|
A colon is used with no explicit operands to cause the template string
|
| 567 |
|
|
to be scanned for %-constructs.
|
| 568 |
|
|
|
| 569 |
|
|
The function name __transfer_from_trampoline is not actually used.
|
| 570 |
|
|
The function definition just permits use of "asm with operands"
|
| 571 |
|
|
(though the operand list is empty). */
|
| 572 |
|
|
#define TRANSFER_FROM_TRAMPOLINE \
|
| 573 |
|
|
void \
|
| 574 |
|
|
__transfer_from_trampoline () \
|
| 575 |
|
|
{ \
|
| 576 |
|
|
register char *a0 asm ("%a0"); \
|
| 577 |
|
|
asm (GLOBAL_ASM_OP "___trampoline"); \
|
| 578 |
|
|
asm ("___trampoline:"); \
|
| 579 |
|
|
asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
|
| 580 |
|
|
asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
|
| 581 |
|
|
asm ("rts":); \
|
| 582 |
|
|
}
|
| 583 |
|
|
|
| 584 |
|
|
/* There are two registers that can always be eliminated on the m68k.
|
| 585 |
|
|
The frame pointer and the arg pointer can be replaced by either the
|
| 586 |
|
|
hard frame pointer or to the stack pointer, depending upon the
|
| 587 |
|
|
circumstances. The hard frame pointer is not used before reload and
|
| 588 |
|
|
so it is not eligible for elimination. */
|
| 589 |
|
|
#define ELIMINABLE_REGS \
|
| 590 |
|
|
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
| 591 |
|
|
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
|
| 592 |
|
|
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
|
| 593 |
|
|
|
| 594 |
|
|
#define CAN_ELIMINATE(FROM, TO) \
|
| 595 |
|
|
((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
|
| 596 |
|
|
|
| 597 |
|
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
| 598 |
|
|
(OFFSET) = m68k_initial_elimination_offset(FROM, TO)
|
| 599 |
|
|
|
| 600 |
|
|
/* Addressing modes, and classification of registers for them. */
|
| 601 |
|
|
|
| 602 |
|
|
#define HAVE_POST_INCREMENT 1
|
| 603 |
|
|
#define HAVE_PRE_DECREMENT 1
|
| 604 |
|
|
|
| 605 |
|
|
/* Macros to check register numbers against specific register classes. */
|
| 606 |
|
|
|
| 607 |
|
|
#define REGNO_OK_FOR_INDEX_P(REGNO) \
|
| 608 |
|
|
((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
|
| 609 |
|
|
#define REGNO_OK_FOR_BASE_P(REGNO) \
|
| 610 |
|
|
(((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
|
| 611 |
|
|
#define REGNO_OK_FOR_DATA_P(REGNO) \
|
| 612 |
|
|
((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
|
| 613 |
|
|
#define REGNO_OK_FOR_FP_P(REGNO) \
|
| 614 |
|
|
(((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
|
| 615 |
|
|
|
| 616 |
|
|
/* Now macros that check whether X is a register and also,
|
| 617 |
|
|
strictly, whether it is in a specified class.
|
| 618 |
|
|
|
| 619 |
|
|
These macros are specific to the m68k, and may be used only
|
| 620 |
|
|
in code for printing assembler insns and in conditions for
|
| 621 |
|
|
define_optimization. */
|
| 622 |
|
|
|
| 623 |
|
|
/* 1 if X is a data register. */
|
| 624 |
|
|
#define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
|
| 625 |
|
|
|
| 626 |
|
|
/* 1 if X is an fp register. */
|
| 627 |
|
|
#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
|
| 628 |
|
|
|
| 629 |
|
|
/* 1 if X is an address register */
|
| 630 |
|
|
#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
|
| 631 |
|
|
|
| 632 |
|
|
|
| 633 |
|
|
#define MAX_REGS_PER_ADDRESS 2
|
| 634 |
|
|
|
| 635 |
|
|
#define CONSTANT_ADDRESS_P(X) \
|
| 636 |
|
|
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|
| 637 |
|
|
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
|
| 638 |
|
|
|| GET_CODE (X) == HIGH)
|
| 639 |
|
|
|
| 640 |
|
|
/* Nonzero if the constant value X is a legitimate general operand.
|
| 641 |
|
|
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
|
| 642 |
|
|
#define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
|
| 643 |
|
|
|
| 644 |
|
|
#ifndef REG_OK_STRICT
|
| 645 |
|
|
#define PCREL_GENERAL_OPERAND_OK 0
|
| 646 |
|
|
#else
|
| 647 |
|
|
#define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
|
| 648 |
|
|
#endif
|
| 649 |
|
|
|
| 650 |
|
|
#define LEGITIMATE_PIC_OPERAND_P(X) \
|
| 651 |
|
|
(! symbolic_operand (X, VOIDmode) \
|
| 652 |
|
|
|| (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
|
| 653 |
|
|
|| PCREL_GENERAL_OPERAND_OK)
|
| 654 |
|
|
|
| 655 |
|
|
#ifndef REG_OK_STRICT
|
| 656 |
|
|
|
| 657 |
|
|
/* Nonzero if X is a hard reg that can be used as an index
|
| 658 |
|
|
or if it is a pseudo reg. */
|
| 659 |
|
|
#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
|
| 660 |
|
|
/* Nonzero if X is a hard reg that can be used as a base reg
|
| 661 |
|
|
or if it is a pseudo reg. */
|
| 662 |
|
|
#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
|
| 663 |
|
|
|
| 664 |
|
|
#else
|
| 665 |
|
|
|
| 666 |
|
|
/* Nonzero if X is a hard reg that can be used as an index. */
|
| 667 |
|
|
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
|
| 668 |
|
|
/* Nonzero if X is a hard reg that can be used as a base reg. */
|
| 669 |
|
|
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
|
| 670 |
|
|
|
| 671 |
|
|
#endif
|
| 672 |
|
|
|
| 673 |
|
|
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
|
| 674 |
|
|
that is a valid memory address for an instruction.
|
| 675 |
|
|
The MODE argument is the machine mode for the MEM expression
|
| 676 |
|
|
that wants to use this address.
|
| 677 |
|
|
|
| 678 |
|
|
When generating PIC, an address involving a SYMBOL_REF is legitimate
|
| 679 |
|
|
if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
|
| 680 |
|
|
We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
|
| 681 |
|
|
and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
|
| 682 |
|
|
|
| 683 |
|
|
Likewise for a LABEL_REF when generating PIC.
|
| 684 |
|
|
|
| 685 |
|
|
The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
|
| 686 |
|
|
|
| 687 |
|
|
/* Allow SUBREG everywhere we allow REG. This results in better code. It
|
| 688 |
|
|
also makes function inlining work when inline functions are called with
|
| 689 |
|
|
arguments that are SUBREGs. */
|
| 690 |
|
|
|
| 691 |
|
|
#define LEGITIMATE_BASE_REG_P(X) \
|
| 692 |
|
|
((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
|
| 693 |
|
|
|| (GET_CODE (X) == SUBREG \
|
| 694 |
|
|
&& GET_CODE (SUBREG_REG (X)) == REG \
|
| 695 |
|
|
&& REG_OK_FOR_BASE_P (SUBREG_REG (X))))
|
| 696 |
|
|
|
| 697 |
|
|
#define INDIRECTABLE_1_ADDRESS_P(X) \
|
| 698 |
|
|
((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
|
| 699 |
|
|
|| LEGITIMATE_BASE_REG_P (X) \
|
| 700 |
|
|
|| ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
|
| 701 |
|
|
&& LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
|
| 702 |
|
|
|| (GET_CODE (X) == PLUS \
|
| 703 |
|
|
&& LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
|
| 704 |
|
|
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
|
| 705 |
|
|
&& (TARGET_68020 \
|
| 706 |
|
|
|| ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
|
| 707 |
|
|
|| (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
|
| 708 |
|
|
&& flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
|
| 709 |
|
|
|| (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
|
| 710 |
|
|
&& flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
|
| 711 |
|
|
|
| 712 |
|
|
#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
|
| 713 |
|
|
{ if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
|
| 714 |
|
|
|
| 715 |
|
|
/* Only labels on dispatch tables are valid for indexing from. */
|
| 716 |
|
|
#define GO_IF_INDEXABLE_BASE(X, ADDR) \
|
| 717 |
|
|
{ rtx temp; \
|
| 718 |
|
|
if (GET_CODE (X) == LABEL_REF \
|
| 719 |
|
|
&& (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
|
| 720 |
|
|
&& GET_CODE (temp) == JUMP_INSN \
|
| 721 |
|
|
&& (GET_CODE (PATTERN (temp)) == ADDR_VEC \
|
| 722 |
|
|
|| GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
|
| 723 |
|
|
goto ADDR; \
|
| 724 |
|
|
if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
|
| 725 |
|
|
|
| 726 |
|
|
#define GO_IF_INDEXING(X, ADDR) \
|
| 727 |
|
|
{ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
|
| 728 |
|
|
{ GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
|
| 729 |
|
|
if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
|
| 730 |
|
|
{ GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
|
| 731 |
|
|
|
| 732 |
|
|
#define GO_IF_INDEXED_ADDRESS(X, ADDR) \
|
| 733 |
|
|
{ GO_IF_INDEXING (X, ADDR); \
|
| 734 |
|
|
if (GET_CODE (X) == PLUS) \
|
| 735 |
|
|
{ if (GET_CODE (XEXP (X, 1)) == CONST_INT \
|
| 736 |
|
|
&& (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
|
| 737 |
|
|
{ rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
|
| 738 |
|
|
if (GET_CODE (XEXP (X, 0)) == CONST_INT \
|
| 739 |
|
|
&& (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
|
| 740 |
|
|
{ rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
|
| 741 |
|
|
|
| 742 |
|
|
/* ColdFire/5200 does not allow HImode index registers. */
|
| 743 |
|
|
#define LEGITIMATE_INDEX_REG_P(X) \
|
| 744 |
|
|
((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
|
| 745 |
|
|
|| (! TARGET_COLDFIRE \
|
| 746 |
|
|
&& GET_CODE (X) == SIGN_EXTEND \
|
| 747 |
|
|
&& GET_CODE (XEXP (X, 0)) == REG \
|
| 748 |
|
|
&& GET_MODE (XEXP (X, 0)) == HImode \
|
| 749 |
|
|
&& REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
|
| 750 |
|
|
|| (GET_CODE (X) == SUBREG \
|
| 751 |
|
|
&& GET_CODE (SUBREG_REG (X)) == REG \
|
| 752 |
|
|
&& REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
|
| 753 |
|
|
|
| 754 |
|
|
#define LEGITIMATE_INDEX_P(X) \
|
| 755 |
|
|
(LEGITIMATE_INDEX_REG_P (X) \
|
| 756 |
|
|
|| ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
|
| 757 |
|
|
&& LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
|
| 758 |
|
|
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
|
| 759 |
|
|
&& (INTVAL (XEXP (X, 1)) == 2 \
|
| 760 |
|
|
|| INTVAL (XEXP (X, 1)) == 4 \
|
| 761 |
|
|
|| (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
|
| 762 |
|
|
|
| 763 |
|
|
/* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
|
| 764 |
|
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
| 765 |
|
|
{ GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
|
| 766 |
|
|
GO_IF_INDEXED_ADDRESS (X, ADDR); \
|
| 767 |
|
|
if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
|
| 768 |
|
|
&& LEGITIMATE_INDEX_P (XEXP (X, 0)) \
|
| 769 |
|
|
&& GET_CODE (XEXP (X, 1)) == LABEL_REF) \
|
| 770 |
|
|
goto ADDR; }
|
| 771 |
|
|
|
| 772 |
|
|
/* Don't call memory_address_noforce for the address to fetch
|
| 773 |
|
|
the switch offset. This address is ok as it stands (see above),
|
| 774 |
|
|
but memory_address_noforce would alter it. */
|
| 775 |
|
|
#define PIC_CASE_VECTOR_ADDRESS(index) index
|
| 776 |
|
|
|
| 777 |
|
|
/* For the 68000, we handle X+REG by loading X into a register R and
|
| 778 |
|
|
using R+REG. R will go in an address reg and indexing will be used.
|
| 779 |
|
|
However, if REG is a broken-out memory address or multiplication,
|
| 780 |
|
|
nothing needs to be done because REG can certainly go in an address reg. */
|
| 781 |
|
|
#define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
|
| 782 |
|
|
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
|
| 783 |
|
|
{ register int ch = (X) != (OLDX); \
|
| 784 |
|
|
if (GET_CODE (X) == PLUS) \
|
| 785 |
|
|
{ int copied = 0; \
|
| 786 |
|
|
if (GET_CODE (XEXP (X, 0)) == MULT) \
|
| 787 |
|
|
{ COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
|
| 788 |
|
|
if (GET_CODE (XEXP (X, 1)) == MULT) \
|
| 789 |
|
|
{ COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
|
| 790 |
|
|
if (ch && GET_CODE (XEXP (X, 1)) == REG \
|
| 791 |
|
|
&& GET_CODE (XEXP (X, 0)) == REG) \
|
| 792 |
|
|
goto WIN; \
|
| 793 |
|
|
if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
|
| 794 |
|
|
if (GET_CODE (XEXP (X, 0)) == REG \
|
| 795 |
|
|
|| (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
|
| 796 |
|
|
&& GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
|
| 797 |
|
|
&& GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
|
| 798 |
|
|
{ register rtx temp = gen_reg_rtx (Pmode); \
|
| 799 |
|
|
register rtx val = force_operand (XEXP (X, 1), 0); \
|
| 800 |
|
|
emit_move_insn (temp, val); \
|
| 801 |
|
|
COPY_ONCE (X); \
|
| 802 |
|
|
XEXP (X, 1) = temp; \
|
| 803 |
|
|
goto WIN; } \
|
| 804 |
|
|
else if (GET_CODE (XEXP (X, 1)) == REG \
|
| 805 |
|
|
|| (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
|
| 806 |
|
|
&& GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
|
| 807 |
|
|
&& GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
|
| 808 |
|
|
{ register rtx temp = gen_reg_rtx (Pmode); \
|
| 809 |
|
|
register rtx val = force_operand (XEXP (X, 0), 0); \
|
| 810 |
|
|
emit_move_insn (temp, val); \
|
| 811 |
|
|
COPY_ONCE (X); \
|
| 812 |
|
|
XEXP (X, 0) = temp; \
|
| 813 |
|
|
goto WIN; }}}
|
| 814 |
|
|
|
| 815 |
|
|
/* On the 68000, only predecrement and postincrement address depend thus
|
| 816 |
|
|
(the amount of decrement or increment being the length of the operand). */
|
| 817 |
|
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
|
| 818 |
|
|
if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
|
| 819 |
|
|
|
| 820 |
|
|
#define CASE_VECTOR_MODE HImode
|
| 821 |
|
|
#define CASE_VECTOR_PC_RELATIVE 1
|
| 822 |
|
|
|
| 823 |
|
|
#define DEFAULT_SIGNED_CHAR 1
|
| 824 |
|
|
#define MOVE_MAX 4
|
| 825 |
|
|
#define SLOW_BYTE_ACCESS 0
|
| 826 |
|
|
|
| 827 |
|
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
| 828 |
|
|
|
| 829 |
|
|
#define STORE_FLAG_VALUE (-1)
|
| 830 |
|
|
|
| 831 |
|
|
#define Pmode SImode
|
| 832 |
|
|
#define FUNCTION_MODE QImode
|
| 833 |
|
|
|
| 834 |
|
|
|
| 835 |
|
|
/* Tell final.c how to eliminate redundant test instructions. */
|
| 836 |
|
|
|
| 837 |
|
|
/* Here we define machine-dependent flags and fields in cc_status
|
| 838 |
|
|
(see `conditions.h'). */
|
| 839 |
|
|
|
| 840 |
|
|
/* Set if the cc value is actually in the 68881, so a floating point
|
| 841 |
|
|
conditional branch must be output. */
|
| 842 |
|
|
#define CC_IN_68881 04000
|
| 843 |
|
|
|
| 844 |
|
|
/* On the 68000, all the insns to store in an address register fail to
|
| 845 |
|
|
set the cc's. However, in some cases these instructions can make it
|
| 846 |
|
|
possibly invalid to use the saved cc's. In those cases we clear out
|
| 847 |
|
|
some or all of the saved cc's so they won't be used. */
|
| 848 |
|
|
#define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
|
| 849 |
|
|
|
| 850 |
|
|
#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
|
| 851 |
|
|
do { if (cc_prev_status.flags & CC_IN_68881) \
|
| 852 |
|
|
return FLOAT; \
|
| 853 |
|
|
if (cc_prev_status.flags & CC_NO_OVERFLOW) \
|
| 854 |
|
|
return NO_OV; \
|
| 855 |
|
|
return NORMAL; } while (0)
|
| 856 |
|
|
|
| 857 |
|
|
/* Control the assembler format that we output. */
|
| 858 |
|
|
|
| 859 |
|
|
#define ASM_APP_ON "#APP\n"
|
| 860 |
|
|
#define ASM_APP_OFF "#NO_APP\n"
|
| 861 |
|
|
#define TEXT_SECTION_ASM_OP "\t.text"
|
| 862 |
|
|
#define DATA_SECTION_ASM_OP "\t.data"
|
| 863 |
|
|
#define GLOBAL_ASM_OP "\t.globl\t"
|
| 864 |
|
|
#define REGISTER_PREFIX ""
|
| 865 |
|
|
#define LOCAL_LABEL_PREFIX ""
|
| 866 |
|
|
#define USER_LABEL_PREFIX "_"
|
| 867 |
|
|
#define IMMEDIATE_PREFIX "#"
|
| 868 |
|
|
|
| 869 |
|
|
#define REGISTER_NAMES \
|
| 870 |
|
|
{REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
|
| 871 |
|
|
REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
|
| 872 |
|
|
REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
|
| 873 |
|
|
REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
|
| 874 |
|
|
REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
|
| 875 |
|
|
REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
|
| 876 |
|
|
REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
|
| 877 |
|
|
REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
|
| 878 |
|
|
REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
|
| 879 |
|
|
|
| 880 |
|
|
#define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
|
| 881 |
|
|
|
| 882 |
|
|
/* Return a register name by index, handling %fp nicely.
|
| 883 |
|
|
We don't replace %fp for targets that don't map it to %a6
|
| 884 |
|
|
since it may confuse GAS. */
|
| 885 |
|
|
#define M68K_REGNAME(r) ( \
|
| 886 |
|
|
((FRAME_POINTER_REGNUM == 14) \
|
| 887 |
|
|
&& ((r) == FRAME_POINTER_REGNUM) \
|
| 888 |
|
|
&& frame_pointer_needed) ? \
|
| 889 |
|
|
M68K_FP_REG_NAME : reg_names[(r)])
|
| 890 |
|
|
|
| 891 |
|
|
/* On the Sun-3, the floating point registers have numbers
|
| 892 |
|
|
18 to 25, not 16 to 23 as they do in the compiler. */
|
| 893 |
|
|
#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
|
| 894 |
|
|
|
| 895 |
|
|
/* Before the prologue, RA is at 0(%sp). */
|
| 896 |
|
|
#define INCOMING_RETURN_ADDR_RTX \
|
| 897 |
|
|
gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
|
| 898 |
|
|
|
| 899 |
|
|
/* We must not use the DBX register numbers for the DWARF 2 CFA column
|
| 900 |
|
|
numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
|
| 901 |
|
|
Instead use the identity mapping. */
|
| 902 |
|
|
#define DWARF_FRAME_REGNUM(REG) REG
|
| 903 |
|
|
|
| 904 |
|
|
/* Before the prologue, the top of the frame is at 4(%sp). */
|
| 905 |
|
|
#define INCOMING_FRAME_SP_OFFSET 4
|
| 906 |
|
|
|
| 907 |
|
|
/* Describe how we implement __builtin_eh_return. */
|
| 908 |
|
|
#define EH_RETURN_DATA_REGNO(N) \
|
| 909 |
|
|
((N) < 2 ? (N) : INVALID_REGNUM)
|
| 910 |
|
|
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
|
| 911 |
|
|
#define EH_RETURN_HANDLER_RTX \
|
| 912 |
|
|
gen_rtx_MEM (Pmode, \
|
| 913 |
|
|
gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
|
| 914 |
|
|
plus_constant (EH_RETURN_STACKADJ_RTX, \
|
| 915 |
|
|
UNITS_PER_WORD)))
|
| 916 |
|
|
|
| 917 |
|
|
/* Select a format to encode pointers in exception handling data. CODE
|
| 918 |
|
|
is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
|
| 919 |
|
|
true if the symbol may be affected by dynamic relocations. */
|
| 920 |
|
|
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
|
| 921 |
|
|
(flag_pic \
|
| 922 |
|
|
? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
|
| 923 |
|
|
: DW_EH_PE_absptr)
|
| 924 |
|
|
|
| 925 |
|
|
#define ASM_OUTPUT_LABELREF(FILE,NAME) \
|
| 926 |
|
|
asm_fprintf (FILE, "%U%s", NAME)
|
| 927 |
|
|
|
| 928 |
|
|
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
|
| 929 |
|
|
sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
|
| 930 |
|
|
|
| 931 |
|
|
#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
|
| 932 |
|
|
asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
|
| 933 |
|
|
#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
|
| 934 |
|
|
asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
|
| 935 |
|
|
|
| 936 |
|
|
/* The m68k does not use absolute case-vectors, but we must define this macro
|
| 937 |
|
|
anyway. */
|
| 938 |
|
|
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
| 939 |
|
|
asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
|
| 940 |
|
|
|
| 941 |
|
|
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
| 942 |
|
|
asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
|
| 943 |
|
|
|
| 944 |
|
|
/* We don't have a way to align to more than a two-byte boundary, so do the
|
| 945 |
|
|
best we can and don't complain. */
|
| 946 |
|
|
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
|
| 947 |
|
|
if ((LOG) >= 1) \
|
| 948 |
|
|
fprintf (FILE, "\t.even\n");
|
| 949 |
|
|
|
| 950 |
|
|
#define ASM_OUTPUT_SKIP(FILE,SIZE) \
|
| 951 |
|
|
fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
|
| 952 |
|
|
|
| 953 |
|
|
#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
|
| 954 |
|
|
( fputs (".comm ", (FILE)), \
|
| 955 |
|
|
assemble_name ((FILE), (NAME)), \
|
| 956 |
|
|
fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
|
| 957 |
|
|
|
| 958 |
|
|
#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
|
| 959 |
|
|
( fputs (".lcomm ", (FILE)), \
|
| 960 |
|
|
assemble_name ((FILE), (NAME)), \
|
| 961 |
|
|
fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
|
| 962 |
|
|
|
| 963 |
|
|
/* Output a float value (represented as a C double) as an immediate operand.
|
| 964 |
|
|
This macro is m68k-specific. */
|
| 965 |
|
|
#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
|
| 966 |
|
|
do { \
|
| 967 |
|
|
if (CODE == 'f') \
|
| 968 |
|
|
{ \
|
| 969 |
|
|
char dstr[30]; \
|
| 970 |
|
|
real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
|
| 971 |
|
|
asm_fprintf ((FILE), "%I0r%s", dstr); \
|
| 972 |
|
|
} \
|
| 973 |
|
|
else \
|
| 974 |
|
|
{ \
|
| 975 |
|
|
long l; \
|
| 976 |
|
|
REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
|
| 977 |
|
|
asm_fprintf ((FILE), "%I0x%lx", l); \
|
| 978 |
|
|
} \
|
| 979 |
|
|
} while (0)
|
| 980 |
|
|
|
| 981 |
|
|
/* Output a double value (represented as a C double) as an immediate operand.
|
| 982 |
|
|
This macro is m68k-specific. */
|
| 983 |
|
|
#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
|
| 984 |
|
|
do { char dstr[30]; \
|
| 985 |
|
|
real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
|
| 986 |
|
|
asm_fprintf (FILE, "%I0r%s", dstr); \
|
| 987 |
|
|
} while (0)
|
| 988 |
|
|
|
| 989 |
|
|
/* Note, long double immediate operands are not actually
|
| 990 |
|
|
generated by m68k.md. */
|
| 991 |
|
|
#define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
|
| 992 |
|
|
do { char dstr[30]; \
|
| 993 |
|
|
real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
|
| 994 |
|
|
asm_fprintf (FILE, "%I0r%s", dstr); \
|
| 995 |
|
|
} while (0)
|
| 996 |
|
|
|
| 997 |
|
|
/* On the 68000, we use several CODE characters:
|
| 998 |
|
|
'.' for dot needed in Motorola-style opcode names.
|
| 999 |
|
|
'-' for an operand pushing on the stack:
|
| 1000 |
|
|
sp@-, -(sp) or -(%sp) depending on the style of syntax.
|
| 1001 |
|
|
'+' for an operand pushing on the stack:
|
| 1002 |
|
|
sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
|
| 1003 |
|
|
'@' for a reference to the top word on the stack:
|
| 1004 |
|
|
sp@, (sp) or (%sp) depending on the style of syntax.
|
| 1005 |
|
|
'#' for an immediate operand prefix (# in MIT and Motorola syntax
|
| 1006 |
|
|
but & in SGS syntax).
|
| 1007 |
|
|
'!' for the fpcr register (used in some float-to-fixed conversions).
|
| 1008 |
|
|
'$' for the letter `s' in an op code, but only on the 68040.
|
| 1009 |
|
|
'&' for the letter `d' in an op code, but only on the 68040.
|
| 1010 |
|
|
'/' for register prefix needed by longlong.h.
|
| 1011 |
|
|
|
| 1012 |
|
|
'b' for byte insn (no effect, on the Sun; this is for the ISI).
|
| 1013 |
|
|
'd' to force memory addressing to be absolute, not relative.
|
| 1014 |
|
|
'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
|
| 1015 |
|
|
'o' for operands to go directly to output_operand_address (bypassing
|
| 1016 |
|
|
print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
|
| 1017 |
|
|
'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
|
| 1018 |
|
|
or print pair of registers as rx:ry. */
|
| 1019 |
|
|
|
| 1020 |
|
|
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
|
| 1021 |
|
|
((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
|
| 1022 |
|
|
|| (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
|
| 1023 |
|
|
|| (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
|
| 1024 |
|
|
|
| 1025 |
|
|
|
| 1026 |
|
|
/* See m68k.c for the m68k specific codes. */
|
| 1027 |
|
|
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
|
| 1028 |
|
|
|
| 1029 |
|
|
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
|
| 1030 |
|
|
|
| 1031 |
|
|
/* Variables in m68k.c */
|
| 1032 |
|
|
extern const char *m68k_library_id_string;
|
| 1033 |
|
|
extern int m68k_last_compare_had_fp_operands;
|
