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;;  Mips.md          Machine Description for MIPS based processors

;;  Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,

;;  1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.

;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr

;;  Changes by       Michael Meissner, meissner@osf.org

;;  64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and

;;  Brendan Eich, brendan@microunity.com.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify

;; it under the terms of the GNU General Public License as published by

;; the Free Software Foundation; either version 2, or (at your option)

;; any later version.

;; GCC is distributed in the hope that it will be useful,

;; but WITHOUT ANY WARRANTY; without even the implied warranty of

;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License

;; along with GCC; see the file COPYING.  If not, write to

;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,

;; Boston, MA 02110-1301, USA.

(define_constants

  [(UNSPEC_LOAD_DF_LOW           0)

   (UNSPEC_LOAD_DF_HIGH          1)

   (UNSPEC_STORE_DF_HIGH         2)

   (UNSPEC_GET_FNADDR            3)

   (UNSPEC_BLOCKAGE              4)

   (UNSPEC_CPRESTORE             5)

   (UNSPEC_EH_RECEIVER           6)

   (UNSPEC_EH_RETURN             7)

   (UNSPEC_CONSTTABLE_INT        8)

   (UNSPEC_CONSTTABLE_FLOAT      9)

   (UNSPEC_ALIGN                14)

   (UNSPEC_HIGH                 17)

   (UNSPEC_LOAD_LEFT            18)

   (UNSPEC_LOAD_RIGHT           19)

   (UNSPEC_STORE_LEFT           20)

   (UNSPEC_STORE_RIGHT          21)

   (UNSPEC_LOADGP               22)

   (UNSPEC_LOAD_CALL            23)

   (UNSPEC_LOAD_GOT             24)

   (UNSPEC_GP                   25)

   (UNSPEC_MFHILO               26)

   (UNSPEC_TLS_LDM              27)

   (UNSPEC_TLS_GET_TP           28)

   (UNSPEC_ADDRESS_FIRST        100)

   (FAKE_CALL_REGNO             79)

   ;; For MIPS Paired-Singled Floating Point Instructions.

   (UNSPEC_MOVE_TF_PS           200)

   (UNSPEC_C                    201)

   ;; MIPS64/MIPS32R2 alnv.ps

   (UNSPEC_ALNV_PS              202)

   ;; MIPS-3D instructions

   (UNSPEC_CABS                 203)

   (UNSPEC_ADDR_PS              204)

   (UNSPEC_CVT_PW_PS            205)

   (UNSPEC_CVT_PS_PW            206)

   (UNSPEC_MULR_PS              207)

   (UNSPEC_RSQRT1               208)

   (UNSPEC_RSQRT2               209)

   (UNSPEC_RECIP1               210)

   (UNSPEC_RECIP2               211)

   ;; MIPS DSP ASE Revision 0.98 3/24/2005

   (UNSPEC_ADDQ                 300)

   (UNSPEC_ADDQ_S               301)

   (UNSPEC_SUBQ                 302)

   (UNSPEC_SUBQ_S               303)

   (UNSPEC_ADDSC                304)

   (UNSPEC_ADDWC                305)

   (UNSPEC_MODSUB               306)

   (UNSPEC_RADDU_W_QB           307)

   (UNSPEC_ABSQ_S               308)

   (UNSPEC_PRECRQ_QB_PH         309)

   (UNSPEC_PRECRQ_PH_W          310)

   (UNSPEC_PRECRQ_RS_PH_W       311)

   (UNSPEC_PRECRQU_S_QB_PH      312)

   (UNSPEC_PRECEQ_W_PHL         313)

   (UNSPEC_PRECEQ_W_PHR         314)

   (UNSPEC_PRECEQU_PH_QBL       315)

   (UNSPEC_PRECEQU_PH_QBR       316)

   (UNSPEC_PRECEQU_PH_QBLA      317)

   (UNSPEC_PRECEQU_PH_QBRA      318)

   (UNSPEC_PRECEU_PH_QBL        319)

   (UNSPEC_PRECEU_PH_QBR        320)

   (UNSPEC_PRECEU_PH_QBLA       321)

   (UNSPEC_PRECEU_PH_QBRA       322)

   (UNSPEC_SHLL                 323)

   (UNSPEC_SHLL_S               324)

   (UNSPEC_SHRL_QB              325)

   (UNSPEC_SHRA_PH              326)

   (UNSPEC_SHRA_R               327)

   (UNSPEC_MULEU_S_PH_QBL       328)

   (UNSPEC_MULEU_S_PH_QBR       329)

   (UNSPEC_MULQ_RS_PH           330)

   (UNSPEC_MULEQ_S_W_PHL        331)

   (UNSPEC_MULEQ_S_W_PHR        332)

   (UNSPEC_DPAU_H_QBL           333)

   (UNSPEC_DPAU_H_QBR           334)

   (UNSPEC_DPSU_H_QBL           335)

   (UNSPEC_DPSU_H_QBR           336)

   (UNSPEC_DPAQ_S_W_PH          337)

   (UNSPEC_DPSQ_S_W_PH          338)

   (UNSPEC_MULSAQ_S_W_PH        339)

   (UNSPEC_DPAQ_SA_L_W          340)

   (UNSPEC_DPSQ_SA_L_W          341)

   (UNSPEC_MAQ_S_W_PHL          342)

   (UNSPEC_MAQ_S_W_PHR          343)

   (UNSPEC_MAQ_SA_W_PHL         344)

   (UNSPEC_MAQ_SA_W_PHR         345)

   (UNSPEC_BITREV               346)

   (UNSPEC_INSV                 347)

   (UNSPEC_REPL_QB              348)

   (UNSPEC_REPL_PH              349)

   (UNSPEC_CMP_EQ               350)

   (UNSPEC_CMP_LT               351)

   (UNSPEC_CMP_LE               352)

   (UNSPEC_CMPGU_EQ_QB          353)

   (UNSPEC_CMPGU_LT_QB          354)

   (UNSPEC_CMPGU_LE_QB          355)

   (UNSPEC_PICK                 356)

   (UNSPEC_PACKRL_PH            357)

   (UNSPEC_EXTR_W               358)

   (UNSPEC_EXTR_R_W             359)

   (UNSPEC_EXTR_RS_W            360)

   (UNSPEC_EXTR_S_H             361)

   (UNSPEC_EXTP                 362)

   (UNSPEC_EXTPDP               363)

   (UNSPEC_SHILO                364)

   (UNSPEC_MTHLIP               365)

   (UNSPEC_WRDSP                366)

   (UNSPEC_RDDSP                367)

  ]

)

(include "predicates.md")

;; ....................

;;

;;      Attributes

;;

;; ....................

(define_attr "got" "unset,xgot_high,load"

  (const_string "unset"))

;; For jal instructions, this attribute is DIRECT when the target address

;; is symbolic and INDIRECT when it is a register.

(define_attr "jal" "unset,direct,indirect"

  (const_string "unset"))

;; This attribute is YES if the instruction is a jal macro (not a

;; real jal instruction).

;;

;; jal is always a macro in SVR4 PIC since it includes an instruction to

;; restore $gp.  Direct jals are also macros in NewABI PIC since they

;; load the target address into $25.

(define_attr "jal_macro" "no,yes"

  (cond [(eq_attr "jal" "direct")

         (symbol_ref "TARGET_ABICALLS != 0")

         (eq_attr "jal" "indirect")

         (symbol_ref "(TARGET_ABICALLS && !TARGET_NEWABI) != 0")]

        (const_string "no")))

;; Classification of each insn.

;; branch       conditional branch

;; jump         unconditional jump

;; call         unconditional call

;; load         load instruction(s)

;; fpload       floating point load

;; fpidxload    floating point indexed load

;; store        store instruction(s)

;; fpstore      floating point store

;; fpidxstore   floating point indexed store

;; prefetch     memory prefetch (register + offset)

;; prefetchx    memory indexed prefetch (register + register)

;; condmove     conditional moves

;; xfer         transfer to/from coprocessor

;; mthilo       transfer to hi/lo registers

;; mfhilo       transfer from hi/lo registers

;; const        load constant

;; arith        integer arithmetic and logical instructions

;; shift        integer shift instructions

;; slt          set less than instructions

;; clz          the clz and clo instructions

;; trap         trap if instructions

;; imul         integer multiply 2 operands

;; imul3        integer multiply 3 operands

;; imadd        integer multiply-add

;; idiv         integer divide

;; fmove        floating point register move

;; fadd         floating point add/subtract

;; fmul         floating point multiply

;; fmadd        floating point multiply-add

;; fdiv         floating point divide

;; frdiv        floating point reciprocal divide

;; frdiv1       floating point reciprocal divide step 1

;; frdiv2       floating point reciprocal divide step 2

;; fabs         floating point absolute value

;; fneg         floating point negation

;; fcmp         floating point compare

;; fcvt         floating point convert

;; fsqrt        floating point square root

;; frsqrt       floating point reciprocal square root

;; frsqrt1      floating point reciprocal square root step1

;; frsqrt2      floating point reciprocal square root step2

;; multi        multiword sequence (or user asm statements)

;; nop          no operation

(define_attr "type"

  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"

  (cond [(eq_attr "jal" "!unset") (const_string "call")

         (eq_attr "got" "load") (const_string "load")]

        (const_string "unknown")))

;; Main data type used by the insn

(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"

  (const_string "unknown"))

;; Mode for conversion types (fcvt)

;; I2S          integer to float single (SI/DI to SF)

;; I2D          integer to float double (SI/DI to DF)

;; S2I          float to integer (SF to SI/DI)

;; D2I          float to integer (DF to SI/DI)

;; D2S          double to float single

;; S2D          float single to double

(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"

  (const_string "unknown"))

;; Is this an extended instruction in mips16 mode?

(define_attr "extended_mips16" "no,yes"

  (const_string "no"))

;; Length of instruction in bytes.

(define_attr "length" ""

   (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].

          ;; If a branch is outside this range, we have a choice of two

          ;; sequences.  For PIC, an out-of-range branch like:

          ;;

          ;;    bne     r1,r2,target

          ;;    dslot

          ;;

          ;; becomes the equivalent of:

          ;;

          ;;    beq     r1,r2,1f

          ;;    dslot

          ;;    la      $at,target

          ;;    jr      $at

          ;;    nop

          ;; 1:

          ;;

          ;; where the load address can be up to three instructions long

          ;; (lw, nop, addiu).

          ;;

          ;; The non-PIC case is similar except that we use a direct

          ;; jump instead of an la/jr pair.  Since the target of this

          ;; jump is an absolute 28-bit bit address (the other bits

          ;; coming from the address of the delay slot) this form cannot

          ;; cross a 256MB boundary.  We could provide the option of

          ;; using la/jr in this case too, but we do not do so at

          ;; present.

          ;;

          ;; Note that this value does not account for the delay slot

          ;; instruction, whose length is added separately.  If the RTL

          ;; pattern has no explicit delay slot, mips_adjust_insn_length

          ;; will add the length of the implicit nop.  The values for

          ;; forward and backward branches will be different as well.

          (eq_attr "type" "branch")

          (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))

                      (le (minus (pc) (match_dup 1)) (const_int 131068)))

                  (const_int 4)

                 (ne (symbol_ref "flag_pic") (const_int 0))

                 (const_int 24)

                 ] (const_int 12))

          (eq_attr "got" "load")

          (const_int 4)

          (eq_attr "got" "xgot_high")

          (const_int 8)

          (eq_attr "type" "const")

          (symbol_ref "mips_const_insns (operands[1]) * 4")

          (eq_attr "type" "load,fpload")

          (symbol_ref "mips_fetch_insns (operands[1]) * 4")

          (eq_attr "type" "store,fpstore")

          (symbol_ref "mips_fetch_insns (operands[0]) * 4")

          ;; In the worst case, a call macro will take 8 instructions:

          ;;

          ;;     lui $25,%call_hi(FOO)

          ;;     addu $25,$25,$28

          ;;     lw $25,%call_lo(FOO)($25)

          ;;     nop

          ;;     jalr $25

          ;;     nop

          ;;     lw $gp,X($sp)

          ;;     nop

          (eq_attr "jal_macro" "yes")

          (const_int 32)

          (and (eq_attr "extended_mips16" "yes")

               (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))

          (const_int 8)

          ;; Various VR4120 errata require a nop to be inserted after a macc

          ;; instruction.  The assembler does this for us, so account for

          ;; the worst-case length here.

          (and (eq_attr "type" "imadd")

               (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))

          (const_int 8)

          ;; VR4120 errata MD(4): if there are consecutive dmult instructions,

          ;; the result of the second one is missed.  The assembler should work

          ;; around this by inserting a nop after the first dmult.

          (and (eq_attr "type" "imul,imul3")

               (and (eq_attr "mode" "DI")

                    (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))

          (const_int 8)

          (eq_attr "type" "idiv")

          (symbol_ref "mips_idiv_insns () * 4")

          ] (const_int 4)))

;; Attribute describing the processor.  This attribute must match exactly

;; with the processor_type enumeration in mips.h.

(define_attr "cpu"

  "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"

  (const (symbol_ref "mips_tune")))

;; The type of hardware hazard associated with this instruction.

;; DELAY means that the next instruction cannot read the result

;; of this one.  HILO means that the next two instructions cannot

;; write to HI or LO.

(define_attr "hazard" "none,delay,hilo"

  (cond [(and (eq_attr "type" "load,fpload,fpidxload")

              (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))

         (const_string "delay")

         (and (eq_attr "type" "xfer")

              (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))

         (const_string "delay")

         (and (eq_attr "type" "fcmp")

              (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))

         (const_string "delay")

         ;; The r4000 multiplication patterns include an mflo instruction.

         (and (eq_attr "type" "imul")

              (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))

         (const_string "hilo")

         (and (eq_attr "type" "mfhilo")

              (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))

         (const_string "hilo")]

        (const_string "none")))

;; Is it a single instruction?

(define_attr "single_insn" "no,yes"

  (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))

;; Can the instruction be put into a delay slot?

(define_attr "can_delay" "no,yes"

  (if_then_else (and (eq_attr "type" "!branch,call,jump")

                     (and (eq_attr "hazard" "none")

                          (eq_attr "single_insn" "yes")))

                (const_string "yes")

                (const_string "no")))

;; Attribute defining whether or not we can use the branch-likely instructions

(define_attr "branch_likely" "no,yes"

  (const

   (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))

                 (const_string "yes")

                 (const_string "no"))))

;; True if an instruction might assign to hi or lo when reloaded.

;; This is used by the TUNE_MACC_CHAINS code.

(define_attr "may_clobber_hilo" "no,yes"

  (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")

                (const_string "yes")

                (const_string "no")))

;; Describe a user's asm statement.

(define_asm_attributes

  [(set_attr "type" "multi")

   (set_attr "can_delay" "no")])

;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated

;; from the same template.

(define_mode_macro GPR [SI (DI "TARGET_64BIT")])

;; This mode macro allows :P to be used for patterns that operate on

;; pointer-sized quantities.  Exactly one of the two alternatives will match.

(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])

;; This mode macro allows :MOVECC to be used anywhere that a

;; conditional-move-type condition is needed.

(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])

;; This mode macro allows the QI and HI extension patterns to be defined from

;; the same template.

(define_mode_macro SHORT [QI HI])

;; This mode macro allows :ANYF to be used wherever a scalar or vector

;; floating-point mode is allowed.

(define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")

                         (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")

                         (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])

;; Like ANYF, but only applies to scalar modes.

(define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")

                            (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])

;; In GPR templates, a string like "subu" will expand to "subu" in the

;; 32-bit version and "dsubu" in the 64-bit version.

(define_mode_attr d [(SI "") (DI "d")])

;; This attribute gives the length suffix for a sign- or zero-extension

;; instruction.

(define_mode_attr size [(QI "b") (HI "h")])

;; This attributes gives the mode mask of a SHORT.

(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])

;; Mode attributes for GPR loads and stores.

(define_mode_attr load [(SI "lw") (DI "ld")])

(define_mode_attr store [(SI "sw") (DI "sd")])

;; Similarly for MIPS IV indexed FPR loads and stores.

(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])

(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])

;; The unextended ranges of the MIPS16 addiu and daddiu instructions

;; are different.  Some forms of unextended addiu have an 8-bit immediate

;; field but the equivalent daddiu has only a 5-bit field.

(define_mode_attr si8_di5 [(SI "8") (DI "5")])

;; This attribute gives the best constraint to use for registers of

;; a given mode.

(define_mode_attr reg [(SI "d") (DI "d") (CC "z")])

;; This attribute gives the format suffix for floating-point operations.

(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])

;; This attribute gives the upper-case mode name for one unit of a

;; floating-point mode.

(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])

;; This attribute works around the early SB-1 rev2 core "F2" erratum:

;;

;; In certain cases, div.s and div.ps may have a rounding error

;; and/or wrong inexact flag.

;;

;; Therefore, we only allow div.s if not working around SB-1 rev2

;; errata or if a slight loss of precision is OK.

(define_mode_attr divide_condition

  [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")

   (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])

; This attribute gives the condition for which sqrt instructions exist.

(define_mode_attr sqrt_condition

  [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])

; This attribute gives the condition for which recip and rsqrt instructions

; exist.

(define_mode_attr recip_condition

  [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])

;; This code macro allows all branch instructions to be generated from

;; a single define_expand template.

(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt

                             eq ne gt ge lt le gtu geu ltu leu])

;; This code macro allows signed and unsigned widening multiplications

;; to use the same template.

(define_code_macro any_extend [sign_extend zero_extend])

;; This code macro allows the three shift instructions to be generated

;; from the same template.

(define_code_macro any_shift [ashift ashiftrt lshiftrt])

;; This code macro allows all native floating-point comparisons to be

;; generated from the same template.

(define_code_macro fcond [unordered uneq unlt unle eq lt le])

;; This code macro is used for comparisons that can be implemented

;; by swapping the operands.

(define_code_macro swapped_fcond [ge gt unge ungt])

;;  expands to an empty string when doing a signed operation and

;; "u" when doing an unsigned operation.

(define_code_attr u [(sign_extend "") (zero_extend "u")])

;;  is like , but the signed form expands to "s" rather than "".

(define_code_attr su [(sign_extend "s") (zero_extend "u")])

;;  expands to the name of the optab for a particular code.

(define_code_attr optab [(ashift "ashl")

                         (ashiftrt "ashr")

                         (lshiftrt "lshr")])

;;  expands to the name of the insn that implements a particular code.

(define_code_attr insn [(ashift "sll")

                        (ashiftrt "sra")

                        (lshiftrt "srl")])

;;  is the c.cond.fmt condition associated with a particular code.

(define_code_attr fcond [(unordered "un")

                         (uneq "ueq")

                         (unlt "ult")

                         (unle "ule")

                         (eq "eq")

                         (lt "lt")

                         (le "le")])

;; Similar, but for swapped conditions.

(define_code_attr swapped_fcond [(ge "le")

                                 (gt "lt")

                                 (unge "ule")

                                 (ungt "ult")])

;; .........................

;;

;;      Branch, call and jump delay slots

;;

;; .........................

(define_delay (and (eq_attr "type" "branch")

                   (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))

  [(eq_attr "can_delay" "yes")

   (nil)

   (and (eq_attr "branch_likely" "yes")

        (eq_attr "can_delay" "yes"))])

(define_delay (eq_attr "type" "jump")

  [(eq_attr "can_delay" "yes")

   (nil)

   (nil)])

(define_delay (and (eq_attr "type" "call")

                   (eq_attr "jal_macro" "no"))

  [(eq_attr "can_delay" "yes")

   (nil)

   (nil)])

;; Pipeline descriptions.

;;

;; generic.md provides a fallback for processors without a specific

;; pipeline description.  It is derived from the old define_function_unit

;; version and uses the "alu" and "imuldiv" units declared below.

;;

;; Some of the processor-specific files are also derived from old

;; define_function_unit descriptions and simply override the parts of

;; generic.md that don't apply.  The other processor-specific files

;; are self-contained.

(define_automaton "alu,imuldiv")

(define_cpu_unit "alu" "alu")

(define_cpu_unit "imuldiv" "imuldiv")

(include "4k.md")

(include "5k.md")

(include "24k.md")

(include "3000.md")

(include "4000.md")

(include "4100.md")

(include "4130.md")

(include "4300.md")

(include "4600.md")

(include "5000.md")

(include "5400.md")

(include "5500.md")

(include "6000.md")

(include "7000.md")

(include "9000.md")

(include "sb1.md")

(include "sr71k.md")

(include "generic.md")

;;

;;  ....................

;;

;;      CONDITIONAL TRAPS

;;

;;  ....................

;;

(define_insn "trap"

  [(trap_if (const_int 1) (const_int 0))]

  ""

{

  if (ISA_HAS_COND_TRAP)

    return "teq\t$0,$0";

  else if (TARGET_MIPS16)

    return "break 0";

  else

    return "break";

}

  [(set_attr "type" "trap")])

(define_expand "conditional_trap"

  [(trap_if (match_operator 0 "comparison_operator"

                            [(match_dup 2) (match_dup 3)])

            (match_operand 1 "const_int_operand"))]

  "ISA_HAS_COND_TRAP"

{

  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT

      && operands[1] == const0_rtx)

    {

      mips_gen_conditional_trap (operands);

      DONE;

    }

  else

    FAIL;

})

(define_insn "*conditional_trap"

  [(trap_if (match_operator:GPR 0 "trap_comparison_operator"

                                [(match_operand:GPR 1 "reg_or_0_operand" "dJ")

                                 (match_operand:GPR 2 "arith_operand" "dI")])

            (const_int 0))]

  "ISA_HAS_COND_TRAP"

  "t%C0\t%z1,%2"

  [(set_attr "type" "trap")])

;;

;;  ....................

;;

;;      ADDITION

;;

;;  ....................

;;

(define_insn "add3"

  [(set (match_operand:ANYF 0 "register_operand" "=f")

        (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")

                   (match_operand:ANYF 2 "register_operand" "f")))]

  ""

  "add.\t%0,%1,%2"

  [(set_attr "type" "fadd")

   (set_attr "mode" "")])

(define_expand "add3"

  [(set (match_operand:GPR 0 "register_operand")

        (plus:GPR (match_operand:GPR 1 "register_operand")

                  (match_operand:GPR 2 "arith_operand")))]

  "")

(define_insn "*add3"

  [(set (match_operand:GPR 0 "register_operand" "=d,d")

        (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")

                  (match_operand:GPR 2 "arith_operand" "d,Q")))]

  "!TARGET_MIPS16"

  "@

    addu\t%0,%1,%2

    addiu\t%0,%1,%2"

  [(set_attr "type" "arith")

   (set_attr "mode" "")])

;; We need to recognize MIPS16 stack pointer additions explicitly, since

;; we don't have a constraint for $sp.  These insns will be generated by

;; the save_restore_insns functions.

(define_insn "*add3_sp1"

  [(set (reg:GPR 29)

        (plus:GPR (reg:GPR 29)

                  (match_operand:GPR 0 "const_arith_operand" "")))]

  "TARGET_MIPS16"

  "addiu\t%$,%$,%0"

  [(set_attr "type" "arith")

   (set_attr "mode" "")

   (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")

                                      (const_int 4)

                                      (const_int 8)))])

(define_insn "*add3_sp2"

  [(set (match_operand:GPR 0 "register_operand" "=d")

        (plus:GPR (reg:GPR 29)

                  (match_operand:GPR 1 "const_arith_operand" "")))]

  "TARGET_MIPS16"

  "addiu\t%0,%$,%1"

  [(set_attr "type" "arith")

   (set_attr "mode" "")

   (set (attr "length") (if_then_else (match_operand 1 "m16_uimm_4")

                                      (const_int 4)

                                      (const_int 8)))])

(define_insn "*add3_mips16"

  [(set (match_operand:GPR 0 "register_operand" "=d,d,d")

        (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")

                  (match_operand:GPR 2 "arith_operand" "Q,O,d")))]

  "TARGET_MIPS16"

  "@

    addiu\t%0,%2

    addiu\t%0,%1,%2

    addu\t%0,%1,%2"

  [(set_attr "type" "arith")

   (set_attr "mode" "")

   (set_attr_alternative "length"

                [(if_then_else (match_operand 2 "m16_simm_1")

                               (const_int 4)

                               (const_int 8))

                 (if_then_else (match_operand 2 "m16_simm4_1")

                               (const_int 4)

                               (const_int 8))

                 (const_int 4)])])

;; On the mips16, we can sometimes split an add of a constant which is

;; a 4 byte instruction into two adds which are both 2 byte

;; instructions.  There are two cases: one where we are adding a

;; constant plus a register to another register, and one where we are

;; simply adding a constant to a register.

(define_split

  [(set (match_operand:SI 0 "register_operand")

        (plus:SI (match_dup 0)

                 (match_operand:SI 1 "const_int_operand")))]

  "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE

   && REG_P (operands[0])

   && M16_REG_P (REGNO (operands[0]))

   && GET_CODE (operands[1]) == CONST_INT

   && ((INTVAL (operands[1]) > 0x7f

        && INTVAL (operands[1]) <= 0x7f + 0x7f)

       || (INTVAL (operands[1]) < - 0x80

           && INTVAL (operands[1]) >= - 0x80 - 0x80))"

  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))

   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]

{

  HOST_WIDE_INT val = INTVAL (operands[1]);

  if (val >= 0)

    {

      operands[1] = GEN_INT (0x7f);

      operands[2] = GEN_INT (val - 0x7f);

    }

  else

    {

      operands[1] = GEN_INT (- 0x80);

      operands[2] = GEN_INT (val + 0x80);

    }

})

(define_split

  [(set (match_operand:SI 0 "register_operand")

        (plus:SI (match_operand:SI 1 "register_operand")

                 (match_operand:SI 2 "const_int_operand")))]

  "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE

   && REG_P (operands[0])

   && M16_REG_P (REGNO (operands[0]))

   && REG_P (operands[1])

   && M16_REG_P (REGNO (operands[1]))

   && REGNO (operands[0]) != REGNO (operands[1])

   && GET_CODE (operands[2]) == CONST_INT

   && ((INTVAL (operands[2]) > 0x7

        && INTVAL (operands[2]) <= 0x7 + 0x7f)

       || (INTVAL (operands[2]) < - 0x8

           && INTVAL (operands[2]) >= - 0x8 - 0x80))"

  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))

   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]

{

  HOST_WIDE_INT val = INTVAL (operands[2]);

  if (val >= 0)

    {

      operands[2] = GEN_INT (0x7);

      operands[3] = GEN_INT (val - 0x7);

    }

  else

    {

      operands[2] = GEN_INT (- 0x8);

      operands[3] = GEN_INT (val + 0x8);

    }

})

(define_split

  [(set (match_operand:DI 0 "register_operand")

        (plus:DI (match_dup 0)

                 (match_operand:DI 1 "const_int_operand")))]

  "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE

   && REG_P (operands[0])

   && M16_REG_P (REGNO (operands[0]))

   && GET_CODE (operands[1]) == CONST_INT

   && ((INTVAL (operands[1]) > 0xf

        && INTVAL (operands[1]) <= 0xf + 0xf)

       || (INTVAL (operands[1]) < - 0x10

           && INTVAL (operands[1]) >= - 0x10 - 0x10))"

  [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))

   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]

{

  HOST_WIDE_INT val = INTVAL (operands[1]);

  if (val >= 0)

    {

      operands[1] = GEN_INT (0xf);

      operands[2] = GEN_INT (val - 0xf);

    }

  else

    {

      operands[1] = GEN_INT (- 0x10);

      operands[2] = GEN_INT (val + 0x10);

    }

})

(define_split

  [(set (match_operand:DI 0 "register_operand")

        (plus:DI (match_operand:DI 1 "register_operand")

                 (match_operand:DI 2 "const_int_operand")))]

  "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE

   && REG_P (operands[0])

   && M16_REG_P (REGNO (operands[0]))

   && REG_P (operands[1])

   && M16_REG_P (REGNO (operands[1]))

   && REGNO (operands[0]) != REGNO (operands[1])

   && GET_CODE (operands[2]) == CONST_INT

   && ((INTVAL (operands[2]) > 0x7

        && INTVAL (operands[2]) <= 0x7 + 0xf)

       || (INTVAL (operands[2]) < - 0x8

           && INTVAL (operands[2]) >= - 0x8 - 0x10))"

  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))

   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]

{

  HOST_WIDE_INT val = INTVAL (operands[2]);

  if (val >= 0)

    {

      operands[2] = GEN_INT (0x7);

      operands[3] = GEN_INT (val - 0x7);

    }

  else

    {

      operands[2] = GEN_INT (- 0x8);

      operands[3] = GEN_INT (val + 0x8);

    }

})

(define_insn "*addsi3_extended"

  [(set (match_operand:DI 0 "register_operand" "=d,d")

        (sign_extend:DI

             (plus:SI (match_operand:SI 1 "register_operand" "d,d")

                      (match_operand:SI 2 "arith_operand" "d,Q"))))]

  "TARGET_64BIT && !TARGET_MIPS16"

  "@

    addu\t%0,%1,%2

    addiu\t%0,%1,%2"

  [(set_attr "type" "arith")

   (set_attr "mode" "SI")])

;; Split this insn so that the addiu splitters can have a crack at it.

;; Use a conservative length estimate until the split.

(define_insn_and_split "*addsi3_extended_mips16"

  [(set (match_operand:DI 0 "register_operand" "=d,d,d")

        (sign_extend:DI

             (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")

                      (match_operand:SI 2 "arith_operand" "Q,O,d"))))]

  "TARGET_64BIT && TARGET_MIPS16"

  "#"

  "&& reload_completed"

  [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]

  { operands[3] = gen_lowpart (SImode, operands[0]); }

  [(set_attr "type" "arith")

   (set_attr "mode" "SI")

   (set_attr "extended_mips16" "yes")])

;;

;;  ....................

;;

;;      SUBTRACTION

;;

;;  ....................

;;

(define_insn "sub3"

  [(set (match_operand:ANYF 0 "register_operand" "=f")

        (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")

                    (match_operand:ANYF 2 "register_operand" "f")))]

  ""

  "sub.\t%0,%1,%2"

  [(set_attr "type" "fadd")

   (set_attr "mode" "")])

(define_insn "sub3"

  [(set (match_operand:GPR 0 "register_operand" "=d")

        (minus:GPR (match_operand:GPR 1 "register_operand" "d")

                   (match_operand:GPR 2 "register_operand" "d")))]

  ""

  "subu\t%0,%1,%2"

  [(set_attr "type" "arith")

   (set_attr "mode" "")])

(define_insn "*subsi3_extended"

  [(set (match_operand:DI 0 "register_operand" "=d")

        (sign_extend:DI

            (minus:SI (match_operand:SI 1 "register_operand" "d")

                      (match_operand:SI 2 "register_operand" "d"))))]

  "TARGET_64BIT"

  "subu\t%0,%1,%2"

  [(set_attr "type" "arith")

   (set_attr "mode" "DI")])

;;

;;  ....................

;;

;;      MULTIPLICATION

;;

;;  ....................

;;

(define_expand "mul3"

  [(set (match_operand:SCALARF 0 "register_operand")

        (mult:SCALARF (match_operand:SCALARF 1 "register_operand")

                      (match_operand:SCALARF 2 "register_operand")))]

  ""

  "")

(define_insn "*mul3"

  [(set (match_operand:SCALARF 0 "register_operand" "=f")

        (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")

                      (match_operand:SCALARF 2 "register_operand" "f")))]

  "!TARGET_4300_MUL_FIX"

  "mul.\t%0,%1,%2"

  [(set_attr "type" "fmul")