OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gcc/] [gcc-4.1.1/] [gcc/] [config/] [mips/] [vr4120-div.S] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 jlechner
/* Support file for -mfix-vr4120.
2
   Copyright (C) 2002, 2004 Free Software Foundation, Inc.
3
 
4
This file is part of GCC.
5
 
6
GCC is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 2, or (at your option)
9
any later version.
10
 
11
GCC is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with GCC; see the file COPYING.  If not, write to
18
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19
Boston, MA 02110-1301, USA.  */
20
 
21
/* This file contains functions which implement divsi3 and modsi3 for
22
   -mfix-vr4120.  div and ddiv do not give the correct result when one
23
   of the operands is negative.  */
24
 
25
        .set    nomips16
26
 
27
#define DIV                                                             \
28
        xor     $3,$4,$5        /* t = x ^ y */ ;                       \
29
        li      $2,0x80000000;                                          \
30
        .set    noreorder;                                              \
31
        bgez    $4,1f           /* x >= 0 */;                           \
32
        and     $3,$3,$2        /* t = (x ^ y) & 0x80000000 in delay slot */ ;\
33
        .set    reorder;                                                \
34
        subu    $4,$0,$4        /* x = -x */ ;                          \
35
1:;                                                                     \
36
        .set    noreorder;                                              \
37
        bgez    $5,2f           /* y >= 0 */ ;                          \
38
        nop;                                                            \
39
        subu    $5,$0,$5        /* y = -y */ ;                          \
40
        .set    reorder;                                                \
41
2:;                                                                     \
42
        divu    $0,$4,$5;       /* we use divu because of INT_MIN */    \
43
        .set    noreorder;                                              \
44
        bne     $5,$0,3f;                                               \
45
        nop;                                                            \
46
        break   7               /* division on zero y */ ;              \
47
3:;                                                                     \
48
        .set    reorder;                                                \
49
        mflo    $2              /* r = x / y */ ;                       \
50
        .set    noreorder;                                              \
51
        beq     $3,$0,4f        /* t == 0 */ ;                          \
52
        nop;                                                            \
53
        subu    $2,$0,$2        /* r = -r */ ;                          \
54
        .set    reorder;                                                \
55
4:
56
 
57
        .globl  __vr4120_divsi3
58
        .ent    __vr4120_divsi3
59
__vr4120_divsi3:
60
        DIV
61
        j       $31
62
        .end    __vr4120_divsi3
63
 
64
        .globl  __vr4120_modsi3
65
        .ent    __vr4120_modsi3
66
__vr4120_modsi3:
67
        move    $6,$4           # x1 = x
68
        move    $7,$5           # y1 = y
69
        DIV
70
        mult    $2,$7           # r = r * y1
71
        mflo    $2
72
        .set    noreorder
73
        j       $31
74
        subu    $2,$6,$2        # r = x1 - r  in delay slot
75
        .end    __vr4120_modsi3

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.