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jlechner |
;; Scheduling description for IBM POWER5 processor.
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;; Copyright (C) 2003, 2004 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 2, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to the
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;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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;; MA 02110-1301, USA.
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;; Sources: IBM Red Book and White Paper on POWER5
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;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
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;; Instructions that update more than one register get broken into two
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;; (split) or more internal ops. The chip can issue up to 5
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;; internal ops per cycle.
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(define_automaton "power5iu,power5fpu,power5misc")
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(define_cpu_unit "iu1_power5,iu2_power5" "power5iu")
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(define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc")
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(define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu")
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(define_cpu_unit "bpu_power5,cru_power5" "power5misc")
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(define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5"
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"power5misc")
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(define_reservation "lsq_power5"
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"(du1_power5,lsu1_power5)\
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|(du2_power5,lsu2_power5)\
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|(du3_power5,lsu2_power5)\
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|(du4_power5,lsu1_power5)")
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(define_reservation "iq_power5"
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"(du1_power5,iu1_power5)\
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|(du2_power5,iu2_power5)\
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|(du3_power5,iu2_power5)\
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|(du4_power5,iu1_power5)")
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(define_reservation "fpq_power5"
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"(du1_power5,fpu1_power5)\
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|(du2_power5,fpu2_power5)\
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|(du3_power5,fpu2_power5)\
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|(du4_power5,fpu1_power5)")
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; Dispatch slots are allocated in order conforming to program order.
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(absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
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(absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
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(absence_set "du3_power5" "du4_power5,du5_power5")
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(absence_set "du4_power5" "du5_power5")
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; Load/store
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(define_insn_reservation "power5-load" 4 ; 3
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "power5"))
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"lsq_power5")
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(define_insn_reservation "power5-load-ext" 5
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(and (eq_attr "type" "load_ext")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
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(define_insn_reservation "power5-load-ext-update" 5
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(and (eq_attr "type" "load_ext_u")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5+du3_power5+du4_power5,\
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lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
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(define_insn_reservation "power5-load-ext-update-indexed" 5
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(and (eq_attr "type" "load_ext_ux")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5+du3_power5+du4_power5,\
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iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
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(define_insn_reservation "power5-load-update-indexed" 3
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(and (eq_attr "type" "load_ux")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5+du3_power5+du4_power5,\
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iu1_power5,lsu2_power5+iu2_power5")
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(define_insn_reservation "power5-load-update" 4 ; 3
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(and (eq_attr "type" "load_u")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,lsu1_power5+iu2_power5")
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(define_insn_reservation "power5-fpload" 6 ; 5
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "power5"))
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"lsq_power5")
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(define_insn_reservation "power5-fpload-update" 6 ; 5
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(and (eq_attr "type" "fpload_u,fpload_ux")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,lsu1_power5+iu2_power5")
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(define_insn_reservation "power5-store" 12
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(and (eq_attr "type" "store")
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(eq_attr "cpu" "power5"))
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"(du1_power5,lsu1_power5,iu1_power5)\
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|(du2_power5,lsu2_power5,iu2_power5)\
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|(du3_power5,lsu2_power5,iu2_power5)\
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|(du4_power5,lsu1_power5,iu1_power5)")
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(define_insn_reservation "power5-store-update" 12
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(and (eq_attr "type" "store_u")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
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(define_insn_reservation "power5-store-update-indexed" 12
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(and (eq_attr "type" "store_ux")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5+du3_power5+du4_power5,\
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iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
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(define_insn_reservation "power5-fpstore" 12
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(and (eq_attr "type" "fpstore")
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(eq_attr "cpu" "power5"))
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"(du1_power5,lsu1_power5,fpu1_power5)\
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|(du2_power5,lsu2_power5,fpu2_power5)\
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|(du3_power5,lsu2_power5,fpu2_power5)\
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|(du4_power5,lsu1_power5,fpu1_power5)")
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(define_insn_reservation "power5-fpstore-update" 12
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(and (eq_attr "type" "fpstore_u,fpstore_ux")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
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(define_insn_reservation "power5-llsc" 11
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(and (eq_attr "type" "load_l,store_c,sync")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5+du3_power5+du4_power5,\
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lsu1_power5")
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; Integer latency is 2 cycles
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(define_insn_reservation "power5-integer" 2
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(and (eq_attr "type" "integer")
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(eq_attr "cpu" "power5"))
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"iq_power5")
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(define_insn_reservation "power5-two" 2
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "power5"))
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"(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\
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|(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\
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|(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\
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|(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)")
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(define_insn_reservation "power5-three" 2
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "power5"))
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"(du1_power5+du2_power5+du3_power5,\
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iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
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|(du2_power5+du3_power5+du4_power5,\
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iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
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|(du3_power5+du4_power5+du1_power5,\
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iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
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|(du4_power5+du1_power5+du2_power5,\
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iu1_power5,nothing,iu2_power5,nothing,iu2_power5)")
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(define_insn_reservation "power5-insert" 4
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(and (eq_attr "type" "insert_word")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
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(define_insn_reservation "power5-cmp" 3
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(and (eq_attr "type" "cmp,fast_compare")
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(eq_attr "cpu" "power5"))
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"iq_power5")
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(define_insn_reservation "power5-compare" 2
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(and (eq_attr "type" "compare,delayed_compare")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,iu1_power5,iu2_power5")
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(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
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(define_insn_reservation "power5-lmul-cmp" 7
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(and (eq_attr "type" "lmul_compare")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,iu1_power5*6,iu2_power5")
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(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
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(define_insn_reservation "power5-imul-cmp" 5
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(and (eq_attr "type" "imul_compare")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,iu1_power5*4,iu2_power5")
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(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
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(define_insn_reservation "power5-lmul" 7
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(and (eq_attr "type" "lmul")
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(eq_attr "cpu" "power5"))
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"(du1_power5,iu1_power5*6)\
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|(du2_power5,iu2_power5*6)\
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|(du3_power5,iu2_power5*6)\
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|(du4_power5,iu1_power5*6)")
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(define_insn_reservation "power5-imul" 5
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(and (eq_attr "type" "imul")
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(eq_attr "cpu" "power5"))
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"(du1_power5,iu1_power5*4)\
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|(du2_power5,iu2_power5*4)\
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|(du3_power5,iu2_power5*4)\
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|(du4_power5,iu1_power5*4)")
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(define_insn_reservation "power5-imul3" 4
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(and (eq_attr "type" "imul2,imul3")
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(eq_attr "cpu" "power5"))
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"(du1_power5,iu1_power5*3)\
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|(du2_power5,iu2_power5*3)\
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|(du3_power5,iu2_power5*3)\
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|(du4_power5,iu1_power5*3)")
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; SPR move only executes in first IU.
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; Integer division only executes in second IU.
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(define_insn_reservation "power5-idiv" 36
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,iu2_power5*35")
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(define_insn_reservation "power5-ldiv" 68
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(and (eq_attr "type" "ldiv")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,iu2_power5*67")
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(define_insn_reservation "power5-mtjmpr" 3
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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(eq_attr "cpu" "power5"))
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"du1_power5,bpu_power5")
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; Branches take dispatch Slot 4. The presence_sets prevent other insn from
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; grabbing previous dispatch slots once this is assigned.
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(define_insn_reservation "power5-branch" 2
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(and (eq_attr "type" "jmpreg,branch")
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(eq_attr "cpu" "power5"))
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"(du5_power5\
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|du4_power5+du5_power5\
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|du3_power5+du4_power5+du5_power5\
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|du2_power5+du3_power5+du4_power5+du5_power5\
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|du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5")
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; Condition Register logical ops are split if non-destructive (RT != RB)
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(define_insn_reservation "power5-crlogical" 2
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(and (eq_attr "type" "cr_logical")
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(eq_attr "cpu" "power5"))
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"du1_power5,cru_power5")
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(define_insn_reservation "power5-delayedcr" 4
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(and (eq_attr "type" "delayed_cr")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5,cru_power5,cru_power5")
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; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
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(define_insn_reservation "power5-mfcr" 6
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "power5"))
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"du1_power5+du2_power5+du3_power5+du4_power5,\
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du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\
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cru_power5,cru_power5,cru_power5")
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; mfcrf (1 field)
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(define_insn_reservation "power5-mfcrf" 3
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(and (eq_attr "type" "mfcrf")
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|
(eq_attr "cpu" "power5"))
|
| 281 |
|
|
"du1_power5,cru_power5")
|
| 282 |
|
|
|
| 283 |
|
|
; mtcrf (1 field)
|
| 284 |
|
|
(define_insn_reservation "power5-mtcr" 4
|
| 285 |
|
|
(and (eq_attr "type" "mtcr")
|
| 286 |
|
|
(eq_attr "cpu" "power5"))
|
| 287 |
|
|
"du1_power5,iu1_power5")
|
| 288 |
|
|
|
| 289 |
|
|
; Basic FP latency is 6 cycles
|
| 290 |
|
|
(define_insn_reservation "power5-fp" 6
|
| 291 |
|
|
(and (eq_attr "type" "fp,dmul")
|
| 292 |
|
|
(eq_attr "cpu" "power5"))
|
| 293 |
|
|
"fpq_power5")
|
| 294 |
|
|
|
| 295 |
|
|
(define_insn_reservation "power5-fpcompare" 5
|
| 296 |
|
|
(and (eq_attr "type" "fpcompare")
|
| 297 |
|
|
(eq_attr "cpu" "power5"))
|
| 298 |
|
|
"fpq_power5")
|
| 299 |
|
|
|
| 300 |
|
|
(define_insn_reservation "power5-sdiv" 33
|
| 301 |
|
|
(and (eq_attr "type" "sdiv,ddiv")
|
| 302 |
|
|
(eq_attr "cpu" "power5"))
|
| 303 |
|
|
"(du1_power5,fpu1_power5*28)\
|
| 304 |
|
|
|(du2_power5,fpu2_power5*28)\
|
| 305 |
|
|
|(du3_power5,fpu2_power5*28)\
|
| 306 |
|
|
|(du4_power5,fpu1_power5*28)")
|
| 307 |
|
|
|
| 308 |
|
|
(define_insn_reservation "power5-sqrt" 40
|
| 309 |
|
|
(and (eq_attr "type" "ssqrt,dsqrt")
|
| 310 |
|
|
(eq_attr "cpu" "power5"))
|
| 311 |
|
|
"(du1_power5,fpu1_power5*35)\
|
| 312 |
|
|
|(du2_power5,fpu2_power5*35)\
|
| 313 |
|
|
|(du3_power5,fpu2_power5*35)\
|
| 314 |
|
|
|(du4_power5,fpu2_power5*35)")
|
| 315 |
|
|
|
| 316 |
|
|
(define_insn_reservation "power5-isync" 2
|
| 317 |
|
|
(and (eq_attr "type" "isync")
|
| 318 |
|
|
(eq_attr "cpu" "power5"))
|
| 319 |
|
|
"du1_power5+du2_power5+du3_power5+du4_power5,\
|
| 320 |
|
|
lsu1_power5")
|
| 321 |
|
|
|
