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;; Scheduling description for IBM Power2 processor.
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;; Copyright (C) 2003, 2004 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 2, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to the
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;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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;; MA 02110-1301, USA.
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(define_automaton "rios2,rios2fp")
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(define_cpu_unit "iu1_rios2,iu2_rios2" "rios2")
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(define_cpu_unit "fpu1_rios2,fpu2_rios2" "rios2fp")
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(define_cpu_unit "bpu_rios2" "rios2")
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;; RIOS2 32-bit 2xIU, 2xFPU, BPU
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;; IU1 can perform all integer operations
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;; IU2 can perform all integer operations except imul and idiv
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(define_insn_reservation "rios2-load" 2
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\
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load_ux,load_u,fpload,fpload_ux,fpload_u,\
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load_l,store_c,sync")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2|iu2_rios2")
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(define_insn_reservation "rios2-store" 2
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(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2|iu2_rios2")
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(define_insn_reservation "rios2-integer" 1
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(and (eq_attr "type" "integer,insert_word")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2|iu2_rios2")
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(define_insn_reservation "rios2-two" 1
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2|iu2_rios2,iu1_rios2|iu2_rios2")
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(define_insn_reservation "rios2-three" 1
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2|iu2_rios2,iu1_rios2|iu2_rios2,iu1_rios2|iu2_rios2")
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(define_insn_reservation "rios2-imul" 2
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2*2")
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(define_insn_reservation "rios2-idiv" 13
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2*13")
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; compare executes on integer unit, but feeds insns which
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; execute on the branch unit.
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(define_insn_reservation "rios2-compare" 3
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(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
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(eq_attr "cpu" "rios2"))
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"(iu1_rios2|iu2_rios2),nothing,bpu_rios2")
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(define_insn_reservation "rios2-fp" 2
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "rios2"))
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"fpu1_rios2|fpu2_rios2")
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(define_insn_reservation "rios2-fpcompare" 5
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "rios2"))
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"(fpu1_rios2|fpu2_rios2),nothing*3,bpu_rios2")
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(define_insn_reservation "rios2-dmul" 2
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "rios2"))
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"fpu1_rios2|fpu2_rios2")
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(define_insn_reservation "rios2-sdiv" 17
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(and (eq_attr "type" "sdiv,ddiv")
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(eq_attr "cpu" "rios2"))
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"(fpu1_rios2*17)|(fpu2_rios2*17)")
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(define_insn_reservation "rios2-ssqrt" 26
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(and (eq_attr "type" "ssqrt,dsqrt")
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(eq_attr "cpu" "rios2"))
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"(fpu1_rios2*26)|(fpu2_rios2*26)")
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(define_insn_reservation "rios2-mfcr" 2
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2,bpu_rios2")
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(define_insn_reservation "rios2-mtcr" 3
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2,bpu_rios2")
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(define_insn_reservation "rios2-crlogical" 3
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(eq_attr "cpu" "rios2"))
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"bpu_rios2")
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(define_insn_reservation "rios2-mtjmpr" 5
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2,bpu_rios2")
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(define_insn_reservation "rios2-mfjmpr" 2
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(and (eq_attr "type" "mfjmpr")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2,bpu_rios2")
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(define_insn_reservation "rios2-branch" 1
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(and (eq_attr "type" "jmpreg,branch,isync")
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(eq_attr "cpu" "rios2"))
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"bpu_rios2")
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