OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gcc/] [gcc-4.1.1/] [gcc/] [config/] [s390/] [s390.c] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 jlechner 
/* Subroutines used for code generation on IBM S/390 and zSeries
2 
   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 
   Free Software Foundation, Inc.
4 
   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 
                  Ulrich Weigand (uweigand@de.ibm.com).
6 
 
7 
This file is part of GCC.
8 
 
9 
GCC is free software; you can redistribute it and/or modify it under
10 
the terms of the GNU General Public License as published by the Free
11 
Software Foundation; either version 2, or (at your option) any later
12 
version.
13 
 
14 
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 
WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
17 
for more details.
18 
 
19 
You should have received a copy of the GNU General Public License
20 
along with GCC; see the file COPYING.  If not, write to the Free
21 
Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 
02110-1301, USA.  */
23 
 
24 
#include "config.h"
25 
#include "system.h"
26 
#include "coretypes.h"
27 
#include "tm.h"
28 
#include "rtl.h"
29 
#include "tree.h"
30 
#include "tm_p.h"
31 
#include "regs.h"
32 
#include "hard-reg-set.h"
33 
#include "real.h"
34 
#include "insn-config.h"
35 
#include "conditions.h"
36 
#include "output.h"
37 
#include "insn-attr.h"
38 
#include "flags.h"
39 
#include "except.h"
40 
#include "function.h"
41 
#include "recog.h"
42 
#include "expr.h"
43 
#include "reload.h"
44 
#include "toplev.h"
45 
#include "basic-block.h"
46 
#include "integrate.h"
47 
#include "ggc.h"
48 
#include "target.h"
49 
#include "target-def.h"
50 
#include "debug.h"
51 
#include "langhooks.h"
52 
#include "optabs.h"
53 
#include "tree-gimple.h"
54 
 
55 
 
56 
/* Define the specific costs for a given cpu.  */
57 
 
58 
struct processor_costs
59 
{
60 
  /* multiplication */
61 
  const int m;        /* cost of an M instruction.  */
62 
  const int mghi;     /* cost of an MGHI instruction.  */
63 
  const int mh;       /* cost of an MH instruction.  */
64 
  const int mhi;      /* cost of an MHI instruction.  */
65 
  const int ml;       /* cost of an ML instruction.  */
66 
  const int mr;       /* cost of an MR instruction.  */
67 
  const int ms;       /* cost of an MS instruction.  */
68 
  const int msg;      /* cost of an MSG instruction.  */
69 
  const int msgf;     /* cost of an MSGF instruction.  */
70 
  const int msgfr;    /* cost of an MSGFR instruction.  */
71 
  const int msgr;     /* cost of an MSGR instruction.  */
72 
  const int msr;      /* cost of an MSR instruction.  */
73 
  const int mult_df;  /* cost of multiplication in DFmode.  */
74 
  const int mxbr;
75 
  /* square root */
76 
  const int sqxbr;    /* cost of square root in TFmode.  */
77 
  const int sqdbr;    /* cost of square root in DFmode.  */
78 
  const int sqebr;    /* cost of square root in SFmode.  */
79 
  /* multiply and add */
80 
  const int madbr;    /* cost of multiply and add in DFmode.  */
81 
  const int maebr;    /* cost of multiply and add in SFmode.  */
82 
  /* division */
83 
  const int dxbr;
84 
  const int dxr;
85 
  const int ddbr;
86 
  const int ddr;
87 
  const int debr;
88 
  const int der;
89 
  const int dlgr;
90 
  const int dlr;
91 
  const int dr;
92 
  const int dsgfr;
93 
  const int dsgr;
94 
};
95 
 
96 
const struct processor_costs *s390_cost;
97 
 
98 
static const
99 
struct processor_costs z900_cost =
100 
{
101 
  COSTS_N_INSNS (5),     /* M     */
102 
  COSTS_N_INSNS (10),    /* MGHI  */
103 
  COSTS_N_INSNS (5),     /* MH    */
104 
  COSTS_N_INSNS (4),     /* MHI   */
105 
  COSTS_N_INSNS (5),     /* ML    */
106 
  COSTS_N_INSNS (5),     /* MR    */
107 
  COSTS_N_INSNS (4),     /* MS    */
108 
  COSTS_N_INSNS (15),    /* MSG   */
109 
  COSTS_N_INSNS (7),     /* MSGF  */
110 
  COSTS_N_INSNS (7),     /* MSGFR */
111 
  COSTS_N_INSNS (10),    /* MSGR  */
112 
  COSTS_N_INSNS (4),     /* MSR   */
113 
  COSTS_N_INSNS (7),     /* multiplication in DFmode */
114 
  COSTS_N_INSNS (13),    /* MXBR */
115 
  COSTS_N_INSNS (136),   /* SQXBR */
116 
  COSTS_N_INSNS (44),    /* SQDBR */
117 
  COSTS_N_INSNS (35),    /* SQEBR */
118 
  COSTS_N_INSNS (18),    /* MADBR */
119 
  COSTS_N_INSNS (13),    /* MAEBR */
120 
  COSTS_N_INSNS (134),   /* DXBR */
121 
  COSTS_N_INSNS (135),   /* DXR */
122 
  COSTS_N_INSNS (30),    /* DDBR */
123 
  COSTS_N_INSNS (30),    /* DDR  */
124 
  COSTS_N_INSNS (27),    /* DEBR */
125 
  COSTS_N_INSNS (26),    /* DER  */
126 
  COSTS_N_INSNS (220),   /* DLGR */
127 
  COSTS_N_INSNS (34),    /* DLR */
128 
  COSTS_N_INSNS (34),    /* DR */
129 
  COSTS_N_INSNS (32),    /* DSGFR */
130 
  COSTS_N_INSNS (32),    /* DSGR */
131 
};
132 
 
133 
static const
134 
struct processor_costs z990_cost =
135 
{
136 
  COSTS_N_INSNS (4),     /* M     */
137 
  COSTS_N_INSNS (2),     /* MGHI  */
138 
  COSTS_N_INSNS (2),     /* MH    */
139 
  COSTS_N_INSNS (2),     /* MHI   */
140 
  COSTS_N_INSNS (4),     /* ML    */
141 
  COSTS_N_INSNS (4),     /* MR    */
142 
  COSTS_N_INSNS (5),     /* MS    */
143 
  COSTS_N_INSNS (6),     /* MSG   */
144 
  COSTS_N_INSNS (4),     /* MSGF  */
145 
  COSTS_N_INSNS (4),     /* MSGFR */
146 
  COSTS_N_INSNS (4),     /* MSGR  */
147 
  COSTS_N_INSNS (4),     /* MSR   */
148 
  COSTS_N_INSNS (1),     /* multiplication in DFmode */
149 
  COSTS_N_INSNS (28),    /* MXBR */
150 
  COSTS_N_INSNS (130),   /* SQXBR */
151 
  COSTS_N_INSNS (66),    /* SQDBR */
152 
  COSTS_N_INSNS (38),    /* SQEBR */
153 
  COSTS_N_INSNS (1),     /* MADBR */
154 
  COSTS_N_INSNS (1),     /* MAEBR */
155 
  COSTS_N_INSNS (60),    /* DXBR */
156 
  COSTS_N_INSNS (72),    /* DXR */
157 
  COSTS_N_INSNS (40),    /* DDBR */
158 
  COSTS_N_INSNS (44),    /* DDR  */
159 
  COSTS_N_INSNS (26),    /* DDBR */
160 
  COSTS_N_INSNS (28),    /* DER  */
161 
  COSTS_N_INSNS (176),   /* DLGR */
162 
  COSTS_N_INSNS (31),    /* DLR */
163 
  COSTS_N_INSNS (31),    /* DR */
164 
  COSTS_N_INSNS (31),    /* DSGFR */
165 
  COSTS_N_INSNS (31),    /* DSGR */
166 
};
167 
 
168 
static const
169 
struct processor_costs z9_109_cost =
170 
{
171 
  COSTS_N_INSNS (4),     /* M     */
172 
  COSTS_N_INSNS (2),     /* MGHI  */
173 
  COSTS_N_INSNS (2),     /* MH    */
174 
  COSTS_N_INSNS (2),     /* MHI   */
175 
  COSTS_N_INSNS (4),     /* ML    */
176 
  COSTS_N_INSNS (4),     /* MR    */
177 
  COSTS_N_INSNS (5),     /* MS    */
178 
  COSTS_N_INSNS (6),     /* MSG   */
179 
  COSTS_N_INSNS (4),     /* MSGF  */
180 
  COSTS_N_INSNS (4),     /* MSGFR */
181 
  COSTS_N_INSNS (4),     /* MSGR  */
182 
  COSTS_N_INSNS (4),     /* MSR   */
183 
  COSTS_N_INSNS (1),     /* multiplication in DFmode */
184 
  COSTS_N_INSNS (28),    /* MXBR */
185 
  COSTS_N_INSNS (130),   /* SQXBR */
186 
  COSTS_N_INSNS (66),    /* SQDBR */
187 
  COSTS_N_INSNS (38),    /* SQEBR */
188 
  COSTS_N_INSNS (1),     /* MADBR */
189 
  COSTS_N_INSNS (1),     /* MAEBR */
190 
  COSTS_N_INSNS (60),    /* DXBR */
191 
  COSTS_N_INSNS (72),    /* DXR */
192 
  COSTS_N_INSNS (40),    /* DDBR */
193 
  COSTS_N_INSNS (37),    /* DDR  */
194 
  COSTS_N_INSNS (26),    /* DDBR */
195 
  COSTS_N_INSNS (28),    /* DER  */
196 
  COSTS_N_INSNS (30),    /* DLGR */
197 
  COSTS_N_INSNS (23),    /* DLR */
198 
  COSTS_N_INSNS (23),    /* DR */
199 
  COSTS_N_INSNS (24),    /* DSGFR */
200 
  COSTS_N_INSNS (24),    /* DSGR */
201 
};
202 
 
203 
extern int reload_completed;
204 
 
205 
/* Save information from a "cmpxx" operation until the branch or scc is
206 
   emitted.  */
207 
rtx s390_compare_op0, s390_compare_op1;
208 
 
209 
/* Save the result of a compare_and_swap  until the branch or scc is
210 
   emitted.  */
211 
rtx s390_compare_emitted = NULL_RTX;
212 
 
213 
/* Structure used to hold the components of a S/390 memory
214 
   address.  A legitimate address on S/390 is of the general
215 
   form
216 
          base + index + displacement
217 
   where any of the components is optional.
218 
 
219 
   base and index are registers of the class ADDR_REGS,
220 
   displacement is an unsigned 12-bit immediate constant.  */
221 
 
222 
struct s390_address
223 
{
224 
  rtx base;
225 
  rtx indx;
226 
  rtx disp;
227 
  bool pointer;
228 
  bool literal_pool;
229 
};
230 
 
231 
/* Which cpu are we tuning for.  */
232 
enum processor_type s390_tune = PROCESSOR_max;
233 
enum processor_flags s390_tune_flags;
234 
/* Which instruction set architecture to use.  */
235 
enum processor_type s390_arch;
236 
enum processor_flags s390_arch_flags;
237 
 
238 
HOST_WIDE_INT s390_warn_framesize = 0;
239 
HOST_WIDE_INT s390_stack_size = 0;
240 
HOST_WIDE_INT s390_stack_guard = 0;
241 
 
242 
/* The following structure is embedded in the machine
243 
   specific part of struct function.  */
244 
 
245 
struct s390_frame_layout GTY (())
246 
{
247 
  /* Offset within stack frame.  */
248 
  HOST_WIDE_INT gprs_offset;
249 
  HOST_WIDE_INT f0_offset;
250 
  HOST_WIDE_INT f4_offset;
251 
  HOST_WIDE_INT f8_offset;
252 
  HOST_WIDE_INT backchain_offset;
253 
 
254 
  /* Number of first and last gpr where slots in the register
255 
     save area are reserved for.  */
256 
  int first_save_gpr_slot;
257 
  int last_save_gpr_slot;
258 
 
259 
  /* Number of first and last gpr to be saved, restored.  */
260 
  int first_save_gpr;
261 
  int first_restore_gpr;
262 
  int last_save_gpr;
263 
  int last_restore_gpr;
264 
 
265 
  /* Bits standing for floating point registers. Set, if the
266 
     respective register has to be saved. Starting with reg 16 (f0)
267 
     at the rightmost bit.
268 
     Bit 15 -  8  7  6  5  4  3  2  1  0
269 
     fpr 15 -  8  7  5  3  1  6  4  2  0
270 
     reg 31 - 24 23 22 21 20 19 18 17 16  */
271 
  unsigned int fpr_bitmap;
272 
 
273 
  /* Number of floating point registers f8-f15 which must be saved.  */
274 
  int high_fprs;
275 
 
276 
  /* Set if return address needs to be saved.
277 
     This flag is set by s390_return_addr_rtx if it could not use
278 
     the initial value of r14 and therefore depends on r14 saved
279 
     to the stack.  */
280 
  bool save_return_addr_p;
281 
 
282 
  /* Size of stack frame.  */
283 
  HOST_WIDE_INT frame_size;
284 
};
285 
 
286 
/* Define the structure for the machine field in struct function.  */
287 
 
288 
struct machine_function GTY(())
289 
{
290 
  struct s390_frame_layout frame_layout;
291 
 
292 
  /* Literal pool base register.  */
293 
  rtx base_reg;
294 
 
295 
  /* True if we may need to perform branch splitting.  */
296 
  bool split_branches_pending_p;
297 
 
298 
  /* True during final stage of literal pool processing.  */
299 
  bool decomposed_literal_pool_addresses_ok_p;
300 
 
301 
  /* Some local-dynamic TLS symbol name.  */
302 
  const char *some_ld_name;
303 
 
304 
  bool has_landing_pad_p;
305 
};
306 
 
307 
/* Few accessor macros for struct cfun->machine->s390_frame_layout.  */
308 
 
309 
#define cfun_frame_layout (cfun->machine->frame_layout)
310 
#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
311 
#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot -           \
312 
  cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
313 
#define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |=    \
314 
  (1 << (BITNUM)))
315 
#define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap &    \
316 
  (1 << (BITNUM))))
317 
 
318 
/* Number of GPRs and FPRs used for argument passing.  */
319 
#define GP_ARG_NUM_REG 5
320 
#define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
321 
 
322 
/* A couple of shortcuts.  */
323 
#define CONST_OK_FOR_J(x) \
324 
        CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
325 
#define CONST_OK_FOR_K(x) \
326 
        CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
327 
#define CONST_OK_FOR_Os(x) \
328 
        CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
329 
#define CONST_OK_FOR_Op(x) \
330 
        CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
331 
#define CONST_OK_FOR_On(x) \
332 
        CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
333 
 
334 
/* Set the has_landing_pad_p flag in struct machine_function to VALUE.  */
335 
 
336 
void
337 
s390_set_has_landing_pad_p (bool value)
338 
{
339 
  cfun->machine->has_landing_pad_p = value;
340 
}
341 
 
342 
/* If two condition code modes are compatible, return a condition code
343 
   mode which is compatible with both.  Otherwise, return
344 
   VOIDmode.  */
345 
 
346 
static enum machine_mode
347 
s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
348 
{
349 
  if (m1 == m2)
350 
    return m1;
351 
 
352 
  switch (m1)
353 
    {
354 
    case CCZmode:
355 
      if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
356 
          || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
357 
        return m2;
358 
      return VOIDmode;
359 
 
360 
    case CCSmode:
361 
    case CCUmode:
362 
    case CCTmode:
363 
    case CCSRmode:
364 
    case CCURmode:
365 
    case CCZ1mode:
366 
      if (m2 == CCZmode)
367 
        return m1;
368 
 
369 
      return VOIDmode;
370 
 
371 
    default:
372 
      return VOIDmode;
373 
    }
374 
  return VOIDmode;
375 
}
376 
 
377 
/* Return true if SET either doesn't set the CC register, or else
378 
   the source and destination have matching CC modes and that
379 
   CC mode is at least as constrained as REQ_MODE.  */
380 
 
381 
static bool
382 
s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
383 
{
384 
  enum machine_mode set_mode;
385 
 
386 
  gcc_assert (GET_CODE (set) == SET);
387 
 
388 
  if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
389 
    return 1;
390 
 
391 
  set_mode = GET_MODE (SET_DEST (set));
392 
  switch (set_mode)
393 
    {
394 
    case CCSmode:
395 
    case CCSRmode:
396 
    case CCUmode:
397 
    case CCURmode:
398 
    case CCLmode:
399 
    case CCL1mode:
400 
    case CCL2mode:
401 
    case CCL3mode:
402 
    case CCT1mode:
403 
    case CCT2mode:
404 
    case CCT3mode:
405 
      if (req_mode != set_mode)
406 
        return 0;
407 
      break;
408 
 
409 
    case CCZmode:
410 
      if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
411 
          && req_mode != CCSRmode && req_mode != CCURmode)
412 
        return 0;
413 
      break;
414 
 
415 
    case CCAPmode:
416 
    case CCANmode:
417 
      if (req_mode != CCAmode)
418 
        return 0;
419 
      break;
420 
 
421 
    default:
422 
      gcc_unreachable ();
423 
    }
424 
 
425 
  return (GET_MODE (SET_SRC (set)) == set_mode);
426 
}
427 
 
428 
/* Return true if every SET in INSN that sets the CC register
429 
   has source and destination with matching CC modes and that
430 
   CC mode is at least as constrained as REQ_MODE.
431 
   If REQ_MODE is VOIDmode, always return false.  */
432 
 
433 
bool
434 
s390_match_ccmode (rtx insn, enum machine_mode req_mode)
435 
{
436 
  int i;
437 
 
438 
  /* s390_tm_ccmode returns VOIDmode to indicate failure.  */
439 
  if (req_mode == VOIDmode)
440 
    return false;
441 
 
442 
  if (GET_CODE (PATTERN (insn)) == SET)
443 
    return s390_match_ccmode_set (PATTERN (insn), req_mode);
444 
 
445 
  if (GET_CODE (PATTERN (insn)) == PARALLEL)
446 
      for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
447 
        {
448 
          rtx set = XVECEXP (PATTERN (insn), 0, i);
449 
          if (GET_CODE (set) == SET)
450 
            if (!s390_match_ccmode_set (set, req_mode))
451 
              return false;
452 
        }
453 
 
454 
  return true;
455 
}
456 
 
457 
/* If a test-under-mask instruction can be used to implement
458 
   (compare (and ... OP1) OP2), return the CC mode required
459 
   to do that.  Otherwise, return VOIDmode.
460 
   MIXED is true if the instruction can distinguish between
461 
   CC1 and CC2 for mixed selected bits (TMxx), it is false
462 
   if the instruction cannot (TM).  */
463 
 
464 
enum machine_mode
465 
s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
466 
{
467 
  int bit0, bit1;
468 
 
469 
  /* ??? Fixme: should work on CONST_DOUBLE as well.  */
470 
  if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
471 
    return VOIDmode;
472 
 
473 
  /* Selected bits all zero: CC0.
474 
     e.g.: int a; if ((a & (16 + 128)) == 0) */
475 
  if (INTVAL (op2) == 0)
476 
    return CCTmode;
477 
 
478 
  /* Selected bits all one: CC3.
479 
     e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
480 
  if (INTVAL (op2) == INTVAL (op1))
481 
    return CCT3mode;
482 
 
483 
  /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
484 
     int a;
485 
     if ((a & (16 + 128)) == 16)         -> CCT1
486 
     if ((a & (16 + 128)) == 128)        -> CCT2  */
487 
  if (mixed)
488 
    {
489 
      bit1 = exact_log2 (INTVAL (op2));
490 
      bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
491 
      if (bit0 != -1 && bit1 != -1)
492 
        return bit0 > bit1 ? CCT1mode : CCT2mode;
493 
    }
494 
 
495 
  return VOIDmode;
496 
}
497 
 
498 
/* Given a comparison code OP (EQ, NE, etc.) and the operands
499 
   OP0 and OP1 of a COMPARE, return the mode to be used for the
500 
   comparison.  */
501 
 
502 
enum machine_mode
503 
s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
504 
{
505 
  switch (code)
506 
    {
507 
      case EQ:
508 
      case NE:
509 
        if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
510 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
511 
          return CCAPmode;
512 
        if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
513 
            && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
514 
          return CCAPmode;
515 
        if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
516 
             || GET_CODE (op1) == NEG)
517 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
518 
          return CCLmode;
519 
 
520 
        if (GET_CODE (op0) == AND)
521 
          {
522 
            /* Check whether we can potentially do it via TM.  */
523 
            enum machine_mode ccmode;
524 
            ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
525 
            if (ccmode != VOIDmode)
526 
              {
527 
                /* Relax CCTmode to CCZmode to allow fall-back to AND
528 
                   if that turns out to be beneficial.  */
529 
                return ccmode == CCTmode ? CCZmode : ccmode;
530 
              }
531 
          }
532 
 
533 
        if (register_operand (op0, HImode)
534 
            && GET_CODE (op1) == CONST_INT
535 
            && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
536 
          return CCT3mode;
537 
        if (register_operand (op0, QImode)
538 
            && GET_CODE (op1) == CONST_INT
539 
            && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
540 
          return CCT3mode;
541 
 
542 
        return CCZmode;
543 
 
544 
      case LE:
545 
      case LT:
546 
      case GE:
547 
      case GT:
548 
        /* The only overflow condition of NEG and ABS happens when
549 
           -INT_MAX is used as parameter, which stays negative. So
550 
           we have an overflow from a positive value to a negative.
551 
           Using CCAP mode the resulting cc can be used for comparisons.  */
552 
        if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
553 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
554 
          return CCAPmode;
555 
 
556 
        /* If constants are involved in an add instruction it is possible to use
557 
           the resulting cc for comparisons with zero. Knowing the sign of the
558 
           constant the overflow behavior gets predictable. e.g.:
559 
             int a, b; if ((b = a + c) > 0)
560 
           with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP  */
561 
        if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
562 
            && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
563 
          {
564 
            if (INTVAL (XEXP((op0), 1)) < 0)
565 
              return CCANmode;
566 
            else
567 
              return CCAPmode;
568 
          }
569 
        /* Fall through.  */
570 
      case UNORDERED:
571 
      case ORDERED:
572 
      case UNEQ:
573 
      case UNLE:
574 
      case UNLT:
575 
      case UNGE:
576 
      case UNGT:
577 
      case LTGT:
578 
        if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
579 
            && GET_CODE (op1) != CONST_INT)
580 
          return CCSRmode;
581 
        return CCSmode;
582 
 
583 
      case LTU:
584 
      case GEU:
585 
        if (GET_CODE (op0) == PLUS
586 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
587 
          return CCL1mode;
588 
 
589 
        if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
590 
            && GET_CODE (op1) != CONST_INT)
591 
          return CCURmode;
592 
        return CCUmode;
593 
 
594 
      case LEU:
595 
      case GTU:
596 
        if (GET_CODE (op0) == MINUS
597 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
598 
          return CCL2mode;
599 
 
600 
        if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
601 
            && GET_CODE (op1) != CONST_INT)
602 
          return CCURmode;
603 
        return CCUmode;
604 
 
605 
      default:
606 
        gcc_unreachable ();
607 
    }
608 
}
609 
 
610 
/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
611 
   that we can implement more efficiently.  */
612 
 
613 
void
614 
s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
615 
{
616 
  /* Convert ZERO_EXTRACT back to AND to enable TM patterns.  */
617 
  if ((*code == EQ || *code == NE)
618 
      && *op1 == const0_rtx
619 
      && GET_CODE (*op0) == ZERO_EXTRACT
620 
      && GET_CODE (XEXP (*op0, 1)) == CONST_INT
621 
      && GET_CODE (XEXP (*op0, 2)) == CONST_INT
622 
      && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
623 
    {
624 
      rtx inner = XEXP (*op0, 0);
625 
      HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
626 
      HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
627 
      HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
628 
 
629 
      if (len > 0 && len < modesize
630 
          && pos >= 0 && pos + len <= modesize
631 
          && modesize <= HOST_BITS_PER_WIDE_INT)
632 
        {
633 
          unsigned HOST_WIDE_INT block;
634 
          block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
635 
          block <<= modesize - pos - len;
636 
 
637 
          *op0 = gen_rtx_AND (GET_MODE (inner), inner,
638 
                              gen_int_mode (block, GET_MODE (inner)));
639 
        }
640 
    }
641 
 
642 
  /* Narrow AND of memory against immediate to enable TM.  */
643 
  if ((*code == EQ || *code == NE)
644 
      && *op1 == const0_rtx
645 
      && GET_CODE (*op0) == AND
646 
      && GET_CODE (XEXP (*op0, 1)) == CONST_INT
647 
      && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
648 
    {
649 
      rtx inner = XEXP (*op0, 0);
650 
      rtx mask = XEXP (*op0, 1);
651 
 
652 
      /* Ignore paradoxical SUBREGs if all extra bits are masked out.  */
653 
      if (GET_CODE (inner) == SUBREG
654 
          && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
655 
          && (GET_MODE_SIZE (GET_MODE (inner))
656 
              >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
657 
          && ((INTVAL (mask)
658 
               & GET_MODE_MASK (GET_MODE (inner))
659 
               & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
660 
              == 0))
661 
        inner = SUBREG_REG (inner);
662 
 
663 
      /* Do not change volatile MEMs.  */
664 
      if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
665 
        {
666 
          int part = s390_single_part (XEXP (*op0, 1),
667 
                                       GET_MODE (inner), QImode, 0);
668 
          if (part >= 0)
669 
            {
670 
              mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
671 
              inner = adjust_address_nv (inner, QImode, part);
672 
              *op0 = gen_rtx_AND (QImode, inner, mask);
673 
            }
674 
        }
675 
    }
676 
 
677 
  /* Narrow comparisons against 0xffff to HImode if possible.  */
678 
  if ((*code == EQ || *code == NE)
679 
      && GET_CODE (*op1) == CONST_INT
680 
      && INTVAL (*op1) == 0xffff
681 
      && SCALAR_INT_MODE_P (GET_MODE (*op0))
682 
      && (nonzero_bits (*op0, GET_MODE (*op0))
683 
          & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
684 
    {
685 
      *op0 = gen_lowpart (HImode, *op0);
686 
      *op1 = constm1_rtx;
687 
    }
688 
 
689 
 
690 
  /* Remove redundant UNSPEC_CMPINT conversions if possible.  */
691 
  if (GET_CODE (*op0) == UNSPEC
692 
      && XINT (*op0, 1) == UNSPEC_CMPINT
693 
      && XVECLEN (*op0, 0) == 1
694 
      && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
695 
      && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
696 
      && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
697 
      && *op1 == const0_rtx)
698 
    {
699 
      enum rtx_code new_code = UNKNOWN;
700 
      switch (*code)
701 
        {
702 
          case EQ: new_code = EQ;  break;
703 
          case NE: new_code = NE;  break;
704 
          case LT: new_code = GTU; break;
705 
          case GT: new_code = LTU; break;
706 
          case LE: new_code = GEU; break;
707 
          case GE: new_code = LEU; break;
708 
          default: break;
709 
        }
710 
 
711 
      if (new_code != UNKNOWN)
712 
        {
713 
          *op0 = XVECEXP (*op0, 0, 0);
714 
          *code = new_code;
715 
        }
716 
    }
717 
 
718 
  /* Simplify cascaded EQ, NE with const0_rtx.  */
719 
  if ((*code == NE || *code == EQ)
720 
      && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
721 
      && GET_MODE (*op0) == SImode
722 
      && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
723 
      && REG_P (XEXP (*op0, 0))
724 
      && XEXP (*op0, 1) == const0_rtx
725 
      && *op1 == const0_rtx)
726 
    {
727 
      if ((*code == EQ && GET_CODE (*op0) == NE)
728 
          || (*code == NE && GET_CODE (*op0) == EQ))
729 
        *code = EQ;
730 
      else
731 
        *code = NE;
732 
      *op0 = XEXP (*op0, 0);
733 
    }
734 
 
735 
  /* Prefer register over memory as first operand.  */
736 
  if (MEM_P (*op0) && REG_P (*op1))
737 
    {
738 
      rtx tem = *op0; *op0 = *op1; *op1 = tem;
739 
      *code = swap_condition (*code);
740 
    }
741 
}
742 
 
743 
/* Emit a compare instruction suitable to implement the comparison
744 
   OP0 CODE OP1.  Return the correct condition RTL to be placed in
745 
   the IF_THEN_ELSE of the conditional branch testing the result.  */
746 
 
747 
rtx
748 
s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
749 
{
750 
  enum machine_mode mode = s390_select_ccmode (code, op0, op1);
751 
  rtx ret = NULL_RTX;
752 
 
753 
  /* Do not output a redundant compare instruction if a compare_and_swap
754 
     pattern already computed the result and the machine modes are compatible.  */
755 
  if (s390_compare_emitted
756 
      && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
757 
          == GET_MODE (s390_compare_emitted)))
758 
    ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
759 
  else
760 
    {
761 
      rtx cc = gen_rtx_REG (mode, CC_REGNUM);
762 
 
763 
      emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
764 
      ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
765 
    }
766 
  s390_compare_emitted = NULL_RTX;
767 
  return ret;
768 
}
769 
 
770 
/* Emit a jump instruction to TARGET.  If COND is NULL_RTX, emit an
771 
   unconditional jump, else a conditional jump under condition COND.  */
772 
 
773 
void
774 
s390_emit_jump (rtx target, rtx cond)
775 
{
776 
  rtx insn;
777 
 
778 
  target = gen_rtx_LABEL_REF (VOIDmode, target);
779 
  if (cond)
780 
    target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
781 
 
782 
  insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
783 
  emit_jump_insn (insn);
784 
}
785 
 
786 
/* Return branch condition mask to implement a branch
787 
   specified by CODE.  Return -1 for invalid comparisons.  */
788 
 
789 
int
790 
s390_branch_condition_mask (rtx code)
791 
{
792 
  const int CC0 = 1 << 3;
793 
  const int CC1 = 1 << 2;
794 
  const int CC2 = 1 << 1;
795 
  const int CC3 = 1 << 0;
796 
 
797 
  gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
798 
  gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
799 
  gcc_assert (XEXP (code, 1) == const0_rtx);
800 
 
801 
  switch (GET_MODE (XEXP (code, 0)))
802 
    {
803 
    case CCZmode:
804 
    case CCZ1mode:
805 
      switch (GET_CODE (code))
806 
        {
807 
        case EQ:        return CC0;
808 
        case NE:        return CC1 | CC2 | CC3;
809 
        default:        return -1;
810 
        }
811 
      break;
812 
 
813 
    case CCT1mode:
814 
      switch (GET_CODE (code))
815 
        {
816 
        case EQ:        return CC1;
817 
        case NE:        return CC0 | CC2 | CC3;
818 
        default:        return -1;
819 
        }
820 
      break;
821 
 
822 
    case CCT2mode:
823 
      switch (GET_CODE (code))
824 
        {
825 
        case EQ:        return CC2;
826 
        case NE:        return CC0 | CC1 | CC3;
827 
        default:        return -1;
828 
        }
829 
      break;
830 
 
831 
    case CCT3mode:
832 
      switch (GET_CODE (code))
833 
        {
834 
        case EQ:        return CC3;
835 
        case NE:        return CC0 | CC1 | CC2;
836 
        default:        return -1;
837 
        }
838 
      break;
839 
 
840 
    case CCLmode:
841 
      switch (GET_CODE (code))
842 
        {
843 
        case EQ:        return CC0 | CC2;
844 
        case NE:        return CC1 | CC3;
845 
        default:        return -1;
846 
        }
847 
      break;
848 
 
849 
    case CCL1mode:
850 
      switch (GET_CODE (code))
851 
        {
852 
        case LTU:       return CC2 | CC3;  /* carry */
853 
        case GEU:       return CC0 | CC1;  /* no carry */
854 
        default:        return -1;
855 
        }
856 
      break;
857 
 
858 
    case CCL2mode:
859 
      switch (GET_CODE (code))
860 
        {
861 
        case GTU:       return CC0 | CC1;  /* borrow */
862 
        case LEU:       return CC2 | CC3;  /* no borrow */
863 
        default:        return -1;
864 
        }
865 
      break;
866 
 
867 
    case CCL3mode:
868 
      switch (GET_CODE (code))
869 
        {
870 
        case EQ:        return CC0 | CC2;
871 
        case NE:        return CC1 | CC3;
872 
        case LTU:       return CC1;
873 
        case GTU:       return CC3;
874 
        case LEU:       return CC1 | CC2;
875 
        case GEU:       return CC2 | CC3;
876 
        default:        return -1;
877 
        }
878 
 
879 
    case CCUmode:
880 
      switch (GET_CODE (code))
881 
        {
882 
        case EQ:        return CC0;
883 
        case NE:        return CC1 | CC2 | CC3;
884 
        case LTU:       return CC1;
885 
        case GTU:       return CC2;
886 
        case LEU:       return CC0 | CC1;
887 
        case GEU:       return CC0 | CC2;
888 
        default:        return -1;
889 
        }
890 
      break;
891 
 
892 
    case CCURmode:
893 
      switch (GET_CODE (code))
894 
        {
895 
        case EQ:        return CC0;
896 
        case NE:        return CC2 | CC1 | CC3;
897 
        case LTU:       return CC2;
898 
        case GTU:       return CC1;
899 
        case LEU:       return CC0 | CC2;
900 
        case GEU:       return CC0 | CC1;
901 
        default:        return -1;
902 
        }
903 
      break;
904 
 
905 
    case CCAPmode:
906 
      switch (GET_CODE (code))
907 
        {
908 
        case EQ:        return CC0;
909 
        case NE:        return CC1 | CC2 | CC3;
910 
        case LT:        return CC1 | CC3;
911 
        case GT:        return CC2;
912 
        case LE:        return CC0 | CC1 | CC3;
913 
        case GE:        return CC0 | CC2;
914 
        default:        return -1;
915 
        }
916 
      break;
917 
 
918 
    case CCANmode:
919 
      switch (GET_CODE (code))
920 
        {
921 
        case EQ:        return CC0;
922 
        case NE:        return CC1 | CC2 | CC3;
923 
        case LT:        return CC1;
924 
        case GT:        return CC2 | CC3;
925 
        case LE:        return CC0 | CC1;
926 
        case GE:        return CC0 | CC2 | CC3;
927 
        default:        return -1;
928 
        }
929 
      break;
930 
 
931 
    case CCSmode:
932 
      switch (GET_CODE (code))
933 
        {
934 
        case EQ:        return CC0;
935 
        case NE:        return CC1 | CC2 | CC3;
936 
        case LT:        return CC1;
937 
        case GT:        return CC2;
938 
        case LE:        return CC0 | CC1;
939 
        case GE:        return CC0 | CC2;
940 
        case UNORDERED: return CC3;
941 
        case ORDERED:   return CC0 | CC1 | CC2;
942 
        case UNEQ:      return CC0 | CC3;
943 
        case UNLT:      return CC1 | CC3;
944 
        case UNGT:      return CC2 | CC3;
945 
        case UNLE:      return CC0 | CC1 | CC3;
946 
        case UNGE:      return CC0 | CC2 | CC3;
947 
        case LTGT:      return CC1 | CC2;
948 
        default:        return -1;
949 
        }
950 
      break;
951 
 
952 
    case CCSRmode:
953 
      switch (GET_CODE (code))
954 
        {
955 
        case EQ:        return CC0;
956 
        case NE:        return CC2 | CC1 | CC3;
957 
        case LT:        return CC2;
958 
        case GT:        return CC1;
959 
        case LE:        return CC0 | CC2;
960 
        case GE:        return CC0 | CC1;
961 
        case UNORDERED: return CC3;
962 
        case ORDERED:   return CC0 | CC2 | CC1;
963 
        case UNEQ:      return CC0 | CC3;
964 
        case UNLT:      return CC2 | CC3;
965 
        case UNGT:      return CC1 | CC3;
966 
        case UNLE:      return CC0 | CC2 | CC3;
967 
        case UNGE:      return CC0 | CC1 | CC3;
968 
        case LTGT:      return CC2 | CC1;
969 
        default:        return -1;
970 
        }
971 
      break;
972 
 
973 
    default:
974 
      return -1;
975 
    }
976 
}
977 
 
978 
/* If INV is false, return assembler mnemonic string to implement
979 
   a branch specified by CODE.  If INV is true, return mnemonic
980 
   for the corresponding inverted branch.  */
981 
 
982 
static const char *
983 
s390_branch_condition_mnemonic (rtx code, int inv)
984 
{
985 
  static const char *const mnemonic[16] =
986 
    {
987 
      NULL, "o", "h", "nle",
988 
      "l", "nhe", "lh", "ne",
989 
      "e", "nlh", "he", "nl",
990 
      "le", "nh", "no", NULL
991 
    };
992 
 
993 
  int mask = s390_branch_condition_mask (code);
994 
  gcc_assert (mask >= 0);
995 
 
996 
  if (inv)
997 
    mask ^= 15;
998 
 
999 
  gcc_assert (mask >= 1 && mask <= 14);
1000 
 
1001 
  return mnemonic[mask];
1002 
}
1003 
 
1004 
/* Return the part of op which has a value different from def.
1005 
   The size of the part is determined by mode.
1006 
   Use this function only if you already know that op really
1007 
   contains such a part.  */
1008 
 
1009 
unsigned HOST_WIDE_INT
1010 
s390_extract_part (rtx op, enum machine_mode mode, int def)
1011 
{
1012 
  unsigned HOST_WIDE_INT value = 0;
1013 
  int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1014 
  int part_bits = GET_MODE_BITSIZE (mode);
1015 
  unsigned HOST_WIDE_INT part_mask
1016 
    = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1017 
  int i;
1018 
 
1019 
  for (i = 0; i < max_parts; i++)
1020 
    {
1021 
      if (i == 0)
1022 
        value = (unsigned HOST_WIDE_INT) INTVAL (op);
1023 
      else
1024 
        value >>= part_bits;
1025 
 
1026 
      if ((value & part_mask) != (def & part_mask))
1027 
        return value & part_mask;
1028 
    }
1029 
 
1030 
  gcc_unreachable ();
1031 
}
1032 
 
1033 
/* If OP is an integer constant of mode MODE with exactly one
1034 
   part of mode PART_MODE unequal to DEF, return the number of that
1035 
   part. Otherwise, return -1.  */
1036 
 
1037 
int
1038 
s390_single_part (rtx op,
1039 
                  enum machine_mode mode,
1040 
                  enum machine_mode part_mode,
1041 
                  int def)
1042 
{
1043 
  unsigned HOST_WIDE_INT value = 0;
1044 
  int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1045 
  unsigned HOST_WIDE_INT part_mask
1046 
    = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1047 
  int i, part = -1;
1048 
 
1049 
  if (GET_CODE (op) != CONST_INT)
1050 
    return -1;
1051 
 
1052 
  for (i = 0; i < n_parts; i++)
1053 
    {
1054 
      if (i == 0)
1055 
        value = (unsigned HOST_WIDE_INT) INTVAL (op);
1056 
      else
1057 
        value >>= GET_MODE_BITSIZE (part_mode);
1058 
 
1059 
      if ((value & part_mask) != (def & part_mask))
1060 
        {
1061 
          if (part != -1)
1062 
            return -1;
1063 
          else
1064 
            part = i;
1065 
        }
1066 
    }
1067 
  return part == -1 ? -1 : n_parts - 1 - part;
1068 
}
1069 
 
1070 
/* Check whether we can (and want to) split a double-word
1071 
   move in mode MODE from SRC to DST into two single-word
1072 
   moves, moving the subword FIRST_SUBWORD first.  */
1073 
 
1074 
bool
1075 
s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1076 
{
1077 
  /* Floating point registers cannot be split.  */
1078 
  if (FP_REG_P (src) || FP_REG_P (dst))
1079 
    return false;
1080 
 
1081 
  /* We don't need to split if operands are directly accessible.  */
1082 
  if (s_operand (src, mode) || s_operand (dst, mode))
1083 
    return false;
1084 
 
1085 
  /* Non-offsettable memory references cannot be split.  */
1086 
  if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1087 
      || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1088 
    return false;
1089 
 
1090 
  /* Moving the first subword must not clobber a register
1091 
     needed to move the second subword.  */
1092 
  if (register_operand (dst, mode))
1093 
    {
1094 
      rtx subreg = operand_subword (dst, first_subword, 0, mode);
1095 
      if (reg_overlap_mentioned_p (subreg, src))
1096 
        return false;
1097 
    }
1098 
 
1099 
  return true;
1100 
}
1101 
 
1102 
/* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1103 
   and [MEM2, MEM2 + SIZE] do overlap and false
1104 
   otherwise.  */
1105 
 
1106 
bool
1107 
s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1108 
{
1109 
  rtx addr1, addr2, addr_delta;
1110 
  HOST_WIDE_INT delta;
1111 
 
1112 
  if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1113 
    return true;
1114 
 
1115 
  if (size == 0)
1116 
    return false;
1117 
 
1118 
  addr1 = XEXP (mem1, 0);
1119 
  addr2 = XEXP (mem2, 0);
1120 
 
1121 
  addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1122 
 
1123 
  /* This overlapping check is used by peepholes merging memory block operations.
1124 
     Overlapping operations would otherwise be recognized by the S/390 hardware
1125 
     and would fall back to a slower implementation. Allowing overlapping
1126 
     operations would lead to slow code but not to wrong code. Therefore we are
1127 
     somewhat optimistic if we cannot prove that the memory blocks are
1128 
     overlapping.
1129 
     That's why we return false here although this may accept operations on
1130 
     overlapping memory areas.  */
1131 
  if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1132 
    return false;
1133 
 
1134 
  delta = INTVAL (addr_delta);
1135 
 
1136 
  if (delta == 0
1137 
      || (delta > 0 && delta < size)
1138 
      || (delta < 0 && -delta < size))
1139 
    return true;
1140 
 
1141 
  return false;
1142 
}
1143 
 
1144 
/* Check whether the address of memory reference MEM2 equals exactly
1145 
   the address of memory reference MEM1 plus DELTA.  Return true if
1146 
   we can prove this to be the case, false otherwise.  */
1147 
 
1148 
bool
1149 
s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1150 
{
1151 
  rtx addr1, addr2, addr_delta;
1152 
 
1153 
  if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1154 
    return false;
1155 
 
1156 
  addr1 = XEXP (mem1, 0);
1157 
  addr2 = XEXP (mem2, 0);
1158 
 
1159 
  addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1160 
  if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1161 
    return false;
1162 
 
1163 
  return true;
1164 
}
1165 
 
1166 
/* Expand logical operator CODE in mode MODE with operands OPERANDS.  */
1167 
 
1168 
void
1169 
s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1170 
                              rtx *operands)
1171 
{
1172 
  enum machine_mode wmode = mode;
1173 
  rtx dst = operands[0];
1174 
  rtx src1 = operands[1];
1175 
  rtx src2 = operands[2];
1176 
  rtx op, clob, tem;
1177 
 
1178 
  /* If we cannot handle the operation directly, use a temp register.  */
1179 
  if (!s390_logical_operator_ok_p (operands))
1180 
    dst = gen_reg_rtx (mode);
1181 
 
1182 
  /* QImode and HImode patterns make sense only if we have a destination
1183 
     in memory.  Otherwise perform the operation in SImode.  */
1184 
  if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1185 
    wmode = SImode;
1186 
 
1187 
  /* Widen operands if required.  */
1188 
  if (mode != wmode)
1189 
    {
1190 
      if (GET_CODE (dst) == SUBREG
1191 
          && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1192 
        dst = tem;
1193 
      else if (REG_P (dst))
1194 
        dst = gen_rtx_SUBREG (wmode, dst, 0);
1195 
      else
1196 
        dst = gen_reg_rtx (wmode);
1197 
 
1198 
      if (GET_CODE (src1) == SUBREG
1199 
          && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1200 
        src1 = tem;
1201 
      else if (GET_MODE (src1) != VOIDmode)
1202 
        src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1203 
 
1204 
      if (GET_CODE (src2) == SUBREG
1205 
          && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1206 
        src2 = tem;
1207 
      else if (GET_MODE (src2) != VOIDmode)
1208 
        src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1209 
    }
1210 
 
1211 
  /* Emit the instruction.  */
1212 
  op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1213 
  clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1214 
  emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1215 
 
1216 
  /* Fix up the destination if needed.  */
1217 
  if (dst != operands[0])
1218 
    emit_move_insn (operands[0], gen_lowpart (mode, dst));
1219 
}
1220 
 
1221 
/* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR).  */
1222 
 
1223 
bool
1224 
s390_logical_operator_ok_p (rtx *operands)
1225 
{
1226 
  /* If the destination operand is in memory, it needs to coincide
1227 
     with one of the source operands.  After reload, it has to be
1228 
     the first source operand.  */
1229 
  if (GET_CODE (operands[0]) == MEM)
1230 
    return rtx_equal_p (operands[0], operands[1])
1231 
           || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1232 
 
1233 
  return true;
1234 
}
1235 
 
1236 
/* Narrow logical operation CODE of memory operand MEMOP with immediate
1237 
   operand IMMOP to switch from SS to SI type instructions.  */
1238 
 
1239 
void
1240 
s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1241 
{
1242 
  int def = code == AND ? -1 : 0;
1243 
  HOST_WIDE_INT mask;
1244 
  int part;
1245 
 
1246 
  gcc_assert (GET_CODE (*memop) == MEM);
1247 
  gcc_assert (!MEM_VOLATILE_P (*memop));
1248 
 
1249 
  mask = s390_extract_part (*immop, QImode, def);
1250 
  part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1251 
  gcc_assert (part >= 0);
1252 
 
1253 
  *memop = adjust_address (*memop, QImode, part);
1254 
  *immop = gen_int_mode (mask, QImode);
1255 
}
1256 
 
1257 
 
1258 
/* How to allocate a 'struct machine_function'.  */
1259 
 
1260 
static struct machine_function *
1261 
s390_init_machine_status (void)
1262 
{
1263 
  return ggc_alloc_cleared (sizeof (struct machine_function));
1264 
}
1265 
 
1266 
/* Change optimizations to be performed, depending on the
1267 
   optimization level.
1268 
 
1269 
   LEVEL is the optimization level specified; 2 if `-O2' is
1270 
   specified, 1 if `-O' is specified, and 0 if neither is specified.
1271 
 
1272 
   SIZE is nonzero if `-Os' is specified and zero otherwise.  */
1273 
 
1274 
void
1275 
optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1276 
{
1277 
  /* ??? There are apparently still problems with -fcaller-saves.  */
1278 
  flag_caller_saves = 0;
1279 
 
1280 
  /* By default, always emit DWARF-2 unwind info.  This allows debugging
1281 
     without maintaining a stack frame back-chain.  */
1282 
  flag_asynchronous_unwind_tables = 1;
1283 
 
1284 
  /* Use MVCLE instructions to decrease code size if requested.  */
1285 
  if (size != 0)
1286 
    target_flags |= MASK_MVCLE;
1287 
}
1288 
 
1289 
/* Return true if ARG is the name of a processor.  Set *TYPE and *FLAGS
1290 
   to the associated processor_type and processor_flags if so.  */
1291 
 
1292 
static bool
1293 
s390_handle_arch_option (const char *arg,
1294 
                         enum processor_type *type,
1295 
                         enum processor_flags *flags)
1296 
{
1297 
  static struct pta
1298 
    {
1299 
      const char *const name;           /* processor name or nickname.  */
1300 
      const enum processor_type processor;
1301 
      const enum processor_flags flags;
1302 
    }
1303 
  const processor_alias_table[] =
1304 
    {
1305 
      {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1306 
      {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1307 
      {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1308 
      {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1309 
                                    | PF_LONG_DISPLACEMENT},
1310 
      {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1311 
                                       | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1312 
    };
1313 
  size_t i;
1314 
 
1315 
  for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1316 
    if (strcmp (arg, processor_alias_table[i].name) == 0)
1317 
      {
1318 
        *type = processor_alias_table[i].processor;
1319 
        *flags = processor_alias_table[i].flags;
1320 
        return true;
1321 
      }
1322 
  return false;
1323 
}
1324 
 
1325 
/* Implement TARGET_HANDLE_OPTION.  */
1326 
 
1327 
static bool
1328 
s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1329 
{
1330 
  switch (code)
1331 
    {
1332 
    case OPT_march_:
1333 
      return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1334 
 
1335 
    case OPT_mstack_guard_:
1336 
      if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1337 
        return false;
1338 
      if (exact_log2 (s390_stack_guard) == -1)
1339 
        error ("stack guard value must be an exact power of 2");
1340 
      return true;
1341 
 
1342 
    case OPT_mstack_size_:
1343 
      if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1344 
        return false;
1345 
      if (exact_log2 (s390_stack_size) == -1)
1346 
        error ("stack size must be an exact power of 2");
1347 
      return true;
1348 
 
1349 
    case OPT_mtune_:
1350 
      return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1351 
 
1352 
    case OPT_mwarn_framesize_:
1353 
      return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1354 
 
1355 
    default:
1356 
      return true;
1357 
    }
1358 
}
1359 
 
1360 
void
1361 
override_options (void)
1362 
{
1363 
  /* Set up function hooks.  */
1364 
  init_machine_status = s390_init_machine_status;
1365 
 
1366 
  /* Architecture mode defaults according to ABI.  */
1367 
  if (!(target_flags_explicit & MASK_ZARCH))
1368 
    {
1369 
      if (TARGET_64BIT)
1370 
        target_flags |= MASK_ZARCH;
1371 
      else
1372 
        target_flags &= ~MASK_ZARCH;
1373 
    }
1374 
 
1375 
  /* Determine processor architectural level.  */
1376 
  if (!s390_arch_string)
1377 
    {
1378 
      s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1379 
      s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1380 
    }
1381 
 
1382 
  /* Determine processor to tune for.  */
1383 
  if (s390_tune == PROCESSOR_max)
1384 
    {
1385 
      s390_tune = s390_arch;
1386 
      s390_tune_flags = s390_arch_flags;
1387 
    }
1388 
 
1389 
  /* Sanity checks.  */
1390 
  if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
1391 
    error ("z/Architecture mode not supported on %s", s390_arch_string);
1392 
  if (TARGET_64BIT && !TARGET_ZARCH)
1393 
    error ("64-bit ABI not supported in ESA/390 mode");
1394 
 
1395 
  /* Set processor cost function.  */
1396 
  if (s390_tune == PROCESSOR_2094_Z9_109)
1397 
    s390_cost = &z9_109_cost;
1398 
  else if (s390_tune == PROCESSOR_2084_Z990)
1399 
    s390_cost = &z990_cost;
1400 
  else
1401 
    s390_cost = &z900_cost;
1402 
 
1403 
  if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1404 
    error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1405 
           "in combination");
1406 
 
1407 
  if (s390_stack_size)
1408 
    {
1409 
      if (!s390_stack_guard)
1410 
        error ("-mstack-size implies use of -mstack-guard");
1411 
      else if (s390_stack_guard >= s390_stack_size)
1412 
        error ("stack size must be greater than the stack guard value");
1413 
      else if (s390_stack_size > 1 << 16)
1414 
        error ("stack size must not be greater than 64k");
1415 
    }
1416 
  else if (s390_stack_guard)
1417 
    error ("-mstack-guard implies use of -mstack-size");
1418 
}
1419 
 
1420 
/* Map for smallest class containing reg regno.  */
1421 
 
1422 
const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1423 
{ GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1424 
  ADDR_REGS,    ADDR_REGS, ADDR_REGS, ADDR_REGS,
1425 
  ADDR_REGS,    ADDR_REGS, ADDR_REGS, ADDR_REGS,
1426 
  ADDR_REGS,    ADDR_REGS, ADDR_REGS, ADDR_REGS,
1427 
  FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
1428 
  FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
1429 
  FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
1430 
  FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
1431 
  ADDR_REGS,    CC_REGS,   ADDR_REGS, ADDR_REGS,
1432 
  ACCESS_REGS,  ACCESS_REGS
1433 
};
1434 
 
1435 
/* Return attribute type of insn.  */
1436 
 
1437 
static enum attr_type
1438 
s390_safe_attr_type (rtx insn)
1439 
{
1440 
  if (recog_memoized (insn) >= 0)
1441 
    return get_attr_type (insn);
1442 
  else
1443 
    return TYPE_NONE;
1444 
}
1445 
 
1446 
/* Return true if DISP is a valid short displacement.  */
1447 
 
1448 
static bool
1449 
s390_short_displacement (rtx disp)
1450 
{
1451 
  /* No displacement is OK.  */
1452 
  if (!disp)
1453 
    return true;
1454 
 
1455 
  /* Integer displacement in range.  */
1456 
  if (GET_CODE (disp) == CONST_INT)
1457 
    return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1458 
 
1459 
  /* GOT offset is not OK, the GOT can be large.  */
1460 
  if (GET_CODE (disp) == CONST
1461 
      && GET_CODE (XEXP (disp, 0)) == UNSPEC
1462 
      && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1463 
          || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1464 
    return false;
1465 
 
1466 
  /* All other symbolic constants are literal pool references,
1467 
     which are OK as the literal pool must be small.  */
1468 
  if (GET_CODE (disp) == CONST)
1469 
    return true;
1470 
 
1471 
  return false;
1472 
}
1473 
 
1474 
/* Decompose a RTL expression ADDR for a memory address into
1475 
   its components, returned in OUT.
1476 
 
1477 
   Returns false if ADDR is not a valid memory address, true
1478 
   otherwise.  If OUT is NULL, don't return the components,
1479 
   but check for validity only.
1480 
 
1481 
   Note: Only addresses in canonical form are recognized.
1482 
   LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1483 
   canonical form so that they will be recognized.  */
1484 
 
1485 
static int
1486 
s390_decompose_address (rtx addr, struct s390_address *out)
1487 
{
1488 
  HOST_WIDE_INT offset = 0;
1489 
  rtx base = NULL_RTX;
1490 
  rtx indx = NULL_RTX;
1491 
  rtx disp = NULL_RTX;
1492 
  rtx orig_disp;
1493 
  bool pointer = false;
1494 
  bool base_ptr = false;
1495 
  bool indx_ptr = false;
1496 
  bool literal_pool = false;
1497 
 
1498 
  /* We may need to substitute the literal pool base register into the address
1499 
     below.  However, at this point we do not know which register is going to
1500 
     be used as base, so we substitute the arg pointer register.  This is going
1501 
     to be treated as holding a pointer below -- it shouldn't be used for any
1502 
     other purpose.  */
1503 
  rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1504 
 
1505 
  /* Decompose address into base + index + displacement.  */
1506 
 
1507 
  if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1508 
    base = addr;
1509 
 
1510 
  else if (GET_CODE (addr) == PLUS)
1511 
    {
1512 
      rtx op0 = XEXP (addr, 0);
1513 
      rtx op1 = XEXP (addr, 1);
1514 
      enum rtx_code code0 = GET_CODE (op0);
1515 
      enum rtx_code code1 = GET_CODE (op1);
1516 
 
1517 
      if (code0 == REG || code0 == UNSPEC)
1518 
        {
1519 
          if (code1 == REG || code1 == UNSPEC)
1520 
            {
1521 
              indx = op0;       /* index + base */
1522 
              base = op1;
1523 
            }
1524 
 
1525 
          else
1526 
            {
1527 
              base = op0;       /* base + displacement */
1528 
              disp = op1;
1529 
            }
1530 
        }
1531 
 
1532 
      else if (code0 == PLUS)
1533 
        {
1534 
          indx = XEXP (op0, 0);  /* index + base + disp */
1535 
          base = XEXP (op0, 1);
1536 
          disp = op1;
1537 
        }
1538 
 
1539 
      else
1540 
        {
1541 
          return false;
1542 
        }
1543 
    }
1544 
 
1545 
  else
1546 
    disp = addr;                /* displacement */
1547 
 
1548 
  /* Extract integer part of displacement.  */
1549 
  orig_disp = disp;
1550 
  if (disp)
1551 
    {
1552 
      if (GET_CODE (disp) == CONST_INT)
1553 
        {
1554 
          offset = INTVAL (disp);
1555 
          disp = NULL_RTX;
1556 
        }
1557 
      else if (GET_CODE (disp) == CONST
1558 
               && GET_CODE (XEXP (disp, 0)) == PLUS
1559 
               && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1560 
        {
1561 
          offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1562 
          disp = XEXP (XEXP (disp, 0), 0);
1563 
        }
1564 
    }
1565 
 
1566 
  /* Strip off CONST here to avoid special case tests later.  */
1567 
  if (disp && GET_CODE (disp) == CONST)
1568 
    disp = XEXP (disp, 0);
1569 
 
1570 
  /* We can convert literal pool addresses to
1571 
     displacements by basing them off the base register.  */
1572 
  if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1573 
    {
1574 
      /* Either base or index must be free to hold the base register.  */
1575 
      if (!base)
1576 
        base = fake_pool_base, literal_pool = true;
1577 
      else if (!indx)
1578 
        indx = fake_pool_base, literal_pool = true;
1579 
      else
1580 
        return false;
1581 
 
1582 
      /* Mark up the displacement.  */
1583 
      disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1584 
                             UNSPEC_LTREL_OFFSET);
1585 
    }
1586 
 
1587 
  /* Validate base register.  */
1588 
  if (base)
1589 
    {
1590 
      if (GET_CODE (base) == UNSPEC)
1591 
        switch (XINT (base, 1))
1592 
          {
1593 
          case UNSPEC_LTREF:
1594 
            if (!disp)
1595 
              disp = gen_rtx_UNSPEC (Pmode,
1596 
                                     gen_rtvec (1, XVECEXP (base, 0, 0)),
1597 
                                     UNSPEC_LTREL_OFFSET);
1598 
            else
1599 
              return false;
1600 
 
1601 
            base = XVECEXP (base, 0, 1);
1602 
            break;
1603 
 
1604 
          case UNSPEC_LTREL_BASE:
1605 
            if (XVECLEN (base, 0) == 1)
1606 
              base = fake_pool_base, literal_pool = true;
1607 
            else
1608 
              base = XVECEXP (base, 0, 1);
1609 
            break;
1610 
 
1611 
          default:
1612 
            return false;
1613 
          }
1614 
 
1615 
      if (GET_CODE (base) != REG || GET_MODE (base) != Pmode)
1616 
        return false;
1617 
 
1618 
      if (REGNO (base) == STACK_POINTER_REGNUM
1619 
          || REGNO (base) == FRAME_POINTER_REGNUM
1620 
          || ((reload_completed || reload_in_progress)
1621 
              && frame_pointer_needed
1622 
              && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1623 
          || REGNO (base) == ARG_POINTER_REGNUM
1624 
          || (flag_pic
1625 
              && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1626 
        pointer = base_ptr = true;
1627 
 
1628 
      if ((reload_completed || reload_in_progress)
1629 
          && base == cfun->machine->base_reg)
1630 
        pointer = base_ptr = literal_pool = true;
1631 
    }
1632 
 
1633 
  /* Validate index register.  */
1634 
  if (indx)
1635 
    {
1636 
      if (GET_CODE (indx) == UNSPEC)
1637 
        switch (XINT (indx, 1))
1638 
          {
1639 
          case UNSPEC_LTREF:
1640 
            if (!disp)
1641 
              disp = gen_rtx_UNSPEC (Pmode,
1642 
                                     gen_rtvec (1, XVECEXP (indx, 0, 0)),
1643 
                                     UNSPEC_LTREL_OFFSET);
1644 
            else
1645 
              return false;
1646 
 
1647 
            indx = XVECEXP (indx, 0, 1);
1648 
            break;
1649 
 
1650 
          case UNSPEC_LTREL_BASE:
1651 
            if (XVECLEN (indx, 0) == 1)
1652 
              indx = fake_pool_base, literal_pool = true;
1653 
            else
1654 
              indx = XVECEXP (indx, 0, 1);
1655 
            break;
1656 
 
1657 
          default:
1658 
            return false;
1659 
          }
1660 
 
1661 
      if (GET_CODE (indx) != REG || GET_MODE (indx) != Pmode)
1662 
        return false;
1663 
 
1664 
      if (REGNO (indx) == STACK_POINTER_REGNUM
1665 
          || REGNO (indx) == FRAME_POINTER_REGNUM
1666 
          || ((reload_completed || reload_in_progress)
1667 
              && frame_pointer_needed
1668 
              && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1669 
          || REGNO (indx) == ARG_POINTER_REGNUM
1670 
          || (flag_pic
1671 
              && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1672 
        pointer = indx_ptr = true;
1673 
 
1674 
      if ((reload_completed || reload_in_progress)
1675 
          && indx == cfun->machine->base_reg)
1676 
        pointer = indx_ptr = literal_pool = true;
1677 
    }
1678 
 
1679 
  /* Prefer to use pointer as base, not index.  */
1680 
  if (base && indx && !base_ptr
1681 
      && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1682 
    {
1683 
      rtx tmp = base;
1684 
      base = indx;
1685 
      indx = tmp;
1686 
    }
1687 
 
1688 
  /* Validate displacement.  */
1689 
  if (!disp)
1690 
    {
1691 
      /* If virtual registers are involved, the displacement will change later
1692 
         anyway as the virtual registers get eliminated.  This could make a
1693 
         valid displacement invalid, but it is more likely to make an invalid
1694 
         displacement valid, because we sometimes access the register save area
1695 
         via negative offsets to one of those registers.
1696 
         Thus we don't check the displacement for validity here.  If after
1697 
         elimination the displacement turns out to be invalid after all,
1698 
         this is fixed up by reload in any case.  */
1699 
      if (base != arg_pointer_rtx
1700 
          && indx != arg_pointer_rtx
1701 
          && base != return_address_pointer_rtx
1702 
          && indx != return_address_pointer_rtx
1703 
          && base != frame_pointer_rtx
1704 
          && indx != frame_pointer_rtx
1705 
          && base != virtual_stack_vars_rtx
1706 
          && indx != virtual_stack_vars_rtx)
1707 
        if (!DISP_IN_RANGE (offset))
1708 
          return false;
1709 
    }
1710 
  else
1711 
    {
1712 
      /* All the special cases are pointers.  */
1713 
      pointer = true;
1714 
 
1715 
      /* In the small-PIC case, the linker converts @GOT
1716 
         and @GOTNTPOFF offsets to possible displacements.  */
1717 
      if (GET_CODE (disp) == UNSPEC
1718 
          && (XINT (disp, 1) == UNSPEC_GOT
1719 
              || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1720 
          && offset == 0
1721 
          && flag_pic == 1)
1722 
        {
1723 
          ;
1724 
        }
1725 
 
1726 
      /* Accept chunkified literal pool symbol references.  */
1727 
      else if (cfun && cfun->machine
1728 
               && cfun->machine->decomposed_literal_pool_addresses_ok_p
1729 
               && GET_CODE (disp) == MINUS
1730 
               && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1731 
               && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1732 
        {
1733 
          ;
1734 
        }
1735 
 
1736 
      /* Accept literal pool references.  */
1737 
      else if (GET_CODE (disp) == UNSPEC
1738 
               && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1739 
        {
1740 
          orig_disp = gen_rtx_CONST (Pmode, disp);
1741 
          if (offset)
1742 
            {
1743 
              /* If we have an offset, make sure it does not
1744 
                 exceed the size of the constant pool entry.  */
1745 
              rtx sym = XVECEXP (disp, 0, 0);
1746 
              if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1747 
                return false;
1748 
 
1749 
              orig_disp = plus_constant (orig_disp, offset);
1750 
            }
1751 
        }
1752 
 
1753 
      else
1754 
        return false;
1755 
    }
1756 
 
1757 
  if (!base && !indx)
1758 
    pointer = true;
1759 
 
1760 
  if (out)
1761 
    {
1762 
      out->base = base;
1763 
      out->indx = indx;
1764 
      out->disp = orig_disp;
1765 
      out->pointer = pointer;
1766 
      out->literal_pool = literal_pool;
1767 
    }
1768 
 
1769 
  return true;
1770 
}
1771 
 
1772 
/* Decompose a RTL expression OP for a shift count into its components,
1773 
   and return the base register in BASE and the offset in OFFSET.
1774 
 
1775 
   Return true if OP is a valid shift count, false if not.  */
1776 
 
1777 
bool
1778 
s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1779 
{
1780 
  HOST_WIDE_INT off = 0;
1781 
 
1782 
  /* We can have an integer constant, an address register,
1783 
     or a sum of the two.  */
1784 
  if (GET_CODE (op) == CONST_INT)
1785 
    {
1786 
      off = INTVAL (op);
1787 
      op = NULL_RTX;
1788 
    }
1789 
  if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
1790 
    {
1791 
      off = INTVAL (XEXP (op, 1));
1792 
      op = XEXP (op, 0);
1793 
    }
1794 
  while (op && GET_CODE (op) == SUBREG)
1795 
    op = SUBREG_REG (op);
1796 
 
1797 
  if (op && GET_CODE (op) != REG)
1798 
    return false;
1799 
 
1800 
  if (offset)
1801 
    *offset = off;
1802 
  if (base)
1803 
    *base = op;
1804 
 
1805 
   return true;
1806 
}
1807 
 
1808 
 
1809 
/* Return true if CODE is a valid address without index.  */
1810 
 
1811 
bool
1812 
s390_legitimate_address_without_index_p (rtx op)
1813 
{
1814 
  struct s390_address addr;
1815 
 
1816 
  if (!s390_decompose_address (XEXP (op, 0), &addr))
1817 
    return false;
1818 
  if (addr.indx)
1819 
    return false;
1820 
 
1821 
  return true;
1822 
}
1823 
 
1824 
/* Return 1 if OP is a valid operand for a C constraint, 0 else.  */
1825 
 
1826 
int
1827 
s390_extra_constraint_str (rtx op, int c, const char * str)
1828 
{
1829 
  struct s390_address addr;
1830 
 
1831 
  gcc_assert (c == str[0]);
1832 
 
1833 
  /* Check for offsettable variants of memory constraints.  */
1834 
  if (c == 'A')
1835 
    {
1836 
      /* Only accept non-volatile MEMs.  */
1837 
      if (!MEM_P (op) || MEM_VOLATILE_P (op))
1838 
        return 0;
1839 
 
1840 
      if ((reload_completed || reload_in_progress)
1841 
          ? !offsettable_memref_p (op)
1842 
          : !offsettable_nonstrict_memref_p (op))
1843 
        return 0;
1844 
 
1845 
      c = str[1];
1846 
    }
1847 
 
1848 
  /* Check for non-literal-pool variants of memory constraints.  */
1849 
  else if (c == 'B')
1850 
    {
1851 
      if (GET_CODE (op) != MEM)
1852 
        return 0;
1853 
      if (!s390_decompose_address (XEXP (op, 0), &addr))
1854 
        return 0;
1855 
      if (addr.literal_pool)
1856 
        return 0;
1857 
 
1858 
      c = str[1];
1859 
    }
1860 
 
1861 
  switch (c)
1862 
    {
1863 
    case 'Q':
1864 
      if (GET_CODE (op) != MEM)
1865 
        return 0;
1866 
      if (!s390_decompose_address (XEXP (op, 0), &addr))
1867 
        return 0;
1868 
      if (addr.indx)
1869 
        return 0;
1870 
 
1871 
      if (TARGET_LONG_DISPLACEMENT)
1872 
        {
1873 
          if (!s390_short_displacement (addr.disp))
1874 
            return 0;
1875 
        }
1876 
      break;
1877 
 
1878 
    case 'R':
1879 
      if (GET_CODE (op) != MEM)
1880 
        return 0;
1881 
 
1882 
      if (TARGET_LONG_DISPLACEMENT)
1883 
        {
1884 
          if (!s390_decompose_address (XEXP (op, 0), &addr))
1885 
            return 0;
1886 
          if (!s390_short_displacement (addr.disp))
1887 
            return 0;
1888 
        }
1889 
      break;
1890 
 
1891 
    case 'S':
1892 
      if (!TARGET_LONG_DISPLACEMENT)
1893 
        return 0;
1894 
      if (GET_CODE (op) != MEM)
1895 
        return 0;
1896 
      if (!s390_decompose_address (XEXP (op, 0), &addr))
1897 
        return 0;
1898 
      if (addr.indx)
1899 
        return 0;
1900 
      if (s390_short_displacement (addr.disp))
1901 
        return 0;
1902 
      break;
1903 
 
1904 
    case 'T':
1905 
      if (!TARGET_LONG_DISPLACEMENT)
1906 
        return 0;
1907 
      if (GET_CODE (op) != MEM)
1908 
        return 0;
1909 
      /* Any invalid address here will be fixed up by reload,
1910 
         so accept it for the most generic constraint.  */
1911 
      if (s390_decompose_address (XEXP (op, 0), &addr)
1912 
          && s390_short_displacement (addr.disp))
1913 
        return 0;
1914 
      break;
1915 
 
1916 
    case 'U':
1917 
      if (TARGET_LONG_DISPLACEMENT)
1918 
        {
1919 
          if (!s390_decompose_address (op, &addr))
1920 
            return 0;
1921 
          if (!s390_short_displacement (addr.disp))
1922 
            return 0;
1923 
        }
1924 
      break;
1925 
 
1926 
    case 'W':
1927 
      if (!TARGET_LONG_DISPLACEMENT)
1928 
        return 0;
1929 
      /* Any invalid address here will be fixed up by reload,
1930 
         so accept it for the most generic constraint.  */
1931 
      if (s390_decompose_address (op, &addr)
1932 
          && s390_short_displacement (addr.disp))
1933 
        return 0;
1934 
      break;
1935 
 
1936 
    case 'Y':
1937 
      /* Simply check for the basic form of a shift count.  Reload will
1938 
         take care of making sure we have a proper base register.  */
1939 
      if (!s390_decompose_shift_count (op, NULL, NULL))
1940 
        return 0;
1941 
      break;
1942 
 
1943 
    default:
1944 
      return 0;
1945 
    }
1946 
 
1947 
  return 1;
1948 
}
1949 
 
1950 
/* Return true if VALUE matches the constraint STR.  */
1951 
 
1952 
int
1953 
s390_const_double_ok_for_constraint_p (rtx value,
1954 
                                       int c,
1955 
                                       const char * str)
1956 
{
1957 
  gcc_assert (c == str[0]);
1958 
 
1959 
  switch (str[0])
1960 
    {
1961 
    case 'G':
1962 
      /* The floating point zero constant.  */
1963 
      return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1964 
              && value == CONST0_RTX (GET_MODE (value)));
1965 
 
1966 
    default:
1967 
      return 0;
1968 
    }
1969 
}
1970 
 
1971 
/* Return true if VALUE matches the constraint STR.  */
1972 
 
1973 
int
1974 
s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
1975 
                                int c,
1976 
                                const char * str)
1977 
{
1978 
  enum machine_mode mode, part_mode;
1979 
  int def;
1980 
  int part, part_goal;
1981 
 
1982 
  gcc_assert (c == str[0]);
1983 
 
1984 
  switch (str[0])
1985 
    {
1986 
    case 'I':
1987 
      return (unsigned int)value < 256;
1988 
 
1989 
    case 'J':
1990 
      return (unsigned int)value < 4096;
1991 
 
1992 
    case 'K':
1993 
      return value >= -32768 && value < 32768;
1994 
 
1995 
    case 'L':
1996 
      return (TARGET_LONG_DISPLACEMENT ?
1997 
              (value >= -524288 && value <= 524287)
1998 
              : (value >= 0 && value <= 4095));
1999 
    case 'M':
2000 
      return value == 2147483647;
2001 
 
2002 
    case 'N':
2003 
      if (str[1] == 'x')
2004 
        part_goal = -1;
2005 
      else
2006 
        part_goal = str[1] - '0';
2007 
 
2008 
      switch (str[2])
2009 
        {
2010 
        case 'Q': part_mode = QImode; break;
2011 
        case 'H': part_mode = HImode; break;
2012 
        case 'S': part_mode = SImode; break;
2013 
        default:  return 0;
2014 
        }
2015 
 
2016 
      switch (str[3])
2017 
        {
2018 
        case 'H': mode = HImode; break;
2019 
        case 'S': mode = SImode; break;
2020 
        case 'D': mode = DImode; break;
2021 
        default: return 0;
2022 
        }
2023 
 
2024 
      switch (str[4])
2025 
        {
2026 
        case '0': def = 0;  break;
2027 
        case 'F': def = -1; break;
2028 
        default: return 0;
2029 
        }
2030 
 
2031 
      if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2032 
        return 0;
2033 
 
2034 
      part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2035 
      if (part < 0)
2036 
        return 0;
2037 
      if (part_goal != -1 && part_goal != part)
2038 
        return 0;
2039 
 
2040 
      break;
2041 
 
2042 
    case 'O':
2043 
      if (!TARGET_EXTIMM)
2044 
        return 0;
2045 
 
2046 
      switch (str[1])
2047 
        {
2048 
        case 's':
2049 
          return trunc_int_for_mode (value, SImode) == value;
2050 
 
2051 
        case 'p':
2052 
          return value == 0
2053 
            || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2054 
 
2055 
        case 'n':
2056 
          return
2057 
            (value == -1
2058 
             || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1)
2059 
            && value != -((HOST_WIDE_INT)1 << 32);
2060 
 
2061 
        default:
2062 
          gcc_unreachable ();
2063 
        }
2064 
      break;
2065 
 
2066 
    case 'P':
2067 
      return legitimate_reload_constant_p (GEN_INT (value));
2068 
 
2069 
    default:
2070 
      return 0;
2071 
    }
2072 
 
2073 
  return 1;
2074 
}
2075 
 
2076 
/* Compute a (partial) cost for rtx X.  Return true if the complete
2077 
   cost has been computed, and false if subexpressions should be
2078 
   scanned.  In either case, *TOTAL contains the cost result.
2079 
   CODE contains GET_CODE (x), OUTER_CODE contains the code
2080 
   of the superexpression of x.  */
2081 
 
2082 
static bool
2083 
s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2084 
{
2085 
  switch (code)
2086 
    {
2087 
    case CONST:
2088 
    case CONST_INT:
2089 
    case LABEL_REF:
2090 
    case SYMBOL_REF:
2091 
    case CONST_DOUBLE:
2092 
    case MEM:
2093 
      *total = 0;
2094 
      return true;
2095 
 
2096 
    case ASHIFT:
2097 
    case ASHIFTRT:
2098 
    case LSHIFTRT:
2099 
    case ROTATE:
2100 
    case ROTATERT:
2101 
    case AND:
2102 
    case IOR:
2103 
    case XOR:
2104 
    case NEG:
2105 
    case NOT:
2106 
      *total = COSTS_N_INSNS (1);
2107 
      return false;
2108 
 
2109 
    case PLUS:
2110 
    case MINUS:
2111 
      /* Check for multiply and add.  */
2112 
      if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2113 
          && GET_CODE (XEXP (x, 0)) == MULT
2114 
          && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2115 
        {
2116 
          /* This is the multiply and add case.  */
2117 
          if (GET_MODE (x) == DFmode)
2118 
            *total = s390_cost->madbr;
2119 
          else
2120 
            *total = s390_cost->maebr;
2121 
          *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2122 
            + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2123 
            + rtx_cost (XEXP (x, 1), code);
2124 
          return true;  /* Do not do an additional recursive descent.  */
2125 
        }
2126 
      *total = COSTS_N_INSNS (1);
2127 
      return false;
2128 
 
2129 
    case MULT:
2130 
      switch (GET_MODE (x))
2131 
        {
2132 
        case SImode:
2133 
          {
2134 
            rtx left = XEXP (x, 0);
2135 
            rtx right = XEXP (x, 1);
2136 
            if (GET_CODE (right) == CONST_INT
2137 
                && CONST_OK_FOR_K (INTVAL (right)))
2138 
              *total = s390_cost->mhi;
2139 
            else if (GET_CODE (left) == SIGN_EXTEND)
2140 
              *total = s390_cost->mh;
2141 
            else
2142 
              *total = s390_cost->ms;  /* msr, ms, msy */
2143 
            break;
2144 
          }
2145 
        case DImode:
2146 
          {
2147 
            rtx left = XEXP (x, 0);
2148 
            rtx right = XEXP (x, 1);
2149 
            if (TARGET_64BIT)
2150 
              {
2151 
                if (GET_CODE (right) == CONST_INT
2152 
                    && CONST_OK_FOR_K (INTVAL (right)))
2153 
                  *total = s390_cost->mghi;
2154 
                else if (GET_CODE (left) == SIGN_EXTEND)
2155 
                  *total = s390_cost->msgf;
2156 
                else
2157 
                  *total = s390_cost->msg;  /* msgr, msg */
2158 
              }
2159 
            else /* TARGET_31BIT */
2160 
              {
2161 
                if (GET_CODE (left) == SIGN_EXTEND
2162 
                    && GET_CODE (right) == SIGN_EXTEND)
2163 
                  /* mulsidi case: mr, m */
2164 
                  *total = s390_cost->m;
2165 
                else if (GET_CODE (left) == ZERO_EXTEND
2166 
                         && GET_CODE (right) == ZERO_EXTEND
2167 
                         && TARGET_CPU_ZARCH)
2168 
                  /* umulsidi case: ml, mlr */
2169 
                  *total = s390_cost->ml;
2170 
                else
2171 
                  /* Complex calculation is required.  */
2172 
                  *total = COSTS_N_INSNS (40);
2173 
              }
2174 
            break;
2175 
          }
2176 
        case SFmode:
2177 
        case DFmode:
2178 
          *total = s390_cost->mult_df;
2179 
          break;
2180 
        case TFmode:
2181 
          *total = s390_cost->mxbr;
2182 
          break;
2183 
        default:
2184 
          return false;
2185 
        }
2186 
      return false;
2187 
 
2188 
    case UDIV:
2189 
    case UMOD:
2190 
      if (GET_MODE (x) == TImode)              /* 128 bit division */
2191 
        *total = s390_cost->dlgr;
2192 
      else if (GET_MODE (x) == DImode)
2193 
        {
2194 
          rtx right = XEXP (x, 1);
2195 
          if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2196 
            *total = s390_cost->dlr;
2197 
          else                                 /* 64 by 64 bit division */
2198 
            *total = s390_cost->dlgr;
2199 
        }
2200 
      else if (GET_MODE (x) == SImode)         /* 32 bit division */
2201 
        *total = s390_cost->dlr;
2202 
      return false;
2203 
 
2204 
    case DIV:
2205 
    case MOD:
2206 
      if (GET_MODE (x) == DImode)
2207 
        {
2208 
          rtx right = XEXP (x, 1);
2209 
          if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2210 
            if (TARGET_64BIT)
2211 
              *total = s390_cost->dsgfr;
2212 
            else
2213 
              *total = s390_cost->dr;
2214 
          else                                 /* 64 by 64 bit division */
2215 
            *total = s390_cost->dsgr;
2216 
        }
2217 
      else if (GET_MODE (x) == SImode)         /* 32 bit division */
2218 
        *total = s390_cost->dlr;
2219 
      else if (GET_MODE (x) == SFmode)
2220 
        {
2221 
          if (TARGET_IEEE_FLOAT)
2222 
            *total = s390_cost->debr;
2223 
          else /* TARGET_IBM_FLOAT */
2224 
            *total = s390_cost->der;
2225 
        }
2226 
      else if (GET_MODE (x) == DFmode)
2227 
        {
2228 
          if (TARGET_IEEE_FLOAT)
2229 
            *total = s390_cost->ddbr;
2230 
          else /* TARGET_IBM_FLOAT */
2231 
            *total = s390_cost->ddr;
2232 
        }
2233 
      else if (GET_MODE (x) == TFmode)
2234 
        {
2235 
          if (TARGET_IEEE_FLOAT)
2236 
            *total = s390_cost->dxbr;
2237 
          else /* TARGET_IBM_FLOAT */
2238 
            *total = s390_cost->dxr;
2239 
        }
2240 
      return false;
2241 
 
2242 
    case SQRT:
2243 
      if (GET_MODE (x) == SFmode)
2244 
        *total = s390_cost->sqebr;
2245 
      else if (GET_MODE (x) == DFmode)
2246 
        *total = s390_cost->sqdbr;
2247 
      else /* TFmode */
2248 
        *total = s390_cost->sqxbr;
2249 
      return false;
2250 
 
2251 
    case SIGN_EXTEND:
2252 
    case ZERO_EXTEND:
2253 
      if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2254 
          || outer_code == PLUS || outer_code == MINUS
2255 
          || outer_code == COMPARE)
2256 
        *total = 0;
2257 
      return false;
2258 
 
2259 
    case COMPARE:
2260 
      *total = COSTS_N_INSNS (1);
2261 
      if (GET_CODE (XEXP (x, 0)) == AND
2262 
          && GET_CODE (XEXP (x, 1)) == CONST_INT
2263 
          && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2264 
        {
2265 
          rtx op0 = XEXP (XEXP (x, 0), 0);
2266 
          rtx op1 = XEXP (XEXP (x, 0), 1);
2267 
          rtx op2 = XEXP (x, 1);
2268 
 
2269 
          if (memory_operand (op0, GET_MODE (op0))
2270 
              && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2271 
            return true;
2272 
          if (register_operand (op0, GET_MODE (op0))
2273 
              && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2274 
            return true;
2275 
        }
2276 
      return false;
2277 
 
2278 
    default:
2279 
      return false;
2280 
    }
2281 
}
2282 
 
2283 
/* Return the cost of an address rtx ADDR.  */
2284 
 
2285 
static int
2286 
s390_address_cost (rtx addr)
2287 
{
2288 
  struct s390_address ad;
2289 
  if (!s390_decompose_address (addr, &ad))
2290 
    return 1000;
2291 
 
2292 
  return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2293 
}
2294 
 
2295 
/* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2296 
   otherwise return 0.  */
2297 
 
2298 
int
2299 
tls_symbolic_operand (rtx op)
2300 
{
2301 
  if (GET_CODE (op) != SYMBOL_REF)
2302 
    return 0;
2303 
  return SYMBOL_REF_TLS_MODEL (op);
2304 
}
2305 
 
2306 
/* Split DImode access register reference REG (on 64-bit) into its constituent
2307 
   low and high parts, and store them into LO and HI.  Note that gen_lowpart/
2308 
   gen_highpart cannot be used as they assume all registers are word-sized,
2309 
   while our access registers have only half that size.  */
2310 
 
2311 
void
2312 
s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2313 
{
2314 
  gcc_assert (TARGET_64BIT);
2315 
  gcc_assert (ACCESS_REG_P (reg));
2316 
  gcc_assert (GET_MODE (reg) == DImode);
2317 
  gcc_assert (!(REGNO (reg) & 1));
2318 
 
2319 
  *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2320 
  *hi = gen_rtx_REG (SImode, REGNO (reg));
2321 
}
2322 
 
2323 
/* Return true if OP contains a symbol reference */
2324 
 
2325 
bool
2326 
symbolic_reference_mentioned_p (rtx op)
2327 
{
2328 
  const char *fmt;
2329 
  int i;
2330 
 
2331 
  if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2332 
    return 1;
2333 
 
2334 
  fmt = GET_RTX_FORMAT (GET_CODE (op));
2335 
  for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2336 
    {
2337 
      if (fmt[i] == 'E')
2338 
        {
2339 
          int j;
2340 
 
2341 
          for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2342 
            if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2343 
              return 1;
2344 
        }
2345 
 
2346 
      else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2347 
        return 1;
2348 
    }
2349 
 
2350 
  return 0;
2351 
}
2352 
 
2353 
/* Return true if OP contains a reference to a thread-local symbol.  */
2354 
 
2355 
bool
2356 
tls_symbolic_reference_mentioned_p (rtx op)
2357 
{
2358 
  const char *fmt;
2359 
  int i;
2360 
 
2361 
  if (GET_CODE (op) == SYMBOL_REF)
2362 
    return tls_symbolic_operand (op);
2363 
 
2364 
  fmt = GET_RTX_FORMAT (GET_CODE (op));
2365 
  for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2366 
    {
2367 
      if (fmt[i] == 'E')
2368 
        {
2369 
          int j;
2370 
 
2371 
          for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2372 
            if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2373 
              return true;
2374 
        }
2375 
 
2376 
      else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2377 
        return true;
2378 
    }
2379 
 
2380 
  return false;
2381 
}
2382 
 
2383 
 
2384 
/* Return true if OP is a legitimate general operand when
2385 
   generating PIC code.  It is given that flag_pic is on
2386 
   and that OP satisfies CONSTANT_P or is a CONST_DOUBLE.  */
2387 
 
2388 
int
2389 
legitimate_pic_operand_p (rtx op)
2390 
{
2391 
  /* Accept all non-symbolic constants.  */
2392 
  if (!SYMBOLIC_CONST (op))
2393 
    return 1;
2394 
 
2395 
  /* Reject everything else; must be handled
2396 
     via emit_symbolic_move.  */
2397 
  return 0;
2398 
}
2399 
 
2400 
/* Returns true if the constant value OP is a legitimate general operand.
2401 
   It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE.  */
2402 
 
2403 
int
2404 
legitimate_constant_p (rtx op)
2405 
{
2406 
  /* Accept all non-symbolic constants.  */
2407 
  if (!SYMBOLIC_CONST (op))
2408 
    return 1;
2409 
 
2410 
  /* Accept immediate LARL operands.  */
2411 
  if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2412 
    return 1;
2413 
 
2414 
  /* Thread-local symbols are never legal constants.  This is
2415 
     so that emit_call knows that computing such addresses
2416 
     might require a function call.  */
2417 
  if (TLS_SYMBOLIC_CONST (op))
2418 
    return 0;
2419 
 
2420 
  /* In the PIC case, symbolic constants must *not* be
2421 
     forced into the literal pool.  We accept them here,
2422 
     so that they will be handled by emit_symbolic_move.  */
2423 
  if (flag_pic)
2424 
    return 1;
2425 
 
2426 
  /* All remaining non-PIC symbolic constants are
2427 
     forced into the literal pool.  */
2428 
  return 0;
2429 
}
2430 
 
2431 
/* Determine if it's legal to put X into the constant pool.  This
2432 
   is not possible if X contains the address of a symbol that is
2433 
   not constant (TLS) or not known at final link time (PIC).  */
2434 
 
2435 
static bool
2436 
s390_cannot_force_const_mem (rtx x)
2437 
{
2438 
  switch (GET_CODE (x))
2439 
    {
2440 
    case CONST_INT:
2441 
    case CONST_DOUBLE:
2442 
      /* Accept all non-symbolic constants.  */
2443 
      return false;
2444 
 
2445 
    case LABEL_REF:
2446 
      /* Labels are OK iff we are non-PIC.  */
2447 
      return flag_pic != 0;
2448 
 
2449 
    case SYMBOL_REF:
2450 
      /* 'Naked' TLS symbol references are never OK,
2451 
         non-TLS symbols are OK iff we are non-PIC.  */
2452 
      if (tls_symbolic_operand (x))
2453 
        return true;
2454 
      else
2455 
        return flag_pic != 0;
2456 
 
2457 
    case CONST:
2458 
      return s390_cannot_force_const_mem (XEXP (x, 0));
2459 
    case PLUS:
2460 
    case MINUS:
2461 
      return s390_cannot_force_const_mem (XEXP (x, 0))
2462 
             || s390_cannot_force_const_mem (XEXP (x, 1));
2463 
 
2464 
    case UNSPEC:
2465 
      switch (XINT (x, 1))
2466 
        {
2467 
        /* Only lt-relative or GOT-relative UNSPECs are OK.  */
2468 
        case UNSPEC_LTREL_OFFSET:
2469 
        case UNSPEC_GOT:
2470 
        case UNSPEC_GOTOFF:
2471 
        case UNSPEC_PLTOFF:
2472 
        case UNSPEC_TLSGD:
2473 
        case UNSPEC_TLSLDM:
2474 
        case UNSPEC_NTPOFF:
2475 
        case UNSPEC_DTPOFF:
2476 
        case UNSPEC_GOTNTPOFF:
2477 
        case UNSPEC_INDNTPOFF:
2478 
          return false;
2479 
 
2480 
        /* If the literal pool shares the code section, be put
2481 
           execute template placeholders into the pool as well.  */
2482 
        case UNSPEC_INSN:
2483 
          return TARGET_CPU_ZARCH;
2484 
 
2485 
        default:
2486 
          return true;
2487 
        }
2488 
      break;
2489 
 
2490 
    default:
2491 
      gcc_unreachable ();
2492 
    }
2493 
}
2494 
 
2495 
/* Returns true if the constant value OP is a legitimate general
2496 
   operand during and after reload.  The difference to
2497 
   legitimate_constant_p is that this function will not accept
2498 
   a constant that would need to be forced to the literal pool
2499 
   before it can be used as operand.  */
2500 
 
2501 
bool
2502 
legitimate_reload_constant_p (rtx op)
2503 
{
2504 
  /* Accept la(y) operands.  */
2505 
  if (GET_CODE (op) == CONST_INT
2506 
      && DISP_IN_RANGE (INTVAL (op)))
2507 
    return true;
2508 
 
2509 
  /* Accept l(g)hi/l(g)fi operands.  */
2510 
  if (GET_CODE (op) == CONST_INT
2511 
      && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2512 
    return true;
2513 
 
2514 
  /* Accept lliXX operands.  */
2515 
  if (TARGET_ZARCH
2516 
      && GET_CODE (op) == CONST_INT
2517 
      && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2518 
      && s390_single_part (op, word_mode, HImode, 0) >= 0)
2519 
  return true;
2520 
 
2521 
  if (TARGET_EXTIMM
2522 
      && GET_CODE (op) == CONST_INT
2523 
      && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2524 
      && s390_single_part (op, word_mode, SImode, 0) >= 0)
2525 
    return true;
2526 
 
2527 
  /* Accept larl operands.  */
2528 
  if (TARGET_CPU_ZARCH
2529 
      && larl_operand (op, VOIDmode))
2530 
    return true;
2531 
 
2532 
  /* Accept lzXX operands.  */
2533 
  if (GET_CODE (op) == CONST_DOUBLE
2534 
      && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2535 
    return true;
2536 
 
2537 
  /* Accept double-word operands that can be split.  */
2538 
  if (GET_CODE (op) == CONST_INT
2539 
      && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2540 
    {
2541 
      enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2542 
      rtx hi = operand_subword (op, 0, 0, dword_mode);
2543 
      rtx lo = operand_subword (op, 1, 0, dword_mode);
2544 
      return legitimate_reload_constant_p (hi)
2545 
             && legitimate_reload_constant_p (lo);
2546 
    }
2547 
 
2548 
  /* Everything else cannot be handled without reload.  */
2549 
  return false;
2550 
}
2551 
 
2552 
/* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2553 
   return the class of reg to actually use.  */
2554 
 
2555 
enum reg_class
2556 
s390_preferred_reload_class (rtx op, enum reg_class class)
2557 
{
2558 
  switch (GET_CODE (op))
2559 
    {
2560 
      /* Constants we cannot reload must be forced into the
2561 
         literal pool.  */
2562 
 
2563 
      case CONST_DOUBLE:
2564 
      case CONST_INT:
2565 
        if (legitimate_reload_constant_p (op))
2566 
          return class;
2567 
        else
2568 
          return NO_REGS;
2569 
 
2570 
      /* If a symbolic constant or a PLUS is reloaded,
2571 
         it is most likely being used as an address, so
2572 
         prefer ADDR_REGS.  If 'class' is not a superset
2573 
         of ADDR_REGS, e.g. FP_REGS, reject this reload.  */
2574 
      case PLUS:
2575 
      case LABEL_REF:
2576 
      case SYMBOL_REF:
2577 
      case CONST:
2578 
        if (reg_class_subset_p (ADDR_REGS, class))
2579 
          return ADDR_REGS;
2580 
        else
2581 
          return NO_REGS;
2582 
 
2583 
      default:
2584 
        break;
2585 
    }
2586 
 
2587 
  return class;
2588 
}
2589 
 
2590 
/* Return the register class of a scratch register needed to
2591 
   load IN into a register of class CLASS in MODE.
2592 
 
2593 
   We need a temporary when loading a PLUS expression which
2594 
   is not a legitimate operand of the LOAD ADDRESS instruction.  */
2595 
 
2596 
enum reg_class
2597 
s390_secondary_input_reload_class (enum reg_class class,
2598 
                                   enum machine_mode mode, rtx in)
2599 
{
2600 
  if (s390_plus_operand (in, mode))
2601 
    return ADDR_REGS;
2602 
 
2603 
  if (reg_classes_intersect_p (FP_REGS, class)
2604 
      && mode == TFmode
2605 
      && GET_CODE (in) == MEM
2606 
      && GET_CODE (XEXP (in, 0)) == PLUS
2607 
      && GET_CODE (XEXP (XEXP (in, 0), 1)) == CONST_INT
2608 
      && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (in, 0), 1))
2609 
                         + GET_MODE_SIZE (mode) - 1))
2610 
    return ADDR_REGS;
2611 
 
2612 
  if (reg_classes_intersect_p (CC_REGS, class))
2613 
    return GENERAL_REGS;
2614 
 
2615 
  return NO_REGS;
2616 
}
2617 
 
2618 
/* Return the register class of a scratch register needed to
2619 
   store a register of class CLASS in MODE into OUT:
2620 
 
2621 
   We need a temporary when storing a double-word to a
2622 
   non-offsettable memory address.  */
2623 
 
2624 
enum reg_class
2625 
s390_secondary_output_reload_class (enum reg_class class,
2626 
                                    enum machine_mode mode, rtx out)
2627 
{
2628 
  if ((TARGET_64BIT ? (mode == TImode || mode == TFmode)
2629 
                    : (mode == DImode || mode == DFmode))
2630 
      && reg_classes_intersect_p (GENERAL_REGS, class)
2631 
      && GET_CODE (out) == MEM
2632 
      && GET_CODE (XEXP (out, 0)) == PLUS
2633 
      && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2634 
      && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2635 
      && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2636 
                         + GET_MODE_SIZE (mode) - 1))
2637 
    return ADDR_REGS;
2638 
 
2639 
  if (reg_classes_intersect_p (FP_REGS, class)
2640 
      && mode == TFmode
2641 
      && GET_CODE (out) == MEM
2642 
      && GET_CODE (XEXP (out, 0)) == PLUS
2643 
      && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2644 
      && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2645 
                         + GET_MODE_SIZE (mode) - 1))
2646 
    return ADDR_REGS;
2647 
 
2648 
  if (reg_classes_intersect_p (CC_REGS, class))
2649 
    return GENERAL_REGS;
2650 
 
2651 
  return NO_REGS;
2652 
}
2653 
 
2654 
/* Generate code to load SRC, which is PLUS that is not a
2655 
   legitimate operand for the LA instruction, into TARGET.
2656 
   SCRATCH may be used as scratch register.  */
2657 
 
2658 
void
2659 
s390_expand_plus_operand (rtx target, rtx src,
2660 
                          rtx scratch)
2661 
{
2662 
  rtx sum1, sum2;
2663 
  struct s390_address ad;
2664 
 
2665 
  /* src must be a PLUS; get its two operands.  */
2666 
  gcc_assert (GET_CODE (src) == PLUS);
2667 
  gcc_assert (GET_MODE (src) == Pmode);
2668 
 
2669 
  /* Check if any of the two operands is already scheduled
2670 
     for replacement by reload.  This can happen e.g. when
2671 
     float registers occur in an address.  */
2672 
  sum1 = find_replacement (&XEXP (src, 0));
2673 
  sum2 = find_replacement (&XEXP (src, 1));
2674 
  src = gen_rtx_PLUS (Pmode, sum1, sum2);
2675 
 
2676 
  /* If the address is already strictly valid, there's nothing to do.  */
2677 
  if (!s390_decompose_address (src, &ad)
2678 
      || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2679 
      || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
2680 
    {
2681 
      /* Otherwise, one of the operands cannot be an address register;
2682 
         we reload its value into the scratch register.  */
2683 
      if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2684 
        {
2685 
          emit_move_insn (scratch, sum1);
2686 
          sum1 = scratch;
2687 
        }
2688 
      if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2689 
        {
2690 
          emit_move_insn (scratch, sum2);
2691 
          sum2 = scratch;
2692 
        }
2693 
 
2694 
      /* According to the way these invalid addresses are generated
2695 
         in reload.c, it should never happen (at least on s390) that
2696 
         *neither* of the PLUS components, after find_replacements
2697 
         was applied, is an address register.  */
2698 
      if (sum1 == scratch && sum2 == scratch)
2699 
        {
2700 
          debug_rtx (src);
2701 
          gcc_unreachable ();
2702 
        }
2703 
 
2704 
      src = gen_rtx_PLUS (Pmode, sum1, sum2);
2705 
    }
2706 
 
2707 
  /* Emit the LOAD ADDRESS pattern.  Note that reload of PLUS
2708 
     is only ever performed on addresses, so we can mark the
2709 
     sum as legitimate for LA in any case.  */
2710 
  s390_load_address (target, src);
2711 
}
2712 
 
2713 
 
2714 
/* Return true if ADDR is a valid memory address.
2715 
   STRICT specifies whether strict register checking applies.  */
2716 
 
2717 
bool
2718 
legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2719 
                      rtx addr, int strict)
2720 
{
2721 
  struct s390_address ad;
2722 
  if (!s390_decompose_address (addr, &ad))
2723 
    return false;
2724 
 
2725 
  if (strict)
2726 
    {
2727 
      if (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2728 
        return false;
2729 
      if (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx))
2730 
        return false;
2731 
    }
2732 
  else
2733 
    {
2734 
      if (ad.base && !REG_OK_FOR_BASE_NONSTRICT_P (ad.base))
2735 
        return false;
2736 
      if (ad.indx && !REG_OK_FOR_INDEX_NONSTRICT_P (ad.indx))
2737 
        return false;
2738 
    }
2739 
 
2740 
  return true;
2741 
}
2742 
 
2743 
/* Return true if OP is a valid operand for the LA instruction.
2744 
   In 31-bit, we need to prove that the result is used as an
2745 
   address, as LA performs only a 31-bit addition.  */
2746 
 
2747 
bool
2748 
legitimate_la_operand_p (rtx op)
2749 
{
2750 
  struct s390_address addr;
2751 
  if (!s390_decompose_address (op, &addr))
2752 
    return false;
2753 
 
2754 
  return (TARGET_64BIT || addr.pointer);
2755 
}
2756 
 
2757 
/* Return true if it is valid *and* preferable to use LA to
2758 
   compute the sum of OP1 and OP2.  */
2759 
 
2760 
bool
2761 
preferred_la_operand_p (rtx op1, rtx op2)
2762 
{
2763 
  struct s390_address addr;
2764 
 
2765 
  if (op2 != const0_rtx)
2766 
    op1 = gen_rtx_PLUS (Pmode, op1, op2);
2767 
 
2768 
  if (!s390_decompose_address (op1, &addr))
2769 
    return false;
2770 
  if (addr.base && !REG_OK_FOR_BASE_STRICT_P (addr.base))
2771 
    return false;
2772 
  if (addr.indx && !REG_OK_FOR_INDEX_STRICT_P (addr.indx))
2773 
    return false;
2774 
 
2775 
  if (!TARGET_64BIT && !addr.pointer)
2776 
    return false;
2777 
 
2778 
  if (addr.pointer)
2779 
    return true;
2780 
 
2781 
  if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2782 
      || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2783 
    return true;
2784 
 
2785 
  return false;
2786 
}
2787 
 
2788 
/* Emit a forced load-address operation to load SRC into DST.
2789 
   This will use the LOAD ADDRESS instruction even in situations
2790 
   where legitimate_la_operand_p (SRC) returns false.  */
2791 
 
2792 
void
2793 
s390_load_address (rtx dst, rtx src)
2794 
{
2795 
  if (TARGET_64BIT)
2796 
    emit_move_insn (dst, src);
2797 
  else
2798 
    emit_insn (gen_force_la_31 (dst, src));
2799 
}
2800 
 
2801 
/* Return a legitimate reference for ORIG (an address) using the
2802 
   register REG.  If REG is 0, a new pseudo is generated.
2803 
 
2804 
   There are two types of references that must be handled:
2805 
 
2806 
   1. Global data references must load the address from the GOT, via
2807 
      the PIC reg.  An insn is emitted to do this load, and the reg is
2808 
      returned.
2809 
 
2810 
   2. Static data references, constant pool addresses, and code labels
2811 
      compute the address as an offset from the GOT, whose base is in
2812 
      the PIC reg.  Static data objects have SYMBOL_FLAG_LOCAL set to
2813 
      differentiate them from global data objects.  The returned
2814 
      address is the PIC reg + an unspec constant.
2815 
 
2816 
   GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2817 
   reg also appears in the address.  */
2818 
 
2819 
rtx
2820 
legitimize_pic_address (rtx orig, rtx reg)
2821 
{
2822 
  rtx addr = orig;
2823 
  rtx new = orig;
2824 
  rtx base;
2825 
 
2826 
  if (GET_CODE (addr) == LABEL_REF
2827 
      || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2828 
    {
2829 
      /* This is a local symbol.  */
2830 
      if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2831 
        {
2832 
          /* Access local symbols PC-relative via LARL.
2833 
             This is the same as in the non-PIC case, so it is
2834 
             handled automatically ...  */
2835 
        }
2836 
      else
2837 
        {
2838 
          /* Access local symbols relative to the GOT.  */
2839 
 
2840 
          rtx temp = reg? reg : gen_reg_rtx (Pmode);
2841 
 
2842 
          if (reload_in_progress || reload_completed)
2843 
            regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2844 
 
2845 
          addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2846 
          addr = gen_rtx_CONST (Pmode, addr);
2847 
          addr = force_const_mem (Pmode, addr);
2848 
          emit_move_insn (temp, addr);
2849 
 
2850 
          new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2851 
          if (reg != 0)
2852 
            {
2853 
              s390_load_address (reg, new);
2854 
              new = reg;
2855 
            }
2856 
        }
2857 
    }
2858 
  else if (GET_CODE (addr) == SYMBOL_REF)
2859 
    {
2860 
      if (reg == 0)
2861 
        reg = gen_reg_rtx (Pmode);
2862 
 
2863 
      if (flag_pic == 1)
2864 
        {
2865 
          /* Assume GOT offset < 4k.  This is handled the same way
2866 
             in both 31- and 64-bit code (@GOT).  */
2867 
 
2868 
          if (reload_in_progress || reload_completed)
2869 
            regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2870 
 
2871 
          new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2872 
          new = gen_rtx_CONST (Pmode, new);
2873 
          new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2874 
          new = gen_const_mem (Pmode, new);
2875 
          emit_move_insn (reg, new);
2876 
          new = reg;
2877 
        }
2878 
      else if (TARGET_CPU_ZARCH)
2879 
        {
2880 
          /* If the GOT offset might be >= 4k, we determine the position
2881 
             of the GOT entry via a PC-relative LARL (@GOTENT).  */
2882 
 
2883 
          rtx temp = gen_reg_rtx (Pmode);
2884 
 
2885 
          new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2886 
          new = gen_rtx_CONST (Pmode, new);
2887 
          emit_move_insn (temp, new);
2888 
 
2889 
          new = gen_const_mem (Pmode, temp);
2890 
          emit_move_insn (reg, new);
2891 
          new = reg;
2892 
        }
2893 
      else
2894 
        {
2895 
          /* If the GOT offset might be >= 4k, we have to load it
2896 
             from the literal pool (@GOT).  */
2897 
 
2898 
          rtx temp = gen_reg_rtx (Pmode);
2899 
 
2900 
          if (reload_in_progress || reload_completed)
2901 
            regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2902 
 
2903 
          addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2904 
          addr = gen_rtx_CONST (Pmode, addr);
2905 
          addr = force_const_mem (Pmode, addr);
2906 
          emit_move_insn (temp, addr);
2907 
 
2908 
          new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2909 
          new = gen_const_mem (Pmode, new);
2910 
          emit_move_insn (reg, new);
2911 
          new = reg;
2912 
        }
2913 
    }
2914 
  else
2915 
    {
2916 
      if (GET_CODE (addr) == CONST)
2917 
        {
2918 
          addr = XEXP (addr, 0);
2919 
          if (GET_CODE (addr) == UNSPEC)
2920 
            {
2921 
              gcc_assert (XVECLEN (addr, 0) == 1);
2922 
              switch (XINT (addr, 1))
2923 
                {
2924 
                  /* If someone moved a GOT-relative UNSPEC
2925 
                     out of the literal pool, force them back in.  */
2926 
                  case UNSPEC_GOTOFF:
2927 
                  case UNSPEC_PLTOFF:
2928 
                    new = force_const_mem (Pmode, orig);
2929 
                    break;
2930 
 
2931 
                  /* @GOT is OK as is if small.  */
2932 
                  case UNSPEC_GOT:
2933 
                    if (flag_pic == 2)
2934 
                      new = force_const_mem (Pmode, orig);
2935 
                    break;
2936 
 
2937 
                  /* @GOTENT is OK as is.  */
2938 
                  case UNSPEC_GOTENT:
2939 
                    break;
2940 
 
2941 
                  /* @PLT is OK as is on 64-bit, must be converted to
2942 
                     GOT-relative @PLTOFF on 31-bit.  */
2943 
                  case UNSPEC_PLT:
2944 
                    if (!TARGET_CPU_ZARCH)
2945 
                      {
2946 
                        rtx temp = reg? reg : gen_reg_rtx (Pmode);
2947 
 
2948 
                        if (reload_in_progress || reload_completed)
2949 
                          regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2950 
 
2951 
                        addr = XVECEXP (addr, 0, 0);
2952 
                        addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
2953 
                                               UNSPEC_PLTOFF);
2954 
                        addr = gen_rtx_CONST (Pmode, addr);
2955 
                        addr = force_const_mem (Pmode, addr);
2956 
                        emit_move_insn (temp, addr);
2957 
 
2958 
                        new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2959 
                        if (reg != 0)
2960 
                          {
2961 
                            s390_load_address (reg, new);
2962 
                            new = reg;
2963 
                          }
2964 
                      }
2965 
                    break;
2966 
 
2967 
                  /* Everything else cannot happen.  */
2968 
                  default:
2969 
                    gcc_unreachable ();
2970 
                }
2971 
            }
2972 
          else
2973 
            gcc_assert (GET_CODE (addr) == PLUS);
2974 
        }
2975 
      if (GET_CODE (addr) == PLUS)
2976 
        {
2977 
          rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2978 
          /* Check first to see if this is a constant offset
2979 
             from a local symbol reference.  */
2980 
          if ((GET_CODE (op0) == LABEL_REF
2981 
                || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
2982 
              && GET_CODE (op1) == CONST_INT)
2983 
            {
2984 
              if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
2985 
                {
2986 
                  if (INTVAL (op1) & 1)
2987 
                    {
2988 
                      /* LARL can't handle odd offsets, so emit a
2989 
                         pair of LARL and LA.  */
2990 
                      rtx temp = reg? reg : gen_reg_rtx (Pmode);
2991 
 
2992 
                      if (!DISP_IN_RANGE (INTVAL (op1)))
2993 
                        {
2994 
                          int even = INTVAL (op1) - 1;
2995 
                          op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
2996 
                          op0 = gen_rtx_CONST (Pmode, op0);
2997 
                          op1 = const1_rtx;
2998 
                        }
2999 
 
3000 
                      emit_move_insn (temp, op0);
3001 
                      new = gen_rtx_PLUS (Pmode, temp, op1);
3002 
 
3003 
                      if (reg != 0)
3004 
                        {
3005 
                          s390_load_address (reg, new);
3006 
                          new = reg;
3007 
                        }
3008 
                    }
3009 
                  else
3010 
                    {
3011 
                      /* If the offset is even, we can just use LARL.
3012 
                         This will happen automatically.  */
3013 
                    }
3014 
                }
3015 
              else
3016 
                {
3017 
                  /* Access local symbols relative to the GOT.  */
3018 
 
3019 
                  rtx temp = reg? reg : gen_reg_rtx (Pmode);
3020 
 
3021 
                  if (reload_in_progress || reload_completed)
3022 
                    regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3023 
 
3024 
                  addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3025 
                                         UNSPEC_GOTOFF);
3026 
                  addr = gen_rtx_PLUS (Pmode, addr, op1);
3027 
                  addr = gen_rtx_CONST (Pmode, addr);
3028 
                  addr = force_const_mem (Pmode, addr);
3029 
                  emit_move_insn (temp, addr);
3030 
 
3031 
                  new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3032 
                  if (reg != 0)
3033 
                    {
3034 
                      s390_load_address (reg, new);
3035 
                      new = reg;
3036 
                    }
3037 
                }
3038 
            }
3039 
 
3040 
          /* Now, check whether it is a GOT relative symbol plus offset
3041 
             that was pulled out of the literal pool.  Force it back in.  */
3042 
 
3043 
          else if (GET_CODE (op0) == UNSPEC
3044 
                   && GET_CODE (op1) == CONST_INT
3045 
                   && XINT (op0, 1) == UNSPEC_GOTOFF)
3046 
            {
3047 
              gcc_assert (XVECLEN (op0, 0) == 1);
3048 
 
3049 
              new = force_const_mem (Pmode, orig);
3050 
            }
3051 
 
3052 
          /* Otherwise, compute the sum.  */
3053 
          else
3054 
            {
3055 
              base = legitimize_pic_address (XEXP (addr, 0), reg);
3056 
              new  = legitimize_pic_address (XEXP (addr, 1),
3057 
                                             base == reg ? NULL_RTX : reg);
3058 
              if (GET_CODE (new) == CONST_INT)
3059 
                new = plus_constant (base, INTVAL (new));
3060 
              else
3061 
                {
3062 
                  if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
3063 
                    {
3064 
                      base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
3065 
                      new = XEXP (new, 1);
3066 
                    }
3067 
                  new = gen_rtx_PLUS (Pmode, base, new);
3068 
                }
3069 
 
3070 
              if (GET_CODE (new) == CONST)
3071 
                new = XEXP (new, 0);
3072 
              new = force_operand (new, 0);
3073 
            }
3074 
        }
3075 
    }
3076 
  return new;
3077 
}
3078 
 
3079 
/* Load the thread pointer into a register.  */
3080 
 
3081 
rtx
3082 
s390_get_thread_pointer (void)
3083 
{
3084 
  rtx tp = gen_reg_rtx (Pmode);
3085 
 
3086 
  emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3087 
  mark_reg_pointer (tp, BITS_PER_WORD);
3088 
 
3089 
  return tp;
3090 
}
3091 
 
3092 
/* Emit a tls call insn. The call target is the SYMBOL_REF stored
3093 
   in s390_tls_symbol which always refers to __tls_get_offset.
3094 
   The returned offset is written to RESULT_REG and an USE rtx is
3095 
   generated for TLS_CALL.  */
3096 
 
3097 
static GTY(()) rtx s390_tls_symbol;
3098 
 
3099 
static void
3100 
s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3101 
{
3102 
  rtx insn;
3103 
 
3104 
  gcc_assert (flag_pic);
3105 
 
3106 
  if (!s390_tls_symbol)
3107 
    s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3108 
 
3109 
  insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3110 
                         gen_rtx_REG (Pmode, RETURN_REGNUM));
3111 
 
3112 
  use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3113 
  CONST_OR_PURE_CALL_P (insn) = 1;
3114 
}
3115 
 
3116 
/* ADDR contains a thread-local SYMBOL_REF.  Generate code to compute
3117 
   this (thread-local) address.  REG may be used as temporary.  */
3118 
 
3119 
static rtx
3120 
legitimize_tls_address (rtx addr, rtx reg)
3121 
{
3122 
  rtx new, tls_call, temp, base, r2, insn;
3123 
 
3124 
  if (GET_CODE (addr) == SYMBOL_REF)
3125 
    switch (tls_symbolic_operand (addr))
3126 
      {
3127 
      case TLS_MODEL_GLOBAL_DYNAMIC:
3128 
        start_sequence ();
3129 
        r2 = gen_rtx_REG (Pmode, 2);
3130 
        tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3131 
        new = gen_rtx_CONST (Pmode, tls_call);
3132 
        new = force_const_mem (Pmode, new);
3133 
        emit_move_insn (r2, new);
3134 
        s390_emit_tls_call_insn (r2, tls_call);
3135 
        insn = get_insns ();
3136 
        end_sequence ();
3137 
 
3138 
        new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3139 
        temp = gen_reg_rtx (Pmode);
3140 
        emit_libcall_block (insn, temp, r2, new);
3141 
 
3142 
        new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3143 
        if (reg != 0)
3144 
          {
3145 
            s390_load_address (reg, new);
3146 
            new = reg;
3147 
          }
3148 
        break;
3149 
 
3150 
      case TLS_MODEL_LOCAL_DYNAMIC:
3151 
        start_sequence ();
3152 
        r2 = gen_rtx_REG (Pmode, 2);
3153 
        tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3154 
        new = gen_rtx_CONST (Pmode, tls_call);
3155 
        new = force_const_mem (Pmode, new);
3156 
        emit_move_insn (r2, new);
3157 
        s390_emit_tls_call_insn (r2, tls_call);
3158 
        insn = get_insns ();
3159 
        end_sequence ();
3160 
 
3161 
        new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3162 
        temp = gen_reg_rtx (Pmode);
3163 
        emit_libcall_block (insn, temp, r2, new);
3164 
 
3165 
        new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3166 
        base = gen_reg_rtx (Pmode);
3167 
        s390_load_address (base, new);
3168 
 
3169 
        new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3170 
        new = gen_rtx_CONST (Pmode, new);
3171 
        new = force_const_mem (Pmode, new);
3172 
        temp = gen_reg_rtx (Pmode);
3173 
        emit_move_insn (temp, new);
3174 
 
3175 
        new = gen_rtx_PLUS (Pmode, base, temp);
3176 
        if (reg != 0)
3177 
          {
3178 
            s390_load_address (reg, new);
3179 
            new = reg;
3180 
          }
3181 
        break;
3182 
 
3183 
      case TLS_MODEL_INITIAL_EXEC:
3184 
        if (flag_pic == 1)
3185 
          {
3186 
            /* Assume GOT offset < 4k.  This is handled the same way
3187 
               in both 31- and 64-bit code.  */
3188 
 
3189 
            if (reload_in_progress || reload_completed)
3190 
              regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3191 
 
3192 
            new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3193 
            new = gen_rtx_CONST (Pmode, new);
3194 
            new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3195 
            new = gen_const_mem (Pmode, new);
3196 
            temp = gen_reg_rtx (Pmode);
3197 
            emit_move_insn (temp, new);
3198 
          }
3199 
        else if (TARGET_CPU_ZARCH)
3200 
          {
3201 
            /* If the GOT offset might be >= 4k, we determine the position
3202 
               of the GOT entry via a PC-relative LARL.  */
3203 
 
3204 
            new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3205 
            new = gen_rtx_CONST (Pmode, new);
3206 
            temp = gen_reg_rtx (Pmode);
3207 
            emit_move_insn (temp, new);
3208 
 
3209 
            new = gen_const_mem (Pmode, temp);
3210 
            temp = gen_reg_rtx (Pmode);
3211 
            emit_move_insn (temp, new);
3212 
          }
3213 
        else if (flag_pic)
3214 
          {
3215 
            /* If the GOT offset might be >= 4k, we have to load it
3216 
               from the literal pool.  */
3217 
 
3218 
            if (reload_in_progress || reload_completed)
3219 
              regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3220 
 
3221 
            new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3222 
            new = gen_rtx_CONST (Pmode, new);
3223 
            new = force_const_mem (Pmode, new);
3224 
            temp = gen_reg_rtx (Pmode);
3225 
            emit_move_insn (temp, new);
3226 
 
3227 
            new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3228 
            new = gen_const_mem (Pmode, new);
3229 
 
3230 
            new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3231 
            temp = gen_reg_rtx (Pmode);
3232 
            emit_insn (gen_rtx_SET (Pmode, temp, new));
3233 
          }
3234 
        else
3235 
          {
3236 
            /* In position-dependent code, load the absolute address of
3237 
               the GOT entry from the literal pool.  */
3238 
 
3239 
            new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3240 
            new = gen_rtx_CONST (Pmode, new);
3241 
            new = force_const_mem (Pmode, new);
3242 
            temp = gen_reg_rtx (Pmode);
3243 
            emit_move_insn (temp, new);
3244 
 
3245 
            new = temp;
3246 
            new = gen_const_mem (Pmode, new);
3247 
            new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3248 
            temp = gen_reg_rtx (Pmode);
3249 
            emit_insn (gen_rtx_SET (Pmode, temp, new));
3250 
          }
3251 
 
3252 
        new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3253 
        if (reg != 0)
3254 
          {
3255 
            s390_load_address (reg, new);
3256 
            new = reg;
3257 
          }
3258 
        break;
3259 
 
3260 
      case TLS_MODEL_LOCAL_EXEC:
3261 
        new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3262 
        new = gen_rtx_CONST (Pmode, new);
3263 
        new = force_const_mem (Pmode, new);
3264 
        temp = gen_reg_rtx (Pmode);
3265 
        emit_move_insn (temp, new);
3266 
 
3267 
        new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3268 
        if (reg != 0)
3269 
          {
3270 
            s390_load_address (reg, new);
3271 
            new = reg;
3272 
          }
3273 
        break;
3274 
 
3275 
      default:
3276 
        gcc_unreachable ();
3277 
      }
3278 
 
3279 
  else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3280 
    {
3281 
      switch (XINT (XEXP (addr, 0), 1))
3282 
        {
3283 
        case UNSPEC_INDNTPOFF:
3284 
          gcc_assert (TARGET_CPU_ZARCH);
3285 
          new = addr;
3286 
          break;
3287 
 
3288 
        default:
3289 
          gcc_unreachable ();
3290 
        }
3291 
    }
3292 
 
3293 
  else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3294 
           && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3295 
    {
3296 
      new = XEXP (XEXP (addr, 0), 0);
3297 
      if (GET_CODE (new) != SYMBOL_REF)
3298 
        new = gen_rtx_CONST (Pmode, new);
3299 
 
3300 
      new = legitimize_tls_address (new, reg);
3301 
      new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3302 
      new = force_operand (new, 0);
3303 
    }
3304 
 
3305 
  else
3306 
    gcc_unreachable ();  /* for now ... */
3307 
 
3308 
  return new;
3309 
}
3310 
 
3311 
/* Emit insns to move operands[1] into operands[0].  */
3312 
 
3313 
void
3314 
emit_symbolic_move (rtx *operands)
3315 
{
3316 
  rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3317 
 
3318 
  if (GET_CODE (operands[0]) == MEM)
3319 
    operands[1] = force_reg (Pmode, operands[1]);
3320 
  else if (TLS_SYMBOLIC_CONST (operands[1]))
3321 
    operands[1] = legitimize_tls_address (operands[1], temp);
3322 
  else if (flag_pic)
3323 
    operands[1] = legitimize_pic_address (operands[1], temp);
3324 
}
3325 
 
3326 
/* Try machine-dependent ways of modifying an illegitimate address X
3327 
   to be legitimate.  If we find one, return the new, valid address.
3328 
 
3329 
   OLDX is the address as it was before break_out_memory_refs was called.
3330 
   In some cases it is useful to look at this to decide what needs to be done.
3331 
 
3332 
   MODE is the mode of the operand pointed to by X.
3333 
 
3334 
   When -fpic is used, special handling is needed for symbolic references.
3335 
   See comments by legitimize_pic_address for details.  */
3336 
 
3337 
rtx
3338 
legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3339 
                    enum machine_mode mode ATTRIBUTE_UNUSED)
3340 
{
3341 
  rtx constant_term = const0_rtx;
3342 
 
3343 
  if (TLS_SYMBOLIC_CONST (x))
3344 
    {
3345 
      x = legitimize_tls_address (x, 0);
3346 
 
3347 
      if (legitimate_address_p (mode, x, FALSE))
3348 
        return x;
3349 
    }
3350 
  else if (flag_pic)
3351 
    {
3352 
      if (SYMBOLIC_CONST (x)
3353 
          || (GET_CODE (x) == PLUS
3354 
              && (SYMBOLIC_CONST (XEXP (x, 0))
3355 
                  || SYMBOLIC_CONST (XEXP (x, 1)))))
3356 
          x = legitimize_pic_address (x, 0);
3357 
 
3358 
      if (legitimate_address_p (mode, x, FALSE))
3359 
        return x;
3360 
    }
3361 
 
3362 
  x = eliminate_constant_term (x, &constant_term);
3363 
 
3364 
  /* Optimize loading of large displacements by splitting them
3365 
     into the multiple of 4K and the rest; this allows the
3366 
     former to be CSE'd if possible.
3367 
 
3368 
     Don't do this if the displacement is added to a register
3369 
     pointing into the stack frame, as the offsets will
3370 
     change later anyway.  */
3371 
 
3372 
  if (GET_CODE (constant_term) == CONST_INT
3373 
      && !TARGET_LONG_DISPLACEMENT
3374 
      && !DISP_IN_RANGE (INTVAL (constant_term))
3375 
      && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3376 
    {
3377 
      HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3378 
      HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3379 
 
3380 
      rtx temp = gen_reg_rtx (Pmode);
3381 
      rtx val  = force_operand (GEN_INT (upper), temp);
3382 
      if (val != temp)
3383 
        emit_move_insn (temp, val);
3384 
 
3385 
      x = gen_rtx_PLUS (Pmode, x, temp);
3386 
      constant_term = GEN_INT (lower);
3387 
    }
3388 
 
3389 
  if (GET_CODE (x) == PLUS)
3390 
    {
3391 
      if (GET_CODE (XEXP (x, 0)) == REG)
3392 
        {
3393 
          rtx temp = gen_reg_rtx (Pmode);
3394 
          rtx val  = force_operand (XEXP (x, 1), temp);
3395 
          if (val != temp)
3396 
            emit_move_insn (temp, val);
3397 
 
3398 
          x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3399 
        }
3400 
 
3401 
      else if (GET_CODE (XEXP (x, 1)) == REG)
3402 
        {
3403 
          rtx temp = gen_reg_rtx (Pmode);
3404 
          rtx val  = force_operand (XEXP (x, 0), temp);
3405 
          if (val != temp)
3406 
            emit_move_insn (temp, val);
3407 
 
3408 
          x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3409 
        }
3410 
    }
3411 
 
3412 
  if (constant_term != const0_rtx)
3413 
    x = gen_rtx_PLUS (Pmode, x, constant_term);
3414 
 
3415 
  return x;
3416 
}
3417 
 
3418 
/* Try a machine-dependent way of reloading an illegitimate address AD
3419 
   operand.  If we find one, push the reload and and return the new address.
3420 
 
3421 
   MODE is the mode of the enclosing MEM.  OPNUM is the operand number
3422 
   and TYPE is the reload type of the current reload.  */
3423 
 
3424 
rtx
3425 
legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3426 
                           int opnum, int type)
3427 
{
3428 
  if (!optimize || TARGET_LONG_DISPLACEMENT)
3429 
    return NULL_RTX;
3430 
 
3431 
  if (GET_CODE (ad) == PLUS)
3432 
    {
3433 
      rtx tem = simplify_binary_operation (PLUS, Pmode,
3434 
                                           XEXP (ad, 0), XEXP (ad, 1));
3435 
      if (tem)
3436 
        ad = tem;
3437 
    }
3438 
 
3439 
  if (GET_CODE (ad) == PLUS
3440 
      && GET_CODE (XEXP (ad, 0)) == REG
3441 
      && GET_CODE (XEXP (ad, 1)) == CONST_INT
3442 
      && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3443 
    {
3444 
      HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3445 
      HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3446 
      rtx cst, tem, new;
3447 
 
3448 
      cst = GEN_INT (upper);
3449 
      if (!legitimate_reload_constant_p (cst))
3450 
        cst = force_const_mem (Pmode, cst);
3451 
 
3452 
      tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3453 
      new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3454 
 
3455 
      push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3456 
                   BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3457 
                   opnum, (enum reload_type) type);
3458 
      return new;
3459 
    }
3460 
 
3461 
  return NULL_RTX;
3462 
}
3463 
 
3464 
/* Emit code to move LEN bytes from DST to SRC.  */
3465 
 
3466 
void
3467 
s390_expand_movmem (rtx dst, rtx src, rtx len)
3468 
{
3469 
  if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3470 
    {
3471 
      if (INTVAL (len) > 0)
3472 
        emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3473 
    }
3474 
 
3475 
  else if (TARGET_MVCLE)
3476 
    {
3477 
      emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3478 
    }
3479 
 
3480 
  else
3481 
    {
3482 
      rtx dst_addr, src_addr, count, blocks, temp;
3483 
      rtx loop_start_label = gen_label_rtx ();
3484 
      rtx loop_end_label = gen_label_rtx ();
3485 
      rtx end_label = gen_label_rtx ();
3486 
      enum machine_mode mode;
3487 
 
3488 
      mode = GET_MODE (len);
3489 
      if (mode == VOIDmode)
3490 
        mode = Pmode;
3491 
 
3492 
      dst_addr = gen_reg_rtx (Pmode);
3493 
      src_addr = gen_reg_rtx (Pmode);
3494 
      count = gen_reg_rtx (mode);
3495 
      blocks = gen_reg_rtx (mode);
3496 
 
3497 
      convert_move (count, len, 1);
3498 
      emit_cmp_and_jump_insns (count, const0_rtx,
3499 
                               EQ, NULL_RTX, mode, 1, end_label);
3500 
 
3501 
      emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3502 
      emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3503 
      dst = change_address (dst, VOIDmode, dst_addr);
3504 
      src = change_address (src, VOIDmode, src_addr);
3505 
 
3506 
      temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3507 
      if (temp != count)
3508 
        emit_move_insn (count, temp);
3509 
 
3510 
      temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3511 
      if (temp != blocks)
3512 
        emit_move_insn (blocks, temp);
3513 
 
3514 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
3515 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
3516 
 
3517 
      emit_label (loop_start_label);
3518 
 
3519 
      emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3520 
      s390_load_address (dst_addr,
3521 
                         gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3522 
      s390_load_address (src_addr,
3523 
                         gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3524 
 
3525 
      temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3526 
      if (temp != blocks)
3527 
        emit_move_insn (blocks, temp);
3528 
 
3529 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
3530 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
3531 
 
3532 
      emit_jump (loop_start_label);
3533 
      emit_label (loop_end_label);
3534 
 
3535 
      emit_insn (gen_movmem_short (dst, src,
3536 
                                   convert_to_mode (Pmode, count, 1)));
3537 
      emit_label (end_label);
3538 
    }
3539 
}
3540 
 
3541 
/* Emit code to set LEN bytes at DST to VAL.
3542 
   Make use of clrmem if VAL is zero.  */
3543 
 
3544 
void
3545 
s390_expand_setmem (rtx dst, rtx len, rtx val)
3546 
{
3547 
  gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3548 
  gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3549 
 
3550 
  if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3551 
    {
3552 
      if (val == const0_rtx && INTVAL (len) <= 256)
3553 
        emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3554 
      else
3555 
        {
3556 
          /* Initialize memory by storing the first byte.  */
3557 
          emit_move_insn (adjust_address (dst, QImode, 0), val);
3558 
 
3559 
          if (INTVAL (len) > 1)
3560 
            {
3561 
              /* Initiate 1 byte overlap move.
3562 
                 The first byte of DST is propagated through DSTP1.
3563 
                 Prepare a movmem for:  DST+1 = DST (length = LEN - 1).
3564 
                 DST is set to size 1 so the rest of the memory location
3565 
                 does not count as source operand.  */
3566 
              rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3567 
              set_mem_size (dst, const1_rtx);
3568 
 
3569 
              emit_insn (gen_movmem_short (dstp1, dst,
3570 
                                           GEN_INT (INTVAL (len) - 2)));
3571 
            }
3572 
        }
3573 
    }
3574 
 
3575 
  else if (TARGET_MVCLE)
3576 
    {
3577 
      val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3578 
      emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3579 
    }
3580 
 
3581 
  else
3582 
    {
3583 
      rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3584 
      rtx loop_start_label = gen_label_rtx ();
3585 
      rtx loop_end_label = gen_label_rtx ();
3586 
      rtx end_label = gen_label_rtx ();
3587 
      enum machine_mode mode;
3588 
 
3589 
      mode = GET_MODE (len);
3590 
      if (mode == VOIDmode)
3591 
        mode = Pmode;
3592 
 
3593 
      dst_addr = gen_reg_rtx (Pmode);
3594 
      src_addr = gen_reg_rtx (Pmode);
3595 
      count = gen_reg_rtx (mode);
3596 
      blocks = gen_reg_rtx (mode);
3597 
 
3598 
      convert_move (count, len, 1);
3599 
      emit_cmp_and_jump_insns (count, const0_rtx,
3600 
                               EQ, NULL_RTX, mode, 1, end_label);
3601 
 
3602 
      emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3603 
      dst = change_address (dst, VOIDmode, dst_addr);
3604 
 
3605 
      if (val == const0_rtx)
3606 
        temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3607 
      else
3608 
        {
3609 
          dstp1 = adjust_address (dst, VOIDmode, 1);
3610 
          set_mem_size (dst, const1_rtx);
3611 
 
3612 
          /* Initialize memory by storing the first byte.  */
3613 
          emit_move_insn (adjust_address (dst, QImode, 0), val);
3614 
 
3615 
          /* If count is 1 we are done.  */
3616 
          emit_cmp_and_jump_insns (count, const1_rtx,
3617 
                                   EQ, NULL_RTX, mode, 1, end_label);
3618 
 
3619 
          temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3620 
        }
3621 
      if (temp != count)
3622 
        emit_move_insn (count, temp);
3623 
 
3624 
      temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3625 
      if (temp != blocks)
3626 
        emit_move_insn (blocks, temp);
3627 
 
3628 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
3629 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
3630 
 
3631 
      emit_label (loop_start_label);
3632 
 
3633 
      if (val == const0_rtx)
3634 
        emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3635 
      else
3636 
        emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3637 
      s390_load_address (dst_addr,
3638 
                         gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3639 
 
3640 
      temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3641 
      if (temp != blocks)
3642 
        emit_move_insn (blocks, temp);
3643 
 
3644 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
3645 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
3646 
 
3647 
      emit_jump (loop_start_label);
3648 
      emit_label (loop_end_label);
3649 
 
3650 
      if (val == const0_rtx)
3651 
        emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3652 
      else
3653 
        emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3654 
      emit_label (end_label);
3655 
    }
3656 
}
3657 
 
3658 
/* Emit code to compare LEN bytes at OP0 with those at OP1,
3659 
   and return the result in TARGET.  */
3660 
 
3661 
void
3662 
s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3663 
{
3664 
  rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3665 
  rtx tmp;
3666 
 
3667 
  /* As the result of CMPINT is inverted compared to what we need,
3668 
     we have to swap the operands.  */
3669 
  tmp = op0; op0 = op1; op1 = tmp;
3670 
 
3671 
  if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3672 
    {
3673 
      if (INTVAL (len) > 0)
3674 
        {
3675 
          emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3676 
          emit_insn (gen_cmpint (target, ccreg));
3677 
        }
3678 
      else
3679 
        emit_move_insn (target, const0_rtx);
3680 
    }
3681 
  else if (TARGET_MVCLE)
3682 
    {
3683 
      emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3684 
      emit_insn (gen_cmpint (target, ccreg));
3685 
    }
3686 
  else
3687 
    {
3688 
      rtx addr0, addr1, count, blocks, temp;
3689 
      rtx loop_start_label = gen_label_rtx ();
3690 
      rtx loop_end_label = gen_label_rtx ();
3691 
      rtx end_label = gen_label_rtx ();
3692 
      enum machine_mode mode;
3693 
 
3694 
      mode = GET_MODE (len);
3695 
      if (mode == VOIDmode)
3696 
        mode = Pmode;
3697 
 
3698 
      addr0 = gen_reg_rtx (Pmode);
3699 
      addr1 = gen_reg_rtx (Pmode);
3700 
      count = gen_reg_rtx (mode);
3701 
      blocks = gen_reg_rtx (mode);
3702 
 
3703 
      convert_move (count, len, 1);
3704 
      emit_cmp_and_jump_insns (count, const0_rtx,
3705 
                               EQ, NULL_RTX, mode, 1, end_label);
3706 
 
3707 
      emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3708 
      emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3709 
      op0 = change_address (op0, VOIDmode, addr0);
3710 
      op1 = change_address (op1, VOIDmode, addr1);
3711 
 
3712 
      temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3713 
      if (temp != count)
3714 
        emit_move_insn (count, temp);
3715 
 
3716 
      temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3717 
      if (temp != blocks)
3718 
        emit_move_insn (blocks, temp);
3719 
 
3720 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
3721 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
3722 
 
3723 
      emit_label (loop_start_label);
3724 
 
3725 
      emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3726 
      temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3727 
      temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3728 
                        gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3729 
      temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3730 
      emit_jump_insn (temp);
3731 
 
3732 
      s390_load_address (addr0,
3733 
                         gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3734 
      s390_load_address (addr1,
3735 
                         gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3736 
 
3737 
      temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3738 
      if (temp != blocks)
3739 
        emit_move_insn (blocks, temp);
3740 
 
3741 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
3742 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
3743 
 
3744 
      emit_jump (loop_start_label);
3745 
      emit_label (loop_end_label);
3746 
 
3747 
      emit_insn (gen_cmpmem_short (op0, op1,
3748 
                                   convert_to_mode (Pmode, count, 1)));
3749 
      emit_label (end_label);
3750 
 
3751 
      emit_insn (gen_cmpint (target, ccreg));
3752 
    }
3753 
}
3754 
 
3755 
 
3756 
/* Expand conditional increment or decrement using alc/slb instructions.
3757 
   Should generate code setting DST to either SRC or SRC + INCREMENT,
3758 
   depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3759 
   Returns true if successful, false otherwise.
3760 
 
3761 
   That makes it possible to implement some if-constructs without jumps e.g.:
3762 
   (borrow = CC0 | CC1 and carry = CC2 | CC3)
3763 
   unsigned int a, b, c;
3764 
   if (a < b)  c++; -> CCU  b > a  -> CC2;    c += carry;
3765 
   if (a < b)  c--; -> CCL3 a - b  -> borrow; c -= borrow;
3766 
   if (a <= b) c++; -> CCL3 b - a  -> borrow; c += carry;
3767 
   if (a <= b) c--; -> CCU  a <= b -> borrow; c -= borrow;
3768 
 
3769 
   Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3770 
   if (a == b) c++; -> CCL3 a ^= b; 0 - a  -> borrow;    c += carry;
3771 
   if (a == b) c--; -> CCU  a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3772 
   if (a != b) c++; -> CCU  a ^= b; a > 0  -> CC2;       c += carry;
3773 
   if (a != b) c--; -> CCL3 a ^= b; 0 - a  -> borrow;    c -= borrow; */
3774 
 
3775 
bool
3776 
s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3777 
                   rtx dst, rtx src, rtx increment)
3778 
{
3779 
  enum machine_mode cmp_mode;
3780 
  enum machine_mode cc_mode;
3781 
  rtx op_res;
3782 
  rtx insn;
3783 
  rtvec p;
3784 
  int ret;
3785 
 
3786 
  if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3787 
      && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3788 
    cmp_mode = SImode;
3789 
  else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3790 
           && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3791 
    cmp_mode = DImode;
3792 
  else
3793 
    return false;
3794 
 
3795 
  /* Try ADD LOGICAL WITH CARRY.  */
3796 
  if (increment == const1_rtx)
3797 
    {
3798 
      /* Determine CC mode to use.  */
3799 
      if (cmp_code == EQ || cmp_code == NE)
3800 
        {
3801 
          if (cmp_op1 != const0_rtx)
3802 
            {
3803 
              cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3804 
                                             NULL_RTX, 0, OPTAB_WIDEN);
3805 
              cmp_op1 = const0_rtx;
3806 
            }
3807 
 
3808 
          cmp_code = cmp_code == EQ ? LEU : GTU;
3809 
        }
3810 
 
3811 
      if (cmp_code == LTU || cmp_code == LEU)
3812 
        {
3813 
          rtx tem = cmp_op0;
3814 
          cmp_op0 = cmp_op1;
3815 
          cmp_op1 = tem;
3816 
          cmp_code = swap_condition (cmp_code);
3817 
        }
3818 
 
3819 
      switch (cmp_code)
3820 
        {
3821 
          case GTU:
3822 
            cc_mode = CCUmode;
3823 
            break;
3824 
 
3825 
          case GEU:
3826 
            cc_mode = CCL3mode;
3827 
            break;
3828 
 
3829 
          default:
3830 
            return false;
3831 
        }
3832 
 
3833 
      /* Emit comparison instruction pattern. */
3834 
      if (!register_operand (cmp_op0, cmp_mode))
3835 
        cmp_op0 = force_reg (cmp_mode, cmp_op0);
3836 
 
3837 
      insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3838 
                          gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3839 
      /* We use insn_invalid_p here to add clobbers if required.  */
3840 
      ret = insn_invalid_p (emit_insn (insn));
3841 
      gcc_assert (!ret);
3842 
 
3843 
      /* Emit ALC instruction pattern.  */
3844 
      op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3845 
                               gen_rtx_REG (cc_mode, CC_REGNUM),
3846 
                               const0_rtx);
3847 
 
3848 
      if (src != const0_rtx)
3849 
        {
3850 
          if (!register_operand (src, GET_MODE (dst)))
3851 
            src = force_reg (GET_MODE (dst), src);
3852 
 
3853 
          src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3854 
          op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3855 
        }
3856 
 
3857 
      p = rtvec_alloc (2);
3858 
      RTVEC_ELT (p, 0) =
3859 
        gen_rtx_SET (VOIDmode, dst, op_res);
3860 
      RTVEC_ELT (p, 1) =
3861 
        gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3862 
      emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3863 
 
3864 
      return true;
3865 
    }
3866 
 
3867 
  /* Try SUBTRACT LOGICAL WITH BORROW.  */
3868 
  if (increment == constm1_rtx)
3869 
    {
3870 
      /* Determine CC mode to use.  */
3871 
      if (cmp_code == EQ || cmp_code == NE)
3872 
        {
3873 
          if (cmp_op1 != const0_rtx)
3874 
            {
3875 
              cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3876 
                                             NULL_RTX, 0, OPTAB_WIDEN);
3877 
              cmp_op1 = const0_rtx;
3878 
            }
3879 
 
3880 
          cmp_code = cmp_code == EQ ? LEU : GTU;
3881 
        }
3882 
 
3883 
      if (cmp_code == GTU || cmp_code == GEU)
3884 
        {
3885 
          rtx tem = cmp_op0;
3886 
          cmp_op0 = cmp_op1;
3887 
          cmp_op1 = tem;
3888 
          cmp_code = swap_condition (cmp_code);
3889 
        }
3890 
 
3891 
      switch (cmp_code)
3892 
        {
3893 
          case LEU:
3894 
            cc_mode = CCUmode;
3895 
            break;
3896 
 
3897 
          case LTU:
3898 
            cc_mode = CCL3mode;
3899 
            break;
3900 
 
3901 
          default:
3902 
            return false;
3903 
        }
3904 
 
3905 
      /* Emit comparison instruction pattern. */
3906 
      if (!register_operand (cmp_op0, cmp_mode))
3907 
        cmp_op0 = force_reg (cmp_mode, cmp_op0);
3908 
 
3909 
      insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3910 
                          gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3911 
      /* We use insn_invalid_p here to add clobbers if required.  */
3912 
      ret = insn_invalid_p (emit_insn (insn));
3913 
      gcc_assert (!ret);
3914 
 
3915 
      /* Emit SLB instruction pattern.  */
3916 
      if (!register_operand (src, GET_MODE (dst)))
3917 
        src = force_reg (GET_MODE (dst), src);
3918 
 
3919 
      op_res = gen_rtx_MINUS (GET_MODE (dst),
3920 
                              gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3921 
                              gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3922 
                                              gen_rtx_REG (cc_mode, CC_REGNUM),
3923 
                                              const0_rtx));
3924 
      p = rtvec_alloc (2);
3925 
      RTVEC_ELT (p, 0) =
3926 
        gen_rtx_SET (VOIDmode, dst, op_res);
3927 
      RTVEC_ELT (p, 1) =
3928 
        gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3929 
      emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3930 
 
3931 
      return true;
3932 
    }
3933 
 
3934 
  return false;
3935 
}
3936 
 
3937 
/* Expand code for the insv template. Return true if successful, false else.  */
3938 
 
3939 
bool
3940 
s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
3941 
{
3942 
  int bitsize = INTVAL (op1);
3943 
  int bitpos = INTVAL (op2);
3944 
 
3945 
  /* We need byte alignment.  */
3946 
  if (bitsize % BITS_PER_UNIT)
3947 
    return false;
3948 
 
3949 
  if (bitpos == 0
3950 
      && memory_operand (dest, VOIDmode)
3951 
      && (register_operand (src, word_mode)
3952 
          || const_int_operand (src, VOIDmode)))
3953 
    {
3954 
      /* Emit standard pattern if possible.  */
3955 
      enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
3956 
      if (GET_MODE_BITSIZE (mode) == bitsize)
3957 
        emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
3958 
 
3959 
      /* (set (ze (mem)) (const_int)).  */
3960 
      else if (const_int_operand (src, VOIDmode))
3961 
        {
3962 
          int size = bitsize / BITS_PER_UNIT;
3963 
          rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
3964 
                                        GET_MODE_SIZE (word_mode) - size);
3965 
 
3966 
          dest = adjust_address (dest, BLKmode, 0);
3967 
          set_mem_size (dest, GEN_INT (size));
3968 
          s390_expand_movmem (dest, src_mem, GEN_INT (size));
3969 
        }
3970 
 
3971 
      /* (set (ze (mem)) (reg)).  */
3972 
      else if (register_operand (src, word_mode))
3973 
        {
3974 
          if (bitsize <= GET_MODE_BITSIZE (SImode))
3975 
            emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
3976 
                                                  const0_rtx), src);
3977 
          else
3978 
            {
3979 
              /* Emit st,stcmh sequence.  */
3980 
              int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
3981 
              int size = stcmh_width / BITS_PER_UNIT;
3982 
 
3983 
              emit_move_insn (adjust_address (dest, SImode, size),
3984 
                              gen_lowpart (SImode, src));
3985 
              set_mem_size (dest, GEN_INT (size));
3986 
              emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
3987 
                                                    (stcmh_width), const0_rtx),
3988 
                              gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
3989 
                                                (GET_MODE_BITSIZE (SImode))));
3990 
            }
3991 
        }
3992 
      else
3993 
        return false;
3994 
 
3995 
      return true;
3996 
    }
3997 
 
3998 
  /* (set (ze (reg)) (const_int)).  */
3999 
  if (TARGET_ZARCH
4000 
      && register_operand (dest, word_mode)
4001 
      && (bitpos % 16) == 0
4002 
      && (bitsize % 16) == 0
4003 
      && const_int_operand (src, VOIDmode))
4004 
    {
4005 
      HOST_WIDE_INT val = INTVAL (src);
4006 
      int regpos = bitpos + bitsize;
4007 
 
4008 
      while (regpos > bitpos)
4009 
        {
4010 
          enum machine_mode putmode;
4011 
          int putsize;
4012 
 
4013 
          if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4014 
            putmode = SImode;
4015 
          else
4016 
            putmode = HImode;
4017 
 
4018 
          putsize = GET_MODE_BITSIZE (putmode);
4019 
          regpos -= putsize;
4020 
          emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4021 
                                                GEN_INT (putsize),
4022 
                                                GEN_INT (regpos)),
4023 
                          gen_int_mode (val, putmode));
4024 
          val >>= putsize;
4025 
        }
4026 
      gcc_assert (regpos == bitpos);
4027 
      return true;
4028 
    }
4029 
 
4030 
  return false;
4031 
}
4032 
 
4033 
/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4034 
   register that holds VAL of mode MODE shifted by COUNT bits.  */
4035 
 
4036 
static inline rtx
4037 
s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4038 
{
4039 
  val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4040 
                             NULL_RTX, 1, OPTAB_DIRECT);
4041 
  return expand_simple_binop (SImode, ASHIFT, val, count,
4042 
                              NULL_RTX, 1, OPTAB_DIRECT);
4043 
}
4044 
 
4045 
/* Structure to hold the initial parameters for a compare_and_swap operation
4046 
   in HImode and QImode.  */
4047 
 
4048 
struct alignment_context
4049 
{
4050 
  rtx memsi;      /* SI aligned memory location.  */
4051 
  rtx shift;      /* Bit offset with regard to lsb.  */
4052 
  rtx modemask;   /* Mask of the HQImode shifted by SHIFT bits.  */
4053 
  rtx modemaski;  /* ~modemask */
4054 
  bool aligned;   /* True if memory is aliged, false else.  */
4055 
};
4056 
 
4057 
/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4058 
   structure AC for transparent simplifying, if the memory alignment is known
4059 
   to be at least 32bit.  MEM is the memory location for the actual operation
4060 
   and MODE its mode.  */
4061 
 
4062 
static void
4063 
init_alignment_context (struct alignment_context *ac, rtx mem,
4064 
                        enum machine_mode mode)
4065 
{
4066 
  ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4067 
  ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4068 
 
4069 
  if (ac->aligned)
4070 
    ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned.  */
4071 
  else
4072 
    {
4073 
      /* Alignment is unknown.  */
4074 
      rtx byteoffset, addr, align;
4075 
 
4076 
      /* Force the address into a register.  */
4077 
      addr = force_reg (Pmode, XEXP (mem, 0));
4078 
 
4079 
      /* Align it to SImode.  */
4080 
      align = expand_simple_binop (Pmode, AND, addr,
4081 
                                   GEN_INT (-GET_MODE_SIZE (SImode)),
4082 
                                   NULL_RTX, 1, OPTAB_DIRECT);
4083 
      /* Generate MEM.  */
4084 
      ac->memsi = gen_rtx_MEM (SImode, align);
4085 
      MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4086 
      set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4087 
      set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4088 
 
4089 
      /* Calculate shiftcount.  */
4090 
      byteoffset = expand_simple_binop (Pmode, AND, addr,
4091 
                                        GEN_INT (GET_MODE_SIZE (SImode) - 1),
4092 
                                        NULL_RTX, 1, OPTAB_DIRECT);
4093 
      /* As we already have some offset, evaluate the remaining distance.  */
4094 
      ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4095 
                                      NULL_RTX, 1, OPTAB_DIRECT);
4096 
 
4097 
    }
4098 
  /* Shift is the byte count, but we need the bitcount.  */
4099 
  ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4100 
                                  NULL_RTX, 1, OPTAB_DIRECT);
4101 
  /* Calculate masks.  */
4102 
  ac->modemask = expand_simple_binop (SImode, ASHIFT,
4103 
                                     GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4104 
                                     NULL_RTX, 1, OPTAB_DIRECT);
4105 
  ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4106 
}
4107 
 
4108 
/* Expand an atomic compare and swap operation for HImode and QImode.  MEM is
4109 
   the memory location, CMP the old value to compare MEM with and NEW the value
4110 
   to set if CMP == MEM.
4111 
   CMP is never in memory for compare_and_swap_cc because
4112 
   expand_bool_compare_and_swap puts it into a register for later compare.  */
4113 
 
4114 
void
4115 
s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new)
4116 
{
4117 
  struct alignment_context ac;
4118 
  rtx cmpv, newv, val, resv, cc;
4119 
  rtx res = gen_reg_rtx (SImode);
4120 
  rtx csloop = gen_label_rtx ();
4121 
  rtx csend = gen_label_rtx ();
4122 
 
4123 
  gcc_assert (register_operand (target, VOIDmode));
4124 
  gcc_assert (MEM_P (mem));
4125 
 
4126 
  init_alignment_context (&ac, mem, mode);
4127 
 
4128 
  /* Shift the values to the correct bit positions.  */
4129 
  if (!(ac.aligned && MEM_P (cmp)))
4130 
    cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4131 
  if (!(ac.aligned && MEM_P (new)))
4132 
    new = s390_expand_mask_and_shift (new, mode, ac.shift);
4133 
 
4134 
  /* Load full word.  Subsequent loads are performed by CS.  */
4135 
  val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4136 
                             NULL_RTX, 1, OPTAB_DIRECT);
4137 
 
4138 
  /* Start CS loop.  */
4139 
  emit_label (csloop);
4140 
  /* val = "<mem>00..0<mem>"
4141 
   * cmp = "00..0<cmp>00..0"
4142 
   * new = "00..0<new>00..0"
4143 
   */
4144 
 
4145 
  /* Patch cmp and new with val at correct position.  */
4146 
  if (ac.aligned && MEM_P (cmp))
4147 
    {
4148 
      cmpv = force_reg (SImode, val);
4149 
      store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4150 
    }
4151 
  else
4152 
    cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4153 
                                                   NULL_RTX, 1, OPTAB_DIRECT));
4154 
  if (ac.aligned && MEM_P (new))
4155 
    {
4156 
      newv = force_reg (SImode, val);
4157 
      store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new);
4158 
    }
4159 
  else
4160 
    newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
4161 
                                                   NULL_RTX, 1, OPTAB_DIRECT));
4162 
 
4163 
  /* Emit compare_and_swap pattern.  */
4164 
  emit_insn (gen_sync_compare_and_swap_ccsi (res, ac.memsi, cmpv, newv));
4165 
 
4166 
  /* Jump to end if we're done (likely?).  */
4167 
  s390_emit_jump (csend, s390_emit_compare (EQ, cmpv, ac.memsi));
4168 
 
4169 
  /* Check for changes outside mode.  */
4170 
  resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4171 
                              NULL_RTX, 1, OPTAB_DIRECT);
4172 
  cc = s390_emit_compare (NE, resv, val);
4173 
  emit_move_insn (val, resv);
4174 
  /* Loop internal if so.  */
4175 
  s390_emit_jump (csloop, cc);
4176 
 
4177 
  emit_label (csend);
4178 
 
4179 
  /* Return the correct part of the bitfield.  */
4180 
  convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4181 
                                             NULL_RTX, 1, OPTAB_DIRECT), 1);
4182 
}
4183 
 
4184 
/* Expand an atomic operation CODE of mode MODE.  MEM is the memory location
4185 
   and VAL the value to play with.  If AFTER is true then store the the value
4186 
   MEM holds after the operation, if AFTER is false then store the value MEM
4187 
   holds before the operation.  If TARGET is zero then discard that value, else
4188 
   store it to TARGET.  */
4189 
 
4190 
void
4191 
s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4192 
                    rtx target, rtx mem, rtx val, bool after)
4193 
{
4194 
  struct alignment_context ac;
4195 
  rtx cmp;
4196 
  rtx new = gen_reg_rtx (SImode);
4197 
  rtx orig = gen_reg_rtx (SImode);
4198 
  rtx csloop = gen_label_rtx ();
4199 
 
4200 
  gcc_assert (!target || register_operand (target, VOIDmode));
4201 
  gcc_assert (MEM_P (mem));
4202 
 
4203 
  init_alignment_context (&ac, mem, mode);
4204 
 
4205 
  /* Shift val to the correct bit positions.
4206 
     Preserve "icm", but prevent "ex icm".  */
4207 
  if (!(ac.aligned && code == SET && MEM_P (val)))
4208 
    val = s390_expand_mask_and_shift (val, mode, ac.shift);
4209 
 
4210 
  /* Further preparation insns.  */
4211 
  if (code == PLUS || code == MINUS)
4212 
    emit_move_insn (orig, val);
4213 
  else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4214 
    val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4215 
                               NULL_RTX, 1, OPTAB_DIRECT);
4216 
 
4217 
  /* Load full word.  Subsequent loads are performed by CS.  */
4218 
  cmp = force_reg (SImode, ac.memsi);
4219 
 
4220 
  /* Start CS loop.  */
4221 
  emit_label (csloop);
4222 
  emit_move_insn (new, cmp);
4223 
 
4224 
  /* Patch new with val at correct position.  */
4225 
  switch (code)
4226 
    {
4227 
    case PLUS:
4228 
    case MINUS:
4229 
      val = expand_simple_binop (SImode, code, new, orig,
4230 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4231 
      val = expand_simple_binop (SImode, AND, val, ac.modemask,
4232 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4233 
      /* FALLTHRU */
4234 
    case SET:
4235 
      if (ac.aligned && MEM_P (val))
4236 
        store_bit_field (new, GET_MODE_BITSIZE (mode), 0, SImode, val);
4237 
      else
4238 
        {
4239 
          new = expand_simple_binop (SImode, AND, new, ac.modemaski,
4240 
                                     NULL_RTX, 1, OPTAB_DIRECT);
4241 
          new = expand_simple_binop (SImode, IOR, new, val,
4242 
                                     NULL_RTX, 1, OPTAB_DIRECT);
4243 
        }
4244 
      break;
4245 
    case AND:
4246 
    case IOR:
4247 
    case XOR:
4248 
      new = expand_simple_binop (SImode, code, new, val,
4249 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4250 
      break;
4251 
    case MULT: /* NAND */
4252 
      new = expand_simple_binop (SImode, XOR, new, ac.modemask,
4253 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4254 
      new = expand_simple_binop (SImode, AND, new, val,
4255 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4256 
      break;
4257 
    default:
4258 
      gcc_unreachable ();
4259 
    }
4260 
  /* Emit compare_and_swap pattern.  */
4261 
  emit_insn (gen_sync_compare_and_swap_ccsi (cmp, ac.memsi, cmp, new));
4262 
 
4263 
  /* Loop until swapped (unlikely?).  */
4264 
  s390_emit_jump (csloop, gen_rtx_fmt_ee (NE, CCZ1mode,
4265 
                                          gen_rtx_REG (CCZ1mode, CC_REGNUM),
4266 
                                          const0_rtx));
4267 
 
4268 
  /* Return the correct part of the bitfield.  */
4269 
  if (target)
4270 
    convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4271 
                                               after ? new : cmp, ac.shift,
4272 
                                               NULL_RTX, 1, OPTAB_DIRECT), 1);
4273 
}
4274 
 
4275 
/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4276 
   We need to emit DTP-relative relocations.  */
4277 
 
4278 
static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4279 
 
4280 
static void
4281 
s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4282 
{
4283 
  switch (size)
4284 
    {
4285 
    case 4:
4286 
      fputs ("\t.long\t", file);
4287 
      break;
4288 
    case 8:
4289 
      fputs ("\t.quad\t", file);
4290 
      break;
4291 
    default:
4292 
      gcc_unreachable ();
4293 
    }
4294 
  output_addr_const (file, x);
4295 
  fputs ("@DTPOFF", file);
4296 
}
4297 
 
4298 
#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4299 
/* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE.  */
4300 
 
4301 
static const char *
4302 
s390_mangle_fundamental_type (tree type)
4303 
{
4304 
  if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4305 
      && TARGET_LONG_DOUBLE_128)
4306 
    return "g";
4307 
 
4308 
  /* For all other types, use normal C++ mangling.  */
4309 
  return NULL;
4310 
}
4311 
#endif
4312 
 
4313 
/* In the name of slightly smaller debug output, and to cater to
4314 
   general assembler lossage, recognize various UNSPEC sequences
4315 
   and turn them back into a direct symbol reference.  */
4316 
 
4317 
static rtx
4318 
s390_delegitimize_address (rtx orig_x)
4319 
{
4320 
  rtx x = orig_x, y;
4321 
 
4322 
  if (GET_CODE (x) != MEM)
4323 
    return orig_x;
4324 
 
4325 
  x = XEXP (x, 0);
4326 
  if (GET_CODE (x) == PLUS
4327 
      && GET_CODE (XEXP (x, 1)) == CONST
4328 
      && GET_CODE (XEXP (x, 0)) == REG
4329 
      && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4330 
    {
4331 
      y = XEXP (XEXP (x, 1), 0);
4332 
      if (GET_CODE (y) == UNSPEC
4333 
          && XINT (y, 1) == UNSPEC_GOT)
4334 
        return XVECEXP (y, 0, 0);
4335 
      return orig_x;
4336 
    }
4337 
 
4338 
  if (GET_CODE (x) == CONST)
4339 
    {
4340 
      y = XEXP (x, 0);
4341 
      if (GET_CODE (y) == UNSPEC
4342 
          && XINT (y, 1) == UNSPEC_GOTENT)
4343 
        return XVECEXP (y, 0, 0);
4344 
      return orig_x;
4345 
    }
4346 
 
4347 
  return orig_x;
4348 
}
4349 
 
4350 
/* Output operand OP to stdio stream FILE.
4351 
   OP is an address (register + offset) which is not used to address data;
4352 
   instead the rightmost bits are interpreted as the value.  */
4353 
 
4354 
static void
4355 
print_shift_count_operand (FILE *file, rtx op)
4356 
{
4357 
  HOST_WIDE_INT offset;
4358 
  rtx base;
4359 
 
4360 
  /* Extract base register and offset.  */
4361 
  if (!s390_decompose_shift_count (op, &base, &offset))
4362 
    gcc_unreachable ();
4363 
 
4364 
  /* Sanity check.  */
4365 
  if (base)
4366 
    {
4367 
      gcc_assert (GET_CODE (base) == REG);
4368 
      gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4369 
      gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4370 
    }
4371 
 
4372 
  /* Offsets are constricted to twelve bits.  */
4373 
  fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4374 
  if (base)
4375 
    fprintf (file, "(%s)", reg_names[REGNO (base)]);
4376 
}
4377 
 
4378 
/* See 'get_some_local_dynamic_name'.  */
4379 
 
4380 
static int
4381 
get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4382 
{
4383 
  rtx x = *px;
4384 
 
4385 
  if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4386 
    {
4387 
      x = get_pool_constant (x);
4388 
      return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4389 
    }
4390 
 
4391 
  if (GET_CODE (x) == SYMBOL_REF
4392 
      && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4393 
    {
4394 
      cfun->machine->some_ld_name = XSTR (x, 0);
4395 
      return 1;
4396 
    }
4397 
 
4398 
  return 0;
4399 
}
4400 
 
4401 
/* Locate some local-dynamic symbol still in use by this function
4402 
   so that we can print its name in local-dynamic base patterns.  */
4403 
 
4404 
static const char *
4405 
get_some_local_dynamic_name (void)
4406 
{
4407 
  rtx insn;
4408 
 
4409 
  if (cfun->machine->some_ld_name)
4410 
    return cfun->machine->some_ld_name;
4411 
 
4412 
  for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4413 
    if (INSN_P (insn)
4414 
        && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4415 
      return cfun->machine->some_ld_name;
4416 
 
4417 
  gcc_unreachable ();
4418 
}
4419 
 
4420 
/* Output machine-dependent UNSPECs occurring in address constant X
4421 
   in assembler syntax to stdio stream FILE.  Returns true if the
4422 
   constant X could be recognized, false otherwise.  */
4423 
 
4424 
bool
4425 
s390_output_addr_const_extra (FILE *file, rtx x)
4426 
{
4427 
  if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4428 
    switch (XINT (x, 1))
4429 
      {
4430 
      case UNSPEC_GOTENT:
4431 
        output_addr_const (file, XVECEXP (x, 0, 0));
4432 
        fprintf (file, "@GOTENT");
4433 
        return true;
4434 
      case UNSPEC_GOT:
4435 
        output_addr_const (file, XVECEXP (x, 0, 0));
4436 
        fprintf (file, "@GOT");
4437 
        return true;
4438 
      case UNSPEC_GOTOFF:
4439 
        output_addr_const (file, XVECEXP (x, 0, 0));
4440 
        fprintf (file, "@GOTOFF");
4441 
        return true;
4442 
      case UNSPEC_PLT:
4443 
        output_addr_const (file, XVECEXP (x, 0, 0));
4444 
        fprintf (file, "@PLT");
4445 
        return true;
4446 
      case UNSPEC_PLTOFF:
4447 
        output_addr_const (file, XVECEXP (x, 0, 0));
4448 
        fprintf (file, "@PLTOFF");
4449 
        return true;
4450 
      case UNSPEC_TLSGD:
4451 
        output_addr_const (file, XVECEXP (x, 0, 0));
4452 
        fprintf (file, "@TLSGD");
4453 
        return true;
4454 
      case UNSPEC_TLSLDM:
4455 
        assemble_name (file, get_some_local_dynamic_name ());
4456 
        fprintf (file, "@TLSLDM");
4457 
        return true;
4458 
      case UNSPEC_DTPOFF:
4459 
        output_addr_const (file, XVECEXP (x, 0, 0));
4460 
        fprintf (file, "@DTPOFF");
4461 
        return true;
4462 
      case UNSPEC_NTPOFF:
4463 
        output_addr_const (file, XVECEXP (x, 0, 0));
4464 
        fprintf (file, "@NTPOFF");
4465 
        return true;
4466 
      case UNSPEC_GOTNTPOFF:
4467 
        output_addr_const (file, XVECEXP (x, 0, 0));
4468 
        fprintf (file, "@GOTNTPOFF");
4469 
        return true;
4470 
      case UNSPEC_INDNTPOFF:
4471 
        output_addr_const (file, XVECEXP (x, 0, 0));
4472 
        fprintf (file, "@INDNTPOFF");
4473 
        return true;
4474 
      }
4475 
 
4476 
  return false;
4477 
}
4478 
 
4479 
/* Output address operand ADDR in assembler syntax to
4480 
   stdio stream FILE.  */
4481 
 
4482 
void
4483 
print_operand_address (FILE *file, rtx addr)
4484 
{
4485 
  struct s390_address ad;
4486 
 
4487 
  if (!s390_decompose_address (addr, &ad)
4488 
      || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
4489 
      || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
4490 
    output_operand_lossage ("cannot decompose address");
4491 
 
4492 
  if (ad.disp)
4493 
    output_addr_const (file, ad.disp);
4494 
  else
4495 
    fprintf (file, "0");
4496 
 
4497 
  if (ad.base && ad.indx)
4498 
    fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4499 
                              reg_names[REGNO (ad.base)]);
4500 
  else if (ad.base)
4501 
    fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4502 
}
4503 
 
4504 
/* Output operand X in assembler syntax to stdio stream FILE.
4505 
   CODE specified the format flag.  The following format flags
4506 
   are recognized:
4507 
 
4508 
    'C': print opcode suffix for branch condition.
4509 
    'D': print opcode suffix for inverse branch condition.
4510 
    'J': print tls_load/tls_gdcall/tls_ldcall suffix
4511 
    'G': print the size of the operand in bytes.
4512 
    'O': print only the displacement of a memory reference.
4513 
    'R': print only the base register of a memory reference.
4514 
    'S': print S-type memory reference (base+displacement).
4515 
    'N': print the second word of a DImode operand.
4516 
    'M': print the second word of a TImode operand.
4517 
    'Y': print shift count operand.
4518 
 
4519 
    'b': print integer X as if it's an unsigned byte.
4520 
    'x': print integer X as if it's an unsigned halfword.
4521 
    'h': print integer X as if it's a signed halfword.
4522 
    'i': print the first nonzero HImode part of X.
4523 
    'j': print the first HImode part unequal to -1 of X.
4524 
    'k': print the first nonzero SImode part of X.
4525 
    'm': print the first SImode part unequal to -1 of X.
4526 
    'o': print integer X as if it's an unsigned 32bit word.  */
4527 
 
4528 
void
4529 
print_operand (FILE *file, rtx x, int code)
4530 
{
4531 
  switch (code)
4532 
    {
4533 
    case 'C':
4534 
      fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4535 
      return;
4536 
 
4537 
    case 'D':
4538 
      fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4539 
      return;
4540 
 
4541 
    case 'J':
4542 
      if (GET_CODE (x) == SYMBOL_REF)
4543 
        {
4544 
          fprintf (file, "%s", ":tls_load:");
4545 
          output_addr_const (file, x);
4546 
        }
4547 
      else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4548 
        {
4549 
          fprintf (file, "%s", ":tls_gdcall:");
4550 
          output_addr_const (file, XVECEXP (x, 0, 0));
4551 
        }
4552 
      else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4553 
        {
4554 
          fprintf (file, "%s", ":tls_ldcall:");
4555 
          assemble_name (file, get_some_local_dynamic_name ());
4556 
        }
4557 
      else
4558 
        gcc_unreachable ();
4559 
      return;
4560 
 
4561 
    case 'G':
4562 
      fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4563 
      return;
4564 
 
4565 
    case 'O':
4566 
      {
4567 
        struct s390_address ad;
4568 
        int ret;
4569 
 
4570 
        gcc_assert (GET_CODE (x) == MEM);
4571 
        ret = s390_decompose_address (XEXP (x, 0), &ad);
4572 
        gcc_assert (ret);
4573 
        gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4574 
        gcc_assert (!ad.indx);
4575 
 
4576 
        if (ad.disp)
4577 
          output_addr_const (file, ad.disp);
4578 
        else
4579 
          fprintf (file, "0");
4580 
      }
4581 
      return;
4582 
 
4583 
    case 'R':
4584 
      {
4585 
        struct s390_address ad;
4586 
        int ret;
4587 
 
4588 
        gcc_assert (GET_CODE (x) == MEM);
4589 
        ret = s390_decompose_address (XEXP (x, 0), &ad);
4590 
        gcc_assert (ret);
4591 
        gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4592 
        gcc_assert (!ad.indx);
4593 
 
4594 
        if (ad.base)
4595 
          fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4596 
        else
4597 
          fprintf (file, "0");
4598 
      }
4599 
      return;
4600 
 
4601 
    case 'S':
4602 
      {
4603 
        struct s390_address ad;
4604 
        int ret;
4605 
 
4606 
        gcc_assert (GET_CODE (x) == MEM);
4607 
        ret = s390_decompose_address (XEXP (x, 0), &ad);
4608 
        gcc_assert (ret);
4609 
        gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4610 
        gcc_assert (!ad.indx);
4611 
 
4612 
        if (ad.disp)
4613 
          output_addr_const (file, ad.disp);
4614 
        else
4615 
          fprintf (file, "0");
4616 
 
4617 
        if (ad.base)
4618 
          fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4619 
      }
4620 
      return;
4621 
 
4622 
    case 'N':
4623 
      if (GET_CODE (x) == REG)
4624 
        x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4625 
      else if (GET_CODE (x) == MEM)
4626 
        x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4627 
      else
4628 
        gcc_unreachable ();
4629 
      break;
4630 
 
4631 
    case 'M':
4632 
      if (GET_CODE (x) == REG)
4633 
        x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4634 
      else if (GET_CODE (x) == MEM)
4635 
        x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4636 
      else
4637 
        gcc_unreachable ();
4638 
      break;
4639 
 
4640 
    case 'Y':
4641 
      print_shift_count_operand (file, x);
4642 
      return;
4643 
    }
4644 
 
4645 
  switch (GET_CODE (x))
4646 
    {
4647 
    case REG:
4648 
      fprintf (file, "%s", reg_names[REGNO (x)]);
4649 
      break;
4650 
 
4651 
    case MEM:
4652 
      output_address (XEXP (x, 0));
4653 
      break;
4654 
 
4655 
    case CONST:
4656 
    case CODE_LABEL:
4657 
    case LABEL_REF:
4658 
    case SYMBOL_REF:
4659 
      output_addr_const (file, x);
4660 
      break;
4661 
 
4662 
    case CONST_INT:
4663 
      if (code == 'b')
4664 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4665 
      else if (code == 'x')
4666 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4667 
      else if (code == 'h')
4668 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4669 
      else if (code == 'i')
4670 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4671 
                 s390_extract_part (x, HImode, 0));
4672 
      else if (code == 'j')
4673 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4674 
                 s390_extract_part (x, HImode, -1));
4675 
      else if (code == 'k')
4676 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4677 
                 s390_extract_part (x, SImode, 0));
4678 
      else if (code == 'm')
4679 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4680 
                 s390_extract_part (x, SImode, -1));
4681 
      else if (code == 'o')
4682 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4683 
      else
4684 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4685 
      break;
4686 
 
4687 
    case CONST_DOUBLE:
4688 
      gcc_assert (GET_MODE (x) == VOIDmode);
4689 
      if (code == 'b')
4690 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4691 
      else if (code == 'x')
4692 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4693 
      else if (code == 'h')
4694 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4695 
      else
4696 
        gcc_unreachable ();
4697 
      break;
4698 
 
4699 
    default:
4700 
      fatal_insn ("UNKNOWN in print_operand !?", x);
4701 
      break;
4702 
    }
4703 
}
4704 
 
4705 
/* Target hook for assembling integer objects.  We need to define it
4706 
   here to work a round a bug in some versions of GAS, which couldn't
4707 
   handle values smaller than INT_MIN when printed in decimal.  */
4708 
 
4709 
static bool
4710 
s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4711 
{
4712 
  if (size == 8 && aligned_p
4713 
      && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4714 
    {
4715 
      fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4716 
               INTVAL (x));
4717 
      return true;
4718 
    }
4719 
  return default_assemble_integer (x, size, aligned_p);
4720 
}
4721 
 
4722 
/* Returns true if register REGNO is used  for forming
4723 
   a memory address in expression X.  */
4724 
 
4725 
static bool
4726 
reg_used_in_mem_p (int regno, rtx x)
4727 
{
4728 
  enum rtx_code code = GET_CODE (x);
4729 
  int i, j;
4730 
  const char *fmt;
4731 
 
4732 
  if (code == MEM)
4733 
    {
4734 
      if (refers_to_regno_p (regno, regno+1,
4735 
                             XEXP (x, 0), 0))
4736 
        return true;
4737 
    }
4738 
  else if (code == SET
4739 
           && GET_CODE (SET_DEST (x)) == PC)
4740 
    {
4741 
      if (refers_to_regno_p (regno, regno+1,
4742 
                             SET_SRC (x), 0))
4743 
        return true;
4744 
    }
4745 
 
4746 
  fmt = GET_RTX_FORMAT (code);
4747 
  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4748 
    {
4749 
      if (fmt[i] == 'e'
4750 
          && reg_used_in_mem_p (regno, XEXP (x, i)))
4751 
        return true;
4752 
 
4753 
      else if (fmt[i] == 'E')
4754 
        for (j = 0; j < XVECLEN (x, i); j++)
4755 
          if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4756 
            return true;
4757 
    }
4758 
  return false;
4759 
}
4760 
 
4761 
/* Returns true if expression DEP_RTX sets an address register
4762 
   used by instruction INSN to address memory.  */
4763 
 
4764 
static bool
4765 
addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4766 
{
4767 
  rtx target, pat;
4768 
 
4769 
  if (GET_CODE (dep_rtx) == INSN)
4770 
      dep_rtx = PATTERN (dep_rtx);
4771 
 
4772 
  if (GET_CODE (dep_rtx) == SET)
4773 
    {
4774 
      target = SET_DEST (dep_rtx);
4775 
      if (GET_CODE (target) == STRICT_LOW_PART)
4776 
        target = XEXP (target, 0);
4777 
      while (GET_CODE (target) == SUBREG)
4778 
        target = SUBREG_REG (target);
4779 
 
4780 
      if (GET_CODE (target) == REG)
4781 
        {
4782 
          int regno = REGNO (target);
4783 
 
4784 
          if (s390_safe_attr_type (insn) == TYPE_LA)
4785 
            {
4786 
              pat = PATTERN (insn);
4787 
              if (GET_CODE (pat) == PARALLEL)
4788 
                {
4789 
                  gcc_assert (XVECLEN (pat, 0) == 2);
4790 
                  pat = XVECEXP (pat, 0, 0);
4791 
                }
4792 
              gcc_assert (GET_CODE (pat) == SET);
4793 
              return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4794 
            }
4795 
          else if (get_attr_atype (insn) == ATYPE_AGEN)
4796 
            return reg_used_in_mem_p (regno, PATTERN (insn));
4797 
        }
4798 
    }
4799 
  return false;
4800 
}
4801 
 
4802 
/* Return 1, if dep_insn sets register used in insn in the agen unit.  */
4803 
 
4804 
int
4805 
s390_agen_dep_p (rtx dep_insn, rtx insn)
4806 
{
4807 
  rtx dep_rtx = PATTERN (dep_insn);
4808 
  int i;
4809 
 
4810 
  if (GET_CODE (dep_rtx) == SET
4811 
      && addr_generation_dependency_p (dep_rtx, insn))
4812 
    return 1;
4813 
  else if (GET_CODE (dep_rtx) == PARALLEL)
4814 
    {
4815 
      for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4816 
        {
4817 
          if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4818 
            return 1;
4819 
        }
4820 
    }
4821 
  return 0;
4822 
}
4823 
 
4824 
/* A C statement (sans semicolon) to update the integer scheduling priority
4825 
   INSN_PRIORITY (INSN).  Increase the priority to execute the INSN earlier,
4826 
   reduce the priority to execute INSN later.  Do not define this macro if
4827 
   you do not need to adjust the scheduling priorities of insns.
4828 
 
4829 
   A STD instruction should be scheduled earlier,
4830 
   in order to use the bypass.  */
4831 
 
4832 
static int
4833 
s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4834 
{
4835 
  if (! INSN_P (insn))
4836 
    return priority;
4837 
 
4838 
  if (s390_tune != PROCESSOR_2084_Z990
4839 
      && s390_tune != PROCESSOR_2094_Z9_109)
4840 
    return priority;
4841 
 
4842 
  switch (s390_safe_attr_type (insn))
4843 
    {
4844 
      case TYPE_FSTOREDF:
4845 
      case TYPE_FSTORESF:
4846 
        priority = priority << 3;
4847 
        break;
4848 
      case TYPE_STORE:
4849 
      case TYPE_STM:
4850 
        priority = priority << 1;
4851 
        break;
4852 
      default:
4853 
        break;
4854 
    }
4855 
  return priority;
4856 
}
4857 
 
4858 
/* The number of instructions that can be issued per cycle.  */
4859 
 
4860 
static int
4861 
s390_issue_rate (void)
4862 
{
4863 
  if (s390_tune == PROCESSOR_2084_Z990
4864 
      || s390_tune == PROCESSOR_2094_Z9_109)
4865 
    return 3;
4866 
  return 1;
4867 
}
4868 
 
4869 
static int
4870 
s390_first_cycle_multipass_dfa_lookahead (void)
4871 
{
4872 
  return 4;
4873 
}
4874 
 
4875 
 
4876 
/* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4877 
   Fix up MEMs as required.  */
4878 
 
4879 
static void
4880 
annotate_constant_pool_refs (rtx *x)
4881 
{
4882 
  int i, j;
4883 
  const char *fmt;
4884 
 
4885 
  gcc_assert (GET_CODE (*x) != SYMBOL_REF
4886 
              || !CONSTANT_POOL_ADDRESS_P (*x));
4887 
 
4888 
  /* Literal pool references can only occur inside a MEM ...  */
4889 
  if (GET_CODE (*x) == MEM)
4890 
    {
4891 
      rtx memref = XEXP (*x, 0);
4892 
 
4893 
      if (GET_CODE (memref) == SYMBOL_REF
4894 
          && CONSTANT_POOL_ADDRESS_P (memref))
4895 
        {
4896 
          rtx base = cfun->machine->base_reg;
4897 
          rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4898 
                                     UNSPEC_LTREF);
4899 
 
4900 
          *x = replace_equiv_address (*x, addr);
4901 
          return;
4902 
        }
4903 
 
4904 
      if (GET_CODE (memref) == CONST
4905 
          && GET_CODE (XEXP (memref, 0)) == PLUS
4906 
          && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4907 
          && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4908 
          && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4909 
        {
4910 
          HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4911 
          rtx sym = XEXP (XEXP (memref, 0), 0);
4912 
          rtx base = cfun->machine->base_reg;
4913 
          rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4914 
                                     UNSPEC_LTREF);
4915 
 
4916 
          *x = replace_equiv_address (*x, plus_constant (addr, off));
4917 
          return;
4918 
        }
4919 
    }
4920 
 
4921 
  /* ... or a load-address type pattern.  */
4922 
  if (GET_CODE (*x) == SET)
4923 
    {
4924 
      rtx addrref = SET_SRC (*x);
4925 
 
4926 
      if (GET_CODE (addrref) == SYMBOL_REF
4927 
          && CONSTANT_POOL_ADDRESS_P (addrref))
4928 
        {
4929 
          rtx base = cfun->machine->base_reg;
4930 
          rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4931 
                                     UNSPEC_LTREF);
4932 
 
4933 
          SET_SRC (*x) = addr;
4934 
          return;
4935 
        }
4936 
 
4937 
      if (GET_CODE (addrref) == CONST
4938 
          && GET_CODE (XEXP (addrref, 0)) == PLUS
4939 
          && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
4940 
          && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
4941 
          && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
4942 
        {
4943 
          HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
4944 
          rtx sym = XEXP (XEXP (addrref, 0), 0);
4945 
          rtx base = cfun->machine->base_reg;
4946 
          rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4947 
                                     UNSPEC_LTREF);
4948 
 
4949 
          SET_SRC (*x) = plus_constant (addr, off);
4950 
          return;
4951 
        }
4952 
    }
4953 
 
4954 
  /* Annotate LTREL_BASE as well.  */
4955 
  if (GET_CODE (*x) == UNSPEC
4956 
      && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4957 
    {
4958 
      rtx base = cfun->machine->base_reg;
4959 
      *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
4960 
                                  UNSPEC_LTREL_BASE);
4961 
      return;
4962 
    }
4963 
 
4964 
  fmt = GET_RTX_FORMAT (GET_CODE (*x));
4965 
  for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4966 
    {
4967 
      if (fmt[i] == 'e')
4968 
        {
4969 
          annotate_constant_pool_refs (&XEXP (*x, i));
4970 
        }
4971 
      else if (fmt[i] == 'E')
4972 
        {
4973 
          for (j = 0; j < XVECLEN (*x, i); j++)
4974 
            annotate_constant_pool_refs (&XVECEXP (*x, i, j));
4975 
        }
4976 
    }
4977 
}
4978 
 
4979 
/* Split all branches that exceed the maximum distance.
4980 
   Returns true if this created a new literal pool entry.  */
4981 
 
4982 
static int
4983 
s390_split_branches (void)
4984 
{
4985 
  rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
4986 
  int new_literal = 0, ret;
4987 
  rtx insn, pat, tmp, target;
4988 
  rtx *label;
4989 
 
4990 
  /* We need correct insn addresses.  */
4991 
 
4992 
  shorten_branches (get_insns ());
4993 
 
4994 
  /* Find all branches that exceed 64KB, and split them.  */
4995 
 
4996 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4997 
    {
4998 
      if (GET_CODE (insn) != JUMP_INSN)
4999 
        continue;
5000 
 
5001 
      pat = PATTERN (insn);
5002 
      if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5003 
        pat = XVECEXP (pat, 0, 0);
5004 
      if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5005 
        continue;
5006 
 
5007 
      if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5008 
        {
5009 
          label = &SET_SRC (pat);
5010 
        }
5011 
      else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5012 
        {
5013 
          if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5014 
            label = &XEXP (SET_SRC (pat), 1);
5015 
          else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5016 
            label = &XEXP (SET_SRC (pat), 2);
5017 
          else
5018 
            continue;
5019 
        }
5020 
      else
5021 
        continue;
5022 
 
5023 
      if (get_attr_length (insn) <= 4)
5024 
        continue;
5025 
 
5026 
      /* We are going to use the return register as scratch register,
5027 
         make sure it will be saved/restored by the prologue/epilogue.  */
5028 
      cfun_frame_layout.save_return_addr_p = 1;
5029 
 
5030 
      if (!flag_pic)
5031 
        {
5032 
          new_literal = 1;
5033 
          tmp = force_const_mem (Pmode, *label);
5034 
          tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5035 
          INSN_ADDRESSES_NEW (tmp, -1);
5036 
          annotate_constant_pool_refs (&PATTERN (tmp));
5037 
 
5038 
          target = temp_reg;
5039 
        }
5040 
      else
5041 
        {
5042 
          new_literal = 1;
5043 
          target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5044 
                                   UNSPEC_LTREL_OFFSET);
5045 
          target = gen_rtx_CONST (Pmode, target);
5046 
          target = force_const_mem (Pmode, target);
5047 
          tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5048 
          INSN_ADDRESSES_NEW (tmp, -1);
5049 
          annotate_constant_pool_refs (&PATTERN (tmp));
5050 
 
5051 
          target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5052 
                                                        cfun->machine->base_reg),
5053 
                                   UNSPEC_LTREL_BASE);
5054 
          target = gen_rtx_PLUS (Pmode, temp_reg, target);
5055 
        }
5056 
 
5057 
      ret = validate_change (insn, label, target, 0);
5058 
      gcc_assert (ret);
5059 
    }
5060 
 
5061 
  return new_literal;
5062 
}
5063 
 
5064 
 
5065 
/* Find an annotated literal pool symbol referenced in RTX X,
5066 
   and store it at REF.  Will abort if X contains references to
5067 
   more than one such pool symbol; multiple references to the same
5068 
   symbol are allowed, however.
5069 
 
5070 
   The rtx pointed to by REF must be initialized to NULL_RTX
5071 
   by the caller before calling this routine.  */
5072 
 
5073 
static void
5074 
find_constant_pool_ref (rtx x, rtx *ref)
5075 
{
5076 
  int i, j;
5077 
  const char *fmt;
5078 
 
5079 
  /* Ignore LTREL_BASE references.  */
5080 
  if (GET_CODE (x) == UNSPEC
5081 
      && XINT (x, 1) == UNSPEC_LTREL_BASE)
5082 
    return;
5083 
  /* Likewise POOL_ENTRY insns.  */
5084 
  if (GET_CODE (x) == UNSPEC_VOLATILE
5085 
      && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5086 
    return;
5087 
 
5088 
  gcc_assert (GET_CODE (x) != SYMBOL_REF
5089 
              || !CONSTANT_POOL_ADDRESS_P (x));
5090 
 
5091 
  if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5092 
    {
5093 
      rtx sym = XVECEXP (x, 0, 0);
5094 
      gcc_assert (GET_CODE (sym) == SYMBOL_REF
5095 
                  && CONSTANT_POOL_ADDRESS_P (sym));
5096 
 
5097 
      if (*ref == NULL_RTX)
5098 
        *ref = sym;
5099 
      else
5100 
        gcc_assert (*ref == sym);
5101 
 
5102 
      return;
5103 
    }
5104 
 
5105 
  fmt = GET_RTX_FORMAT (GET_CODE (x));
5106 
  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5107 
    {
5108 
      if (fmt[i] == 'e')
5109 
        {
5110 
          find_constant_pool_ref (XEXP (x, i), ref);
5111 
        }
5112 
      else if (fmt[i] == 'E')
5113 
        {
5114 
          for (j = 0; j < XVECLEN (x, i); j++)
5115 
            find_constant_pool_ref (XVECEXP (x, i, j), ref);
5116 
        }
5117 
    }
5118 
}
5119 
 
5120 
/* Replace every reference to the annotated literal pool
5121 
   symbol REF in X by its base plus OFFSET.  */
5122 
 
5123 
static void
5124 
replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5125 
{
5126 
  int i, j;
5127 
  const char *fmt;
5128 
 
5129 
  gcc_assert (*x != ref);
5130 
 
5131 
  if (GET_CODE (*x) == UNSPEC
5132 
      && XINT (*x, 1) == UNSPEC_LTREF
5133 
      && XVECEXP (*x, 0, 0) == ref)
5134 
    {
5135 
      *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5136 
      return;
5137 
    }
5138 
 
5139 
  if (GET_CODE (*x) == PLUS
5140 
      && GET_CODE (XEXP (*x, 1)) == CONST_INT
5141 
      && GET_CODE (XEXP (*x, 0)) == UNSPEC
5142 
      && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5143 
      && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5144 
    {
5145 
      rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5146 
      *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5147 
      return;
5148 
    }
5149 
 
5150 
  fmt = GET_RTX_FORMAT (GET_CODE (*x));
5151 
  for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5152 
    {
5153 
      if (fmt[i] == 'e')
5154 
        {
5155 
          replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5156 
        }
5157 
      else if (fmt[i] == 'E')
5158 
        {
5159 
          for (j = 0; j < XVECLEN (*x, i); j++)
5160 
            replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5161 
        }
5162 
    }
5163 
}
5164 
 
5165 
/* Check whether X contains an UNSPEC_LTREL_BASE.
5166 
   Return its constant pool symbol if found, NULL_RTX otherwise.  */
5167 
 
5168 
static rtx
5169 
find_ltrel_base (rtx x)
5170 
{
5171 
  int i, j;
5172 
  const char *fmt;
5173 
 
5174 
  if (GET_CODE (x) == UNSPEC
5175 
      && XINT (x, 1) == UNSPEC_LTREL_BASE)
5176 
    return XVECEXP (x, 0, 0);
5177 
 
5178 
  fmt = GET_RTX_FORMAT (GET_CODE (x));
5179 
  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5180 
    {
5181 
      if (fmt[i] == 'e')
5182 
        {
5183 
          rtx fnd = find_ltrel_base (XEXP (x, i));
5184 
          if (fnd)
5185 
            return fnd;
5186 
        }
5187 
      else if (fmt[i] == 'E')
5188 
        {
5189 
          for (j = 0; j < XVECLEN (x, i); j++)
5190 
            {
5191 
              rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5192 
              if (fnd)
5193 
                return fnd;
5194 
            }
5195 
        }
5196 
    }
5197 
 
5198 
  return NULL_RTX;
5199 
}
5200 
 
5201 
/* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base.  */
5202 
 
5203 
static void
5204 
replace_ltrel_base (rtx *x)
5205 
{
5206 
  int i, j;
5207 
  const char *fmt;
5208 
 
5209 
  if (GET_CODE (*x) == UNSPEC
5210 
      && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5211 
    {
5212 
      *x = XVECEXP (*x, 0, 1);
5213 
      return;
5214 
    }
5215 
 
5216 
  fmt = GET_RTX_FORMAT (GET_CODE (*x));
5217 
  for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5218 
    {
5219 
      if (fmt[i] == 'e')
5220 
        {
5221 
          replace_ltrel_base (&XEXP (*x, i));
5222 
        }
5223 
      else if (fmt[i] == 'E')
5224 
        {
5225 
          for (j = 0; j < XVECLEN (*x, i); j++)
5226 
            replace_ltrel_base (&XVECEXP (*x, i, j));
5227 
        }
5228 
    }
5229 
}
5230 
 
5231 
 
5232 
/* We keep a list of constants which we have to add to internal
5233 
   constant tables in the middle of large functions.  */
5234 
 
5235 
#define NR_C_MODES 8
5236 
enum machine_mode constant_modes[NR_C_MODES] =
5237 
{
5238 
  TFmode, TImode,
5239 
  DFmode, DImode,
5240 
  SFmode, SImode,
5241 
  HImode,
5242 
  QImode
5243 
};
5244 
 
5245 
struct constant
5246 
{
5247 
  struct constant *next;
5248 
  rtx value;
5249 
  rtx label;
5250 
};
5251 
 
5252 
struct constant_pool
5253 
{
5254 
  struct constant_pool *next;
5255 
  rtx first_insn;
5256 
  rtx pool_insn;
5257 
  bitmap insns;
5258 
 
5259 
  struct constant *constants[NR_C_MODES];
5260 
  struct constant *execute;
5261 
  rtx label;
5262 
  int size;
5263 
};
5264 
 
5265 
/* Allocate new constant_pool structure.  */
5266 
 
5267 
static struct constant_pool *
5268 
s390_alloc_pool (void)
5269 
{
5270 
  struct constant_pool *pool;
5271 
  int i;
5272 
 
5273 
  pool = (struct constant_pool *) xmalloc (sizeof *pool);
5274 
  pool->next = NULL;
5275 
  for (i = 0; i < NR_C_MODES; i++)
5276 
    pool->constants[i] = NULL;
5277 
 
5278 
  pool->execute = NULL;
5279 
  pool->label = gen_label_rtx ();
5280 
  pool->first_insn = NULL_RTX;
5281 
  pool->pool_insn = NULL_RTX;
5282 
  pool->insns = BITMAP_ALLOC (NULL);
5283 
  pool->size = 0;
5284 
 
5285 
  return pool;
5286 
}
5287 
 
5288 
/* Create new constant pool covering instructions starting at INSN
5289 
   and chain it to the end of POOL_LIST.  */
5290 
 
5291 
static struct constant_pool *
5292 
s390_start_pool (struct constant_pool **pool_list, rtx insn)
5293 
{
5294 
  struct constant_pool *pool, **prev;
5295 
 
5296 
  pool = s390_alloc_pool ();
5297 
  pool->first_insn = insn;
5298 
 
5299 
  for (prev = pool_list; *prev; prev = &(*prev)->next)
5300 
    ;
5301 
  *prev = pool;
5302 
 
5303 
  return pool;
5304 
}
5305 
 
5306 
/* End range of instructions covered by POOL at INSN and emit
5307 
   placeholder insn representing the pool.  */
5308 
 
5309 
static void
5310 
s390_end_pool (struct constant_pool *pool, rtx insn)
5311 
{
5312 
  rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5313 
 
5314 
  if (!insn)
5315 
    insn = get_last_insn ();
5316 
 
5317 
  pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5318 
  INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5319 
}
5320 
 
5321 
/* Add INSN to the list of insns covered by POOL.  */
5322 
 
5323 
static void
5324 
s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5325 
{
5326 
  bitmap_set_bit (pool->insns, INSN_UID (insn));
5327 
}
5328 
 
5329 
/* Return pool out of POOL_LIST that covers INSN.  */
5330 
 
5331 
static struct constant_pool *
5332 
s390_find_pool (struct constant_pool *pool_list, rtx insn)
5333 
{
5334 
  struct constant_pool *pool;
5335 
 
5336 
  for (pool = pool_list; pool; pool = pool->next)
5337 
    if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5338 
      break;
5339 
 
5340 
  return pool;
5341 
}
5342 
 
5343 
/* Add constant VAL of mode MODE to the constant pool POOL.  */
5344 
 
5345 
static void
5346 
s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5347 
{
5348 
  struct constant *c;
5349 
  int i;
5350 
 
5351 
  for (i = 0; i < NR_C_MODES; i++)
5352 
    if (constant_modes[i] == mode)
5353 
      break;
5354 
  gcc_assert (i != NR_C_MODES);
5355 
 
5356 
  for (c = pool->constants[i]; c != NULL; c = c->next)
5357 
    if (rtx_equal_p (val, c->value))
5358 
      break;
5359 
 
5360 
  if (c == NULL)
5361 
    {
5362 
      c = (struct constant *) xmalloc (sizeof *c);
5363 
      c->value = val;
5364 
      c->label = gen_label_rtx ();
5365 
      c->next = pool->constants[i];
5366 
      pool->constants[i] = c;
5367 
      pool->size += GET_MODE_SIZE (mode);
5368 
    }
5369 
}
5370 
 
5371 
/* Find constant VAL of mode MODE in the constant pool POOL.
5372 
   Return an RTX describing the distance from the start of
5373 
   the pool to the location of the new constant.  */
5374 
 
5375 
static rtx
5376 
s390_find_constant (struct constant_pool *pool, rtx val,
5377 
                    enum machine_mode mode)
5378 
{
5379 
  struct constant *c;
5380 
  rtx offset;
5381 
  int i;
5382 
 
5383 
  for (i = 0; i < NR_C_MODES; i++)
5384 
    if (constant_modes[i] == mode)
5385 
      break;
5386 
  gcc_assert (i != NR_C_MODES);
5387 
 
5388 
  for (c = pool->constants[i]; c != NULL; c = c->next)
5389 
    if (rtx_equal_p (val, c->value))
5390 
      break;
5391 
 
5392 
  gcc_assert (c);
5393 
 
5394 
  offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5395 
                                 gen_rtx_LABEL_REF (Pmode, pool->label));
5396 
  offset = gen_rtx_CONST (Pmode, offset);
5397 
  return offset;
5398 
}
5399 
 
5400 
/* Check whether INSN is an execute.  Return the label_ref to its
5401 
   execute target template if so, NULL_RTX otherwise.  */
5402 
 
5403 
static rtx
5404 
s390_execute_label (rtx insn)
5405 
{
5406 
  if (GET_CODE (insn) == INSN
5407 
      && GET_CODE (PATTERN (insn)) == PARALLEL
5408 
      && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5409 
      && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5410 
    return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5411 
 
5412 
  return NULL_RTX;
5413 
}
5414 
 
5415 
/* Add execute target for INSN to the constant pool POOL.  */
5416 
 
5417 
static void
5418 
s390_add_execute (struct constant_pool *pool, rtx insn)
5419 
{
5420 
  struct constant *c;
5421 
 
5422 
  for (c = pool->execute; c != NULL; c = c->next)
5423 
    if (INSN_UID (insn) == INSN_UID (c->value))
5424 
      break;
5425 
 
5426 
  if (c == NULL)
5427 
    {
5428 
      c = (struct constant *) xmalloc (sizeof *c);
5429 
      c->value = insn;
5430 
      c->label = gen_label_rtx ();
5431 
      c->next = pool->execute;
5432 
      pool->execute = c;
5433 
      pool->size += 6;
5434 
    }
5435 
}
5436 
 
5437 
/* Find execute target for INSN in the constant pool POOL.
5438 
   Return an RTX describing the distance from the start of
5439 
   the pool to the location of the execute target.  */
5440 
 
5441 
static rtx
5442 
s390_find_execute (struct constant_pool *pool, rtx insn)
5443 
{
5444 
  struct constant *c;
5445 
  rtx offset;
5446 
 
5447 
  for (c = pool->execute; c != NULL; c = c->next)
5448 
    if (INSN_UID (insn) == INSN_UID (c->value))
5449 
      break;
5450 
 
5451 
  gcc_assert (c);
5452 
 
5453 
  offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5454 
                                 gen_rtx_LABEL_REF (Pmode, pool->label));
5455 
  offset = gen_rtx_CONST (Pmode, offset);
5456 
  return offset;
5457 
}
5458 
 
5459 
/* For an execute INSN, extract the execute target template.  */
5460 
 
5461 
static rtx
5462 
s390_execute_target (rtx insn)
5463 
{
5464 
  rtx pattern = PATTERN (insn);
5465 
  gcc_assert (s390_execute_label (insn));
5466 
 
5467 
  if (XVECLEN (pattern, 0) == 2)
5468 
    {
5469 
      pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5470 
    }
5471 
  else
5472 
    {
5473 
      rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5474 
      int i;
5475 
 
5476 
      for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5477 
        RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5478 
 
5479 
      pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5480 
    }
5481 
 
5482 
  return pattern;
5483 
}
5484 
 
5485 
/* Indicate that INSN cannot be duplicated.  This is the case for
5486 
   execute insns that carry a unique label.  */
5487 
 
5488 
static bool
5489 
s390_cannot_copy_insn_p (rtx insn)
5490 
{
5491 
  rtx label = s390_execute_label (insn);
5492 
  return label && label != const0_rtx;
5493 
}
5494 
 
5495 
/* Dump out the constants in POOL.  If REMOTE_LABEL is true,
5496 
   do not emit the pool base label.  */
5497 
 
5498 
static void
5499 
s390_dump_pool (struct constant_pool *pool, bool remote_label)
5500 
{
5501 
  struct constant *c;
5502 
  rtx insn = pool->pool_insn;
5503 
  int i;
5504 
 
5505 
  /* Switch to rodata section.  */
5506 
  if (TARGET_CPU_ZARCH)
5507 
    {
5508 
      insn = emit_insn_after (gen_pool_section_start (), insn);
5509 
      INSN_ADDRESSES_NEW (insn, -1);
5510 
    }
5511 
 
5512 
  /* Ensure minimum pool alignment.  */
5513 
  if (TARGET_CPU_ZARCH)
5514 
    insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5515 
  else
5516 
    insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5517 
  INSN_ADDRESSES_NEW (insn, -1);
5518 
 
5519 
  /* Emit pool base label.  */
5520 
  if (!remote_label)
5521 
    {
5522 
      insn = emit_label_after (pool->label, insn);
5523 
      INSN_ADDRESSES_NEW (insn, -1);
5524 
    }
5525 
 
5526 
  /* Dump constants in descending alignment requirement order,
5527 
     ensuring proper alignment for every constant.  */
5528 
  for (i = 0; i < NR_C_MODES; i++)
5529 
    for (c = pool->constants[i]; c; c = c->next)
5530 
      {
5531 
        /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references.  */
5532 
        rtx value = c->value;
5533 
        if (GET_CODE (value) == CONST
5534 
            && GET_CODE (XEXP (value, 0)) == UNSPEC
5535 
            && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5536 
            && XVECLEN (XEXP (value, 0), 0) == 1)
5537 
          {
5538 
            value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5539 
                                   gen_rtx_LABEL_REF (VOIDmode, pool->label));
5540 
            value = gen_rtx_CONST (VOIDmode, value);
5541 
          }
5542 
 
5543 
        insn = emit_label_after (c->label, insn);
5544 
        INSN_ADDRESSES_NEW (insn, -1);
5545 
 
5546 
        value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5547 
                                         gen_rtvec (1, value),
5548 
                                         UNSPECV_POOL_ENTRY);
5549 
        insn = emit_insn_after (value, insn);
5550 
        INSN_ADDRESSES_NEW (insn, -1);
5551 
      }
5552 
 
5553 
  /* Ensure minimum alignment for instructions.  */
5554 
  insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5555 
  INSN_ADDRESSES_NEW (insn, -1);
5556 
 
5557 
  /* Output in-pool execute template insns.  */
5558 
  for (c = pool->execute; c; c = c->next)
5559 
    {
5560 
      insn = emit_label_after (c->label, insn);
5561 
      INSN_ADDRESSES_NEW (insn, -1);
5562 
 
5563 
      insn = emit_insn_after (s390_execute_target (c->value), insn);
5564 
      INSN_ADDRESSES_NEW (insn, -1);
5565 
    }
5566 
 
5567 
  /* Switch back to previous section.  */
5568 
  if (TARGET_CPU_ZARCH)
5569 
    {
5570 
      insn = emit_insn_after (gen_pool_section_end (), insn);
5571 
      INSN_ADDRESSES_NEW (insn, -1);
5572 
    }
5573 
 
5574 
  insn = emit_barrier_after (insn);
5575 
  INSN_ADDRESSES_NEW (insn, -1);
5576 
 
5577 
  /* Remove placeholder insn.  */
5578 
  remove_insn (pool->pool_insn);
5579 
}
5580 
 
5581 
/* Free all memory used by POOL.  */
5582 
 
5583 
static void
5584 
s390_free_pool (struct constant_pool *pool)
5585 
{
5586 
  struct constant *c, *next;
5587 
  int i;
5588 
 
5589 
  for (i = 0; i < NR_C_MODES; i++)
5590 
    for (c = pool->constants[i]; c; c = next)
5591 
      {
5592 
        next = c->next;
5593 
        free (c);
5594 
      }
5595 
 
5596 
  for (c = pool->execute; c; c = next)
5597 
    {
5598 
      next = c->next;
5599 
      free (c);
5600 
    }
5601 
 
5602 
  BITMAP_FREE (pool->insns);
5603 
  free (pool);
5604 
}
5605 
 
5606 
 
5607 
/* Collect main literal pool.  Return NULL on overflow.  */
5608 
 
5609 
static struct constant_pool *
5610 
s390_mainpool_start (void)
5611 
{
5612 
  struct constant_pool *pool;
5613 
  rtx insn;
5614 
 
5615 
  pool = s390_alloc_pool ();
5616 
 
5617 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5618 
    {
5619 
      if (GET_CODE (insn) == INSN
5620 
          && GET_CODE (PATTERN (insn)) == SET
5621 
          && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5622 
          && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5623 
        {
5624 
          gcc_assert (!pool->pool_insn);
5625 
          pool->pool_insn = insn;
5626 
        }
5627 
 
5628 
      if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5629 
        {
5630 
          s390_add_execute (pool, insn);
5631 
        }
5632 
      else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5633 
        {
5634 
          rtx pool_ref = NULL_RTX;
5635 
          find_constant_pool_ref (PATTERN (insn), &pool_ref);
5636 
          if (pool_ref)
5637 
            {
5638 
              rtx constant = get_pool_constant (pool_ref);
5639 
              enum machine_mode mode = get_pool_mode (pool_ref);
5640 
              s390_add_constant (pool, constant, mode);
5641 
            }
5642 
        }
5643 
    }
5644 
 
5645 
  gcc_assert (pool->pool_insn || pool->size == 0);
5646 
 
5647 
  if (pool->size >= 4096)
5648 
    {
5649 
      /* We're going to chunkify the pool, so remove the main
5650 
         pool placeholder insn.  */
5651 
      remove_insn (pool->pool_insn);
5652 
 
5653 
      s390_free_pool (pool);
5654 
      pool = NULL;
5655 
    }
5656 
 
5657 
  return pool;
5658 
}
5659 
 
5660 
/* POOL holds the main literal pool as collected by s390_mainpool_start.
5661 
   Modify the current function to output the pool constants as well as
5662 
   the pool register setup instruction.  */
5663 
 
5664 
static void
5665 
s390_mainpool_finish (struct constant_pool *pool)
5666 
{
5667 
  rtx base_reg = cfun->machine->base_reg;
5668 
  rtx insn;
5669 
 
5670 
  /* If the pool is empty, we're done.  */
5671 
  if (pool->size == 0)
5672 
    {
5673 
      /* We don't actually need a base register after all.  */
5674 
      cfun->machine->base_reg = NULL_RTX;
5675 
 
5676 
      if (pool->pool_insn)
5677 
        remove_insn (pool->pool_insn);
5678 
      s390_free_pool (pool);
5679 
      return;
5680 
    }
5681 
 
5682 
  /* We need correct insn addresses.  */
5683 
  shorten_branches (get_insns ());
5684 
 
5685 
  /* On zSeries, we use a LARL to load the pool register.  The pool is
5686 
     located in the .rodata section, so we emit it after the function.  */
5687 
  if (TARGET_CPU_ZARCH)
5688 
    {
5689 
      insn = gen_main_base_64 (base_reg, pool->label);
5690 
      insn = emit_insn_after (insn, pool->pool_insn);
5691 
      INSN_ADDRESSES_NEW (insn, -1);
5692 
      remove_insn (pool->pool_insn);
5693 
 
5694 
      insn = get_last_insn ();
5695 
      pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5696 
      INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5697 
 
5698 
      s390_dump_pool (pool, 0);
5699 
    }
5700 
 
5701 
  /* On S/390, if the total size of the function's code plus literal pool
5702 
     does not exceed 4096 bytes, we use BASR to set up a function base
5703 
     pointer, and emit the literal pool at the end of the function.  */
5704 
  else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5705 
           + pool->size + 8 /* alignment slop */ < 4096)
5706 
    {
5707 
      insn = gen_main_base_31_small (base_reg, pool->label);
5708 
      insn = emit_insn_after (insn, pool->pool_insn);
5709 
      INSN_ADDRESSES_NEW (insn, -1);
5710 
      remove_insn (pool->pool_insn);
5711 
 
5712 
      insn = emit_label_after (pool->label, insn);
5713 
      INSN_ADDRESSES_NEW (insn, -1);
5714 
 
5715 
      insn = get_last_insn ();
5716 
      pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5717 
      INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5718 
 
5719 
      s390_dump_pool (pool, 1);
5720 
    }
5721 
 
5722 
  /* Otherwise, we emit an inline literal pool and use BASR to branch
5723 
     over it, setting up the pool register at the same time.  */
5724 
  else
5725 
    {
5726 
      rtx pool_end = gen_label_rtx ();
5727 
 
5728 
      insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5729 
      insn = emit_insn_after (insn, pool->pool_insn);
5730 
      INSN_ADDRESSES_NEW (insn, -1);
5731 
      remove_insn (pool->pool_insn);
5732 
 
5733 
      insn = emit_label_after (pool->label, insn);
5734 
      INSN_ADDRESSES_NEW (insn, -1);
5735 
 
5736 
      pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5737 
      INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5738 
 
5739 
      insn = emit_label_after (pool_end, pool->pool_insn);
5740 
      INSN_ADDRESSES_NEW (insn, -1);
5741 
 
5742 
      s390_dump_pool (pool, 1);
5743 
    }
5744 
 
5745 
 
5746 
  /* Replace all literal pool references.  */
5747 
 
5748 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5749 
    {
5750 
      if (INSN_P (insn))
5751 
        replace_ltrel_base (&PATTERN (insn));
5752 
 
5753 
      if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5754 
        {
5755 
          rtx addr, pool_ref = NULL_RTX;
5756 
          find_constant_pool_ref (PATTERN (insn), &pool_ref);
5757 
          if (pool_ref)
5758 
            {
5759 
              if (s390_execute_label (insn))
5760 
                addr = s390_find_execute (pool, insn);
5761 
              else
5762 
                addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5763 
                                                 get_pool_mode (pool_ref));
5764 
 
5765 
              replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5766 
              INSN_CODE (insn) = -1;
5767 
            }
5768 
        }
5769 
    }
5770 
 
5771 
 
5772 
  /* Free the pool.  */
5773 
  s390_free_pool (pool);
5774 
}
5775 
 
5776 
/* POOL holds the main literal pool as collected by s390_mainpool_start.
5777 
   We have decided we cannot use this pool, so revert all changes
5778 
   to the current function that were done by s390_mainpool_start.  */
5779 
static void
5780 
s390_mainpool_cancel (struct constant_pool *pool)
5781 
{
5782 
  /* We didn't actually change the instruction stream, so simply
5783 
     free the pool memory.  */
5784 
  s390_free_pool (pool);
5785 
}
5786 
 
5787 
 
5788 
/* Chunkify the literal pool.  */
5789 
 
5790 
#define S390_POOL_CHUNK_MIN     0xc00
5791 
#define S390_POOL_CHUNK_MAX     0xe00
5792 
 
5793 
static struct constant_pool *
5794 
s390_chunkify_start (void)
5795 
{
5796 
  struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5797 
  int extra_size = 0;
5798 
  bitmap far_labels;
5799 
  rtx pending_ltrel = NULL_RTX;
5800 
  rtx insn;
5801 
 
5802 
  rtx (*gen_reload_base) (rtx, rtx) =
5803 
    TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5804 
 
5805 
 
5806 
  /* We need correct insn addresses.  */
5807 
 
5808 
  shorten_branches (get_insns ());
5809 
 
5810 
  /* Scan all insns and move literals to pool chunks.  */
5811 
 
5812 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5813 
    {
5814 
      /* Check for pending LTREL_BASE.  */
5815 
      if (INSN_P (insn))
5816 
        {
5817 
          rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5818 
          if (ltrel_base)
5819 
            {
5820 
              gcc_assert (ltrel_base == pending_ltrel);
5821 
              pending_ltrel = NULL_RTX;
5822 
            }
5823 
        }
5824 
 
5825 
      if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5826 
        {
5827 
          if (!curr_pool)
5828 
            curr_pool = s390_start_pool (&pool_list, insn);
5829 
 
5830 
          s390_add_execute (curr_pool, insn);
5831 
          s390_add_pool_insn (curr_pool, insn);
5832 
        }
5833 
      else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5834 
        {
5835 
          rtx pool_ref = NULL_RTX;
5836 
          find_constant_pool_ref (PATTERN (insn), &pool_ref);
5837 
          if (pool_ref)
5838 
            {
5839 
              rtx constant = get_pool_constant (pool_ref);
5840 
              enum machine_mode mode = get_pool_mode (pool_ref);
5841 
 
5842 
              if (!curr_pool)
5843 
                curr_pool = s390_start_pool (&pool_list, insn);
5844 
 
5845 
              s390_add_constant (curr_pool, constant, mode);
5846 
              s390_add_pool_insn (curr_pool, insn);
5847 
 
5848 
              /* Don't split the pool chunk between a LTREL_OFFSET load
5849 
                 and the corresponding LTREL_BASE.  */
5850 
              if (GET_CODE (constant) == CONST
5851 
                  && GET_CODE (XEXP (constant, 0)) == UNSPEC
5852 
                  && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5853 
                {
5854 
                  gcc_assert (!pending_ltrel);
5855 
                  pending_ltrel = pool_ref;
5856 
                }
5857 
            }
5858 
        }
5859 
 
5860 
      if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5861 
        {
5862 
          if (curr_pool)
5863 
            s390_add_pool_insn (curr_pool, insn);
5864 
          /* An LTREL_BASE must follow within the same basic block.  */
5865 
          gcc_assert (!pending_ltrel);
5866 
        }
5867 
 
5868 
      if (!curr_pool
5869 
          || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5870 
          || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5871 
        continue;
5872 
 
5873 
      if (TARGET_CPU_ZARCH)
5874 
        {
5875 
          if (curr_pool->size < S390_POOL_CHUNK_MAX)
5876 
            continue;
5877 
 
5878 
          s390_end_pool (curr_pool, NULL_RTX);
5879 
          curr_pool = NULL;
5880 
        }
5881 
      else
5882 
        {
5883 
          int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5884 
                           - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5885 
                         + extra_size;
5886 
 
5887 
          /* We will later have to insert base register reload insns.
5888 
             Those will have an effect on code size, which we need to
5889 
             consider here.  This calculation makes rather pessimistic
5890 
             worst-case assumptions.  */
5891 
          if (GET_CODE (insn) == CODE_LABEL)
5892 
            extra_size += 6;
5893 
 
5894 
          if (chunk_size < S390_POOL_CHUNK_MIN
5895 
              && curr_pool->size < S390_POOL_CHUNK_MIN)
5896 
            continue;
5897 
 
5898 
          /* Pool chunks can only be inserted after BARRIERs ...  */
5899 
          if (GET_CODE (insn) == BARRIER)
5900 
            {
5901 
              s390_end_pool (curr_pool, insn);
5902 
              curr_pool = NULL;
5903 
              extra_size = 0;
5904 
            }
5905 
 
5906 
          /* ... so if we don't find one in time, create one.  */
5907 
          else if ((chunk_size > S390_POOL_CHUNK_MAX
5908 
                   || curr_pool->size > S390_POOL_CHUNK_MAX))
5909 
            {
5910 
              rtx label, jump, barrier;
5911 
 
5912 
              /* We can insert the barrier only after a 'real' insn.  */
5913 
              if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5914 
                continue;
5915 
              if (get_attr_length (insn) == 0)
5916 
                continue;
5917 
 
5918 
              /* Don't separate LTREL_BASE from the corresponding
5919 
                 LTREL_OFFSET load.  */
5920 
              if (pending_ltrel)
5921 
                continue;
5922 
 
5923 
              label = gen_label_rtx ();
5924 
              jump = emit_jump_insn_after (gen_jump (label), insn);
5925 
              barrier = emit_barrier_after (jump);
5926 
              insn = emit_label_after (label, barrier);
5927 
              JUMP_LABEL (jump) = label;
5928 
              LABEL_NUSES (label) = 1;
5929 
 
5930 
              INSN_ADDRESSES_NEW (jump, -1);
5931 
              INSN_ADDRESSES_NEW (barrier, -1);
5932 
              INSN_ADDRESSES_NEW (insn, -1);
5933 
 
5934 
              s390_end_pool (curr_pool, barrier);
5935 
              curr_pool = NULL;
5936 
              extra_size = 0;
5937 
            }
5938 
        }
5939 
    }
5940 
 
5941 
  if (curr_pool)
5942 
    s390_end_pool (curr_pool, NULL_RTX);
5943 
  gcc_assert (!pending_ltrel);
5944 
 
5945 
  /* Find all labels that are branched into
5946 
     from an insn belonging to a different chunk.  */
5947 
 
5948 
  far_labels = BITMAP_ALLOC (NULL);
5949 
 
5950 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5951 
    {
5952 
      /* Labels marked with LABEL_PRESERVE_P can be target
5953 
         of non-local jumps, so we have to mark them.
5954 
         The same holds for named labels.
5955 
 
5956 
         Don't do that, however, if it is the label before
5957 
         a jump table.  */
5958 
 
5959 
      if (GET_CODE (insn) == CODE_LABEL
5960 
          && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
5961 
        {
5962 
          rtx vec_insn = next_real_insn (insn);
5963 
          rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5964 
                        PATTERN (vec_insn) : NULL_RTX;
5965 
          if (!vec_pat
5966 
              || !(GET_CODE (vec_pat) == ADDR_VEC
5967 
                   || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5968 
            bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
5969 
        }
5970 
 
5971 
      /* If we have a direct jump (conditional or unconditional)
5972 
         or a casesi jump, check all potential targets.  */
5973 
      else if (GET_CODE (insn) == JUMP_INSN)
5974 
        {
5975 
          rtx pat = PATTERN (insn);
5976 
          if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5977 
            pat = XVECEXP (pat, 0, 0);
5978 
 
5979 
          if (GET_CODE (pat) == SET)
5980 
            {
5981 
              rtx label = JUMP_LABEL (insn);
5982 
              if (label)
5983 
                {
5984 
                  if (s390_find_pool (pool_list, label)
5985 
                      != s390_find_pool (pool_list, insn))
5986 
                    bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
5987 
                }
5988 
            }
5989 
          else if (GET_CODE (pat) == PARALLEL
5990 
                   && XVECLEN (pat, 0) == 2
5991 
                   && GET_CODE (XVECEXP (pat, 0, 0)) == SET
5992 
                   && GET_CODE (XVECEXP (pat, 0, 1)) == USE
5993 
                   && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
5994 
            {
5995 
              /* Find the jump table used by this casesi jump.  */
5996 
              rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
5997 
              rtx vec_insn = next_real_insn (vec_label);
5998 
              rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5999 
                            PATTERN (vec_insn) : NULL_RTX;
6000 
              if (vec_pat
6001 
                  && (GET_CODE (vec_pat) == ADDR_VEC
6002 
                      || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6003 
                {
6004 
                  int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6005 
 
6006 
                  for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6007 
                    {
6008 
                      rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6009 
 
6010 
                      if (s390_find_pool (pool_list, label)
6011 
                          != s390_find_pool (pool_list, insn))
6012 
                        bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6013 
                    }
6014 
                }
6015 
            }
6016 
        }
6017 
    }
6018 
 
6019 
  /* Insert base register reload insns before every pool.  */
6020 
 
6021 
  for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6022 
    {
6023 
      rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6024 
                                      curr_pool->label);
6025 
      rtx insn = curr_pool->first_insn;
6026 
      INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6027 
    }
6028 
 
6029 
  /* Insert base register reload insns at every far label.  */
6030 
 
6031 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6032 
    if (GET_CODE (insn) == CODE_LABEL
6033 
        && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6034 
      {
6035 
        struct constant_pool *pool = s390_find_pool (pool_list, insn);
6036 
        if (pool)
6037 
          {
6038 
            rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6039 
                                            pool->label);
6040 
            INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6041 
          }
6042 
      }
6043 
 
6044 
 
6045 
  BITMAP_FREE (far_labels);
6046 
 
6047 
 
6048 
  /* Recompute insn addresses.  */
6049 
 
6050 
  init_insn_lengths ();
6051 
  shorten_branches (get_insns ());
6052 
 
6053 
  return pool_list;
6054 
}
6055 
 
6056 
/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6057 
   After we have decided to use this list, finish implementing
6058 
   all changes to the current function as required.  */
6059 
 
6060 
static void
6061 
s390_chunkify_finish (struct constant_pool *pool_list)
6062 
{
6063 
  struct constant_pool *curr_pool = NULL;
6064 
  rtx insn;
6065 
 
6066 
 
6067 
  /* Replace all literal pool references.  */
6068 
 
6069 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6070 
    {
6071 
      if (INSN_P (insn))
6072 
        replace_ltrel_base (&PATTERN (insn));
6073 
 
6074 
      curr_pool = s390_find_pool (pool_list, insn);
6075 
      if (!curr_pool)
6076 
        continue;
6077 
 
6078 
      if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6079 
        {
6080 
          rtx addr, pool_ref = NULL_RTX;
6081 
          find_constant_pool_ref (PATTERN (insn), &pool_ref);
6082 
          if (pool_ref)
6083 
            {
6084 
              if (s390_execute_label (insn))
6085 
                addr = s390_find_execute (curr_pool, insn);
6086 
              else
6087 
                addr = s390_find_constant (curr_pool,
6088 
                                           get_pool_constant (pool_ref),
6089 
                                           get_pool_mode (pool_ref));
6090 
 
6091 
              replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6092 
              INSN_CODE (insn) = -1;
6093 
            }
6094 
        }
6095 
    }
6096 
 
6097 
  /* Dump out all literal pools.  */
6098 
 
6099 
  for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6100 
    s390_dump_pool (curr_pool, 0);
6101 
 
6102 
  /* Free pool list.  */
6103 
 
6104 
  while (pool_list)
6105 
    {
6106 
      struct constant_pool *next = pool_list->next;
6107 
      s390_free_pool (pool_list);
6108 
      pool_list = next;
6109 
    }
6110 
}
6111 
 
6112 
/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6113 
   We have decided we cannot use this list, so revert all changes
6114 
   to the current function that were done by s390_chunkify_start.  */
6115 
 
6116 
static void
6117 
s390_chunkify_cancel (struct constant_pool *pool_list)
6118 
{
6119 
  struct constant_pool *curr_pool = NULL;
6120 
  rtx insn;
6121 
 
6122 
  /* Remove all pool placeholder insns.  */
6123 
 
6124 
  for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6125 
    {
6126 
      /* Did we insert an extra barrier?  Remove it.  */
6127 
      rtx barrier = PREV_INSN (curr_pool->pool_insn);
6128 
      rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6129 
      rtx label = NEXT_INSN (curr_pool->pool_insn);
6130 
 
6131 
      if (jump && GET_CODE (jump) == JUMP_INSN
6132 
          && barrier && GET_CODE (barrier) == BARRIER
6133 
          && label && GET_CODE (label) == CODE_LABEL
6134 
          && GET_CODE (PATTERN (jump)) == SET
6135 
          && SET_DEST (PATTERN (jump)) == pc_rtx
6136 
          && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6137 
          && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6138 
        {
6139 
          remove_insn (jump);
6140 
          remove_insn (barrier);
6141 
          remove_insn (label);
6142 
        }
6143 
 
6144 
      remove_insn (curr_pool->pool_insn);
6145 
    }
6146 
 
6147 
  /* Remove all base register reload insns.  */
6148 
 
6149 
  for (insn = get_insns (); insn; )
6150 
    {
6151 
      rtx next_insn = NEXT_INSN (insn);
6152 
 
6153 
      if (GET_CODE (insn) == INSN
6154 
          && GET_CODE (PATTERN (insn)) == SET
6155 
          && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6156 
          && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6157 
        remove_insn (insn);
6158 
 
6159 
      insn = next_insn;
6160 
    }
6161 
 
6162 
  /* Free pool list.  */
6163 
 
6164 
  while (pool_list)
6165 
    {
6166 
      struct constant_pool *next = pool_list->next;
6167 
      s390_free_pool (pool_list);
6168 
      pool_list = next;
6169 
    }
6170 
}
6171 
 
6172 
 
6173 
/* Output the constant pool entry EXP in mode MODE with alignment ALIGN.  */
6174 
 
6175 
void
6176 
s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6177 
{
6178 
  REAL_VALUE_TYPE r;
6179 
 
6180 
  switch (GET_MODE_CLASS (mode))
6181 
    {
6182 
    case MODE_FLOAT:
6183 
      gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6184 
 
6185 
      REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6186 
      assemble_real (r, mode, align);
6187 
      break;
6188 
 
6189 
    case MODE_INT:
6190 
      assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6191 
      break;
6192 
 
6193 
    default:
6194 
      gcc_unreachable ();
6195 
    }
6196 
}
6197 
 
6198 
 
6199 
/* Return an RTL expression representing the value of the return address
6200 
   for the frame COUNT steps up from the current frame.  FRAME is the
6201 
   frame pointer of that frame.  */
6202 
 
6203 
rtx
6204 
s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6205 
{
6206 
  int offset;
6207 
  rtx addr;
6208 
 
6209 
  /* Without backchain, we fail for all but the current frame.  */
6210 
 
6211 
  if (!TARGET_BACKCHAIN && count > 0)
6212 
    return NULL_RTX;
6213 
 
6214 
  /* For the current frame, we need to make sure the initial
6215 
     value of RETURN_REGNUM is actually saved.  */
6216 
 
6217 
  if (count == 0)
6218 
    {
6219 
      /* On non-z architectures branch splitting could overwrite r14.  */
6220 
      if (TARGET_CPU_ZARCH)
6221 
        return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6222 
      else
6223 
        {
6224 
          cfun_frame_layout.save_return_addr_p = true;
6225 
          return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6226 
        }
6227 
    }
6228 
 
6229 
  if (TARGET_PACKED_STACK)
6230 
    offset = -2 * UNITS_PER_WORD;
6231 
  else
6232 
    offset = RETURN_REGNUM * UNITS_PER_WORD;
6233 
 
6234 
  addr = plus_constant (frame, offset);
6235 
  addr = memory_address (Pmode, addr);
6236 
  return gen_rtx_MEM (Pmode, addr);
6237 
}
6238 
 
6239 
/* Return an RTL expression representing the back chain stored in
6240 
   the current stack frame.  */
6241 
 
6242 
rtx
6243 
s390_back_chain_rtx (void)
6244 
{
6245 
  rtx chain;
6246 
 
6247 
  gcc_assert (TARGET_BACKCHAIN);
6248 
 
6249 
  if (TARGET_PACKED_STACK)
6250 
    chain = plus_constant (stack_pointer_rtx,
6251 
                           STACK_POINTER_OFFSET - UNITS_PER_WORD);
6252 
  else
6253 
    chain = stack_pointer_rtx;
6254 
 
6255 
  chain = gen_rtx_MEM (Pmode, chain);
6256 
  return chain;
6257 
}
6258 
 
6259 
/* Find first call clobbered register unused in a function.
6260 
   This could be used as base register in a leaf function
6261 
   or for holding the return address before epilogue.  */
6262 
 
6263 
static int
6264 
find_unused_clobbered_reg (void)
6265 
{
6266 
  int i;
6267 
  for (i = 0; i < 6; i++)
6268 
    if (!regs_ever_live[i])
6269 
      return i;
6270 
  return 0;
6271 
}
6272 
 
6273 
 
6274 
/* Helper function for s390_regs_ever_clobbered.  Sets the fields in DATA for all
6275 
   clobbered hard regs in SETREG.  */
6276 
 
6277 
static void
6278 
s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
6279 
{
6280 
  int *regs_ever_clobbered = (int *)data;
6281 
  unsigned int i, regno;
6282 
  enum machine_mode mode = GET_MODE (setreg);
6283 
 
6284 
  if (GET_CODE (setreg) == SUBREG)
6285 
    {
6286 
      rtx inner = SUBREG_REG (setreg);
6287 
      if (!GENERAL_REG_P (inner))
6288 
        return;
6289 
      regno = subreg_regno (setreg);
6290 
    }
6291 
  else if (GENERAL_REG_P (setreg))
6292 
    regno = REGNO (setreg);
6293 
  else
6294 
    return;
6295 
 
6296 
  for (i = regno;
6297 
       i < regno + HARD_REGNO_NREGS (regno, mode);
6298 
       i++)
6299 
    regs_ever_clobbered[i] = 1;
6300 
}
6301 
 
6302 
/* Walks through all basic blocks of the current function looking
6303 
   for clobbered hard regs using s390_reg_clobbered_rtx.  The fields
6304 
   of the passed integer array REGS_EVER_CLOBBERED are set to one for
6305 
   each of those regs.  */
6306 
 
6307 
static void
6308 
s390_regs_ever_clobbered (int *regs_ever_clobbered)
6309 
{
6310 
  basic_block cur_bb;
6311 
  rtx cur_insn;
6312 
  unsigned int i;
6313 
 
6314 
  memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6315 
 
6316 
  /* For non-leaf functions we have to consider all call clobbered regs to be
6317 
     clobbered.  */
6318 
  if (!current_function_is_leaf)
6319 
    {
6320 
      for (i = 0; i < 16; i++)
6321 
        regs_ever_clobbered[i] = call_really_used_regs[i];
6322 
    }
6323 
 
6324 
  /* Make the "magic" eh_return registers live if necessary.  For regs_ever_live
6325 
     this work is done by liveness analysis (mark_regs_live_at_end).
6326 
     Special care is needed for functions containing landing pads.  Landing pads
6327 
     may use the eh registers, but the code which sets these registers is not
6328 
     contained in that function.  Hence s390_regs_ever_clobbered is not able to
6329 
     deal with this automatically.  */
6330 
  if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
6331 
    for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6332 
      if (current_function_calls_eh_return
6333 
          || (cfun->machine->has_landing_pad_p
6334 
              && regs_ever_live [EH_RETURN_DATA_REGNO (i)]))
6335 
        regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6336 
 
6337 
  /* For nonlocal gotos all call-saved registers have to be saved.
6338 
     This flag is also set for the unwinding code in libgcc.
6339 
     See expand_builtin_unwind_init.  For regs_ever_live this is done by
6340 
     reload.  */
6341 
  if (current_function_has_nonlocal_label)
6342 
    for (i = 0; i < 16; i++)
6343 
      if (!call_really_used_regs[i])
6344 
        regs_ever_clobbered[i] = 1;
6345 
 
6346 
  FOR_EACH_BB (cur_bb)
6347 
    {
6348 
      FOR_BB_INSNS (cur_bb, cur_insn)
6349 
        {
6350 
          if (INSN_P (cur_insn))
6351 
            note_stores (PATTERN (cur_insn),
6352 
                         s390_reg_clobbered_rtx,
6353 
                         regs_ever_clobbered);
6354 
        }
6355 
    }
6356 
}
6357 
 
6358 
/* Determine the frame area which actually has to be accessed
6359 
   in the function epilogue. The values are stored at the
6360 
   given pointers AREA_BOTTOM (address of the lowest used stack
6361 
   address) and AREA_TOP (address of the first item which does
6362 
   not belong to the stack frame).  */
6363 
 
6364 
static void
6365 
s390_frame_area (int *area_bottom, int *area_top)
6366 
{
6367 
  int b, t;
6368 
  int i;
6369 
 
6370 
  b = INT_MAX;
6371 
  t = INT_MIN;
6372 
 
6373 
  if (cfun_frame_layout.first_restore_gpr != -1)
6374 
    {
6375 
      b = (cfun_frame_layout.gprs_offset
6376 
           + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6377 
      t = b + (cfun_frame_layout.last_restore_gpr
6378 
               - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6379 
    }
6380 
 
6381 
  if (TARGET_64BIT && cfun_save_high_fprs_p)
6382 
    {
6383 
      b = MIN (b, cfun_frame_layout.f8_offset);
6384 
      t = MAX (t, (cfun_frame_layout.f8_offset
6385 
                   + cfun_frame_layout.high_fprs * 8));
6386 
    }
6387 
 
6388 
  if (!TARGET_64BIT)
6389 
    for (i = 2; i < 4; i++)
6390 
      if (cfun_fpr_bit_p (i))
6391 
        {
6392 
          b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6393 
          t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6394 
        }
6395 
 
6396 
  *area_bottom = b;
6397 
  *area_top = t;
6398 
}
6399 
 
6400 
/* Fill cfun->machine with info about register usage of current function.
6401 
   Return in CLOBBERED_REGS which GPRs are currently considered set.  */
6402 
 
6403 
static void
6404 
s390_register_info (int clobbered_regs[])
6405 
{
6406 
  int i, j;
6407 
 
6408 
  /* fprs 8 - 15 are call saved for 64 Bit ABI.  */
6409 
  cfun_frame_layout.fpr_bitmap = 0;
6410 
  cfun_frame_layout.high_fprs = 0;
6411 
  if (TARGET_64BIT)
6412 
    for (i = 24; i < 32; i++)
6413 
      if (regs_ever_live[i] && !global_regs[i])
6414 
        {
6415 
          cfun_set_fpr_bit (i - 16);
6416 
          cfun_frame_layout.high_fprs++;
6417 
        }
6418 
 
6419 
  /* Find first and last gpr to be saved.  We trust regs_ever_live
6420 
     data, except that we don't save and restore global registers.
6421 
 
6422 
     Also, all registers with special meaning to the compiler need
6423 
     to be handled extra.  */
6424 
 
6425 
  s390_regs_ever_clobbered (clobbered_regs);
6426 
 
6427 
  for (i = 0; i < 16; i++)
6428 
    clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6429 
 
6430 
  if (frame_pointer_needed)
6431 
    clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6432 
 
6433 
  if (flag_pic)
6434 
    clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6435 
      |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6436 
 
6437 
  clobbered_regs[BASE_REGNUM]
6438 
    |= (cfun->machine->base_reg
6439 
        && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6440 
 
6441 
  clobbered_regs[RETURN_REGNUM]
6442 
    |= (!current_function_is_leaf
6443 
        || TARGET_TPF_PROFILING
6444 
        || cfun->machine->split_branches_pending_p
6445 
        || cfun_frame_layout.save_return_addr_p
6446 
        || current_function_calls_eh_return
6447 
        || current_function_stdarg);
6448 
 
6449 
  clobbered_regs[STACK_POINTER_REGNUM]
6450 
    |= (!current_function_is_leaf
6451 
        || TARGET_TPF_PROFILING
6452 
        || cfun_save_high_fprs_p
6453 
        || get_frame_size () > 0
6454 
        || current_function_calls_alloca
6455 
        || current_function_stdarg);
6456 
 
6457 
  for (i = 6; i < 16; i++)
6458 
    if (regs_ever_live[i] || clobbered_regs[i])
6459 
      break;
6460 
  for (j = 15; j > i; j--)
6461 
    if (regs_ever_live[j] || clobbered_regs[j])
6462 
      break;
6463 
 
6464 
  if (i == 16)
6465 
    {
6466 
      /* Nothing to save/restore.  */
6467 
      cfun_frame_layout.first_save_gpr_slot = -1;
6468 
      cfun_frame_layout.last_save_gpr_slot = -1;
6469 
      cfun_frame_layout.first_save_gpr = -1;
6470 
      cfun_frame_layout.first_restore_gpr = -1;
6471 
      cfun_frame_layout.last_save_gpr = -1;
6472 
      cfun_frame_layout.last_restore_gpr = -1;
6473 
    }
6474 
  else
6475 
    {
6476 
      /* Save slots for gprs from i to j.  */
6477 
      cfun_frame_layout.first_save_gpr_slot = i;
6478 
      cfun_frame_layout.last_save_gpr_slot = j;
6479 
 
6480 
      for (i = cfun_frame_layout.first_save_gpr_slot;
6481 
           i < cfun_frame_layout.last_save_gpr_slot + 1;
6482 
           i++)
6483 
        if (clobbered_regs[i])
6484 
          break;
6485 
 
6486 
      for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6487 
        if (clobbered_regs[j])
6488 
          break;
6489 
 
6490 
      if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6491 
        {
6492 
          /* Nothing to save/restore.  */
6493 
          cfun_frame_layout.first_save_gpr = -1;
6494 
          cfun_frame_layout.first_restore_gpr = -1;
6495 
          cfun_frame_layout.last_save_gpr = -1;
6496 
          cfun_frame_layout.last_restore_gpr = -1;
6497 
        }
6498 
      else
6499 
        {
6500 
          /* Save / Restore from gpr i to j.  */
6501 
          cfun_frame_layout.first_save_gpr = i;
6502 
          cfun_frame_layout.first_restore_gpr = i;
6503 
          cfun_frame_layout.last_save_gpr = j;
6504 
          cfun_frame_layout.last_restore_gpr = j;
6505 
        }
6506 
    }
6507 
 
6508 
  if (current_function_stdarg)
6509 
    {
6510 
      /* Varargs functions need to save gprs 2 to 6.  */
6511 
      if (cfun->va_list_gpr_size
6512 
          && current_function_args_info.gprs < GP_ARG_NUM_REG)
6513 
        {
6514 
          int min_gpr = current_function_args_info.gprs;
6515 
          int max_gpr = min_gpr + cfun->va_list_gpr_size;
6516 
          if (max_gpr > GP_ARG_NUM_REG)
6517 
            max_gpr = GP_ARG_NUM_REG;
6518 
 
6519 
          if (cfun_frame_layout.first_save_gpr == -1
6520 
              || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6521 
            {
6522 
              cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6523 
              cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
6524 
            }
6525 
 
6526 
          if (cfun_frame_layout.last_save_gpr == -1
6527 
              || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6528 
            {
6529 
              cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6530 
              cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
6531 
            }
6532 
        }
6533 
 
6534 
      /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved.  */
6535 
      if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6536 
          && current_function_args_info.fprs < FP_ARG_NUM_REG)
6537 
        {
6538 
          int min_fpr = current_function_args_info.fprs;
6539 
          int max_fpr = min_fpr + cfun->va_list_fpr_size;
6540 
          if (max_fpr > FP_ARG_NUM_REG)
6541 
            max_fpr = FP_ARG_NUM_REG;
6542 
 
6543 
          /* ??? This is currently required to ensure proper location
6544 
             of the fpr save slots within the va_list save area.  */
6545 
          if (TARGET_PACKED_STACK)
6546 
            min_fpr = 0;
6547 
 
6548 
          for (i = min_fpr; i < max_fpr; i++)
6549 
            cfun_set_fpr_bit (i);
6550 
        }
6551 
    }
6552 
 
6553 
  if (!TARGET_64BIT)
6554 
    for (i = 2; i < 4; i++)
6555 
      if (regs_ever_live[i + 16] && !global_regs[i + 16])
6556 
        cfun_set_fpr_bit (i);
6557 
}
6558 
 
6559 
/* Fill cfun->machine with info about frame of current function.  */
6560 
 
6561 
static void
6562 
s390_frame_info (void)
6563 
{
6564 
  int i;
6565 
 
6566 
  cfun_frame_layout.frame_size = get_frame_size ();
6567 
  if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6568 
    fatal_error ("total size of local variables exceeds architecture limit");
6569 
 
6570 
  if (!TARGET_PACKED_STACK)
6571 
    {
6572 
      cfun_frame_layout.backchain_offset = 0;
6573 
      cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6574 
      cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6575 
      cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6576 
      cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
6577 
                                       * UNITS_PER_WORD);
6578 
    }
6579 
  else if (TARGET_BACKCHAIN) /* kernel stack layout */
6580 
    {
6581 
      cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6582 
                                            - UNITS_PER_WORD);
6583 
      cfun_frame_layout.gprs_offset
6584 
        = (cfun_frame_layout.backchain_offset
6585 
           - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
6586 
           * UNITS_PER_WORD);
6587 
 
6588 
      if (TARGET_64BIT)
6589 
        {
6590 
          cfun_frame_layout.f4_offset
6591 
            = (cfun_frame_layout.gprs_offset
6592 
               - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6593 
 
6594 
          cfun_frame_layout.f0_offset
6595 
            = (cfun_frame_layout.f4_offset
6596 
               - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6597 
        }
6598 
      else
6599 
        {
6600 
          /* On 31 bit we have to care about alignment of the
6601 
             floating point regs to provide fastest access.  */
6602 
          cfun_frame_layout.f0_offset
6603 
            = ((cfun_frame_layout.gprs_offset
6604 
                & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6605 
               - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6606 
 
6607 
          cfun_frame_layout.f4_offset
6608 
            = (cfun_frame_layout.f0_offset
6609 
               - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6610 
        }
6611 
    }
6612 
  else /* no backchain */
6613 
    {
6614 
      cfun_frame_layout.f4_offset
6615 
        = (STACK_POINTER_OFFSET
6616 
           - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6617 
 
6618 
      cfun_frame_layout.f0_offset
6619 
        = (cfun_frame_layout.f4_offset
6620 
           - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6621 
 
6622 
      cfun_frame_layout.gprs_offset
6623 
        = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6624 
    }
6625 
 
6626 
  if (current_function_is_leaf
6627 
      && !TARGET_TPF_PROFILING
6628 
      && cfun_frame_layout.frame_size == 0
6629 
      && !cfun_save_high_fprs_p
6630 
      && !current_function_calls_alloca
6631 
      && !current_function_stdarg)
6632 
    return;
6633 
 
6634 
  if (!TARGET_PACKED_STACK)
6635 
    cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6636 
                                     + current_function_outgoing_args_size
6637 
                                     + cfun_frame_layout.high_fprs * 8);
6638 
  else
6639 
    {
6640 
      if (TARGET_BACKCHAIN)
6641 
        cfun_frame_layout.frame_size += UNITS_PER_WORD;
6642 
 
6643 
      /* No alignment trouble here because f8-f15 are only saved under
6644 
         64 bit.  */
6645 
      cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6646 
                                               cfun_frame_layout.f4_offset),
6647 
                                          cfun_frame_layout.gprs_offset)
6648 
                                     - cfun_frame_layout.high_fprs * 8);
6649 
 
6650 
      cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6651 
 
6652 
      for (i = 0; i < 8; i++)
6653 
        if (cfun_fpr_bit_p (i))
6654 
          cfun_frame_layout.frame_size += 8;
6655 
 
6656 
      cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6657 
 
6658 
      /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6659 
         the frame size to sustain 8 byte alignment of stack frames.  */
6660 
      cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6661 
                                       STACK_BOUNDARY / BITS_PER_UNIT - 1)
6662 
                                      & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6663 
 
6664 
      cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6665 
    }
6666 
}
6667 
 
6668 
/* Generate frame layout.  Fills in register and frame data for the current
6669 
   function in cfun->machine.  This routine can be called multiple times;
6670 
   it will re-do the complete frame layout every time.  */
6671 
 
6672 
static void
6673 
s390_init_frame_layout (void)
6674 
{
6675 
  HOST_WIDE_INT frame_size;
6676 
  int base_used;
6677 
  int clobbered_regs[16];
6678 
 
6679 
  /* On S/390 machines, we may need to perform branch splitting, which
6680 
     will require both base and return address register.  We have no
6681 
     choice but to assume we're going to need them until right at the
6682 
     end of the machine dependent reorg phase.  */
6683 
  if (!TARGET_CPU_ZARCH)
6684 
    cfun->machine->split_branches_pending_p = true;
6685 
 
6686 
  do
6687 
    {
6688 
      frame_size = cfun_frame_layout.frame_size;
6689 
 
6690 
      /* Try to predict whether we'll need the base register.  */
6691 
      base_used = cfun->machine->split_branches_pending_p
6692 
                  || current_function_uses_const_pool
6693 
                  || (!DISP_IN_RANGE (-frame_size)
6694 
                      && !CONST_OK_FOR_K (-frame_size));
6695 
 
6696 
      /* Decide which register to use as literal pool base.  In small
6697 
         leaf functions, try to use an unused call-clobbered register
6698 
         as base register to avoid save/restore overhead.  */
6699 
      if (!base_used)
6700 
        cfun->machine->base_reg = NULL_RTX;
6701 
      else if (current_function_is_leaf && !regs_ever_live[5])
6702 
        cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6703 
      else
6704 
        cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6705 
 
6706 
      s390_register_info (clobbered_regs);
6707 
      s390_frame_info ();
6708 
    }
6709 
  while (frame_size != cfun_frame_layout.frame_size);
6710 
}
6711 
 
6712 
/* Update frame layout.  Recompute actual register save data based on
6713 
   current info and update regs_ever_live for the special registers.
6714 
   May be called multiple times, but may never cause *more* registers
6715 
   to be saved than s390_init_frame_layout allocated room for.  */
6716 
 
6717 
static void
6718 
s390_update_frame_layout (void)
6719 
{
6720 
  int clobbered_regs[16];
6721 
 
6722 
  s390_register_info (clobbered_regs);
6723 
 
6724 
  regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6725 
  regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6726 
  regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6727 
 
6728 
  if (cfun->machine->base_reg)
6729 
    regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6730 
}
6731 
 
6732 
/* Return nonzero if register OLD_REG can be renamed to register NEW_REG.  */
6733 
 
6734 
bool
6735 
s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
6736 
{
6737 
   /* Once we've decided upon a register to use as base register, it must
6738 
      no longer be used for any other purpose.  */
6739 
  if (cfun->machine->base_reg)
6740 
    if (REGNO (cfun->machine->base_reg) == old_reg
6741 
        || REGNO (cfun->machine->base_reg) == new_reg)
6742 
      return false;
6743 
 
6744 
  return true;
6745 
}
6746 
 
6747 
/* Return true if register FROM can be eliminated via register TO.  */
6748 
 
6749 
bool
6750 
s390_can_eliminate (int from, int to)
6751 
{
6752 
  /* On zSeries machines, we have not marked the base register as fixed.
6753 
     Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6754 
     If a function requires the base register, we say here that this
6755 
     elimination cannot be performed.  This will cause reload to free
6756 
     up the base register (as if it were fixed).  On the other hand,
6757 
     if the current function does *not* require the base register, we
6758 
     say here the elimination succeeds, which in turn allows reload
6759 
     to allocate the base register for any other purpose.  */
6760 
  if (from == BASE_REGNUM && to == BASE_REGNUM)
6761 
    {
6762 
      if (TARGET_CPU_ZARCH)
6763 
        {
6764 
          s390_init_frame_layout ();
6765 
          return cfun->machine->base_reg == NULL_RTX;
6766 
        }
6767 
 
6768 
      return false;
6769 
    }
6770 
 
6771 
  /* Everything else must point into the stack frame.  */
6772 
  gcc_assert (to == STACK_POINTER_REGNUM
6773 
              || to == HARD_FRAME_POINTER_REGNUM);
6774 
 
6775 
  gcc_assert (from == FRAME_POINTER_REGNUM
6776 
              || from == ARG_POINTER_REGNUM
6777 
              || from == RETURN_ADDRESS_POINTER_REGNUM);
6778 
 
6779 
  /* Make sure we actually saved the return address.  */
6780 
  if (from == RETURN_ADDRESS_POINTER_REGNUM)
6781 
    if (!current_function_calls_eh_return
6782 
        && !current_function_stdarg
6783 
        && !cfun_frame_layout.save_return_addr_p)
6784 
      return false;
6785 
 
6786 
  return true;
6787 
}
6788 
 
6789 
/* Return offset between register FROM and TO initially after prolog.  */
6790 
 
6791 
HOST_WIDE_INT
6792 
s390_initial_elimination_offset (int from, int to)
6793 
{
6794 
  HOST_WIDE_INT offset;
6795 
  int index;
6796 
 
6797 
  /* ??? Why are we called for non-eliminable pairs?  */
6798 
  if (!s390_can_eliminate (from, to))
6799 
    return 0;
6800 
 
6801 
  switch (from)
6802 
    {
6803 
    case FRAME_POINTER_REGNUM:
6804 
      offset = (get_frame_size()
6805 
                + STACK_POINTER_OFFSET
6806 
                + current_function_outgoing_args_size);
6807 
      break;
6808 
 
6809 
    case ARG_POINTER_REGNUM:
6810 
      s390_init_frame_layout ();
6811 
      offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6812 
      break;
6813 
 
6814 
    case RETURN_ADDRESS_POINTER_REGNUM:
6815 
      s390_init_frame_layout ();
6816 
      index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
6817 
      gcc_assert (index >= 0);
6818 
      offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6819 
      offset += index * UNITS_PER_WORD;
6820 
      break;
6821 
 
6822 
    case BASE_REGNUM:
6823 
      offset = 0;
6824 
      break;
6825 
 
6826 
    default:
6827 
      gcc_unreachable ();
6828 
    }
6829 
 
6830 
  return offset;
6831 
}
6832 
 
6833 
/* Emit insn to save fpr REGNUM at offset OFFSET relative
6834 
   to register BASE.  Return generated insn.  */
6835 
 
6836 
static rtx
6837 
save_fpr (rtx base, int offset, int regnum)
6838 
{
6839 
  rtx addr;
6840 
  addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6841 
 
6842 
  if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6843 
    set_mem_alias_set (addr, get_varargs_alias_set ());
6844 
  else
6845 
    set_mem_alias_set (addr, get_frame_alias_set ());
6846 
 
6847 
  return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6848 
}
6849 
 
6850 
/* Emit insn to restore fpr REGNUM from offset OFFSET relative
6851 
   to register BASE.  Return generated insn.  */
6852 
 
6853 
static rtx
6854 
restore_fpr (rtx base, int offset, int regnum)
6855 
{
6856 
  rtx addr;
6857 
  addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6858 
  set_mem_alias_set (addr, get_frame_alias_set ());
6859 
 
6860 
  return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6861 
}
6862 
 
6863 
/* Generate insn to save registers FIRST to LAST into
6864 
   the register save area located at offset OFFSET
6865 
   relative to register BASE.  */
6866 
 
6867 
static rtx
6868 
save_gprs (rtx base, int offset, int first, int last)
6869 
{
6870 
  rtx addr, insn, note;
6871 
  int i;
6872 
 
6873 
  addr = plus_constant (base, offset);
6874 
  addr = gen_rtx_MEM (Pmode, addr);
6875 
 
6876 
  set_mem_alias_set (addr, get_frame_alias_set ());
6877 
 
6878 
  /* Special-case single register.  */
6879 
  if (first == last)
6880 
    {
6881 
      if (TARGET_64BIT)
6882 
        insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
6883 
      else
6884 
        insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
6885 
 
6886 
      RTX_FRAME_RELATED_P (insn) = 1;
6887 
      return insn;
6888 
    }
6889 
 
6890 
 
6891 
  insn = gen_store_multiple (addr,
6892 
                             gen_rtx_REG (Pmode, first),
6893 
                             GEN_INT (last - first + 1));
6894 
 
6895 
  if (first <= 6 && current_function_stdarg)
6896 
    for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6897 
      {
6898 
        rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
6899 
 
6900 
        if (first + i <= 6)
6901 
          set_mem_alias_set (mem, get_varargs_alias_set ());
6902 
      }
6903 
 
6904 
  /* We need to set the FRAME_RELATED flag on all SETs
6905 
     inside the store-multiple pattern.
6906 
 
6907 
     However, we must not emit DWARF records for registers 2..5
6908 
     if they are stored for use by variable arguments ...
6909 
 
6910 
     ??? Unfortunately, it is not enough to simply not the
6911 
     FRAME_RELATED flags for those SETs, because the first SET
6912 
     of the PARALLEL is always treated as if it had the flag
6913 
     set, even if it does not.  Therefore we emit a new pattern
6914 
     without those registers as REG_FRAME_RELATED_EXPR note.  */
6915 
 
6916 
  if (first >= 6)
6917 
    {
6918 
      rtx pat = PATTERN (insn);
6919 
 
6920 
      for (i = 0; i < XVECLEN (pat, 0); i++)
6921 
        if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
6922 
          RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
6923 
 
6924 
      RTX_FRAME_RELATED_P (insn) = 1;
6925 
    }
6926 
  else if (last >= 6)
6927 
    {
6928 
      addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
6929 
      note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
6930 
                                 gen_rtx_REG (Pmode, 6),
6931 
                                 GEN_INT (last - 6 + 1));
6932 
      note = PATTERN (note);
6933 
 
6934 
      REG_NOTES (insn) =
6935 
        gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6936 
                           note, REG_NOTES (insn));
6937 
 
6938 
      for (i = 0; i < XVECLEN (note, 0); i++)
6939 
        if (GET_CODE (XVECEXP (note, 0, i)) == SET)
6940 
          RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
6941 
 
6942 
      RTX_FRAME_RELATED_P (insn) = 1;
6943 
    }
6944 
 
6945 
  return insn;
6946 
}
6947 
 
6948 
/* Generate insn to restore registers FIRST to LAST from
6949 
   the register save area located at offset OFFSET
6950 
   relative to register BASE.  */
6951 
 
6952 
static rtx
6953 
restore_gprs (rtx base, int offset, int first, int last)
6954 
{
6955 
  rtx addr, insn;
6956 
 
6957 
  addr = plus_constant (base, offset);
6958 
  addr = gen_rtx_MEM (Pmode, addr);
6959 
  set_mem_alias_set (addr, get_frame_alias_set ());
6960 
 
6961 
  /* Special-case single register.  */
6962 
  if (first == last)
6963 
    {
6964 
      if (TARGET_64BIT)
6965 
        insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
6966 
      else
6967 
        insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
6968 
 
6969 
      return insn;
6970 
    }
6971 
 
6972 
  insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
6973 
                            addr,
6974 
                            GEN_INT (last - first + 1));
6975 
  return insn;
6976 
}
6977 
 
6978 
/* Return insn sequence to load the GOT register.  */
6979 
 
6980 
static GTY(()) rtx got_symbol;
6981 
rtx
6982 
s390_load_got (void)
6983 
{
6984 
  rtx insns;
6985 
 
6986 
  if (!got_symbol)
6987 
    {
6988 
      got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
6989 
      SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
6990 
    }
6991 
 
6992 
  start_sequence ();
6993 
 
6994 
  if (TARGET_CPU_ZARCH)
6995 
    {
6996 
      emit_move_insn (pic_offset_table_rtx, got_symbol);
6997 
    }
6998 
  else
6999 
    {
7000 
      rtx offset;
7001 
 
7002 
      offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7003 
                               UNSPEC_LTREL_OFFSET);
7004 
      offset = gen_rtx_CONST (Pmode, offset);
7005 
      offset = force_const_mem (Pmode, offset);
7006 
 
7007 
      emit_move_insn (pic_offset_table_rtx, offset);
7008 
 
7009 
      offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7010 
                               UNSPEC_LTREL_BASE);
7011 
      offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7012 
 
7013 
      emit_move_insn (pic_offset_table_rtx, offset);
7014 
    }
7015 
 
7016 
  insns = get_insns ();
7017 
  end_sequence ();
7018 
  return insns;
7019 
}
7020 
 
7021 
/* Expand the prologue into a bunch of separate insns.  */
7022 
 
7023 
void
7024 
s390_emit_prologue (void)
7025 
{
7026 
  rtx insn, addr;
7027 
  rtx temp_reg;
7028 
  int i;
7029 
  int offset;
7030 
  int next_fpr = 0;
7031 
 
7032 
  /* Complete frame layout.  */
7033 
 
7034 
  s390_update_frame_layout ();
7035 
 
7036 
  /* Annotate all constant pool references to let the scheduler know
7037 
     they implicitly use the base register.  */
7038 
 
7039 
  push_topmost_sequence ();
7040 
 
7041 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7042 
    if (INSN_P (insn))
7043 
      annotate_constant_pool_refs (&PATTERN (insn));
7044 
 
7045 
  pop_topmost_sequence ();
7046 
 
7047 
  /* Choose best register to use for temp use within prologue.
7048 
     See below for why TPF must use the register 1.  */
7049 
 
7050 
  if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7051 
      && !current_function_is_leaf
7052 
      && !TARGET_TPF_PROFILING)
7053 
    temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7054 
  else
7055 
    temp_reg = gen_rtx_REG (Pmode, 1);
7056 
 
7057 
  /* Save call saved gprs.  */
7058 
  if (cfun_frame_layout.first_save_gpr != -1)
7059 
    {
7060 
      insn = save_gprs (stack_pointer_rtx,
7061 
                        cfun_frame_layout.gprs_offset +
7062 
                        UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7063 
                                          - cfun_frame_layout.first_save_gpr_slot),
7064 
                        cfun_frame_layout.first_save_gpr,
7065 
                        cfun_frame_layout.last_save_gpr);
7066 
      emit_insn (insn);
7067 
    }
7068 
 
7069 
  /* Dummy insn to mark literal pool slot.  */
7070 
 
7071 
  if (cfun->machine->base_reg)
7072 
    emit_insn (gen_main_pool (cfun->machine->base_reg));
7073 
 
7074 
  offset = cfun_frame_layout.f0_offset;
7075 
 
7076 
  /* Save f0 and f2.  */
7077 
  for (i = 0; i < 2; i++)
7078 
    {
7079 
      if (cfun_fpr_bit_p (i))
7080 
        {
7081 
          save_fpr (stack_pointer_rtx, offset, i + 16);
7082 
          offset += 8;
7083 
        }
7084 
      else if (!TARGET_PACKED_STACK)
7085 
          offset += 8;
7086 
    }
7087 
 
7088 
  /* Save f4 and f6.  */
7089 
  offset = cfun_frame_layout.f4_offset;
7090 
  for (i = 2; i < 4; i++)
7091 
    {
7092 
      if (cfun_fpr_bit_p (i))
7093 
        {
7094 
          insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7095 
          offset += 8;
7096 
 
7097 
          /* If f4 and f6 are call clobbered they are saved due to stdargs and
7098 
             therefore are not frame related.  */
7099 
          if (!call_really_used_regs[i + 16])
7100 
            RTX_FRAME_RELATED_P (insn) = 1;
7101 
        }
7102 
      else if (!TARGET_PACKED_STACK)
7103 
        offset += 8;
7104 
    }
7105 
 
7106 
  if (TARGET_PACKED_STACK
7107 
      && cfun_save_high_fprs_p
7108 
      && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7109 
    {
7110 
      offset = (cfun_frame_layout.f8_offset
7111 
                + (cfun_frame_layout.high_fprs - 1) * 8);
7112 
 
7113 
      for (i = 15; i > 7 && offset >= 0; i--)
7114 
        if (cfun_fpr_bit_p (i))
7115 
          {
7116 
            insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7117 
 
7118 
            RTX_FRAME_RELATED_P (insn) = 1;
7119 
            offset -= 8;
7120 
          }
7121 
      if (offset >= cfun_frame_layout.f8_offset)
7122 
        next_fpr = i + 16;
7123 
    }
7124 
 
7125 
  if (!TARGET_PACKED_STACK)
7126 
    next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7127 
 
7128 
  /* Decrement stack pointer.  */
7129 
 
7130 
  if (cfun_frame_layout.frame_size > 0)
7131 
    {
7132 
      rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7133 
 
7134 
      if (s390_stack_size)
7135 
        {
7136 
          HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7137 
                                            & ~(s390_stack_guard - 1));
7138 
          rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7139 
                               GEN_INT (stack_check_mask));
7140 
 
7141 
          if (TARGET_64BIT)
7142 
            gen_cmpdi (t, const0_rtx);
7143 
          else
7144 
            gen_cmpsi (t, const0_rtx);
7145 
 
7146 
          emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7147 
                                                       gen_rtx_REG (CCmode,
7148 
                                                                    CC_REGNUM),
7149 
                                                       const0_rtx),
7150 
                                           const0_rtx));
7151 
        }
7152 
 
7153 
      if (s390_warn_framesize > 0
7154 
          && cfun_frame_layout.frame_size >= s390_warn_framesize)
7155 
        warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7156 
                 current_function_name (), cfun_frame_layout.frame_size);
7157 
 
7158 
      if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7159 
        warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7160 
 
7161 
      /* Save incoming stack pointer into temp reg.  */
7162 
      if (TARGET_BACKCHAIN || next_fpr)
7163 
        insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7164 
 
7165 
      /* Subtract frame size from stack pointer.  */
7166 
 
7167 
      if (DISP_IN_RANGE (INTVAL (frame_off)))
7168 
        {
7169 
          insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7170 
                              gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7171 
                                            frame_off));
7172 
          insn = emit_insn (insn);
7173 
        }
7174 
      else
7175 
        {
7176 
          if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7177 
            frame_off = force_const_mem (Pmode, frame_off);
7178 
 
7179 
          insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7180 
          annotate_constant_pool_refs (&PATTERN (insn));
7181 
        }
7182 
 
7183 
      RTX_FRAME_RELATED_P (insn) = 1;
7184 
      REG_NOTES (insn) =
7185 
        gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7186 
                           gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7187 
                             gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7188 
                               GEN_INT (-cfun_frame_layout.frame_size))),
7189 
                           REG_NOTES (insn));
7190 
 
7191 
      /* Set backchain.  */
7192 
 
7193 
      if (TARGET_BACKCHAIN)
7194 
        {
7195 
          if (cfun_frame_layout.backchain_offset)
7196 
            addr = gen_rtx_MEM (Pmode,
7197 
                                plus_constant (stack_pointer_rtx,
7198 
                                  cfun_frame_layout.backchain_offset));
7199 
          else
7200 
            addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7201 
          set_mem_alias_set (addr, get_frame_alias_set ());
7202 
          insn = emit_insn (gen_move_insn (addr, temp_reg));
7203 
        }
7204 
 
7205 
      /* If we support asynchronous exceptions (e.g. for Java),
7206 
         we need to make sure the backchain pointer is set up
7207 
         before any possibly trapping memory access.  */
7208 
 
7209 
      if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7210 
        {
7211 
          addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7212 
          emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
7213 
        }
7214 
    }
7215 
 
7216 
  /* Save fprs 8 - 15 (64 bit ABI).  */
7217 
 
7218 
  if (cfun_save_high_fprs_p && next_fpr)
7219 
    {
7220 
      insn = emit_insn (gen_add2_insn (temp_reg,
7221 
                                       GEN_INT (cfun_frame_layout.f8_offset)));
7222 
 
7223 
      offset = 0;
7224 
 
7225 
      for (i = 24; i <= next_fpr; i++)
7226 
        if (cfun_fpr_bit_p (i - 16))
7227 
          {
7228 
            rtx addr = plus_constant (stack_pointer_rtx,
7229 
                                      cfun_frame_layout.frame_size
7230 
                                      + cfun_frame_layout.f8_offset
7231 
                                      + offset);
7232 
 
7233 
            insn = save_fpr (temp_reg, offset, i);
7234 
            offset += 8;
7235 
            RTX_FRAME_RELATED_P (insn) = 1;
7236 
            REG_NOTES (insn) =
7237 
              gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7238 
                                 gen_rtx_SET (VOIDmode,
7239 
                                              gen_rtx_MEM (DFmode, addr),
7240 
                                              gen_rtx_REG (DFmode, i)),
7241 
                                 REG_NOTES (insn));
7242 
          }
7243 
    }
7244 
 
7245 
  /* Set frame pointer, if needed.  */
7246 
 
7247 
  if (frame_pointer_needed)
7248 
    {
7249 
      insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7250 
      RTX_FRAME_RELATED_P (insn) = 1;
7251 
    }
7252 
 
7253 
  /* Set up got pointer, if needed.  */
7254 
 
7255 
  if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7256 
    {
7257 
      rtx insns = s390_load_got ();
7258 
 
7259 
      for (insn = insns; insn; insn = NEXT_INSN (insn))
7260 
        {
7261 
          annotate_constant_pool_refs (&PATTERN (insn));
7262 
 
7263 
          REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7264 
                                                REG_NOTES (insn));
7265 
        }
7266 
 
7267 
      emit_insn (insns);
7268 
    }
7269 
 
7270 
  if (TARGET_TPF_PROFILING)
7271 
    {
7272 
      /* Generate a BAS instruction to serve as a function
7273 
         entry intercept to facilitate the use of tracing
7274 
         algorithms located at the branch target.  */
7275 
      emit_insn (gen_prologue_tpf ());
7276 
 
7277 
      /* Emit a blockage here so that all code
7278 
         lies between the profiling mechanisms.  */
7279 
      emit_insn (gen_blockage ());
7280 
    }
7281 
}
7282 
 
7283 
/* Expand the epilogue into a bunch of separate insns.  */
7284 
 
7285 
void
7286 
s390_emit_epilogue (bool sibcall)
7287 
{
7288 
  rtx frame_pointer, return_reg;
7289 
  int area_bottom, area_top, offset = 0;
7290 
  int next_offset;
7291 
  rtvec p;
7292 
  int i;
7293 
 
7294 
  if (TARGET_TPF_PROFILING)
7295 
    {
7296 
 
7297 
      /* Generate a BAS instruction to serve as a function
7298 
         entry intercept to facilitate the use of tracing
7299 
         algorithms located at the branch target.  */
7300 
 
7301 
      /* Emit a blockage here so that all code
7302 
         lies between the profiling mechanisms.  */
7303 
      emit_insn (gen_blockage ());
7304 
 
7305 
      emit_insn (gen_epilogue_tpf ());
7306 
    }
7307 
 
7308 
  /* Check whether to use frame or stack pointer for restore.  */
7309 
 
7310 
  frame_pointer = (frame_pointer_needed
7311 
                   ? hard_frame_pointer_rtx : stack_pointer_rtx);
7312 
 
7313 
  s390_frame_area (&area_bottom, &area_top);
7314 
 
7315 
  /* Check whether we can access the register save area.
7316 
     If not, increment the frame pointer as required.  */
7317 
 
7318 
  if (area_top <= area_bottom)
7319 
    {
7320 
      /* Nothing to restore.  */
7321 
    }
7322 
  else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7323 
           && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7324 
    {
7325 
      /* Area is in range.  */
7326 
      offset = cfun_frame_layout.frame_size;
7327 
    }
7328 
  else
7329 
    {
7330 
      rtx insn, frame_off;
7331 
 
7332 
      offset = area_bottom < 0 ? -area_bottom : 0;
7333 
      frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7334 
 
7335 
      if (DISP_IN_RANGE (INTVAL (frame_off)))
7336 
        {
7337 
          insn = gen_rtx_SET (VOIDmode, frame_pointer,
7338 
                              gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7339 
          insn = emit_insn (insn);
7340 
        }
7341 
      else
7342 
        {
7343 
          if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7344 
            frame_off = force_const_mem (Pmode, frame_off);
7345 
 
7346 
          insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7347 
          annotate_constant_pool_refs (&PATTERN (insn));
7348 
        }
7349 
    }
7350 
 
7351 
  /* Restore call saved fprs.  */
7352 
 
7353 
  if (TARGET_64BIT)
7354 
    {
7355 
      if (cfun_save_high_fprs_p)
7356 
        {
7357 
          next_offset = cfun_frame_layout.f8_offset;
7358 
          for (i = 24; i < 32; i++)
7359 
            {
7360 
              if (cfun_fpr_bit_p (i - 16))
7361 
                {
7362 
                  restore_fpr (frame_pointer,
7363 
                               offset + next_offset, i);
7364 
                  next_offset += 8;
7365 
                }
7366 
            }
7367 
        }
7368 
 
7369 
    }
7370 
  else
7371 
    {
7372 
      next_offset = cfun_frame_layout.f4_offset;
7373 
      for (i = 18; i < 20; i++)
7374 
        {
7375 
          if (cfun_fpr_bit_p (i - 16))
7376 
            {
7377 
              restore_fpr (frame_pointer,
7378 
                           offset + next_offset, i);
7379 
              next_offset += 8;
7380 
            }
7381 
          else if (!TARGET_PACKED_STACK)
7382 
            next_offset += 8;
7383 
        }
7384 
 
7385 
    }
7386 
 
7387 
  /* Return register.  */
7388 
 
7389 
  return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7390 
 
7391 
  /* Restore call saved gprs.  */
7392 
 
7393 
  if (cfun_frame_layout.first_restore_gpr != -1)
7394 
    {
7395 
      rtx insn, addr;
7396 
      int i;
7397 
 
7398 
      /* Check for global register and save them
7399 
         to stack location from where they get restored.  */
7400 
 
7401 
      for (i = cfun_frame_layout.first_restore_gpr;
7402 
           i <= cfun_frame_layout.last_restore_gpr;
7403 
           i++)
7404 
        {
7405 
          /* These registers are special and need to be
7406 
             restored in any case.  */
7407 
          if (i == STACK_POINTER_REGNUM
7408 
              || i == RETURN_REGNUM
7409 
              || i == BASE_REGNUM
7410 
              || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
7411 
            continue;
7412 
 
7413 
          if (global_regs[i])
7414 
            {
7415 
              addr = plus_constant (frame_pointer,
7416 
                                    offset + cfun_frame_layout.gprs_offset
7417 
                                    + (i - cfun_frame_layout.first_save_gpr_slot)
7418 
                                    * UNITS_PER_WORD);
7419 
              addr = gen_rtx_MEM (Pmode, addr);
7420 
              set_mem_alias_set (addr, get_frame_alias_set ());
7421 
              emit_move_insn (addr, gen_rtx_REG (Pmode, i));
7422 
            }
7423 
        }
7424 
 
7425 
      if (! sibcall)
7426 
        {
7427 
          /* Fetch return address from stack before load multiple,
7428 
             this will do good for scheduling.  */
7429 
 
7430 
          if (cfun_frame_layout.save_return_addr_p
7431 
              || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
7432 
                  && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7433 
            {
7434 
              int return_regnum = find_unused_clobbered_reg();
7435 
              if (!return_regnum)
7436 
                return_regnum = 4;
7437 
              return_reg = gen_rtx_REG (Pmode, return_regnum);
7438 
 
7439 
              addr = plus_constant (frame_pointer,
7440 
                                    offset + cfun_frame_layout.gprs_offset
7441 
                                    + (RETURN_REGNUM
7442 
                                       - cfun_frame_layout.first_save_gpr_slot)
7443 
                                    * UNITS_PER_WORD);
7444 
              addr = gen_rtx_MEM (Pmode, addr);
7445 
              set_mem_alias_set (addr, get_frame_alias_set ());
7446 
              emit_move_insn (return_reg, addr);
7447 
            }
7448 
        }
7449 
 
7450 
      insn = restore_gprs (frame_pointer,
7451 
                           offset + cfun_frame_layout.gprs_offset
7452 
                           + (cfun_frame_layout.first_restore_gpr
7453 
                              - cfun_frame_layout.first_save_gpr_slot)
7454 
                           * UNITS_PER_WORD,
7455 
                           cfun_frame_layout.first_restore_gpr,
7456 
                           cfun_frame_layout.last_restore_gpr);
7457 
      emit_insn (insn);
7458 
    }
7459 
 
7460 
  if (! sibcall)
7461 
    {
7462 
 
7463 
      /* Return to caller.  */
7464 
 
7465 
      p = rtvec_alloc (2);
7466 
 
7467 
      RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
7468 
      RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
7469 
      emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
7470 
    }
7471 
}
7472 
 
7473 
 
7474 
/* Return the size in bytes of a function argument of
7475 
   type TYPE and/or mode MODE.  At least one of TYPE or
7476 
   MODE must be specified.  */
7477 
 
7478 
static int
7479 
s390_function_arg_size (enum machine_mode mode, tree type)
7480 
{
7481 
  if (type)
7482 
    return int_size_in_bytes (type);
7483 
 
7484 
  /* No type info available for some library calls ...  */
7485 
  if (mode != BLKmode)
7486 
    return GET_MODE_SIZE (mode);
7487 
 
7488 
  /* If we have neither type nor mode, abort */
7489 
  gcc_unreachable ();
7490 
}
7491 
 
7492 
/* Return true if a function argument of type TYPE and mode MODE
7493 
   is to be passed in a floating-point register, if available.  */
7494 
 
7495 
static bool
7496 
s390_function_arg_float (enum machine_mode mode, tree type)
7497 
{
7498 
  int size = s390_function_arg_size (mode, type);
7499 
  if (size > 8)
7500 
    return false;
7501 
 
7502 
  /* Soft-float changes the ABI: no floating-point registers are used.  */
7503 
  if (TARGET_SOFT_FLOAT)
7504 
    return false;
7505 
 
7506 
  /* No type info available for some library calls ...  */
7507 
  if (!type)
7508 
    return mode == SFmode || mode == DFmode;
7509 
 
7510 
  /* The ABI says that record types with a single member are treated
7511 
     just like that member would be.  */
7512 
  while (TREE_CODE (type) == RECORD_TYPE)
7513 
    {
7514 
      tree field, single = NULL_TREE;
7515 
 
7516 
      for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7517 
        {
7518 
          if (TREE_CODE (field) != FIELD_DECL)
7519 
            continue;
7520 
 
7521 
          if (single == NULL_TREE)
7522 
            single = TREE_TYPE (field);
7523 
          else
7524 
            return false;
7525 
        }
7526 
 
7527 
      if (single == NULL_TREE)
7528 
        return false;
7529 
      else
7530 
        type = single;
7531 
    }
7532 
 
7533 
  return TREE_CODE (type) == REAL_TYPE;
7534 
}
7535 
 
7536 
/* Return true if a function argument of type TYPE and mode MODE
7537 
   is to be passed in an integer register, or a pair of integer
7538 
   registers, if available.  */
7539 
 
7540 
static bool
7541 
s390_function_arg_integer (enum machine_mode mode, tree type)
7542 
{
7543 
  int size = s390_function_arg_size (mode, type);
7544 
  if (size > 8)
7545 
    return false;
7546 
 
7547 
  /* No type info available for some library calls ...  */
7548 
  if (!type)
7549 
    return GET_MODE_CLASS (mode) == MODE_INT
7550 
           || (TARGET_SOFT_FLOAT &&  GET_MODE_CLASS (mode) == MODE_FLOAT);
7551 
 
7552 
  /* We accept small integral (and similar) types.  */
7553 
  if (INTEGRAL_TYPE_P (type)
7554 
      || POINTER_TYPE_P (type)
7555 
      || TREE_CODE (type) == OFFSET_TYPE
7556 
      || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7557 
    return true;
7558 
 
7559 
  /* We also accept structs of size 1, 2, 4, 8 that are not
7560 
     passed in floating-point registers.  */
7561 
  if (AGGREGATE_TYPE_P (type)
7562 
      && exact_log2 (size) >= 0
7563 
      && !s390_function_arg_float (mode, type))
7564 
    return true;
7565 
 
7566 
  return false;
7567 
}
7568 
 
7569 
/* Return 1 if a function argument of type TYPE and mode MODE
7570 
   is to be passed by reference.  The ABI specifies that only
7571 
   structures of size 1, 2, 4, or 8 bytes are passed by value,
7572 
   all other structures (and complex numbers) are passed by
7573 
   reference.  */
7574 
 
7575 
static bool
7576 
s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7577 
                        enum machine_mode mode, tree type,
7578 
                        bool named ATTRIBUTE_UNUSED)
7579 
{
7580 
  int size = s390_function_arg_size (mode, type);
7581 
  if (size > 8)
7582 
    return true;
7583 
 
7584 
  if (type)
7585 
    {
7586 
      if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7587 
        return 1;
7588 
 
7589 
      if (TREE_CODE (type) == COMPLEX_TYPE
7590 
          || TREE_CODE (type) == VECTOR_TYPE)
7591 
        return 1;
7592 
    }
7593 
 
7594 
  return 0;
7595 
}
7596 
 
7597 
/* Update the data in CUM to advance over an argument of mode MODE and
7598 
   data type TYPE.  (TYPE is null for libcalls where that information
7599 
   may not be available.).  The boolean NAMED specifies whether the
7600 
   argument is a named argument (as opposed to an unnamed argument
7601 
   matching an ellipsis).  */
7602 
 
7603 
void
7604 
s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7605 
                           tree type, int named ATTRIBUTE_UNUSED)
7606 
{
7607 
  if (s390_function_arg_float (mode, type))
7608 
    {
7609 
      cum->fprs += 1;
7610 
    }
7611 
  else if (s390_function_arg_integer (mode, type))
7612 
    {
7613 
      int size = s390_function_arg_size (mode, type);
7614 
      cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7615 
    }
7616 
  else
7617 
    gcc_unreachable ();
7618 
}
7619 
 
7620 
/* Define where to put the arguments to a function.
7621 
   Value is zero to push the argument on the stack,
7622 
   or a hard register in which to store the argument.
7623 
 
7624 
   MODE is the argument's machine mode.
7625 
   TYPE is the data type of the argument (as a tree).
7626 
    This is null for libcalls where that information may
7627 
    not be available.
7628 
   CUM is a variable of type CUMULATIVE_ARGS which gives info about
7629 
    the preceding args and about the function being called.
7630 
   NAMED is nonzero if this argument is a named parameter
7631 
    (otherwise it is an extra parameter matching an ellipsis).
7632 
 
7633 
   On S/390, we use general purpose registers 2 through 6 to
7634 
   pass integer, pointer, and certain structure arguments, and
7635 
   floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7636 
   to pass floating point arguments.  All remaining arguments
7637 
   are pushed to the stack.  */
7638 
 
7639 
rtx
7640 
s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7641 
                   int named ATTRIBUTE_UNUSED)
7642 
{
7643 
  if (s390_function_arg_float (mode, type))
7644 
    {
7645 
      if (cum->fprs + 1 > FP_ARG_NUM_REG)
7646 
        return 0;
7647 
      else
7648 
        return gen_rtx_REG (mode, cum->fprs + 16);
7649 
    }
7650 
  else if (s390_function_arg_integer (mode, type))
7651 
    {
7652 
      int size = s390_function_arg_size (mode, type);
7653 
      int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7654 
 
7655 
      if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7656 
        return 0;
7657 
      else
7658 
        return gen_rtx_REG (mode, cum->gprs + 2);
7659 
    }
7660 
 
7661 
  /* After the real arguments, expand_call calls us once again
7662 
     with a void_type_node type.  Whatever we return here is
7663 
     passed as operand 2 to the call expanders.
7664 
 
7665 
     We don't need this feature ...  */
7666 
  else if (type == void_type_node)
7667 
    return const0_rtx;
7668 
 
7669 
  gcc_unreachable ();
7670 
}
7671 
 
7672 
/* Return true if return values of type TYPE should be returned
7673 
   in a memory buffer whose address is passed by the caller as
7674 
   hidden first argument.  */
7675 
 
7676 
static bool
7677 
s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7678 
{
7679 
  /* We accept small integral (and similar) types.  */
7680 
  if (INTEGRAL_TYPE_P (type)
7681 
      || POINTER_TYPE_P (type)
7682 
      || TREE_CODE (type) == OFFSET_TYPE
7683 
      || TREE_CODE (type) == REAL_TYPE)
7684 
    return int_size_in_bytes (type) > 8;
7685 
 
7686 
  /* Aggregates and similar constructs are always returned
7687 
     in memory.  */
7688 
  if (AGGREGATE_TYPE_P (type)
7689 
      || TREE_CODE (type) == COMPLEX_TYPE
7690 
      || TREE_CODE (type) == VECTOR_TYPE)
7691 
    return true;
7692 
 
7693 
  /* ??? We get called on all sorts of random stuff from
7694 
     aggregate_value_p.  We can't abort, but it's not clear
7695 
     what's safe to return.  Pretend it's a struct I guess.  */
7696 
  return true;
7697 
}
7698 
 
7699 
/* Define where to return a (scalar) value of type TYPE.
7700 
   If TYPE is null, define where to return a (scalar)
7701 
   value of mode MODE from a libcall.  */
7702 
 
7703 
rtx
7704 
s390_function_value (tree type, enum machine_mode mode)
7705 
{
7706 
  if (type)
7707 
    {
7708 
      int unsignedp = TYPE_UNSIGNED (type);
7709 
      mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7710 
    }
7711 
 
7712 
  gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
7713 
               || GET_MODE_CLASS (mode) == MODE_FLOAT);
7714 
  gcc_assert (GET_MODE_SIZE (mode) <= 8);
7715 
 
7716 
  if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
7717 
    return gen_rtx_REG (mode, 16);
7718 
  else
7719 
    return gen_rtx_REG (mode, 2);
7720 
}
7721 
 
7722 
 
7723 
/* Create and return the va_list datatype.
7724 
 
7725 
   On S/390, va_list is an array type equivalent to
7726 
 
7727 
      typedef struct __va_list_tag
7728 
        {
7729 
            long __gpr;
7730 
            long __fpr;
7731 
            void *__overflow_arg_area;
7732 
            void *__reg_save_area;
7733 
        } va_list[1];
7734 
 
7735 
   where __gpr and __fpr hold the number of general purpose
7736 
   or floating point arguments used up to now, respectively,
7737 
   __overflow_arg_area points to the stack location of the
7738 
   next argument passed on the stack, and __reg_save_area
7739 
   always points to the start of the register area in the
7740 
   call frame of the current function.  The function prologue
7741 
   saves all registers used for argument passing into this
7742 
   area if the function uses variable arguments.  */
7743 
 
7744 
static tree
7745 
s390_build_builtin_va_list (void)
7746 
{
7747 
  tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7748 
 
7749 
  record = lang_hooks.types.make_type (RECORD_TYPE);
7750 
 
7751 
  type_decl =
7752 
    build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7753 
 
7754 
  f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7755 
                      long_integer_type_node);
7756 
  f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7757 
                      long_integer_type_node);
7758 
  f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7759 
                      ptr_type_node);
7760 
  f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7761 
                      ptr_type_node);
7762 
 
7763 
  va_list_gpr_counter_field = f_gpr;
7764 
  va_list_fpr_counter_field = f_fpr;
7765 
 
7766 
  DECL_FIELD_CONTEXT (f_gpr) = record;
7767 
  DECL_FIELD_CONTEXT (f_fpr) = record;
7768 
  DECL_FIELD_CONTEXT (f_ovf) = record;
7769 
  DECL_FIELD_CONTEXT (f_sav) = record;
7770 
 
7771 
  TREE_CHAIN (record) = type_decl;
7772 
  TYPE_NAME (record) = type_decl;
7773 
  TYPE_FIELDS (record) = f_gpr;
7774 
  TREE_CHAIN (f_gpr) = f_fpr;
7775 
  TREE_CHAIN (f_fpr) = f_ovf;
7776 
  TREE_CHAIN (f_ovf) = f_sav;
7777 
 
7778 
  layout_type (record);
7779 
 
7780 
  /* The correct type is an array type of one element.  */
7781 
  return build_array_type (record, build_index_type (size_zero_node));
7782 
}
7783 
 
7784 
/* Implement va_start by filling the va_list structure VALIST.
7785 
   STDARG_P is always true, and ignored.
7786 
   NEXTARG points to the first anonymous stack argument.
7787 
 
7788 
   The following global variables are used to initialize
7789 
   the va_list structure:
7790 
 
7791 
     current_function_args_info:
7792 
       holds number of gprs and fprs used for named arguments.
7793 
     current_function_arg_offset_rtx:
7794 
       holds the offset of the first anonymous stack argument
7795 
       (relative to the virtual arg pointer).  */
7796 
 
7797 
void
7798 
s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7799 
{
7800 
  HOST_WIDE_INT n_gpr, n_fpr;
7801 
  int off;
7802 
  tree f_gpr, f_fpr, f_ovf, f_sav;
7803 
  tree gpr, fpr, ovf, sav, t;
7804 
 
7805 
  f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7806 
  f_fpr = TREE_CHAIN (f_gpr);
7807 
  f_ovf = TREE_CHAIN (f_fpr);
7808 
  f_sav = TREE_CHAIN (f_ovf);
7809 
 
7810 
  valist = build_va_arg_indirect_ref (valist);
7811 
  gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7812 
  fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7813 
  ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7814 
  sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7815 
 
7816 
  /* Count number of gp and fp argument registers used.  */
7817 
 
7818 
  n_gpr = current_function_args_info.gprs;
7819 
  n_fpr = current_function_args_info.fprs;
7820 
 
7821 
  if (cfun->va_list_gpr_size)
7822 
    {
7823 
      t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7824 
                 build_int_cst (NULL_TREE, n_gpr));
7825 
      TREE_SIDE_EFFECTS (t) = 1;
7826 
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7827 
    }
7828 
 
7829 
  if (cfun->va_list_fpr_size)
7830 
    {
7831 
      t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7832 
                 build_int_cst (NULL_TREE, n_fpr));
7833 
      TREE_SIDE_EFFECTS (t) = 1;
7834 
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7835 
    }
7836 
 
7837 
  /* Find the overflow area.  */
7838 
  if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7839 
      || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
7840 
    {
7841 
      t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
7842 
 
7843 
      off = INTVAL (current_function_arg_offset_rtx);
7844 
      off = off < 0 ? 0 : off;
7845 
      if (TARGET_DEBUG_ARG)
7846 
        fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
7847 
                 (int)n_gpr, (int)n_fpr, off);
7848 
 
7849 
      t = build (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
7850 
 
7851 
      t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7852 
      TREE_SIDE_EFFECTS (t) = 1;
7853 
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7854 
    }
7855 
 
7856 
  /* Find the register save area.  */
7857 
  if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
7858 
      || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
7859 
    {
7860 
      t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
7861 
      t = build (PLUS_EXPR, TREE_TYPE (sav), t,
7862 
                 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
7863 
 
7864 
      t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7865 
      TREE_SIDE_EFFECTS (t) = 1;
7866 
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7867 
    }
7868 
}
7869 
 
7870 
/* Implement va_arg by updating the va_list structure
7871 
   VALIST as required to retrieve an argument of type
7872 
   TYPE, and returning that argument.
7873 
 
7874 
   Generates code equivalent to:
7875 
 
7876 
   if (integral value) {
7877 
     if (size  <= 4 && args.gpr < 5 ||
7878 
         size  > 4 && args.gpr < 4 )
7879 
       ret = args.reg_save_area[args.gpr+8]
7880 
     else
7881 
       ret = *args.overflow_arg_area++;
7882 
   } else if (float value) {
7883 
     if (args.fgpr < 2)
7884 
       ret = args.reg_save_area[args.fpr+64]
7885 
     else
7886 
       ret = *args.overflow_arg_area++;
7887 
   } else if (aggregate value) {
7888 
     if (args.gpr < 5)
7889 
       ret = *args.reg_save_area[args.gpr]
7890 
     else
7891 
       ret = **args.overflow_arg_area++;
7892 
   } */
7893 
 
7894 
static tree
7895 
s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
7896 
                      tree *post_p ATTRIBUTE_UNUSED)
7897 
{
7898 
  tree f_gpr, f_fpr, f_ovf, f_sav;
7899 
  tree gpr, fpr, ovf, sav, reg, t, u;
7900 
  int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
7901 
  tree lab_false, lab_over, addr;
7902 
 
7903 
  f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7904 
  f_fpr = TREE_CHAIN (f_gpr);
7905 
  f_ovf = TREE_CHAIN (f_fpr);
7906 
  f_sav = TREE_CHAIN (f_ovf);
7907 
 
7908 
  valist = build_va_arg_indirect_ref (valist);
7909 
  gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7910 
  fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7911 
  ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7912 
  sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7913 
 
7914 
  size = int_size_in_bytes (type);
7915 
 
7916 
  if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
7917 
    {
7918 
      if (TARGET_DEBUG_ARG)
7919 
        {
7920 
          fprintf (stderr, "va_arg: aggregate type");
7921 
          debug_tree (type);
7922 
        }
7923 
 
7924 
      /* Aggregates are passed by reference.  */
7925 
      indirect_p = 1;
7926 
      reg = gpr;
7927 
      n_reg = 1;
7928 
 
7929 
      /* kernel stack layout on 31 bit: It is assumed here that no padding
7930 
         will be added by s390_frame_info because for va_args always an even
7931 
         number of gprs has to be saved r15-r2 = 14 regs.  */
7932 
      sav_ofs = 2 * UNITS_PER_WORD;
7933 
      sav_scale = UNITS_PER_WORD;
7934 
      size = UNITS_PER_WORD;
7935 
      max_reg = GP_ARG_NUM_REG - n_reg;
7936 
    }
7937 
  else if (s390_function_arg_float (TYPE_MODE (type), type))
7938 
    {
7939 
      if (TARGET_DEBUG_ARG)
7940 
        {
7941 
          fprintf (stderr, "va_arg: float type");
7942 
          debug_tree (type);
7943 
        }
7944 
 
7945 
      /* FP args go in FP registers, if present.  */
7946 
      indirect_p = 0;
7947 
      reg = fpr;
7948 
      n_reg = 1;
7949 
      sav_ofs = 16 * UNITS_PER_WORD;
7950 
      sav_scale = 8;
7951 
      max_reg = FP_ARG_NUM_REG - n_reg;
7952 
    }
7953 
  else
7954 
    {
7955 
      if (TARGET_DEBUG_ARG)
7956 
        {
7957 
          fprintf (stderr, "va_arg: other type");
7958 
          debug_tree (type);
7959 
        }
7960 
 
7961 
      /* Otherwise into GP registers.  */
7962 
      indirect_p = 0;
7963 
      reg = gpr;
7964 
      n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7965 
 
7966 
      /* kernel stack layout on 31 bit: It is assumed here that no padding
7967 
         will be added by s390_frame_info because for va_args always an even
7968 
         number of gprs has to be saved r15-r2 = 14 regs.  */
7969 
      sav_ofs = 2 * UNITS_PER_WORD;
7970 
 
7971 
      if (size < UNITS_PER_WORD)
7972 
        sav_ofs += UNITS_PER_WORD - size;
7973 
 
7974 
      sav_scale = UNITS_PER_WORD;
7975 
      max_reg = GP_ARG_NUM_REG - n_reg;
7976 
    }
7977 
 
7978 
  /* Pull the value out of the saved registers ...  */
7979 
 
7980 
  lab_false = create_artificial_label ();
7981 
  lab_over = create_artificial_label ();
7982 
  addr = create_tmp_var (ptr_type_node, "addr");
7983 
  DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
7984 
 
7985 
  t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
7986 
  t = build2 (GT_EXPR, boolean_type_node, reg, t);
7987 
  u = build1 (GOTO_EXPR, void_type_node, lab_false);
7988 
  t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
7989 
  gimplify_and_add (t, pre_p);
7990 
 
7991 
  t = build2 (PLUS_EXPR, ptr_type_node, sav,
7992 
              fold_convert (ptr_type_node, size_int (sav_ofs)));
7993 
  u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
7994 
              fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
7995 
  t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
7996 
 
7997 
  t = build2 (MODIFY_EXPR, void_type_node, addr, t);
7998 
  gimplify_and_add (t, pre_p);
7999 
 
8000 
  t = build1 (GOTO_EXPR, void_type_node, lab_over);
8001 
  gimplify_and_add (t, pre_p);
8002 
 
8003 
  t = build1 (LABEL_EXPR, void_type_node, lab_false);
8004 
  append_to_statement_list (t, pre_p);
8005 
 
8006 
 
8007 
  /* ... Otherwise out of the overflow area.  */
8008 
 
8009 
  t = ovf;
8010 
  if (size < UNITS_PER_WORD)
8011 
    t = build2 (PLUS_EXPR, ptr_type_node, t,
8012 
                fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
8013 
 
8014 
  gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8015 
 
8016 
  u = build2 (MODIFY_EXPR, void_type_node, addr, t);
8017 
  gimplify_and_add (u, pre_p);
8018 
 
8019 
  t = build2 (PLUS_EXPR, ptr_type_node, t,
8020 
              fold_convert (ptr_type_node, size_int (size)));
8021 
  t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t);
8022 
  gimplify_and_add (t, pre_p);
8023 
 
8024 
  t = build1 (LABEL_EXPR, void_type_node, lab_over);
8025 
  append_to_statement_list (t, pre_p);
8026 
 
8027 
 
8028 
  /* Increment register save count.  */
8029 
 
8030 
  u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8031 
              fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8032 
  gimplify_and_add (u, pre_p);
8033 
 
8034 
  if (indirect_p)
8035 
    {
8036 
      t = build_pointer_type (build_pointer_type (type));
8037 
      addr = fold_convert (t, addr);
8038 
      addr = build_va_arg_indirect_ref (addr);
8039 
    }
8040 
  else
8041 
    {
8042 
      t = build_pointer_type (type);
8043 
      addr = fold_convert (t, addr);
8044 
    }
8045 
 
8046 
  return build_va_arg_indirect_ref (addr);
8047 
}
8048 
 
8049 
 
8050 
/* Builtins.  */
8051 
 
8052 
enum s390_builtin
8053 
{
8054 
  S390_BUILTIN_THREAD_POINTER,
8055 
  S390_BUILTIN_SET_THREAD_POINTER,
8056 
 
8057 
  S390_BUILTIN_max
8058 
};
8059 
 
8060 
static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
8061 
  CODE_FOR_get_tp_64,
8062 
  CODE_FOR_set_tp_64
8063 
};
8064 
 
8065 
static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8066 
  CODE_FOR_get_tp_31,
8067 
  CODE_FOR_set_tp_31
8068 
};
8069 
 
8070 
static void
8071 
s390_init_builtins (void)
8072 
{
8073 
  tree ftype;
8074 
 
8075 
  ftype = build_function_type (ptr_type_node, void_list_node);
8076 
  lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
8077 
                               S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8078 
                               NULL, NULL_TREE);
8079 
 
8080 
  ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8081 
  lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
8082 
                               S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8083 
                               NULL, NULL_TREE);
8084 
}
8085 
 
8086 
/* Expand an expression EXP that calls a built-in function,
8087 
   with result going to TARGET if that's convenient
8088 
   (and in mode MODE if that's convenient).
8089 
   SUBTARGET may be used as the target for computing one of EXP's operands.
8090 
   IGNORE is nonzero if the value is to be ignored.  */
8091 
 
8092 
static rtx
8093 
s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8094 
                     enum machine_mode mode ATTRIBUTE_UNUSED,
8095 
                     int ignore ATTRIBUTE_UNUSED)
8096 
{
8097 
#define MAX_ARGS 2
8098 
 
8099 
  unsigned int const *code_for_builtin =
8100 
    TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8101 
 
8102 
  tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8103 
  unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8104 
  tree arglist = TREE_OPERAND (exp, 1);
8105 
  enum insn_code icode;
8106 
  rtx op[MAX_ARGS], pat;
8107 
  int arity;
8108 
  bool nonvoid;
8109 
 
8110 
  if (fcode >= S390_BUILTIN_max)
8111 
    internal_error ("bad builtin fcode");
8112 
  icode = code_for_builtin[fcode];
8113 
  if (icode == 0)
8114 
    internal_error ("bad builtin fcode");
8115 
 
8116 
  nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8117 
 
8118 
  for (arglist = TREE_OPERAND (exp, 1), arity = 0;
8119 
       arglist;
8120 
       arglist = TREE_CHAIN (arglist), arity++)
8121 
    {
8122 
      const struct insn_operand_data *insn_op;
8123 
 
8124 
      tree arg = TREE_VALUE (arglist);
8125 
      if (arg == error_mark_node)
8126 
        return NULL_RTX;
8127 
      if (arity > MAX_ARGS)
8128 
        return NULL_RTX;
8129 
 
8130 
      insn_op = &insn_data[icode].operand[arity + nonvoid];
8131 
 
8132 
      op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8133 
 
8134 
      if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8135 
        op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8136 
    }
8137 
 
8138 
  if (nonvoid)
8139 
    {
8140 
      enum machine_mode tmode = insn_data[icode].operand[0].mode;
8141 
      if (!target
8142 
          || GET_MODE (target) != tmode
8143 
          || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8144 
        target = gen_reg_rtx (tmode);
8145 
    }
8146 
 
8147 
  switch (arity)
8148 
    {
8149 
    case 0:
8150 
      pat = GEN_FCN (icode) (target);
8151 
      break;
8152 
    case 1:
8153 
      if (nonvoid)
8154 
        pat = GEN_FCN (icode) (target, op[0]);
8155 
      else
8156 
        pat = GEN_FCN (icode) (op[0]);
8157 
      break;
8158 
    case 2:
8159 
      pat = GEN_FCN (icode) (target, op[0], op[1]);
8160 
      break;
8161 
    default:
8162 
      gcc_unreachable ();
8163 
    }
8164 
  if (!pat)
8165 
    return NULL_RTX;
8166 
  emit_insn (pat);
8167 
 
8168 
  if (nonvoid)
8169 
    return target;
8170 
  else
8171 
    return const0_rtx;
8172 
}
8173 
 
8174 
 
8175 
/* Output assembly code for the trampoline template to
8176 
   stdio stream FILE.
8177 
 
8178 
   On S/390, we use gpr 1 internally in the trampoline code;
8179 
   gpr 0 is used to hold the static chain.  */
8180 
 
8181 
void
8182 
s390_trampoline_template (FILE *file)
8183 
{
8184 
  rtx op[2];
8185 
  op[0] = gen_rtx_REG (Pmode, 0);
8186 
  op[1] = gen_rtx_REG (Pmode, 1);
8187 
 
8188 
  if (TARGET_64BIT)
8189 
    {
8190 
      output_asm_insn ("basr\t%1,0", op);
8191 
      output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8192 
      output_asm_insn ("br\t%1", op);
8193 
      ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8194 
    }
8195 
  else
8196 
    {
8197 
      output_asm_insn ("basr\t%1,0", op);
8198 
      output_asm_insn ("lm\t%0,%1,6(%1)", op);
8199 
      output_asm_insn ("br\t%1", op);
8200 
      ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8201 
    }
8202 
}
8203 
 
8204 
/* Emit RTL insns to initialize the variable parts of a trampoline.
8205 
   FNADDR is an RTX for the address of the function's pure code.
8206 
   CXT is an RTX for the static chain value for the function.  */
8207 
 
8208 
void
8209 
s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8210 
{
8211 
  emit_move_insn (gen_rtx_MEM (Pmode,
8212 
                   memory_address (Pmode,
8213 
                   plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8214 
  emit_move_insn (gen_rtx_MEM (Pmode,
8215 
                   memory_address (Pmode,
8216 
                   plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8217 
}
8218 
 
8219 
/* Return rtx for 64-bit constant formed from the 32-bit subwords
8220 
   LOW and HIGH, independent of the host word size.  */
8221 
 
8222 
rtx
8223 
s390_gen_rtx_const_DI (int high, int low)
8224 
{
8225 
#if HOST_BITS_PER_WIDE_INT >= 64
8226 
  HOST_WIDE_INT val;
8227 
  val = (HOST_WIDE_INT)high;
8228 
  val <<= 32;
8229 
  val |= (HOST_WIDE_INT)low;
8230 
 
8231 
  return GEN_INT (val);
8232 
#else
8233 
#if HOST_BITS_PER_WIDE_INT >= 32
8234 
  return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
8235 
#else
8236 
  gcc_unreachable ();
8237 
#endif
8238 
#endif
8239 
}
8240 
 
8241 
/* Output assembler code to FILE to increment profiler label # LABELNO
8242 
   for profiling a function entry.  */
8243 
 
8244 
void
8245 
s390_function_profiler (FILE *file, int labelno)
8246 
{
8247 
  rtx op[7];
8248 
 
8249 
  char label[128];
8250 
  ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8251 
 
8252 
  fprintf (file, "# function profiler \n");
8253 
 
8254 
  op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8255 
  op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8256 
  op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8257 
 
8258 
  op[2] = gen_rtx_REG (Pmode, 1);
8259 
  op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8260 
  SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8261 
 
8262 
  op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8263 
  if (flag_pic)
8264 
    {
8265 
      op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8266 
      op[4] = gen_rtx_CONST (Pmode, op[4]);
8267 
    }
8268 
 
8269 
  if (TARGET_64BIT)
8270 
    {
8271 
      output_asm_insn ("stg\t%0,%1", op);
8272 
      output_asm_insn ("larl\t%2,%3", op);
8273 
      output_asm_insn ("brasl\t%0,%4", op);
8274 
      output_asm_insn ("lg\t%0,%1", op);
8275 
    }
8276 
  else if (!flag_pic)
8277 
    {
8278 
      op[6] = gen_label_rtx ();
8279 
 
8280 
      output_asm_insn ("st\t%0,%1", op);
8281 
      output_asm_insn ("bras\t%2,%l6", op);
8282 
      output_asm_insn (".long\t%4", op);
8283 
      output_asm_insn (".long\t%3", op);
8284 
      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8285 
      output_asm_insn ("l\t%0,0(%2)", op);
8286 
      output_asm_insn ("l\t%2,4(%2)", op);
8287 
      output_asm_insn ("basr\t%0,%0", op);
8288 
      output_asm_insn ("l\t%0,%1", op);
8289 
    }
8290 
  else
8291 
    {
8292 
      op[5] = gen_label_rtx ();
8293 
      op[6] = gen_label_rtx ();
8294 
 
8295 
      output_asm_insn ("st\t%0,%1", op);
8296 
      output_asm_insn ("bras\t%2,%l6", op);
8297 
      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8298 
      output_asm_insn (".long\t%4-%l5", op);
8299 
      output_asm_insn (".long\t%3-%l5", op);
8300 
      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8301 
      output_asm_insn ("lr\t%0,%2", op);
8302 
      output_asm_insn ("a\t%0,0(%2)", op);
8303 
      output_asm_insn ("a\t%2,4(%2)", op);
8304 
      output_asm_insn ("basr\t%0,%0", op);
8305 
      output_asm_insn ("l\t%0,%1", op);
8306 
    }
8307 
}
8308 
 
8309 
/* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8310 
   into its SYMBOL_REF_FLAGS.  */
8311 
 
8312 
static void
8313 
s390_encode_section_info (tree decl, rtx rtl, int first)
8314 
{
8315 
  default_encode_section_info (decl, rtl, first);
8316 
 
8317 
  /* If a variable has a forced alignment to < 2 bytes, mark it with
8318 
     SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand.  */
8319 
  if (TREE_CODE (decl) == VAR_DECL
8320 
      && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8321 
    SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8322 
}
8323 
 
8324 
/* Output thunk to FILE that implements a C++ virtual function call (with
8325 
   multiple inheritance) to FUNCTION.  The thunk adjusts the this pointer
8326 
   by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8327 
   stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8328 
   relative to the resulting this pointer.  */
8329 
 
8330 
static void
8331 
s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8332 
                      HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8333 
                      tree function)
8334 
{
8335 
  rtx op[10];
8336 
  int nonlocal = 0;
8337 
 
8338 
  /* Operand 0 is the target function.  */
8339 
  op[0] = XEXP (DECL_RTL (function), 0);
8340 
  if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8341 
    {
8342 
      nonlocal = 1;
8343 
      op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8344 
                              TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8345 
      op[0] = gen_rtx_CONST (Pmode, op[0]);
8346 
    }
8347 
 
8348 
  /* Operand 1 is the 'this' pointer.  */
8349 
  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8350 
    op[1] = gen_rtx_REG (Pmode, 3);
8351 
  else
8352 
    op[1] = gen_rtx_REG (Pmode, 2);
8353 
 
8354 
  /* Operand 2 is the delta.  */
8355 
  op[2] = GEN_INT (delta);
8356 
 
8357 
  /* Operand 3 is the vcall_offset.  */
8358 
  op[3] = GEN_INT (vcall_offset);
8359 
 
8360 
  /* Operand 4 is the temporary register.  */
8361 
  op[4] = gen_rtx_REG (Pmode, 1);
8362 
 
8363 
  /* Operands 5 to 8 can be used as labels.  */
8364 
  op[5] = NULL_RTX;
8365 
  op[6] = NULL_RTX;
8366 
  op[7] = NULL_RTX;
8367 
  op[8] = NULL_RTX;
8368 
 
8369 
  /* Operand 9 can be used for temporary register.  */
8370 
  op[9] = NULL_RTX;
8371 
 
8372 
  /* Generate code.  */
8373 
  if (TARGET_64BIT)
8374 
    {
8375 
      /* Setup literal pool pointer if required.  */
8376 
      if ((!DISP_IN_RANGE (delta)
8377 
           && !CONST_OK_FOR_K (delta)
8378 
           && !CONST_OK_FOR_Os (delta))
8379 
          || (!DISP_IN_RANGE (vcall_offset)
8380 
              && !CONST_OK_FOR_K (vcall_offset)
8381 
              && !CONST_OK_FOR_Os (vcall_offset)))
8382 
        {
8383 
          op[5] = gen_label_rtx ();
8384 
          output_asm_insn ("larl\t%4,%5", op);
8385 
        }
8386 
 
8387 
      /* Add DELTA to this pointer.  */
8388 
      if (delta)
8389 
        {
8390 
          if (CONST_OK_FOR_J (delta))
8391 
            output_asm_insn ("la\t%1,%2(%1)", op);
8392 
          else if (DISP_IN_RANGE (delta))
8393 
            output_asm_insn ("lay\t%1,%2(%1)", op);
8394 
          else if (CONST_OK_FOR_K (delta))
8395 
            output_asm_insn ("aghi\t%1,%2", op);
8396 
          else if (CONST_OK_FOR_Os (delta))
8397 
            output_asm_insn ("agfi\t%1,%2", op);
8398 
          else
8399 
            {
8400 
              op[6] = gen_label_rtx ();
8401 
              output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8402 
            }
8403 
        }
8404 
 
8405 
      /* Perform vcall adjustment.  */
8406 
      if (vcall_offset)
8407 
        {
8408 
          if (DISP_IN_RANGE (vcall_offset))
8409 
            {
8410 
              output_asm_insn ("lg\t%4,0(%1)", op);
8411 
              output_asm_insn ("ag\t%1,%3(%4)", op);
8412 
            }
8413 
          else if (CONST_OK_FOR_K (vcall_offset))
8414 
            {
8415 
              output_asm_insn ("lghi\t%4,%3", op);
8416 
              output_asm_insn ("ag\t%4,0(%1)", op);
8417 
              output_asm_insn ("ag\t%1,0(%4)", op);
8418 
            }
8419 
          else if (CONST_OK_FOR_Os (vcall_offset))
8420 
            {
8421 
              output_asm_insn ("lgfi\t%4,%3", op);
8422 
              output_asm_insn ("ag\t%4,0(%1)", op);
8423 
              output_asm_insn ("ag\t%1,0(%4)", op);
8424 
            }
8425 
          else
8426 
            {
8427 
              op[7] = gen_label_rtx ();
8428 
              output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
8429 
              output_asm_insn ("ag\t%4,0(%1)", op);
8430 
              output_asm_insn ("ag\t%1,0(%4)", op);
8431 
            }
8432 
        }
8433 
 
8434 
      /* Jump to target.  */
8435 
      output_asm_insn ("jg\t%0", op);
8436 
 
8437 
      /* Output literal pool if required.  */
8438 
      if (op[5])
8439 
        {
8440 
          output_asm_insn (".align\t4", op);
8441 
          targetm.asm_out.internal_label (file, "L",
8442 
                                          CODE_LABEL_NUMBER (op[5]));
8443 
        }
8444 
      if (op[6])
8445 
        {
8446 
          targetm.asm_out.internal_label (file, "L",
8447 
                                          CODE_LABEL_NUMBER (op[6]));
8448 
          output_asm_insn (".long\t%2", op);
8449 
        }
8450 
      if (op[7])
8451 
        {
8452 
          targetm.asm_out.internal_label (file, "L",
8453 
                                          CODE_LABEL_NUMBER (op[7]));
8454 
          output_asm_insn (".long\t%3", op);
8455 
        }
8456 
    }
8457 
  else
8458 
    {
8459 
      /* Setup base pointer if required.  */
8460 
      if (!vcall_offset
8461 
          || (!DISP_IN_RANGE (delta)
8462 
              && !CONST_OK_FOR_K (delta)
8463 
              && !CONST_OK_FOR_Os (delta))
8464 
          || (!DISP_IN_RANGE (delta)
8465 
              && !CONST_OK_FOR_K (vcall_offset)
8466 
              && !CONST_OK_FOR_Os (vcall_offset)))
8467 
        {
8468 
          op[5] = gen_label_rtx ();
8469 
          output_asm_insn ("basr\t%4,0", op);
8470 
          targetm.asm_out.internal_label (file, "L",
8471 
                                          CODE_LABEL_NUMBER (op[5]));
8472 
        }
8473 
 
8474 
      /* Add DELTA to this pointer.  */
8475 
      if (delta)
8476 
        {
8477 
          if (CONST_OK_FOR_J (delta))
8478 
            output_asm_insn ("la\t%1,%2(%1)", op);
8479 
          else if (DISP_IN_RANGE (delta))
8480 
            output_asm_insn ("lay\t%1,%2(%1)", op);
8481 
          else if (CONST_OK_FOR_K (delta))
8482 
            output_asm_insn ("ahi\t%1,%2", op);
8483 
          else if (CONST_OK_FOR_Os (delta))
8484 
            output_asm_insn ("afi\t%1,%2", op);
8485 
          else
8486 
            {
8487 
              op[6] = gen_label_rtx ();
8488 
              output_asm_insn ("a\t%1,%6-%5(%4)", op);
8489 
            }
8490 
        }
8491 
 
8492 
      /* Perform vcall adjustment.  */
8493 
      if (vcall_offset)
8494 
        {
8495 
          if (CONST_OK_FOR_J (vcall_offset))
8496 
            {
8497 
              output_asm_insn ("l\t%4,0(%1)", op);
8498 
              output_asm_insn ("a\t%1,%3(%4)", op);
8499 
            }
8500 
          else if (DISP_IN_RANGE (vcall_offset))
8501 
            {
8502 
              output_asm_insn ("l\t%4,0(%1)", op);
8503 
              output_asm_insn ("ay\t%1,%3(%4)", op);
8504 
            }
8505 
          else if (CONST_OK_FOR_K (vcall_offset))
8506 
            {
8507 
              output_asm_insn ("lhi\t%4,%3", op);
8508 
              output_asm_insn ("a\t%4,0(%1)", op);
8509 
              output_asm_insn ("a\t%1,0(%4)", op);
8510 
            }
8511 
          else if (CONST_OK_FOR_Os (vcall_offset))
8512 
            {
8513 
              output_asm_insn ("iilf\t%4,%3", op);
8514 
              output_asm_insn ("a\t%4,0(%1)", op);
8515 
              output_asm_insn ("a\t%1,0(%4)", op);
8516 
            }
8517 
          else
8518 
            {
8519 
              op[7] = gen_label_rtx ();
8520 
              output_asm_insn ("l\t%4,%7-%5(%4)", op);
8521 
              output_asm_insn ("a\t%4,0(%1)", op);
8522 
              output_asm_insn ("a\t%1,0(%4)", op);
8523 
            }
8524 
 
8525 
          /* We had to clobber the base pointer register.
8526 
             Re-setup the base pointer (with a different base).  */
8527 
          op[5] = gen_label_rtx ();
8528 
          output_asm_insn ("basr\t%4,0", op);
8529 
          targetm.asm_out.internal_label (file, "L",
8530 
                                          CODE_LABEL_NUMBER (op[5]));
8531 
        }
8532 
 
8533 
      /* Jump to target.  */
8534 
      op[8] = gen_label_rtx ();
8535 
 
8536 
      if (!flag_pic)
8537 
        output_asm_insn ("l\t%4,%8-%5(%4)", op);
8538 
      else if (!nonlocal)
8539 
        output_asm_insn ("a\t%4,%8-%5(%4)", op);
8540 
      /* We cannot call through .plt, since .plt requires %r12 loaded.  */
8541 
      else if (flag_pic == 1)
8542 
        {
8543 
          output_asm_insn ("a\t%4,%8-%5(%4)", op);
8544 
          output_asm_insn ("l\t%4,%0(%4)", op);
8545 
        }
8546 
      else if (flag_pic == 2)
8547 
        {
8548 
          op[9] = gen_rtx_REG (Pmode, 0);
8549 
          output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8550 
          output_asm_insn ("a\t%4,%8-%5(%4)", op);
8551 
          output_asm_insn ("ar\t%4,%9", op);
8552 
          output_asm_insn ("l\t%4,0(%4)", op);
8553 
        }
8554 
 
8555 
      output_asm_insn ("br\t%4", op);
8556 
 
8557 
      /* Output literal pool.  */
8558 
      output_asm_insn (".align\t4", op);
8559 
 
8560 
      if (nonlocal && flag_pic == 2)
8561 
        output_asm_insn (".long\t%0", op);
8562 
      if (nonlocal)
8563 
        {
8564 
          op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8565 
          SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8566 
        }
8567 
 
8568 
      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8569 
      if (!flag_pic)
8570 
        output_asm_insn (".long\t%0", op);
8571 
      else
8572 
        output_asm_insn (".long\t%0-%5", op);
8573 
 
8574 
      if (op[6])
8575 
        {
8576 
          targetm.asm_out.internal_label (file, "L",
8577 
                                          CODE_LABEL_NUMBER (op[6]));
8578 
          output_asm_insn (".long\t%2", op);
8579 
        }
8580 
      if (op[7])
8581 
        {
8582 
          targetm.asm_out.internal_label (file, "L",
8583 
                                          CODE_LABEL_NUMBER (op[7]));
8584 
          output_asm_insn (".long\t%3", op);
8585 
        }
8586 
    }
8587 
}
8588 
 
8589 
static bool
8590 
s390_valid_pointer_mode (enum machine_mode mode)
8591 
{
8592 
  return (mode == SImode || (TARGET_64BIT && mode == DImode));
8593 
}
8594 
 
8595 
/* Checks whether the given ARGUMENT_LIST would use a caller
8596 
   saved register.  This is used to decide whether sibling call
8597 
   optimization could be performed on the respective function
8598 
   call.  */
8599 
 
8600 
static bool
8601 
s390_call_saved_register_used (tree argument_list)
8602 
{
8603 
  CUMULATIVE_ARGS cum;
8604 
  tree parameter;
8605 
  enum machine_mode mode;
8606 
  tree type;
8607 
  rtx parm_rtx;
8608 
  int reg;
8609 
 
8610 
  INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8611 
 
8612 
  while (argument_list)
8613 
    {
8614 
      parameter = TREE_VALUE (argument_list);
8615 
      argument_list = TREE_CHAIN (argument_list);
8616 
 
8617 
      gcc_assert (parameter);
8618 
 
8619 
      /* For an undeclared variable passed as parameter we will get
8620 
         an ERROR_MARK node here.  */
8621 
      if (TREE_CODE (parameter) == ERROR_MARK)
8622 
        return true;
8623 
 
8624 
      type = TREE_TYPE (parameter);
8625 
      gcc_assert (type);
8626 
 
8627 
      mode = TYPE_MODE (type);
8628 
      gcc_assert (mode);
8629 
 
8630 
      if (pass_by_reference (&cum, mode, type, true))
8631 
        {
8632 
          mode = Pmode;
8633 
          type = build_pointer_type (type);
8634 
        }
8635 
 
8636 
       parm_rtx = s390_function_arg (&cum, mode, type, 0);
8637 
 
8638 
       s390_function_arg_advance (&cum, mode, type, 0);
8639 
 
8640 
       if (parm_rtx && REG_P (parm_rtx))
8641 
         {
8642 
           for (reg = 0;
8643 
                reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8644 
                reg++)
8645 
             if (! call_used_regs[reg + REGNO (parm_rtx)])
8646 
               return true;
8647 
         }
8648 
    }
8649 
  return false;
8650 
}
8651 
 
8652 
/* Return true if the given call expression can be
8653 
   turned into a sibling call.
8654 
   DECL holds the declaration of the function to be called whereas
8655 
   EXP is the call expression itself.  */
8656 
 
8657 
static bool
8658 
s390_function_ok_for_sibcall (tree decl, tree exp)
8659 
{
8660 
  /* The TPF epilogue uses register 1.  */
8661 
  if (TARGET_TPF_PROFILING)
8662 
    return false;
8663 
 
8664 
  /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8665 
     which would have to be restored before the sibcall.  */
8666 
  if (!TARGET_64BIT && flag_pic && decl && TREE_PUBLIC (decl))
8667 
    return false;
8668 
 
8669 
  /* Register 6 on s390 is available as an argument register but unfortunately
8670 
     "caller saved". This makes functions needing this register for arguments
8671 
     not suitable for sibcalls.  */
8672 
  if (TREE_OPERAND (exp, 1)
8673 
      && s390_call_saved_register_used (TREE_OPERAND (exp, 1)))
8674 
      return false;
8675 
 
8676 
  return true;
8677 
}
8678 
 
8679 
/* Return the fixed registers used for condition codes.  */
8680 
 
8681 
static bool
8682 
s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8683 
{
8684 
  *p1 = CC_REGNUM;
8685 
  *p2 = INVALID_REGNUM;
8686 
 
8687 
  return true;
8688 
}
8689 
 
8690 
/* This function is used by the call expanders of the machine description.
8691 
   It emits the call insn itself together with the necessary operations
8692 
   to adjust the target address and returns the emitted insn.
8693 
   ADDR_LOCATION is the target address rtx
8694 
   TLS_CALL the location of the thread-local symbol
8695 
   RESULT_REG the register where the result of the call should be stored
8696 
   RETADDR_REG the register where the return address should be stored
8697 
               If this parameter is NULL_RTX the call is considered
8698 
               to be a sibling call.  */
8699 
 
8700 
rtx
8701 
s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8702 
                rtx retaddr_reg)
8703 
{
8704 
  bool plt_call = false;
8705 
  rtx insn;
8706 
  rtx call;
8707 
  rtx clobber;
8708 
  rtvec vec;
8709 
 
8710 
  /* Direct function calls need special treatment.  */
8711 
  if (GET_CODE (addr_location) == SYMBOL_REF)
8712 
    {
8713 
      /* When calling a global routine in PIC mode, we must
8714 
         replace the symbol itself with the PLT stub.  */
8715 
      if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8716 
        {
8717 
          addr_location = gen_rtx_UNSPEC (Pmode,
8718 
                                          gen_rtvec (1, addr_location),
8719 
                                          UNSPEC_PLT);
8720 
          addr_location = gen_rtx_CONST (Pmode, addr_location);
8721 
          plt_call = true;
8722 
        }
8723 
 
8724 
      /* Unless we can use the bras(l) insn, force the
8725 
         routine address into a register.  */
8726 
      if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8727 
        {
8728 
          if (flag_pic)
8729 
            addr_location = legitimize_pic_address (addr_location, 0);
8730 
          else
8731 
            addr_location = force_reg (Pmode, addr_location);
8732 
        }
8733 
    }
8734 
 
8735 
  /* If it is already an indirect call or the code above moved the
8736 
     SYMBOL_REF to somewhere else make sure the address can be found in
8737 
     register 1.  */
8738 
  if (retaddr_reg == NULL_RTX
8739 
      && GET_CODE (addr_location) != SYMBOL_REF
8740 
      && !plt_call)
8741 
    {
8742 
      emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8743 
      addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8744 
    }
8745 
 
8746 
  addr_location = gen_rtx_MEM (QImode, addr_location);
8747 
  call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8748 
 
8749 
  if (result_reg != NULL_RTX)
8750 
    call = gen_rtx_SET (VOIDmode, result_reg, call);
8751 
 
8752 
  if (retaddr_reg != NULL_RTX)
8753 
    {
8754 
      clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8755 
 
8756 
      if (tls_call != NULL_RTX)
8757 
        vec = gen_rtvec (3, call, clobber,
8758 
                         gen_rtx_USE (VOIDmode, tls_call));
8759 
      else
8760 
        vec = gen_rtvec (2, call, clobber);
8761 
 
8762 
      call = gen_rtx_PARALLEL (VOIDmode, vec);
8763 
    }
8764 
 
8765 
  insn = emit_call_insn (call);
8766 
 
8767 
  /* 31-bit PLT stubs and tls calls use the GOT register implicitly.  */
8768 
  if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8769 
    {
8770 
      /* s390_function_ok_for_sibcall should
8771 
         have denied sibcalls in this case.  */
8772 
      gcc_assert (retaddr_reg != NULL_RTX);
8773 
 
8774 
      use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8775 
    }
8776 
  return insn;
8777 
}
8778 
 
8779 
/* Implement CONDITIONAL_REGISTER_USAGE.  */
8780 
 
8781 
void
8782 
s390_conditional_register_usage (void)
8783 
{
8784 
  int i;
8785 
 
8786 
  if (flag_pic)
8787 
    {
8788 
      fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8789 
      call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8790 
    }
8791 
  if (TARGET_CPU_ZARCH)
8792 
    {
8793 
      fixed_regs[BASE_REGNUM] = 0;
8794 
      call_used_regs[BASE_REGNUM] = 0;
8795 
      fixed_regs[RETURN_REGNUM] = 0;
8796 
      call_used_regs[RETURN_REGNUM] = 0;
8797 
    }
8798 
  if (TARGET_64BIT)
8799 
    {
8800 
      for (i = 24; i < 32; i++)
8801 
        call_used_regs[i] = call_really_used_regs[i] = 0;
8802 
    }
8803 
  else
8804 
    {
8805 
      for (i = 18; i < 20; i++)
8806 
        call_used_regs[i] = call_really_used_regs[i] = 0;
8807 
    }
8808 
 
8809 
  if (TARGET_SOFT_FLOAT)
8810 
    {
8811 
      for (i = 16; i < 32; i++)
8812 
        call_used_regs[i] = fixed_regs[i] = 1;
8813 
    }
8814 
}
8815 
 
8816 
/* Corresponding function to eh_return expander.  */
8817 
 
8818 
static GTY(()) rtx s390_tpf_eh_return_symbol;
8819 
void
8820 
s390_emit_tpf_eh_return (rtx target)
8821 
{
8822 
  rtx insn, reg;
8823 
 
8824 
  if (!s390_tpf_eh_return_symbol)
8825 
    s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8826 
 
8827 
  reg = gen_rtx_REG (Pmode, 2);
8828 
 
8829 
  emit_move_insn (reg, target);
8830 
  insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8831 
                                     gen_rtx_REG (Pmode, RETURN_REGNUM));
8832 
  use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8833 
 
8834 
  emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8835 
}
8836 
 
8837 
/* Rework the prologue/epilogue to avoid saving/restoring
8838 
   registers unnecessarily.  */
8839 
 
8840 
static void
8841 
s390_optimize_prologue (void)
8842 
{
8843 
  rtx insn, new_insn, next_insn;
8844 
 
8845 
  /* Do a final recompute of the frame-related data.  */
8846 
 
8847 
  s390_update_frame_layout ();
8848 
 
8849 
  /* If all special registers are in fact used, there's nothing we
8850 
     can do, so no point in walking the insn list.  */
8851 
 
8852 
  if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
8853 
      && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
8854 
      && (TARGET_CPU_ZARCH
8855 
          || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
8856 
              && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
8857 
    return;
8858 
 
8859 
  /* Search for prologue/epilogue insns and replace them.  */
8860 
 
8861 
  for (insn = get_insns (); insn; insn = next_insn)
8862 
    {
8863 
      int first, last, off;
8864 
      rtx set, base, offset;
8865 
 
8866 
      next_insn = NEXT_INSN (insn);
8867 
 
8868 
      if (GET_CODE (insn) != INSN)
8869 
        continue;
8870 
 
8871 
      if (GET_CODE (PATTERN (insn)) == PARALLEL
8872 
          && store_multiple_operation (PATTERN (insn), VOIDmode))
8873 
        {
8874 
          set = XVECEXP (PATTERN (insn), 0, 0);
8875 
          first = REGNO (SET_SRC (set));
8876 
          last = first + XVECLEN (PATTERN (insn), 0) - 1;
8877 
          offset = const0_rtx;
8878 
          base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8879 
          off = INTVAL (offset);
8880 
 
8881 
          if (GET_CODE (base) != REG || off < 0)
8882 
            continue;
8883 
          if (cfun_frame_layout.first_save_gpr != -1
8884 
              && (cfun_frame_layout.first_save_gpr < first
8885 
                  || cfun_frame_layout.last_save_gpr > last))
8886 
            continue;
8887 
          if (REGNO (base) != STACK_POINTER_REGNUM
8888 
              && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8889 
            continue;
8890 
          if (first > BASE_REGNUM || last < BASE_REGNUM)
8891 
            continue;
8892 
 
8893 
          if (cfun_frame_layout.first_save_gpr != -1)
8894 
            {
8895 
              new_insn  = save_gprs (base,
8896 
                                     off + (cfun_frame_layout.first_save_gpr
8897 
                                            - first) * UNITS_PER_WORD,
8898 
                                     cfun_frame_layout.first_save_gpr,
8899 
                                     cfun_frame_layout.last_save_gpr);
8900 
              new_insn = emit_insn_before (new_insn, insn);
8901 
              INSN_ADDRESSES_NEW (new_insn, -1);
8902 
            }
8903 
 
8904 
          remove_insn (insn);
8905 
          continue;
8906 
        }
8907 
 
8908 
      if (cfun_frame_layout.first_save_gpr == -1
8909 
          && GET_CODE (PATTERN (insn)) == SET
8910 
          && GET_CODE (SET_SRC (PATTERN (insn))) == REG
8911 
          && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
8912 
              || (!TARGET_CPU_ZARCH
8913 
                  && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
8914 
          && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
8915 
        {
8916 
          set = PATTERN (insn);
8917 
          first = REGNO (SET_SRC (set));
8918 
          offset = const0_rtx;
8919 
          base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8920 
          off = INTVAL (offset);
8921 
 
8922 
          if (GET_CODE (base) != REG || off < 0)
8923 
            continue;
8924 
          if (REGNO (base) != STACK_POINTER_REGNUM
8925 
              && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8926 
            continue;
8927 
 
8928 
          remove_insn (insn);
8929 
          continue;
8930 
        }
8931 
 
8932 
      if (GET_CODE (PATTERN (insn)) == PARALLEL
8933 
          && load_multiple_operation (PATTERN (insn), VOIDmode))
8934 
        {
8935 
          set = XVECEXP (PATTERN (insn), 0, 0);
8936 
          first = REGNO (SET_DEST (set));
8937 
          last = first + XVECLEN (PATTERN (insn), 0) - 1;
8938 
          offset = const0_rtx;
8939 
          base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8940 
          off = INTVAL (offset);
8941 
 
8942 
          if (GET_CODE (base) != REG || off < 0)
8943 
            continue;
8944 
          if (cfun_frame_layout.first_restore_gpr != -1
8945 
              && (cfun_frame_layout.first_restore_gpr < first
8946 
                  || cfun_frame_layout.last_restore_gpr > last))
8947 
            continue;
8948 
          if (REGNO (base) != STACK_POINTER_REGNUM
8949 
              && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8950 
            continue;
8951 
          if (first > BASE_REGNUM || last < BASE_REGNUM)
8952 
            continue;
8953 
 
8954 
          if (cfun_frame_layout.first_restore_gpr != -1)
8955 
            {
8956 
              new_insn = restore_gprs (base,
8957 
                                       off + (cfun_frame_layout.first_restore_gpr
8958 
                                              - first) * UNITS_PER_WORD,
8959 
                                       cfun_frame_layout.first_restore_gpr,
8960 
                                       cfun_frame_layout.last_restore_gpr);
8961 
              new_insn = emit_insn_before (new_insn, insn);
8962 
              INSN_ADDRESSES_NEW (new_insn, -1);
8963 
            }
8964 
 
8965 
          remove_insn (insn);
8966 
          continue;
8967 
        }
8968 
 
8969 
      if (cfun_frame_layout.first_restore_gpr == -1
8970 
          && GET_CODE (PATTERN (insn)) == SET
8971 
          && GET_CODE (SET_DEST (PATTERN (insn))) == REG
8972 
          && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
8973 
              || (!TARGET_CPU_ZARCH
8974 
                  && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
8975 
          && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
8976 
        {
8977 
          set = PATTERN (insn);
8978 
          first = REGNO (SET_DEST (set));
8979 
          offset = const0_rtx;
8980 
          base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8981 
          off = INTVAL (offset);
8982 
 
8983 
          if (GET_CODE (base) != REG || off < 0)
8984 
            continue;
8985 
          if (REGNO (base) != STACK_POINTER_REGNUM
8986 
              && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8987 
            continue;
8988 
 
8989 
          remove_insn (insn);
8990 
          continue;
8991 
        }
8992 
    }
8993 
}
8994 
 
8995 
/* Perform machine-dependent processing.  */
8996 
 
8997 
static void
8998 
s390_reorg (void)
8999 
{
9000 
  bool pool_overflow = false;
9001 
 
9002 
  /* Make sure all splits have been performed; splits after
9003 
     machine_dependent_reorg might confuse insn length counts.  */
9004 
  split_all_insns_noflow ();
9005 
 
9006 
  /* From here on decomposed literal pool addresses must be accepted.  */
9007 
  cfun->machine->decomposed_literal_pool_addresses_ok_p = true;
9008 
 
9009 
  /* Install the main literal pool and the associated base
9010 
     register load insns.
9011 
 
9012 
     In addition, there are two problematic situations we need
9013 
     to correct:
9014 
 
9015 
     - the literal pool might be > 4096 bytes in size, so that
9016 
       some of its elements cannot be directly accessed
9017 
 
9018 
     - a branch target might be > 64K away from the branch, so that
9019 
       it is not possible to use a PC-relative instruction.
9020 
 
9021 
     To fix those, we split the single literal pool into multiple
9022 
     pool chunks, reloading the pool base register at various
9023 
     points throughout the function to ensure it always points to
9024 
     the pool chunk the following code expects, and / or replace
9025 
     PC-relative branches by absolute branches.
9026 
 
9027 
     However, the two problems are interdependent: splitting the
9028 
     literal pool can move a branch further away from its target,
9029 
     causing the 64K limit to overflow, and on the other hand,
9030 
     replacing a PC-relative branch by an absolute branch means
9031 
     we need to put the branch target address into the literal
9032 
     pool, possibly causing it to overflow.
9033 
 
9034 
     So, we loop trying to fix up both problems until we manage
9035 
     to satisfy both conditions at the same time.  Note that the
9036 
     loop is guaranteed to terminate as every pass of the loop
9037 
     strictly decreases the total number of PC-relative branches
9038 
     in the function.  (This is not completely true as there
9039 
     might be branch-over-pool insns introduced by chunkify_start.
9040 
     Those never need to be split however.)  */
9041 
 
9042 
  for (;;)
9043 
    {
9044 
      struct constant_pool *pool = NULL;
9045 
 
9046 
      /* Collect the literal pool.  */
9047 
      if (!pool_overflow)
9048 
        {
9049 
          pool = s390_mainpool_start ();
9050 
          if (!pool)
9051 
            pool_overflow = true;
9052 
        }
9053 
 
9054 
      /* If literal pool overflowed, start to chunkify it.  */
9055 
      if (pool_overflow)
9056 
        pool = s390_chunkify_start ();
9057 
 
9058 
      /* Split out-of-range branches.  If this has created new
9059 
         literal pool entries, cancel current chunk list and
9060 
         recompute it.  zSeries machines have large branch
9061 
         instructions, so we never need to split a branch.  */
9062 
      if (!TARGET_CPU_ZARCH && s390_split_branches ())
9063 
        {
9064 
          if (pool_overflow)
9065 
            s390_chunkify_cancel (pool);
9066 
          else
9067 
            s390_mainpool_cancel (pool);
9068 
 
9069 
          continue;
9070 
        }
9071 
 
9072 
      /* If we made it up to here, both conditions are satisfied.
9073 
         Finish up literal pool related changes.  */
9074 
      if (pool_overflow)
9075 
        s390_chunkify_finish (pool);
9076 
      else
9077 
        s390_mainpool_finish (pool);
9078 
 
9079 
      /* We're done splitting branches.  */
9080 
      cfun->machine->split_branches_pending_p = false;
9081 
      break;
9082 
    }
9083 
 
9084 
  /* Generate out-of-pool execute target insns.  */
9085 
  if (TARGET_CPU_ZARCH)
9086 
    {
9087 
      rtx insn, label, target;
9088 
 
9089 
      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9090 
        {
9091 
          label = s390_execute_label (insn);
9092 
          if (!label)
9093 
            continue;
9094 
 
9095 
          gcc_assert (label != const0_rtx);
9096 
 
9097 
          target = emit_label (XEXP (label, 0));
9098 
          INSN_ADDRESSES_NEW (target, -1);
9099 
 
9100 
          target = emit_insn (s390_execute_target (insn));
9101 
          INSN_ADDRESSES_NEW (target, -1);
9102 
        }
9103 
    }
9104 
 
9105 
  /* Try to optimize prologue and epilogue further.  */
9106 
  s390_optimize_prologue ();
9107 
}
9108 
 
9109 
 
9110 
/* Initialize GCC target structure.  */
9111 
 
9112 
#undef  TARGET_ASM_ALIGNED_HI_OP
9113 
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9114 
#undef  TARGET_ASM_ALIGNED_DI_OP
9115 
#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9116 
#undef  TARGET_ASM_INTEGER
9117 
#define TARGET_ASM_INTEGER s390_assemble_integer
9118 
 
9119 
#undef  TARGET_ASM_OPEN_PAREN
9120 
#define TARGET_ASM_OPEN_PAREN ""
9121 
 
9122 
#undef  TARGET_ASM_CLOSE_PAREN
9123 
#define TARGET_ASM_CLOSE_PAREN ""
9124 
 
9125 
#undef TARGET_DEFAULT_TARGET_FLAGS
9126 
#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9127 
#undef TARGET_HANDLE_OPTION
9128 
#define TARGET_HANDLE_OPTION s390_handle_option
9129 
 
9130 
#undef  TARGET_ENCODE_SECTION_INFO
9131 
#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9132 
 
9133 
#ifdef HAVE_AS_TLS
9134 
#undef TARGET_HAVE_TLS
9135 
#define TARGET_HAVE_TLS true
9136 
#endif
9137 
#undef TARGET_CANNOT_FORCE_CONST_MEM
9138 
#define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9139 
 
9140 
#undef TARGET_DELEGITIMIZE_ADDRESS
9141 
#define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9142 
 
9143 
#undef TARGET_RETURN_IN_MEMORY
9144 
#define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9145 
 
9146 
#undef  TARGET_INIT_BUILTINS
9147 
#define TARGET_INIT_BUILTINS s390_init_builtins
9148 
#undef  TARGET_EXPAND_BUILTIN
9149 
#define TARGET_EXPAND_BUILTIN s390_expand_builtin
9150 
 
9151 
#undef TARGET_ASM_OUTPUT_MI_THUNK
9152 
#define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9153 
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9154 
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9155 
 
9156 
#undef  TARGET_SCHED_ADJUST_PRIORITY
9157 
#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9158 
#undef TARGET_SCHED_ISSUE_RATE
9159 
#define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9160 
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9161 
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9162 
 
9163 
#undef TARGET_CANNOT_COPY_INSN_P
9164 
#define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9165 
#undef TARGET_RTX_COSTS
9166 
#define TARGET_RTX_COSTS s390_rtx_costs
9167 
#undef TARGET_ADDRESS_COST
9168 
#define TARGET_ADDRESS_COST s390_address_cost
9169 
 
9170 
#undef TARGET_MACHINE_DEPENDENT_REORG
9171 
#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9172 
 
9173 
#undef TARGET_VALID_POINTER_MODE
9174 
#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9175 
 
9176 
#undef TARGET_BUILD_BUILTIN_VA_LIST
9177 
#define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9178 
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
9179 
#define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9180 
 
9181 
#undef TARGET_PROMOTE_FUNCTION_ARGS
9182 
#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9183 
#undef TARGET_PROMOTE_FUNCTION_RETURN
9184 
#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9185 
#undef TARGET_PASS_BY_REFERENCE
9186 
#define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9187 
 
9188 
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
9189 
#define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9190 
 
9191 
#undef TARGET_FIXED_CONDITION_CODE_REGS
9192 
#define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9193 
 
9194 
#undef TARGET_CC_MODES_COMPATIBLE
9195 
#define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9196 
 
9197 
#undef TARGET_INVALID_WITHIN_DOLOOP
9198 
#define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9199 
 
9200 
#ifdef HAVE_AS_TLS
9201 
#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9202 
#define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9203 
#endif
9204 
 
9205 
#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9206 
#undef TARGET_MANGLE_FUNDAMENTAL_TYPE
9207 
#define TARGET_MANGLE_FUNDAMENTAL_TYPE s390_mangle_fundamental_type
9208 
#endif
9209 
 
9210 
struct gcc_target targetm = TARGET_INITIALIZER;
9211 
 
9212 
#include "gt-s390.h"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.