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1 12 jlechner 
;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 
;;  Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 
;;  Free Software Foundation, Inc.
4 
;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 
;;                 Ulrich Weigand (uweigand@de.ibm.com).
6 
 
7 
;; This file is part of GCC.
8 
 
9 
;; GCC is free software; you can redistribute it and/or modify it under
10 
;; the terms of the GNU General Public License as published by the Free
11 
;; Software Foundation; either version 2, or (at your option) any later
12 
;; version.
13 
 
14 
;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 
;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 
;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
17 
;; for more details.
18 
 
19 
;; You should have received a copy of the GNU General Public License
20 
;; along with GCC; see the file COPYING.  If not, write to the Free
21 
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 
;; 02110-1301, USA.
23 
 
24 
;;
25 
;; Special constraints for s/390 machine description:
26 
;;
27 
;;    a -- Any address register from 1 to 15.
28 
;;    c -- Condition code register 33.
29 
;;    d -- Any register from 0 to 15.
30 
;;    f -- Floating point registers.
31 
;;    t -- Access registers 36 and 37.
32 
;;    G -- Const double zero operand
33 
;;    I -- An 8-bit constant (0..255).
34 
;;    J -- A 12-bit constant (0..4095).
35 
;;    K -- A 16-bit constant (-32768..32767).
36 
;;    L -- Value appropriate as displacement.
37 
;;         (0..4095) for short displacement
38 
;;         (-524288..524287) for long displacement
39 
;;    M -- Constant integer with a value of 0x7fffffff.
40 
;;    N -- Multiple letter constraint followed by 4 parameter letters.
41 
;;         0..9,x:  number of the part counting from most to least significant
42 
;;         H,Q:     mode of the part
43 
;;         D,S,H:   mode of the containing operand
44 
;;         0,F:     value of the other parts (F - all bits set)
45 
;;
46 
;;         The constraint matches if the specified part of a constant
47 
;;         has a value different from its other parts.  If the letter x
48 
;;         is specified instead of a part number, the constraint matches
49 
;;         if there is any single part with non-default value.
50 
;;    O -- Multiple letter constraint followed by 1 parameter.
51 
;;         s:  Signed extended immediate value (-2G .. 2G-1).
52 
;;         p:  Positive extended immediate value (0 .. 4G-1).
53 
;;         n:  Negative extended immediate value (-4G+1 .. -1).
54 
;;         These constraints do not accept any operand if the machine does
55 
;;         not provide the extended-immediate facility.
56 
;;    P -- Any integer constant that can be loaded without literal pool.
57 
;;    Q -- Memory reference without index register and with short displacement.
58 
;;    R -- Memory reference with index register and short displacement.
59 
;;    S -- Memory reference without index register but with long displacement.
60 
;;    T -- Memory reference with index register and long displacement.
61 
;;    A -- Multiple letter constraint followed by Q, R, S, or T:
62 
;;         Offsettable memory reference of type specified by second letter.
63 
;;    B -- Multiple letter constraint followed by Q, R, S, or T:
64 
;;         Memory reference of the type specified by second letter that
65 
;;         does *not* refer to a literal pool entry.
66 
;;    U -- Pointer with short displacement.
67 
;;    W -- Pointer with long displacement.
68 
;;    Y -- Shift count operand.
69 
;;
70 
;; Special formats used for outputting 390 instructions.
71 
;;
72 
;;     %C: print opcode suffix for branch condition.
73 
;;     %D: print opcode suffix for inverse branch condition.
74 
;;     %J: print tls_load/tls_gdcall/tls_ldcall suffix
75 
;;     %G: print the size of the operand in bytes.
76 
;;     %O: print only the displacement of a memory reference.
77 
;;     %R: print only the base register of a memory reference.
78 
;;     %S: print S-type memory reference (base+displacement).
79 
;;     %N: print the second word of a DImode operand.
80 
;;     %M: print the second word of a TImode operand.
81 
;;     %Y: print shift count operand.
82 
;;
83 
;;     %b: print integer X as if it's an unsigned byte.
84 
;;     %x: print integer X as if it's an unsigned halfword.
85 
;;     %h: print integer X as if it's a signed halfword.
86 
;;     %i: print the first nonzero HImode part of X.
87 
;;     %j: print the first HImode part unequal to -1 of X.
88 
;;     %k: print the first nonzero SImode part of X.
89 
;;     %m: print the first SImode part unequal to -1 of X.
90 
;;     %o: print integer X as if it's an unsigned 32bit word.
91 
;;
92 
;; We have a special constraint for pattern matching.
93 
;;
94 
;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
95 
;;
96 
 
97 
;;
98 
;; UNSPEC usage
99 
;;
100 
 
101 
(define_constants
102 
  [; Miscellaneous
103 
   (UNSPEC_ROUND                1)
104 
   (UNSPEC_CMPINT               2)
105 
   (UNSPEC_ICM                  10)
106 
 
107 
   ; GOT/PLT and lt-relative accesses
108 
   (UNSPEC_LTREL_OFFSET         100)
109 
   (UNSPEC_LTREL_BASE           101)
110 
   (UNSPEC_GOTENT               110)
111 
   (UNSPEC_GOT                  111)
112 
   (UNSPEC_GOTOFF               112)
113 
   (UNSPEC_PLT                  113)
114 
   (UNSPEC_PLTOFF               114)
115 
 
116 
   ; Literal pool
117 
   (UNSPEC_RELOAD_BASE          210)
118 
   (UNSPEC_MAIN_BASE            211)
119 
   (UNSPEC_LTREF                212)
120 
   (UNSPEC_INSN                 213)
121 
   (UNSPEC_EXECUTE              214)
122 
 
123 
   ; TLS relocation specifiers
124 
   (UNSPEC_TLSGD                500)
125 
   (UNSPEC_TLSLDM               501)
126 
   (UNSPEC_NTPOFF               502)
127 
   (UNSPEC_DTPOFF               503)
128 
   (UNSPEC_GOTNTPOFF            504)
129 
   (UNSPEC_INDNTPOFF            505)
130 
 
131 
   ; TLS support
132 
   (UNSPEC_TLSLDM_NTPOFF        511)
133 
   (UNSPEC_TLS_LOAD             512)
134 
 
135 
   ; String Functions
136 
   (UNSPEC_SRST                 600)
137 
   (UNSPEC_MVST                 601)
138 
 
139 
   ; Stack Smashing Protector
140 
   (UNSPEC_SP_SET               700)
141 
   (UNSPEC_SP_TEST              701)
142 
 ])
143 
 
144 
;;
145 
;; UNSPEC_VOLATILE usage
146 
;;
147 
 
148 
(define_constants
149 
  [; Blockage
150 
   (UNSPECV_BLOCKAGE            0)
151 
 
152 
   ; TPF Support
153 
   (UNSPECV_TPF_PROLOGUE        20)
154 
   (UNSPECV_TPF_EPILOGUE        21)
155 
 
156 
   ; Literal pool
157 
   (UNSPECV_POOL                200)
158 
   (UNSPECV_POOL_SECTION        201)
159 
   (UNSPECV_POOL_ALIGN          202)
160 
   (UNSPECV_POOL_ENTRY          203)
161 
   (UNSPECV_MAIN_POOL           300)
162 
 
163 
   ; TLS support
164 
   (UNSPECV_SET_TP              500)
165 
 
166 
   ; Atomic Support
167 
   (UNSPECV_MB                  700)
168 
   (UNSPECV_CAS                 701)
169 
  ])
170 
 
171 
;;
172 
;; Registers
173 
;;
174 
 
175 
(define_constants
176 
  [
177 
   ; Sibling call register.
178 
   (SIBCALL_REGNUM               1)
179 
   ; Literal pool base register.
180 
   (BASE_REGNUM                 13)
181 
   ; Return address register.
182 
   (RETURN_REGNUM               14)
183 
   ; Condition code register.
184 
   (CC_REGNUM                   33)
185 
   ; Thread local storage pointer register.
186 
   (TP_REGNUM                   36)
187 
  ])
188 
 
189 
 
190 
;; Instruction operand type as used in the Principles of Operation.
191 
;; Used to determine defaults for length and other attribute values.
192 
 
193 
(define_attr "op_type"
194 
  "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
195 
  (const_string "NN"))
196 
 
197 
;; Instruction type attribute used for scheduling.
198 
 
199 
(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
200 
                     cs,vs,store,sem,idiv,
201 
                     imulhi,imulsi,imuldi,
202 
                     branch,jsr,fsimptf,fsimpdf,fsimpsf,
203 
                     floadtf,floaddf,floadsf,fstoredf,fstoresf,
204 
                     fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
205 
                     ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf,
206 
                     ftrunctf,ftruncdf,other"
207 
  (cond [(eq_attr "op_type" "NN")  (const_string "other")
208 
         (eq_attr "op_type" "SS")  (const_string "cs")]
209 
    (const_string "integer")))
210 
 
211 
;; Another attribute used for scheduling purposes:
212 
;;   agen: Instruction uses the address generation unit
213 
;;   reg: Instruction does not use the agen unit
214 
 
215 
(define_attr "atype" "agen,reg"
216 
  (cond [(eq_attr "op_type" "E")   (const_string "reg")
217 
         (eq_attr "op_type" "RR")  (const_string "reg")
218 
         (eq_attr "op_type" "RX")  (const_string "agen")
219 
         (eq_attr "op_type" "RI")  (const_string "reg")
220 
         (eq_attr "op_type" "RRE") (const_string "reg")
221 
         (eq_attr "op_type" "RS")  (const_string "agen")
222 
         (eq_attr "op_type" "RSI") (const_string "agen")
223 
         (eq_attr "op_type" "S")   (const_string "agen")
224 
         (eq_attr "op_type" "SI")  (const_string "agen")
225 
         (eq_attr "op_type" "SS")  (const_string "agen")
226 
         (eq_attr "op_type" "SSE") (const_string "agen")
227 
         (eq_attr "op_type" "RXE") (const_string "agen")
228 
         (eq_attr "op_type" "RSE") (const_string "agen")
229 
         (eq_attr "op_type" "RIL") (const_string "agen")
230 
         (eq_attr "op_type" "RXY") (const_string "agen")
231 
         (eq_attr "op_type" "RSY") (const_string "agen")
232 
         (eq_attr "op_type" "SIY") (const_string "agen")]
233 
    (const_string "agen")))
234 
 
235 
;; Length in bytes.
236 
 
237 
(define_attr "length" ""
238 
  (cond [(eq_attr "op_type" "E")   (const_int 2)
239 
         (eq_attr "op_type" "RR")  (const_int 2)
240 
         (eq_attr "op_type" "RX")  (const_int 4)
241 
         (eq_attr "op_type" "RI")  (const_int 4)
242 
         (eq_attr "op_type" "RRE") (const_int 4)
243 
         (eq_attr "op_type" "RS")  (const_int 4)
244 
         (eq_attr "op_type" "RSI") (const_int 4)
245 
         (eq_attr "op_type" "S")   (const_int 4)
246 
         (eq_attr "op_type" "SI")  (const_int 4)
247 
         (eq_attr "op_type" "SS")  (const_int 6)
248 
         (eq_attr "op_type" "SSE") (const_int 6)
249 
         (eq_attr "op_type" "RXE") (const_int 6)
250 
         (eq_attr "op_type" "RSE") (const_int 6)
251 
         (eq_attr "op_type" "RIL") (const_int 6)
252 
         (eq_attr "op_type" "RXY") (const_int 6)
253 
         (eq_attr "op_type" "RSY") (const_int 6)
254 
         (eq_attr "op_type" "SIY") (const_int 6)]
255 
    (const_int 6)))
256 
 
257 
 
258 
;; Processor type.  This attribute must exactly match the processor_type
259 
;; enumeration in s390.h.  The current machine description does not
260 
;; distinguish between g5 and g6, but there are differences between the two
261 
;; CPUs could in theory be modeled.
262 
 
263 
(define_attr "cpu" "g5,g6,z900,z990,z9_109"
264 
  (const (symbol_ref "s390_tune")))
265 
 
266 
;; Pipeline description for z900.  For lack of anything better,
267 
;; this description is also used for the g5 and g6.
268 
(include "2064.md")
269 
 
270 
;; Pipeline description for z990.
271 
(include "2084.md")
272 
 
273 
;; Predicates
274 
(include "predicates.md")
275 
 
276 
;; Other includes
277 
(include "tpf.md")
278 
 
279 
;; Macros
280 
 
281 
;; This mode macro allows floating point patterns to be generated from the
282 
;; same template.
283 
(define_mode_macro FPR [TF DF SF])
284 
(define_mode_macro DSF [DF SF])
285 
 
286 
;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
287 
;; from the same template.
288 
(define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
289 
 
290 
;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
291 
;; from the same template.
292 
(define_mode_macro GPR [(DI "TARGET_64BIT") SI])
293 
(define_mode_macro DSI [DI SI])
294 
 
295 
;; This mode macro allows :P to be used for patterns that operate on
296 
;; pointer-sized quantities.  Exactly one of the two alternatives will match.
297 
(define_mode_macro DP  [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
298 
(define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
299 
 
300 
;; This mode macro allows the QI and HI patterns to be defined from
301 
;; the same template.
302 
(define_mode_macro HQI [HI QI])
303 
 
304 
;; This mode macro allows the integer patterns to be defined from the
305 
;; same template.
306 
(define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
307 
 
308 
;; This macro allows to unify all 'bCOND' expander patterns.
309 
(define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
310 
                            ordered uneq unlt ungt unle unge ltgt])
311 
 
312 
;; This macro allows to unify all 'sCOND' patterns.
313 
(define_code_macro SCOND [ltu gtu leu geu])
314 
 
315 
;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
316 
;; the same template.
317 
(define_code_macro SHIFT [ashift lshiftrt])
318 
 
319 
;; These macros allow to combine most atomic operations.
320 
(define_code_macro ATOMIC [and ior xor plus minus mult])
321 
(define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
322 
                          (plus "add") (minus "sub") (mult "nand")])
323 
 
324 
 
325 
;; In FPR templates, a string like "ltbr" will expand to "ltxbr" in TFmode,
326 
;; "ltdbr" in DFmode, and "ltebr" in SFmode.
327 
(define_mode_attr xde [(TF "x") (DF "d") (SF "e")])
328 
 
329 
;; In FPR templates, a string like "mbr" will expand to "mxbr" in TFmode,
330 
;; "mdbr" in DFmode, and "meebr" in SFmode.
331 
(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")])
332 
 
333 
;; In FPR templates, "" will expand to "RRE" in TFmode and "RR" otherwise.
334 
;; Likewise for "".
335 
(define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
336 
(define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
337 
 
338 
;; In FPR templates, "" will expand to "f" in TFmode and "R" otherwise.
339 
;; This is used to disable the memory alternative in TFmode patterns.
340 
(define_mode_attr Rf [(TF "f") (DF "R") (SF "R")])
341 
 
342 
;; In SHIFT templates, a string like "sdl" will expand to "sldl" in
343 
;; 'ashift' and "srdl" in 'lshiftrt'.
344 
(define_code_attr lr [(ashift "l") (lshiftrt "r")])
345 
 
346 
;; In SHIFT templates, this attribute holds the correct standard name for the
347 
;; pattern itself and the corresponding function calls.
348 
(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
349 
 
350 
;; This attribute handles differences in the instruction 'type' and will result
351 
;; in "RRE" for DImode and "RR" for SImode.
352 
(define_mode_attr E [(DI "E") (SI "")])
353 
 
354 
;; This attribute handles differences in the instruction 'type' and will result
355 
;; in "RSE" for TImode and "RS" for DImode.
356 
(define_mode_attr TE [(TI "E") (DI "")])
357 
 
358 
;; In GPR templates, a string like "lcr" will expand to "lcgr" in DImode
359 
;; and "lcr" in SImode.
360 
(define_mode_attr g [(DI "g") (SI "")])
361 
 
362 
;; In DP templates, a string like "cds" will expand to "cdsg" in TImode
363 
;; and "cds" in DImode.
364 
(define_mode_attr tg [(TI "g") (DI "")])
365 
 
366 
;; In GPR templates, a string like "cdbr" will expand to "cgdbr" in DImode
367 
;; and "cfdbr" in SImode.
368 
(define_mode_attr gf [(DI "g") (SI "f")])
369 
 
370 
;; ICM mask required to load MODE value into the lowest subreg
371 
;; of a SImode register.
372 
(define_mode_attr icm_lo [(HI "3") (QI "1")])
373 
 
374 
;; In HQI templates, a string like "llg" will expand to "llgh" in
375 
;; HImode and "llgc" in QImode.
376 
(define_mode_attr hc [(HI "h") (QI "c")])
377 
 
378 
;; In P templates, the mode  will expand to "TI" in DImode and "DI"
379 
;; in SImode.
380 
(define_mode_attr DBL [(DI "TI") (SI "DI")])
381 
 
382 
;; Maximum unsigned integer that fits in MODE.
383 
(define_mode_attr max_uint [(HI "65535") (QI "255")])
384 
 
385 
 
386 
;;
387 
;;- Compare instructions.
388 
;;
389 
 
390 
(define_expand "cmp"
391 
  [(set (reg:CC CC_REGNUM)
392 
        (compare:CC (match_operand:GPR 0 "register_operand" "")
393 
                    (match_operand:GPR 1 "general_operand" "")))]
394 
  ""
395 
{
396 
  s390_compare_op0 = operands[0];
397 
  s390_compare_op1 = operands[1];
398 
  DONE;
399 
})
400 
 
401 
(define_expand "cmp"
402 
  [(set (reg:CC CC_REGNUM)
403 
        (compare:CC (match_operand:FPR 0 "register_operand" "")
404 
                    (match_operand:FPR 1 "general_operand" "")))]
405 
  "TARGET_HARD_FLOAT"
406 
{
407 
  s390_compare_op0 = operands[0];
408 
  s390_compare_op1 = operands[1];
409 
  DONE;
410 
})
411 
 
412 
 
413 
; Test-under-Mask instructions
414 
 
415 
(define_insn "*tmqi_mem"
416 
  [(set (reg CC_REGNUM)
417 
        (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
418 
                         (match_operand:QI 1 "immediate_operand" "n,n"))
419 
                 (match_operand:QI 2 "immediate_operand" "n,n")))]
420 
  "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
421 
  "@
422 
   tm\t%S0,%b1
423 
   tmy\t%S0,%b1"
424 
  [(set_attr "op_type" "SI,SIY")])
425 
 
426 
(define_insn "*tmdi_reg"
427 
  [(set (reg CC_REGNUM)
428 
        (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
429 
                         (match_operand:DI 1 "immediate_operand"
430 
                                             "N0HD0,N1HD0,N2HD0,N3HD0"))
431 
                 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
432 
  "TARGET_64BIT
433 
   && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
434 
   && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
435 
  "@
436 
   tmhh\t%0,%i1
437 
   tmhl\t%0,%i1
438 
   tmlh\t%0,%i1
439 
   tmll\t%0,%i1"
440 
  [(set_attr "op_type" "RI")])
441 
 
442 
(define_insn "*tmsi_reg"
443 
  [(set (reg CC_REGNUM)
444 
        (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
445 
                         (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
446 
                 (match_operand:SI 2 "immediate_operand" "n,n")))]
447 
  "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
448 
   && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
449 
  "@
450 
   tmh\t%0,%i1
451 
   tml\t%0,%i1"
452 
  [(set_attr "op_type" "RI")])
453 
 
454 
(define_insn "*tm_full"
455 
  [(set (reg CC_REGNUM)
456 
        (compare (match_operand:HQI 0 "register_operand" "d")
457 
                 (match_operand:HQI 1 "immediate_operand" "n")))]
458 
  "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
459 
  "tml\t%0,"
460 
  [(set_attr "op_type" "RI")])
461 
 
462 
 
463 
; Load-and-Test instructions
464 
 
465 
(define_insn "*tstdi_sign"
466 
  [(set (reg CC_REGNUM)
467 
        (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
468 
                                         (const_int 32)) (const_int 32))
469 
                 (match_operand:DI 1 "const0_operand" "")))
470 
   (set (match_operand:DI 2 "register_operand" "=d")
471 
        (sign_extend:DI (match_dup 0)))]
472 
  "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
473 
  "ltgfr\t%2,%0"
474 
  [(set_attr "op_type" "RRE")])
475 
 
476 
(define_insn "*tstdi_extimm"
477 
  [(set (reg CC_REGNUM)
478 
        (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
479 
                 (match_operand:DI 1 "const0_operand" "")))
480 
   (set (match_operand:DI 2 "register_operand" "=d,d")
481 
        (match_dup 0))]
482 
  "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
483 
  "@
484 
   ltgr\t%2,%0
485 
   ltg\t%2,%0"
486 
  [(set_attr "op_type" "RRE,RXY")])
487 
 
488 
(define_insn "*tstdi_cconly_extimm"
489 
  [(set (reg CC_REGNUM)
490 
        (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
491 
                 (match_operand:DI 1 "const0_operand" "")))
492 
   (clobber (match_scratch:DI 2 "=X,d"))]
493 
  "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
494 
  "@
495 
   ltgr\t%0,%0
496 
   ltg\t%2,%0"
497 
  [(set_attr "op_type" "RRE,RXY")])
498 
 
499 
(define_insn "*tstdi"
500 
  [(set (reg CC_REGNUM)
501 
        (compare (match_operand:DI 0 "register_operand" "d")
502 
                 (match_operand:DI 1 "const0_operand" "")))
503 
   (set (match_operand:DI 2 "register_operand" "=d")
504 
        (match_dup 0))]
505 
  "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
506 
  "ltgr\t%2,%0"
507 
  [(set_attr "op_type" "RRE")])
508 
 
509 
(define_insn "*tstdi_cconly"
510 
  [(set (reg CC_REGNUM)
511 
        (compare (match_operand:DI 0 "register_operand" "d")
512 
                 (match_operand:DI 1 "const0_operand" "")))]
513 
  "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
514 
  "ltgr\t%0,%0"
515 
  [(set_attr "op_type" "RRE")])
516 
 
517 
(define_insn "*tstdi_cconly_31"
518 
  [(set (reg CC_REGNUM)
519 
        (compare (match_operand:DI 0 "register_operand" "d")
520 
                 (match_operand:DI 1 "const0_operand" "")))]
521 
  "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
522 
  "srda\t%0,0"
523 
  [(set_attr "op_type" "RS")
524 
   (set_attr "atype"   "reg")])
525 
 
526 
(define_insn "*tstsi_extimm"
527 
  [(set (reg CC_REGNUM)
528 
        (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
529 
                 (match_operand:SI 1 "const0_operand" "")))
530 
   (set (match_operand:SI 2 "register_operand" "=d,d")
531 
        (match_dup 0))]
532 
  "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
533 
  "@
534 
   ltr\t%2,%0
535 
   lt\t%2,%0"
536 
  [(set_attr "op_type" "RR,RXY")])
537 
 
538 
(define_insn "*tstsi_cconly_extimm"
539 
  [(set (reg CC_REGNUM)
540 
        (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
541 
                 (match_operand:SI 1 "const0_operand" "")))
542 
   (clobber (match_scratch:SI 2 "=X,d"))]
543 
  "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
544 
  "@
545 
   ltr\t%0,%0
546 
   lt\t%2,%0"
547 
  [(set_attr "op_type" "RR,RXY")])
548 
 
549 
(define_insn "*tstsi"
550 
  [(set (reg CC_REGNUM)
551 
        (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
552 
                 (match_operand:SI 1 "const0_operand" "")))
553 
   (set (match_operand:SI 2 "register_operand" "=d,d,d")
554 
        (match_dup 0))]
555 
  "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
556 
  "@
557 
   ltr\t%2,%0
558 
   icm\t%2,15,%S0
559 
   icmy\t%2,15,%S0"
560 
  [(set_attr "op_type" "RR,RS,RSY")])
561 
 
562 
(define_insn "*tstsi_cconly"
563 
  [(set (reg CC_REGNUM)
564 
        (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
565 
                 (match_operand:SI 1 "const0_operand" "")))
566 
   (clobber (match_scratch:SI 2 "=X,d,d"))]
567 
  "s390_match_ccmode(insn, CCSmode)"
568 
  "@
569 
   ltr\t%0,%0
570 
   icm\t%2,15,%S0
571 
   icmy\t%2,15,%S0"
572 
  [(set_attr "op_type" "RR,RS,RSY")])
573 
 
574 
(define_insn "*tstsi_cconly2"
575 
  [(set (reg CC_REGNUM)
576 
        (compare (match_operand:SI 0 "register_operand" "d")
577 
                 (match_operand:SI 1 "const0_operand" "")))]
578 
  "s390_match_ccmode(insn, CCSmode)"
579 
  "ltr\t%0,%0"
580 
  [(set_attr "op_type" "RR")])
581 
 
582 
(define_insn "*tstCCT"
583 
  [(set (reg CC_REGNUM)
584 
        (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
585 
                 (match_operand:HQI 1 "const0_operand" "")))
586 
   (set (match_operand:HQI 2 "register_operand" "=d,d,0")
587 
        (match_dup 0))]
588 
  "s390_match_ccmode(insn, CCTmode)"
589 
  "@
590 
   icm\t%2,,%S0
591 
   icmy\t%2,,%S0
592 
   tml\t%0,"
593 
  [(set_attr "op_type" "RS,RSY,RI")])
594 
 
595 
(define_insn "*tsthiCCT_cconly"
596 
  [(set (reg CC_REGNUM)
597 
        (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
598 
                 (match_operand:HI 1 "const0_operand" "")))
599 
   (clobber (match_scratch:HI 2 "=d,d,X"))]
600 
  "s390_match_ccmode(insn, CCTmode)"
601 
  "@
602 
   icm\t%2,3,%S0
603 
   icmy\t%2,3,%S0
604 
   tml\t%0,65535"
605 
  [(set_attr "op_type" "RS,RSY,RI")])
606 
 
607 
(define_insn "*tstqiCCT_cconly"
608 
  [(set (reg CC_REGNUM)
609 
        (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
610 
                 (match_operand:QI 1 "const0_operand" "")))]
611 
  "s390_match_ccmode(insn, CCTmode)"
612 
  "@
613 
   cli\t%S0,0
614 
   cliy\t%S0,0
615 
   tml\t%0,255"
616 
  [(set_attr "op_type" "SI,SIY,RI")])
617 
 
618 
(define_insn "*tst"
619 
  [(set (reg CC_REGNUM)
620 
        (compare (match_operand:HQI 0 "s_operand" "Q,S")
621 
                 (match_operand:HQI 1 "const0_operand" "")))
622 
   (set (match_operand:HQI 2 "register_operand" "=d,d")
623 
        (match_dup 0))]
624 
  "s390_match_ccmode(insn, CCSmode)"
625 
  "@
626 
   icm\t%2,,%S0
627 
   icmy\t%2,,%S0"
628 
  [(set_attr "op_type" "RS,RSY")])
629 
 
630 
(define_insn "*tst_cconly"
631 
  [(set (reg CC_REGNUM)
632 
        (compare (match_operand:HQI 0 "s_operand" "Q,S")
633 
                 (match_operand:HQI 1 "const0_operand" "")))
634 
   (clobber (match_scratch:HQI 2 "=d,d"))]
635 
  "s390_match_ccmode(insn, CCSmode)"
636 
  "@
637 
   icm\t%2,,%S0
638 
   icmy\t%2,,%S0"
639 
  [(set_attr "op_type" "RS,RSY")])
640 
 
641 
 
642 
; Compare (equality) instructions
643 
 
644 
(define_insn "*cmpdi_cct"
645 
  [(set (reg CC_REGNUM)
646 
        (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
647 
                 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
648 
  "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
649 
  "@
650 
   cgr\t%0,%1
651 
   cghi\t%0,%h1
652 
   cgfi\t%0,%1
653 
   cg\t%0,%1
654 
   #"
655 
  [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
656 
 
657 
(define_insn "*cmpsi_cct"
658 
  [(set (reg CC_REGNUM)
659 
        (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
660 
                 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
661 
  "s390_match_ccmode (insn, CCTmode)"
662 
  "@
663 
   cr\t%0,%1
664 
   chi\t%0,%h1
665 
   cfi\t%0,%1
666 
   c\t%0,%1
667 
   cy\t%0,%1
668 
   #"
669 
  [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
670 
 
671 
 
672 
; Compare (signed) instructions
673 
 
674 
(define_insn "*cmpdi_ccs_sign"
675 
  [(set (reg CC_REGNUM)
676 
        (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
677 
                 (match_operand:DI 0 "register_operand" "d,d")))]
678 
  "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
679 
  "@
680 
   cgfr\t%0,%1
681 
   cgf\t%0,%1"
682 
  [(set_attr "op_type" "RRE,RXY")])
683 
 
684 
(define_insn "*cmpdi_ccs"
685 
  [(set (reg CC_REGNUM)
686 
        (compare (match_operand:DI 0 "register_operand" "d,d,d,d")
687 
                 (match_operand:DI 1 "general_operand" "d,K,Os,m")))]
688 
  "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
689 
  "@
690 
   cgr\t%0,%1
691 
   cghi\t%0,%h1
692 
   cgfi\t%0,%1
693 
   cg\t%0,%1"
694 
  [(set_attr "op_type" "RRE,RI,RIL,RXY")])
695 
 
696 
(define_insn "*cmpsi_ccs_sign"
697 
  [(set (reg CC_REGNUM)
698 
        (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
699 
                 (match_operand:SI 0 "register_operand" "d,d")))]
700 
  "s390_match_ccmode(insn, CCSRmode)"
701 
  "@
702 
   ch\t%0,%1
703 
   chy\t%0,%1"
704 
  [(set_attr "op_type" "RX,RXY")])
705 
 
706 
(define_insn "*cmpsi_ccs"
707 
  [(set (reg CC_REGNUM)
708 
        (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
709 
                 (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
710 
  "s390_match_ccmode(insn, CCSmode)"
711 
  "@
712 
   cr\t%0,%1
713 
   chi\t%0,%h1
714 
   cfi\t%0,%1
715 
   c\t%0,%1
716 
   cy\t%0,%1"
717 
  [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
718 
 
719 
 
720 
; Compare (unsigned) instructions
721 
 
722 
(define_insn "*cmpdi_ccu_zero"
723 
  [(set (reg CC_REGNUM)
724 
        (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
725 
                 (match_operand:DI 0 "register_operand" "d,d")))]
726 
  "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
727 
  "@
728 
   clgfr\t%0,%1
729 
   clgf\t%0,%1"
730 
  [(set_attr "op_type" "RRE,RXY")])
731 
 
732 
(define_insn "*cmpdi_ccu"
733 
  [(set (reg CC_REGNUM)
734 
        (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
735 
                 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
736 
  "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
737 
  "@
738 
   clgr\t%0,%1
739 
   clgfi\t%0,%1
740 
   clg\t%0,%1
741 
   #
742 
   #"
743 
  [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
744 
 
745 
(define_insn "*cmpsi_ccu"
746 
  [(set (reg CC_REGNUM)
747 
        (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
748 
                 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
749 
  "s390_match_ccmode (insn, CCUmode)"
750 
  "@
751 
   clr\t%0,%1
752 
   clfi\t%0,%o1
753 
   cl\t%0,%1
754 
   cly\t%0,%1
755 
   #
756 
   #"
757 
  [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
758 
 
759 
(define_insn "*cmphi_ccu"
760 
  [(set (reg CC_REGNUM)
761 
        (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
762 
                 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
763 
  "s390_match_ccmode (insn, CCUmode)
764 
   && !register_operand (operands[1], HImode)"
765 
  "@
766 
   clm\t%0,3,%S1
767 
   clmy\t%0,3,%S1
768 
   #
769 
   #"
770 
  [(set_attr "op_type" "RS,RSY,SS,SS")])
771 
 
772 
(define_insn "*cmpqi_ccu"
773 
  [(set (reg CC_REGNUM)
774 
        (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
775 
                 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
776 
  "s390_match_ccmode (insn, CCUmode)
777 
   && !register_operand (operands[1], QImode)"
778 
  "@
779 
   clm\t%0,1,%S1
780 
   clmy\t%0,1,%S1
781 
   cli\t%S0,%b1
782 
   cliy\t%S0,%b1
783 
   #
784 
   #"
785 
  [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
786 
 
787 
 
788 
; Block compare (CLC) instruction patterns.
789 
 
790 
(define_insn "*clc"
791 
  [(set (reg CC_REGNUM)
792 
        (compare (match_operand:BLK 0 "memory_operand" "Q")
793 
                 (match_operand:BLK 1 "memory_operand" "Q")))
794 
   (use (match_operand 2 "const_int_operand" "n"))]
795 
  "s390_match_ccmode (insn, CCUmode)
796 
   && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
797 
  "clc\t%O0(%2,%R0),%S1"
798 
  [(set_attr "op_type" "SS")])
799 
 
800 
(define_split
801 
  [(set (reg CC_REGNUM)
802 
        (compare (match_operand 0 "memory_operand" "")
803 
                 (match_operand 1 "memory_operand" "")))]
804 
  "reload_completed
805 
   && s390_match_ccmode (insn, CCUmode)
806 
   && GET_MODE (operands[0]) == GET_MODE (operands[1])
807 
   && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
808 
  [(parallel
809 
    [(set (match_dup 0) (match_dup 1))
810 
     (use (match_dup 2))])]
811 
{
812 
  operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
813 
  operands[0] = adjust_address (operands[0], BLKmode, 0);
814 
  operands[1] = adjust_address (operands[1], BLKmode, 0);
815 
 
816 
  operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
817 
                                 operands[0], operands[1]);
818 
  operands[0] = SET_DEST (PATTERN (curr_insn));
819 
})
820 
 
821 
 
822 
; (DF|SF) instructions
823 
 
824 
(define_insn "*cmp_ccs_0"
825 
  [(set (reg CC_REGNUM)
826 
        (compare (match_operand:FPR 0 "register_operand" "f")
827 
                 (match_operand:FPR 1 "const0_operand" "")))]
828 
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
829 
  "ltbr\t%0,%0"
830 
   [(set_attr "op_type" "RRE")
831 
    (set_attr "type"  "fsimp")])
832 
 
833 
(define_insn "*cmp_ccs_0_ibm"
834 
  [(set (reg CC_REGNUM)
835 
        (compare (match_operand:FPR 0 "register_operand" "f")
836 
                 (match_operand:FPR 1 "const0_operand" "")))]
837 
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
838 
  "ltr\t%0,%0"
839 
   [(set_attr "op_type" "")
840 
    (set_attr "type"  "fsimp")])
841 
 
842 
(define_insn "*cmp_ccs"
843 
  [(set (reg CC_REGNUM)
844 
        (compare (match_operand:FPR 0 "register_operand" "f,f")
845 
                 (match_operand:FPR 1 "general_operand" "f,")))]
846 
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
847 
  "@
848 
   cbr\t%0,%1
849 
   cb\t%0,%1"
850 
   [(set_attr "op_type" "RRE,RXE")
851 
    (set_attr "type"  "fsimp")])
852 
 
853 
(define_insn "*cmp_ccs_ibm"
854 
  [(set (reg CC_REGNUM)
855 
        (compare (match_operand:FPR 0 "register_operand" "f,f")
856 
                 (match_operand:FPR 1 "general_operand" "f,")))]
857 
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
858 
  "@
859 
   cr\t%0,%1
860 
   c\t%0,%1"
861 
   [(set_attr "op_type" ",")
862 
    (set_attr "type"  "fsimp")])
863 
 
864 
 
865 
;;
866 
;;- Move instructions.
867 
;;
868 
 
869 
;
870 
; movti instruction pattern(s).
871 
;
872 
 
873 
(define_insn "movti"
874 
  [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
875 
        (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
876 
  "TARGET_64BIT"
877 
  "@
878 
   lmg\t%0,%N0,%S1
879 
   stmg\t%1,%N1,%S0
880 
   #
881 
   #
882 
   #"
883 
  [(set_attr "op_type" "RSY,RSY,*,*,SS")
884 
   (set_attr "type" "lm,stm,*,*,*")])
885 
 
886 
(define_split
887 
  [(set (match_operand:TI 0 "nonimmediate_operand" "")
888 
        (match_operand:TI 1 "general_operand" ""))]
889 
  "TARGET_64BIT && reload_completed
890 
   && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
891 
  [(set (match_dup 2) (match_dup 4))
892 
   (set (match_dup 3) (match_dup 5))]
893 
{
894 
  operands[2] = operand_subword (operands[0], 0, 0, TImode);
895 
  operands[3] = operand_subword (operands[0], 1, 0, TImode);
896 
  operands[4] = operand_subword (operands[1], 0, 0, TImode);
897 
  operands[5] = operand_subword (operands[1], 1, 0, TImode);
898 
})
899 
 
900 
(define_split
901 
  [(set (match_operand:TI 0 "nonimmediate_operand" "")
902 
        (match_operand:TI 1 "general_operand" ""))]
903 
  "TARGET_64BIT && reload_completed
904 
   && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
905 
  [(set (match_dup 2) (match_dup 4))
906 
   (set (match_dup 3) (match_dup 5))]
907 
{
908 
  operands[2] = operand_subword (operands[0], 1, 0, TImode);
909 
  operands[3] = operand_subword (operands[0], 0, 0, TImode);
910 
  operands[4] = operand_subword (operands[1], 1, 0, TImode);
911 
  operands[5] = operand_subword (operands[1], 0, 0, TImode);
912 
})
913 
 
914 
(define_split
915 
  [(set (match_operand:TI 0 "register_operand" "")
916 
        (match_operand:TI 1 "memory_operand" ""))]
917 
  "TARGET_64BIT && reload_completed
918 
   && !s_operand (operands[1], VOIDmode)"
919 
  [(set (match_dup 0) (match_dup 1))]
920 
{
921 
  rtx addr = operand_subword (operands[0], 1, 0, TImode);
922 
  s390_load_address (addr, XEXP (operands[1], 0));
923 
  operands[1] = replace_equiv_address (operands[1], addr);
924 
})
925 
 
926 
(define_expand "reload_outti"
927 
  [(parallel [(match_operand:TI 0 "" "")
928 
              (match_operand:TI 1 "register_operand" "d")
929 
              (match_operand:DI 2 "register_operand" "=&a")])]
930 
  "TARGET_64BIT"
931 
{
932 
  gcc_assert (MEM_P (operands[0]));
933 
  s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
934 
  operands[0] = replace_equiv_address (operands[0], operands[2]);
935 
  emit_move_insn (operands[0], operands[1]);
936 
  DONE;
937 
})
938 
 
939 
;
940 
; movdi instruction pattern(s).
941 
;
942 
 
943 
(define_expand "movdi"
944 
  [(set (match_operand:DI 0 "general_operand" "")
945 
        (match_operand:DI 1 "general_operand" ""))]
946 
  ""
947 
{
948 
  /* Handle symbolic constants.  */
949 
  if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
950 
    emit_symbolic_move (operands);
951 
})
952 
 
953 
(define_insn "*movdi_larl"
954 
  [(set (match_operand:DI 0 "register_operand" "=d")
955 
        (match_operand:DI 1 "larl_operand" "X"))]
956 
  "TARGET_64BIT
957 
   && !FP_REG_P (operands[0])"
958 
  "larl\t%0,%1"
959 
   [(set_attr "op_type" "RIL")
960 
    (set_attr "type"    "larl")])
961 
 
962 
(define_insn "*movdi_64extimm"
963 
  [(set (match_operand:DI 0 "nonimmediate_operand"
964 
                            "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
965 
        (match_operand:DI 1 "general_operand"
966 
                            "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
967 
  "TARGET_64BIT && TARGET_EXTIMM"
968 
  "@
969 
   lghi\t%0,%h1
970 
   llihh\t%0,%i1
971 
   llihl\t%0,%i1
972 
   llilh\t%0,%i1
973 
   llill\t%0,%i1
974 
   lgfi\t%0,%1
975 
   llihf\t%0,%k1
976 
   llilf\t%0,%k1
977 
   lay\t%0,%a1
978 
   lgr\t%0,%1
979 
   lg\t%0,%1
980 
   stg\t%1,%0
981 
   ldr\t%0,%1
982 
   ld\t%0,%1
983 
   ldy\t%0,%1
984 
   std\t%1,%0
985 
   stdy\t%1,%0
986 
   #
987 
   #
988 
   stam\t%1,%N1,%S0
989 
   lam\t%0,%N0,%S1
990 
   #"
991 
  [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
992 
                        RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
993 
   (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
994 
                     floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
995 
 
996 
(define_insn "*movdi_64"
997 
  [(set (match_operand:DI 0 "nonimmediate_operand"
998 
                            "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
999 
        (match_operand:DI 1 "general_operand"
1000 
                            "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1001 
  "TARGET_64BIT && !TARGET_EXTIMM"
1002 
  "@
1003 
   lghi\t%0,%h1
1004 
   llihh\t%0,%i1
1005 
   llihl\t%0,%i1
1006 
   llilh\t%0,%i1
1007 
   llill\t%0,%i1
1008 
   lay\t%0,%a1
1009 
   lgr\t%0,%1
1010 
   lg\t%0,%1
1011 
   stg\t%1,%0
1012 
   ldr\t%0,%1
1013 
   ld\t%0,%1
1014 
   ldy\t%0,%1
1015 
   std\t%1,%0
1016 
   stdy\t%1,%0
1017 
   #
1018 
   #
1019 
   stam\t%1,%N1,%S0
1020 
   lam\t%0,%N0,%S1
1021 
   #"
1022 
  [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
1023 
                        RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1024 
   (set_attr "type" "*,*,*,*,*,la,lr,load,store,
1025 
                     floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1026 
 
1027 
(define_split
1028 
  [(set (match_operand:DI 0 "register_operand" "")
1029 
        (match_operand:DI 1 "register_operand" ""))]
1030 
  "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1031 
  [(set (match_dup 2) (match_dup 3))
1032 
   (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1033 
   (set (strict_low_part (match_dup 2)) (match_dup 4))]
1034 
  "operands[2] = gen_lowpart (SImode, operands[0]);
1035 
   s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1036 
 
1037 
(define_split
1038 
  [(set (match_operand:DI 0 "register_operand" "")
1039 
        (match_operand:DI 1 "register_operand" ""))]
1040 
  "TARGET_64BIT && ACCESS_REG_P (operands[0])
1041 
   && dead_or_set_p (insn, operands[1])"
1042 
  [(set (match_dup 3) (match_dup 2))
1043 
   (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1044 
   (set (match_dup 4) (match_dup 2))]
1045 
  "operands[2] = gen_lowpart (SImode, operands[1]);
1046 
   s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1047 
 
1048 
(define_split
1049 
  [(set (match_operand:DI 0 "register_operand" "")
1050 
        (match_operand:DI 1 "register_operand" ""))]
1051 
  "TARGET_64BIT && ACCESS_REG_P (operands[0])
1052 
   && !dead_or_set_p (insn, operands[1])"
1053 
  [(set (match_dup 3) (match_dup 2))
1054 
   (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1055 
   (set (match_dup 4) (match_dup 2))
1056 
   (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1057 
  "operands[2] = gen_lowpart (SImode, operands[1]);
1058 
   s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1059 
 
1060 
(define_insn "*movdi_31"
1061 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1062 
        (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1063 
  "!TARGET_64BIT"
1064 
  "@
1065 
   lm\t%0,%N0,%S1
1066 
   lmy\t%0,%N0,%S1
1067 
   stm\t%1,%N1,%S0
1068 
   stmy\t%1,%N1,%S0
1069 
   #
1070 
   #
1071 
   ldr\t%0,%1
1072 
   ld\t%0,%1
1073 
   ldy\t%0,%1
1074 
   std\t%1,%0
1075 
   stdy\t%1,%0
1076 
   #"
1077 
  [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1078 
   (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1079 
 
1080 
(define_split
1081 
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
1082 
        (match_operand:DI 1 "general_operand" ""))]
1083 
  "!TARGET_64BIT && reload_completed
1084 
   && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1085 
  [(set (match_dup 2) (match_dup 4))
1086 
   (set (match_dup 3) (match_dup 5))]
1087 
{
1088 
  operands[2] = operand_subword (operands[0], 0, 0, DImode);
1089 
  operands[3] = operand_subword (operands[0], 1, 0, DImode);
1090 
  operands[4] = operand_subword (operands[1], 0, 0, DImode);
1091 
  operands[5] = operand_subword (operands[1], 1, 0, DImode);
1092 
})
1093 
 
1094 
(define_split
1095 
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
1096 
        (match_operand:DI 1 "general_operand" ""))]
1097 
  "!TARGET_64BIT && reload_completed
1098 
   && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1099 
  [(set (match_dup 2) (match_dup 4))
1100 
   (set (match_dup 3) (match_dup 5))]
1101 
{
1102 
  operands[2] = operand_subword (operands[0], 1, 0, DImode);
1103 
  operands[3] = operand_subword (operands[0], 0, 0, DImode);
1104 
  operands[4] = operand_subword (operands[1], 1, 0, DImode);
1105 
  operands[5] = operand_subword (operands[1], 0, 0, DImode);
1106 
})
1107 
 
1108 
(define_split
1109 
  [(set (match_operand:DI 0 "register_operand" "")
1110 
        (match_operand:DI 1 "memory_operand" ""))]
1111 
  "!TARGET_64BIT && reload_completed
1112 
   && !FP_REG_P (operands[0])
1113 
   && !s_operand (operands[1], VOIDmode)"
1114 
  [(set (match_dup 0) (match_dup 1))]
1115 
{
1116 
  rtx addr = operand_subword (operands[0], 1, 0, DImode);
1117 
  s390_load_address (addr, XEXP (operands[1], 0));
1118 
  operands[1] = replace_equiv_address (operands[1], addr);
1119 
})
1120 
 
1121 
(define_expand "reload_outdi"
1122 
  [(parallel [(match_operand:DI 0 "" "")
1123 
              (match_operand:DI 1 "register_operand" "d")
1124 
              (match_operand:SI 2 "register_operand" "=&a")])]
1125 
  "!TARGET_64BIT"
1126 
{
1127 
  gcc_assert (MEM_P (operands[0]));
1128 
  s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1129 
  operands[0] = replace_equiv_address (operands[0], operands[2]);
1130 
  emit_move_insn (operands[0], operands[1]);
1131 
  DONE;
1132 
})
1133 
 
1134 
(define_peephole2
1135 
  [(set (match_operand:DI 0 "register_operand" "")
1136 
        (mem:DI (match_operand 1 "address_operand" "")))]
1137 
  "TARGET_64BIT
1138 
   && !FP_REG_P (operands[0])
1139 
   && GET_CODE (operands[1]) == SYMBOL_REF
1140 
   && CONSTANT_POOL_ADDRESS_P (operands[1])
1141 
   && get_pool_mode (operands[1]) == DImode
1142 
   && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1143 
  [(set (match_dup 0) (match_dup 2))]
1144 
  "operands[2] = get_pool_constant (operands[1]);")
1145 
 
1146 
(define_insn "*la_64"
1147 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
1148 
        (match_operand:QI 1 "address_operand" "U,W"))]
1149 
  "TARGET_64BIT"
1150 
  "@
1151 
   la\t%0,%a1
1152 
   lay\t%0,%a1"
1153 
  [(set_attr "op_type" "RX,RXY")
1154 
   (set_attr "type"    "la")])
1155 
 
1156 
(define_peephole2
1157 
  [(parallel
1158 
    [(set (match_operand:DI 0 "register_operand" "")
1159 
          (match_operand:QI 1 "address_operand" ""))
1160 
     (clobber (reg:CC CC_REGNUM))])]
1161 
  "TARGET_64BIT
1162 
   && preferred_la_operand_p (operands[1], const0_rtx)"
1163 
  [(set (match_dup 0) (match_dup 1))]
1164 
  "")
1165 
 
1166 
(define_peephole2
1167 
  [(set (match_operand:DI 0 "register_operand" "")
1168 
        (match_operand:DI 1 "register_operand" ""))
1169 
   (parallel
1170 
    [(set (match_dup 0)
1171 
          (plus:DI (match_dup 0)
1172 
                   (match_operand:DI 2 "nonmemory_operand" "")))
1173 
     (clobber (reg:CC CC_REGNUM))])]
1174 
  "TARGET_64BIT
1175 
   && !reg_overlap_mentioned_p (operands[0], operands[2])
1176 
   && preferred_la_operand_p (operands[1], operands[2])"
1177 
  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1178 
  "")
1179 
 
1180 
(define_expand "reload_indi"
1181 
  [(parallel [(match_operand:DI 0 "register_operand" "=a")
1182 
              (match_operand:DI 1 "s390_plus_operand" "")
1183 
              (match_operand:DI 2 "register_operand" "=&a")])]
1184 
  "TARGET_64BIT"
1185 
{
1186 
  s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1187 
  DONE;
1188 
})
1189 
 
1190 
;
1191 
; movsi instruction pattern(s).
1192 
;
1193 
 
1194 
(define_expand "movsi"
1195 
  [(set (match_operand:SI 0 "general_operand" "")
1196 
        (match_operand:SI 1 "general_operand" ""))]
1197 
  ""
1198 
{
1199 
  /* Handle symbolic constants.  */
1200 
  if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1201 
    emit_symbolic_move (operands);
1202 
})
1203 
 
1204 
(define_insn "*movsi_larl"
1205 
  [(set (match_operand:SI 0 "register_operand" "=d")
1206 
        (match_operand:SI 1 "larl_operand" "X"))]
1207 
  "!TARGET_64BIT && TARGET_CPU_ZARCH
1208 
   && !FP_REG_P (operands[0])"
1209 
  "larl\t%0,%1"
1210 
   [(set_attr "op_type" "RIL")
1211 
    (set_attr "type"    "larl")])
1212 
 
1213 
(define_insn "*movsi_zarch"
1214 
  [(set (match_operand:SI 0 "nonimmediate_operand"
1215 
                            "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1216 
        (match_operand:SI 1 "general_operand"
1217 
                            "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1218 
  "TARGET_ZARCH"
1219 
  "@
1220 
   lhi\t%0,%h1
1221 
   llilh\t%0,%i1
1222 
   llill\t%0,%i1
1223 
   iilf\t%0,%o1
1224 
   lay\t%0,%a1
1225 
   lr\t%0,%1
1226 
   l\t%0,%1
1227 
   ly\t%0,%1
1228 
   st\t%1,%0
1229 
   sty\t%1,%0
1230 
   ler\t%0,%1
1231 
   le\t%0,%1
1232 
   ley\t%0,%1
1233 
   ste\t%1,%0
1234 
   stey\t%1,%0
1235 
   ear\t%0,%1
1236 
   sar\t%0,%1
1237 
   stam\t%1,%1,%S0
1238 
   lam\t%0,%0,%S1
1239 
   #"
1240 
  [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1241 
                        RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1242 
   (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1243 
                     floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1244 
 
1245 
(define_insn "*movsi_esa"
1246 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1247 
        (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1248 
  "!TARGET_ZARCH"
1249 
  "@
1250 
   lhi\t%0,%h1
1251 
   lr\t%0,%1
1252 
   l\t%0,%1
1253 
   st\t%1,%0
1254 
   ler\t%0,%1
1255 
   le\t%0,%1
1256 
   ste\t%1,%0
1257 
   ear\t%0,%1
1258 
   sar\t%0,%1
1259 
   stam\t%1,%1,%S0
1260 
   lam\t%0,%0,%S1
1261 
   #"
1262 
  [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1263 
   (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1264 
 
1265 
(define_peephole2
1266 
  [(set (match_operand:SI 0 "register_operand" "")
1267 
        (mem:SI (match_operand 1 "address_operand" "")))]
1268 
  "!FP_REG_P (operands[0])
1269 
   && GET_CODE (operands[1]) == SYMBOL_REF
1270 
   && CONSTANT_POOL_ADDRESS_P (operands[1])
1271 
   && get_pool_mode (operands[1]) == SImode
1272 
   && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1273 
  [(set (match_dup 0) (match_dup 2))]
1274 
  "operands[2] = get_pool_constant (operands[1]);")
1275 
 
1276 
(define_insn "*la_31"
1277 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
1278 
        (match_operand:QI 1 "address_operand" "U,W"))]
1279 
  "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1280 
  "@
1281 
   la\t%0,%a1
1282 
   lay\t%0,%a1"
1283 
  [(set_attr "op_type"  "RX,RXY")
1284 
   (set_attr "type"     "la")])
1285 
 
1286 
(define_peephole2
1287 
  [(parallel
1288 
    [(set (match_operand:SI 0 "register_operand" "")
1289 
          (match_operand:QI 1 "address_operand" ""))
1290 
     (clobber (reg:CC CC_REGNUM))])]
1291 
  "!TARGET_64BIT
1292 
   && preferred_la_operand_p (operands[1], const0_rtx)"
1293 
  [(set (match_dup 0) (match_dup 1))]
1294 
  "")
1295 
 
1296 
(define_peephole2
1297 
  [(set (match_operand:SI 0 "register_operand" "")
1298 
        (match_operand:SI 1 "register_operand" ""))
1299 
   (parallel
1300 
    [(set (match_dup 0)
1301 
          (plus:SI (match_dup 0)
1302 
                   (match_operand:SI 2 "nonmemory_operand" "")))
1303 
     (clobber (reg:CC CC_REGNUM))])]
1304 
  "!TARGET_64BIT
1305 
   && !reg_overlap_mentioned_p (operands[0], operands[2])
1306 
   && preferred_la_operand_p (operands[1], operands[2])"
1307 
  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1308 
  "")
1309 
 
1310 
(define_insn "*la_31_and"
1311 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
1312 
        (and:SI (match_operand:QI 1 "address_operand" "U,W")
1313 
                (const_int 2147483647)))]
1314 
  "!TARGET_64BIT"
1315 
  "@
1316 
   la\t%0,%a1
1317 
   lay\t%0,%a1"
1318 
  [(set_attr "op_type"  "RX,RXY")
1319 
   (set_attr "type"     "la")])
1320 
 
1321 
(define_insn_and_split "*la_31_and_cc"
1322 
  [(set (match_operand:SI 0 "register_operand" "=d")
1323 
        (and:SI (match_operand:QI 1 "address_operand" "p")
1324 
                (const_int 2147483647)))
1325 
   (clobber (reg:CC CC_REGNUM))]
1326 
  "!TARGET_64BIT"
1327 
  "#"
1328 
  "&& reload_completed"
1329 
  [(set (match_dup 0)
1330 
        (and:SI (match_dup 1) (const_int 2147483647)))]
1331 
  ""
1332 
  [(set_attr "op_type"  "RX")
1333 
   (set_attr "type"     "la")])
1334 
 
1335 
(define_insn "force_la_31"
1336 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
1337 
        (match_operand:QI 1 "address_operand" "U,W"))
1338 
   (use (const_int 0))]
1339 
  "!TARGET_64BIT"
1340 
  "@
1341 
   la\t%0,%a1
1342 
   lay\t%0,%a1"
1343 
  [(set_attr "op_type"  "RX")
1344 
   (set_attr "type"     "la")])
1345 
 
1346 
(define_expand "reload_insi"
1347 
  [(parallel [(match_operand:SI 0 "register_operand" "=a")
1348 
              (match_operand:SI 1 "s390_plus_operand" "")
1349 
              (match_operand:SI 2 "register_operand" "=&a")])]
1350 
  "!TARGET_64BIT"
1351 
{
1352 
  s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1353 
  DONE;
1354 
})
1355 
 
1356 
;
1357 
; movhi instruction pattern(s).
1358 
;
1359 
 
1360 
(define_expand "movhi"
1361 
  [(set (match_operand:HI 0 "nonimmediate_operand" "")
1362 
        (match_operand:HI 1 "general_operand" ""))]
1363 
  ""
1364 
{
1365 
  /* Make it explicit that loading a register from memory
1366 
     always sign-extends (at least) to SImode.  */
1367 
  if (optimize && !no_new_pseudos
1368 
      && register_operand (operands[0], VOIDmode)
1369 
      && GET_CODE (operands[1]) == MEM)
1370 
    {
1371 
      rtx tmp = gen_reg_rtx (SImode);
1372 
      rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1373 
      emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1374 
      operands[1] = gen_lowpart (HImode, tmp);
1375 
    }
1376 
})
1377 
 
1378 
(define_insn "*movhi"
1379 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1380 
        (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1381 
  ""
1382 
  "@
1383 
   lr\t%0,%1
1384 
   lhi\t%0,%h1
1385 
   lh\t%0,%1
1386 
   lhy\t%0,%1
1387 
   sth\t%1,%0
1388 
   sthy\t%1,%0
1389 
   #"
1390 
  [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1391 
   (set_attr "type" "lr,*,*,*,store,store,*")])
1392 
 
1393 
(define_peephole2
1394 
  [(set (match_operand:HI 0 "register_operand" "")
1395 
        (mem:HI (match_operand 1 "address_operand" "")))]
1396 
  "GET_CODE (operands[1]) == SYMBOL_REF
1397 
   && CONSTANT_POOL_ADDRESS_P (operands[1])
1398 
   && get_pool_mode (operands[1]) == HImode
1399 
   && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1400 
  [(set (match_dup 0) (match_dup 2))]
1401 
  "operands[2] = get_pool_constant (operands[1]);")
1402 
 
1403 
;
1404 
; movqi instruction pattern(s).
1405 
;
1406 
 
1407 
(define_expand "movqi"
1408 
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
1409 
        (match_operand:QI 1 "general_operand" ""))]
1410 
  ""
1411 
{
1412 
  /* On z/Architecture, zero-extending from memory to register
1413 
     is just as fast as a QImode load.  */
1414 
  if (TARGET_ZARCH && optimize && !no_new_pseudos
1415 
      && register_operand (operands[0], VOIDmode)
1416 
      && GET_CODE (operands[1]) == MEM)
1417 
    {
1418 
      rtx tmp = gen_reg_rtx (word_mode);
1419 
      rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1420 
      emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1421 
      operands[1] = gen_lowpart (QImode, tmp);
1422 
    }
1423 
})
1424 
 
1425 
(define_insn "*movqi"
1426 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1427 
        (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1428 
  ""
1429 
  "@
1430 
   lr\t%0,%1
1431 
   lhi\t%0,%b1
1432 
   ic\t%0,%1
1433 
   icy\t%0,%1
1434 
   stc\t%1,%0
1435 
   stcy\t%1,%0
1436 
   mvi\t%S0,%b1
1437 
   mviy\t%S0,%b1
1438 
   #"
1439 
  [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1440 
   (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1441 
 
1442 
(define_peephole2
1443 
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
1444 
        (mem:QI (match_operand 1 "address_operand" "")))]
1445 
  "GET_CODE (operands[1]) == SYMBOL_REF
1446 
   && CONSTANT_POOL_ADDRESS_P (operands[1])
1447 
   && get_pool_mode (operands[1]) == QImode
1448 
   && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1449 
  [(set (match_dup 0) (match_dup 2))]
1450 
  "operands[2] = get_pool_constant (operands[1]);")
1451 
 
1452 
;
1453 
; movstrictqi instruction pattern(s).
1454 
;
1455 
 
1456 
(define_insn "*movstrictqi"
1457 
  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1458 
                         (match_operand:QI 1 "memory_operand" "R,T"))]
1459 
  ""
1460 
  "@
1461 
   ic\t%0,%1
1462 
   icy\t%0,%1"
1463 
  [(set_attr "op_type"  "RX,RXY")])
1464 
 
1465 
;
1466 
; movstricthi instruction pattern(s).
1467 
;
1468 
 
1469 
(define_insn "*movstricthi"
1470 
  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1471 
                         (match_operand:HI 1 "memory_operand" "Q,S"))
1472 
   (clobber (reg:CC CC_REGNUM))]
1473 
  ""
1474 
  "@
1475 
   icm\t%0,3,%S1
1476 
   icmy\t%0,3,%S1"
1477 
  [(set_attr "op_type" "RS,RSY")])
1478 
 
1479 
;
1480 
; movstrictsi instruction pattern(s).
1481 
;
1482 
 
1483 
(define_insn "movstrictsi"
1484 
  [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1485 
                         (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1486 
  "TARGET_64BIT"
1487 
  "@
1488 
   lr\t%0,%1
1489 
   l\t%0,%1
1490 
   ly\t%0,%1
1491 
   ear\t%0,%1"
1492 
  [(set_attr "op_type" "RR,RX,RXY,RRE")
1493 
   (set_attr "type" "lr,load,load,*")])
1494 
 
1495 
;
1496 
; movtf instruction pattern(s).
1497 
;
1498 
 
1499 
(define_expand "movtf"
1500 
  [(set (match_operand:TF 0 "nonimmediate_operand" "")
1501 
        (match_operand:TF 1 "general_operand"       ""))]
1502 
  ""
1503 
  "")
1504 
 
1505 
(define_insn "*movtf_64"
1506 
  [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,d,QS,d,o,Q")
1507 
        (match_operand:TF 1 "general_operand"       "G,f,o,f,QS,d,dm,d,Q"))]
1508 
  "TARGET_64BIT"
1509 
  "@
1510 
   lzxr\t%0
1511 
   lxr\t%0,%1
1512 
   #
1513 
   #
1514 
   lmg\t%0,%N0,%S1
1515 
   stmg\t%1,%N1,%S0
1516 
   #
1517 
   #
1518 
   #"
1519 
  [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
1520 
   (set_attr "type"    "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
1521 
 
1522 
(define_insn "*movtf_31"
1523 
  [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
1524 
        (match_operand:TF 1 "general_operand"       "G,f,o,f,Q"))]
1525 
  "!TARGET_64BIT"
1526 
  "@
1527 
   lzxr\t%0
1528 
   lxr\t%0,%1
1529 
   #
1530 
   #
1531 
   #"
1532 
  [(set_attr "op_type" "RRE,RRE,*,*,*")
1533 
   (set_attr "type"    "fsimptf,fsimptf,*,*,*")])
1534 
 
1535 
; TFmode in GPRs splitters
1536 
 
1537 
(define_split
1538 
  [(set (match_operand:TF 0 "nonimmediate_operand" "")
1539 
        (match_operand:TF 1 "general_operand" ""))]
1540 
  "TARGET_64BIT && reload_completed
1541 
   && s390_split_ok_p (operands[0], operands[1], TFmode, 0)"
1542 
  [(set (match_dup 2) (match_dup 4))
1543 
   (set (match_dup 3) (match_dup 5))]
1544 
{
1545 
  operands[2] = operand_subword (operands[0], 0, 0, TFmode);
1546 
  operands[3] = operand_subword (operands[0], 1, 0, TFmode);
1547 
  operands[4] = operand_subword (operands[1], 0, 0, TFmode);
1548 
  operands[5] = operand_subword (operands[1], 1, 0, TFmode);
1549 
})
1550 
 
1551 
(define_split
1552 
  [(set (match_operand:TF 0 "nonimmediate_operand" "")
1553 
        (match_operand:TF 1 "general_operand" ""))]
1554 
  "TARGET_64BIT && reload_completed
1555 
   && s390_split_ok_p (operands[0], operands[1], TFmode, 1)"
1556 
  [(set (match_dup 2) (match_dup 4))
1557 
   (set (match_dup 3) (match_dup 5))]
1558 
{
1559 
  operands[2] = operand_subword (operands[0], 1, 0, TFmode);
1560 
  operands[3] = operand_subword (operands[0], 0, 0, TFmode);
1561 
  operands[4] = operand_subword (operands[1], 1, 0, TFmode);
1562 
  operands[5] = operand_subword (operands[1], 0, 0, TFmode);
1563 
})
1564 
 
1565 
(define_split
1566 
  [(set (match_operand:TF 0 "register_operand" "")
1567 
        (match_operand:TF 1 "memory_operand" ""))]
1568 
  "TARGET_64BIT && reload_completed
1569 
   && !FP_REG_P (operands[0])
1570 
   && !s_operand (operands[1], VOIDmode)"
1571 
  [(set (match_dup 0) (match_dup 1))]
1572 
{
1573 
  rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1574 
  s390_load_address (addr, XEXP (operands[1], 0));
1575 
  operands[1] = replace_equiv_address (operands[1], addr);
1576 
})
1577 
 
1578 
; TFmode in FPRs splitters
1579 
 
1580 
(define_split
1581 
  [(set (match_operand:TF 0 "register_operand" "")
1582 
        (match_operand:TF 1 "memory_operand" ""))]
1583 
  "reload_completed && offsettable_memref_p (operands[1])
1584 
   && FP_REG_P (operands[0])"
1585 
  [(set (match_dup 2) (match_dup 4))
1586 
   (set (match_dup 3) (match_dup 5))]
1587 
{
1588 
  operands[2] = simplify_gen_subreg (DFmode, operands[0], TFmode, 0);
1589 
  operands[3] = simplify_gen_subreg (DFmode, operands[0], TFmode, 8);
1590 
  operands[4] = adjust_address_nv (operands[1], DFmode, 0);
1591 
  operands[5] = adjust_address_nv (operands[1], DFmode, 8);
1592 
})
1593 
 
1594 
(define_split
1595 
  [(set (match_operand:TF 0 "memory_operand" "")
1596 
        (match_operand:TF 1 "register_operand" ""))]
1597 
  "reload_completed && offsettable_memref_p (operands[0])
1598 
   && FP_REG_P (operands[1])"
1599 
  [(set (match_dup 2) (match_dup 4))
1600 
   (set (match_dup 3) (match_dup 5))]
1601 
{
1602 
  operands[2] = adjust_address_nv (operands[0], DFmode, 0);
1603 
  operands[3] = adjust_address_nv (operands[0], DFmode, 8);
1604 
  operands[4] = simplify_gen_subreg (DFmode, operands[1], TFmode, 0);
1605 
  operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, 8);
1606 
})
1607 
 
1608 
(define_expand "reload_outtf"
1609 
  [(parallel [(match_operand:TF 0 "" "")
1610 
              (match_operand:TF 1 "register_operand" "f")
1611 
              (match_operand:SI 2 "register_operand" "=&a")])]
1612 
  ""
1613 
{
1614 
  rtx addr = gen_lowpart (Pmode, operands[2]);
1615 
 
1616 
  gcc_assert (MEM_P (operands[0]));
1617 
  s390_load_address (addr, find_replacement (&XEXP (operands[0], 0)));
1618 
  operands[0] = replace_equiv_address (operands[0], addr);
1619 
  emit_move_insn (operands[0], operands[1]);
1620 
  DONE;
1621 
})
1622 
 
1623 
(define_expand "reload_intf"
1624 
  [(parallel [(match_operand:TF 0 "register_operand" "=f")
1625 
              (match_operand:TF 1 "" "")
1626 
              (match_operand:SI 2 "register_operand" "=&a")])]
1627 
  ""
1628 
{
1629 
  rtx addr = gen_lowpart (Pmode, operands[2]);
1630 
 
1631 
  gcc_assert (MEM_P (operands[1]));
1632 
  s390_load_address (addr, find_replacement (&XEXP (operands[1], 0)));
1633 
  operands[1] = replace_equiv_address (operands[1], addr);
1634 
  emit_move_insn (operands[0], operands[1]);
1635 
  DONE;
1636 
})
1637 
 
1638 
;
1639 
; movdf instruction pattern(s).
1640 
;
1641 
 
1642 
(define_expand "movdf"
1643 
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
1644 
        (match_operand:DF 1 "general_operand"  ""))]
1645 
  ""
1646 
  "")
1647 
 
1648 
(define_insn "*movdf_64"
1649 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1650 
        (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1651 
  "TARGET_64BIT"
1652 
  "@
1653 
   lzdr\t%0
1654 
   ldr\t%0,%1
1655 
   ld\t%0,%1
1656 
   ldy\t%0,%1
1657 
   std\t%1,%0
1658 
   stdy\t%1,%0
1659 
   lgr\t%0,%1
1660 
   lg\t%0,%1
1661 
   stg\t%1,%0
1662 
   #"
1663 
  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1664 
   (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1665 
 
1666 
(define_insn "*movdf_31"
1667 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1668 
        (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1669 
  "!TARGET_64BIT"
1670 
  "@
1671 
   lzdr\t%0
1672 
   ldr\t%0,%1
1673 
   ld\t%0,%1
1674 
   ldy\t%0,%1
1675 
   std\t%1,%0
1676 
   stdy\t%1,%0
1677 
   lm\t%0,%N0,%S1
1678 
   lmy\t%0,%N0,%S1
1679 
   stm\t%1,%N1,%S0
1680 
   stmy\t%1,%N1,%S0
1681 
   #
1682 
   #
1683 
   #"
1684 
  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1685 
   (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1686 
                     lm,lm,stm,stm,*,*,*")])
1687 
 
1688 
(define_split
1689 
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
1690 
        (match_operand:DF 1 "general_operand" ""))]
1691 
  "!TARGET_64BIT && reload_completed
1692 
   && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1693 
  [(set (match_dup 2) (match_dup 4))
1694 
   (set (match_dup 3) (match_dup 5))]
1695 
{
1696 
  operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1697 
  operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1698 
  operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1699 
  operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1700 
})
1701 
 
1702 
(define_split
1703 
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
1704 
        (match_operand:DF 1 "general_operand" ""))]
1705 
  "!TARGET_64BIT && reload_completed
1706 
   && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1707 
  [(set (match_dup 2) (match_dup 4))
1708 
   (set (match_dup 3) (match_dup 5))]
1709 
{
1710 
  operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1711 
  operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1712 
  operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1713 
  operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1714 
})
1715 
 
1716 
(define_split
1717 
  [(set (match_operand:DF 0 "register_operand" "")
1718 
        (match_operand:DF 1 "memory_operand" ""))]
1719 
  "!TARGET_64BIT && reload_completed
1720 
   && !FP_REG_P (operands[0])
1721 
   && !s_operand (operands[1], VOIDmode)"
1722 
  [(set (match_dup 0) (match_dup 1))]
1723 
{
1724 
  rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1725 
  s390_load_address (addr, XEXP (operands[1], 0));
1726 
  operands[1] = replace_equiv_address (operands[1], addr);
1727 
})
1728 
 
1729 
(define_expand "reload_outdf"
1730 
  [(parallel [(match_operand:DF 0 "" "")
1731 
              (match_operand:DF 1 "register_operand" "d")
1732 
              (match_operand:SI 2 "register_operand" "=&a")])]
1733 
  "!TARGET_64BIT"
1734 
{
1735 
  gcc_assert (MEM_P (operands[0]));
1736 
  s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1737 
  operands[0] = replace_equiv_address (operands[0], operands[2]);
1738 
  emit_move_insn (operands[0], operands[1]);
1739 
  DONE;
1740 
})
1741 
 
1742 
;
1743 
; movsf instruction pattern(s).
1744 
;
1745 
 
1746 
(define_insn "movsf"
1747 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1748 
        (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1749 
  ""
1750 
  "@
1751 
   lzer\t%0
1752 
   ler\t%0,%1
1753 
   le\t%0,%1
1754 
   ley\t%0,%1
1755 
   ste\t%1,%0
1756 
   stey\t%1,%0
1757 
   lr\t%0,%1
1758 
   l\t%0,%1
1759 
   ly\t%0,%1
1760 
   st\t%1,%0
1761 
   sty\t%1,%0
1762 
   #"
1763 
  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1764 
   (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1765 
                     lr,load,load,store,store,*")])
1766 
 
1767 
;
1768 
; movcc instruction pattern
1769 
;
1770 
 
1771 
(define_insn "movcc"
1772 
  [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1773 
        (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1774 
  ""
1775 
  "@
1776 
   lr\t%0,%1
1777 
   tmh\t%1,12288
1778 
   ipm\t%0
1779 
   st\t%0,%1
1780 
   sty\t%0,%1
1781 
   l\t%1,%0
1782 
   ly\t%1,%0"
1783 
  [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1784 
   (set_attr "type" "lr,*,*,store,store,load,load")])
1785 
 
1786 
;
1787 
; Block move (MVC) patterns.
1788 
;
1789 
 
1790 
(define_insn "*mvc"
1791 
  [(set (match_operand:BLK 0 "memory_operand" "=Q")
1792 
        (match_operand:BLK 1 "memory_operand" "Q"))
1793 
   (use (match_operand 2 "const_int_operand" "n"))]
1794 
  "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1795 
  "mvc\t%O0(%2,%R0),%S1"
1796 
  [(set_attr "op_type" "SS")])
1797 
 
1798 
(define_split
1799 
  [(set (match_operand 0 "memory_operand" "")
1800 
        (match_operand 1 "memory_operand" ""))]
1801 
  "reload_completed
1802 
   && GET_MODE (operands[0]) == GET_MODE (operands[1])
1803 
   && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1804 
  [(parallel
1805 
    [(set (match_dup 0) (match_dup 1))
1806 
     (use (match_dup 2))])]
1807 
{
1808 
  operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1809 
  operands[0] = adjust_address (operands[0], BLKmode, 0);
1810 
  operands[1] = adjust_address (operands[1], BLKmode, 0);
1811 
})
1812 
 
1813 
(define_peephole2
1814 
  [(parallel
1815 
    [(set (match_operand:BLK 0 "memory_operand" "")
1816 
          (match_operand:BLK 1 "memory_operand" ""))
1817 
     (use (match_operand 2 "const_int_operand" ""))])
1818 
   (parallel
1819 
    [(set (match_operand:BLK 3 "memory_operand" "")
1820 
          (match_operand:BLK 4 "memory_operand" ""))
1821 
     (use (match_operand 5 "const_int_operand" ""))])]
1822 
  "s390_offset_p (operands[0], operands[3], operands[2])
1823 
   && s390_offset_p (operands[1], operands[4], operands[2])
1824 
   && !s390_overlap_p (operands[0], operands[1],
1825 
                       INTVAL (operands[2]) + INTVAL (operands[5]))
1826 
   && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1827 
  [(parallel
1828 
    [(set (match_dup 6) (match_dup 7))
1829 
     (use (match_dup 8))])]
1830 
  "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1831 
   operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1832 
   operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1833 
 
1834 
 
1835 
;
1836 
; load_multiple pattern(s).
1837 
;
1838 
; ??? Due to reload problems with replacing registers inside match_parallel
1839 
; we currently support load_multiple/store_multiple only after reload.
1840 
;
1841 
 
1842 
(define_expand "load_multiple"
1843 
  [(match_par_dup 3 [(set (match_operand 0 "" "")
1844 
                          (match_operand 1 "" ""))
1845 
                     (use (match_operand 2 "" ""))])]
1846 
  "reload_completed"
1847 
{
1848 
  enum machine_mode mode;
1849 
  int regno;
1850 
  int count;
1851 
  rtx from;
1852 
  int i, off;
1853 
 
1854 
  /* Support only loading a constant number of fixed-point registers from
1855 
     memory and only bother with this if more than two */
1856 
  if (GET_CODE (operands[2]) != CONST_INT
1857 
      || INTVAL (operands[2]) < 2
1858 
      || INTVAL (operands[2]) > 16
1859 
      || GET_CODE (operands[1]) != MEM
1860 
      || GET_CODE (operands[0]) != REG
1861 
      || REGNO (operands[0]) >= 16)
1862 
    FAIL;
1863 
 
1864 
  count = INTVAL (operands[2]);
1865 
  regno = REGNO (operands[0]);
1866 
  mode = GET_MODE (operands[0]);
1867 
  if (mode != SImode && mode != word_mode)
1868 
    FAIL;
1869 
 
1870 
  operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1871 
  if (no_new_pseudos)
1872 
    {
1873 
      if (GET_CODE (XEXP (operands[1], 0)) == REG)
1874 
        {
1875 
          from = XEXP (operands[1], 0);
1876 
          off = 0;
1877 
        }
1878 
      else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1879 
               && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1880 
               && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1881 
        {
1882 
          from = XEXP (XEXP (operands[1], 0), 0);
1883 
          off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1884 
        }
1885 
      else
1886 
        FAIL;
1887 
    }
1888 
  else
1889 
    {
1890 
      from = force_reg (Pmode, XEXP (operands[1], 0));
1891 
      off = 0;
1892 
    }
1893 
 
1894 
  for (i = 0; i < count; i++)
1895 
    XVECEXP (operands[3], 0, i)
1896 
      = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1897 
                     change_address (operands[1], mode,
1898 
                       plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1899 
})
1900 
 
1901 
(define_insn "*load_multiple_di"
1902 
  [(match_parallel 0 "load_multiple_operation"
1903 
                   [(set (match_operand:DI 1 "register_operand" "=r")
1904 
                         (match_operand:DI 2 "s_operand" "QS"))])]
1905 
  "reload_completed && word_mode == DImode"
1906 
{
1907 
  int words = XVECLEN (operands[0], 0);
1908 
  operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1909 
  return "lmg\t%1,%0,%S2";
1910 
}
1911 
   [(set_attr "op_type" "RSY")
1912 
    (set_attr "type"    "lm")])
1913 
 
1914 
(define_insn "*load_multiple_si"
1915 
  [(match_parallel 0 "load_multiple_operation"
1916 
                   [(set (match_operand:SI 1 "register_operand" "=r,r")
1917 
                         (match_operand:SI 2 "s_operand" "Q,S"))])]
1918 
  "reload_completed"
1919 
{
1920 
  int words = XVECLEN (operands[0], 0);
1921 
  operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1922 
  return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1923 
}
1924 
   [(set_attr "op_type" "RS,RSY")
1925 
    (set_attr "type"    "lm")])
1926 
 
1927 
;
1928 
; store multiple pattern(s).
1929 
;
1930 
 
1931 
(define_expand "store_multiple"
1932 
  [(match_par_dup 3 [(set (match_operand 0 "" "")
1933 
                          (match_operand 1 "" ""))
1934 
                     (use (match_operand 2 "" ""))])]
1935 
  "reload_completed"
1936 
{
1937 
  enum machine_mode mode;
1938 
  int regno;
1939 
  int count;
1940 
  rtx to;
1941 
  int i, off;
1942 
 
1943 
  /* Support only storing a constant number of fixed-point registers to
1944 
     memory and only bother with this if more than two.  */
1945 
  if (GET_CODE (operands[2]) != CONST_INT
1946 
      || INTVAL (operands[2]) < 2
1947 
      || INTVAL (operands[2]) > 16
1948 
      || GET_CODE (operands[0]) != MEM
1949 
      || GET_CODE (operands[1]) != REG
1950 
      || REGNO (operands[1]) >= 16)
1951 
    FAIL;
1952 
 
1953 
  count = INTVAL (operands[2]);
1954 
  regno = REGNO (operands[1]);
1955 
  mode = GET_MODE (operands[1]);
1956 
  if (mode != SImode && mode != word_mode)
1957 
    FAIL;
1958 
 
1959 
  operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1960 
 
1961 
  if (no_new_pseudos)
1962 
    {
1963 
      if (GET_CODE (XEXP (operands[0], 0)) == REG)
1964 
        {
1965 
          to = XEXP (operands[0], 0);
1966 
          off = 0;
1967 
        }
1968 
      else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1969 
               && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1970 
               && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1971 
        {
1972 
          to = XEXP (XEXP (operands[0], 0), 0);
1973 
          off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1974 
        }
1975 
      else
1976 
        FAIL;
1977 
    }
1978 
  else
1979 
    {
1980 
      to = force_reg (Pmode, XEXP (operands[0], 0));
1981 
      off = 0;
1982 
    }
1983 
 
1984 
  for (i = 0; i < count; i++)
1985 
    XVECEXP (operands[3], 0, i)
1986 
      = gen_rtx_SET (VOIDmode,
1987 
                     change_address (operands[0], mode,
1988 
                       plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1989 
                     gen_rtx_REG (mode, regno + i));
1990 
})
1991 
 
1992 
(define_insn "*store_multiple_di"
1993 
  [(match_parallel 0 "store_multiple_operation"
1994 
                   [(set (match_operand:DI 1 "s_operand" "=QS")
1995 
                         (match_operand:DI 2 "register_operand" "r"))])]
1996 
  "reload_completed && word_mode == DImode"
1997 
{
1998 
  int words = XVECLEN (operands[0], 0);
1999 
  operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2000 
  return "stmg\t%2,%0,%S1";
2001 
}
2002 
   [(set_attr "op_type" "RSY")
2003 
    (set_attr "type"    "stm")])
2004 
 
2005 
 
2006 
(define_insn "*store_multiple_si"
2007 
  [(match_parallel 0 "store_multiple_operation"
2008 
                   [(set (match_operand:SI 1 "s_operand" "=Q,S")
2009 
                         (match_operand:SI 2 "register_operand" "r,r"))])]
2010 
  "reload_completed"
2011 
{
2012 
  int words = XVECLEN (operands[0], 0);
2013 
  operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2014 
  return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2015 
}
2016 
   [(set_attr "op_type" "RS,RSY")
2017 
    (set_attr "type"    "stm")])
2018 
 
2019 
;;
2020 
;; String instructions.
2021 
;;
2022 
 
2023 
(define_insn "*execute"
2024 
  [(match_parallel 0 ""
2025 
    [(unspec [(match_operand 1 "register_operand" "a")
2026 
              (match_operand:BLK 2 "memory_operand" "R")
2027 
              (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2028 
  "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2029 
   && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2030 
  "ex\t%1,%2"
2031 
  [(set_attr "op_type" "RX")
2032 
   (set_attr "type" "cs")])
2033 
 
2034 
 
2035 
;
2036 
; strlenM instruction pattern(s).
2037 
;
2038 
 
2039 
(define_expand "strlen"
2040 
  [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2041 
   (parallel
2042 
    [(set (match_dup 4)
2043 
          (unspec:P [(const_int 0)
2044 
                      (match_operand:BLK 1 "memory_operand" "")
2045 
                      (reg:SI 0)
2046 
                      (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2047 
     (clobber (scratch:P))
2048 
     (clobber (reg:CC CC_REGNUM))])
2049 
   (parallel
2050 
    [(set (match_operand:P 0 "register_operand" "")
2051 
          (minus:P (match_dup 4) (match_dup 5)))
2052 
     (clobber (reg:CC CC_REGNUM))])]
2053 
  ""
2054 
{
2055 
  operands[4] = gen_reg_rtx (Pmode);
2056 
  operands[5] = gen_reg_rtx (Pmode);
2057 
  emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2058 
  operands[1] = replace_equiv_address (operands[1], operands[5]);
2059 
})
2060 
 
2061 
(define_insn "*strlen"
2062 
  [(set (match_operand:P 0 "register_operand" "=a")
2063 
        (unspec:P [(match_operand:P 2 "general_operand" "0")
2064 
                    (mem:BLK (match_operand:P 3 "register_operand" "1"))
2065 
                    (reg:SI 0)
2066 
                    (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2067 
   (clobber (match_scratch:P 1 "=a"))
2068 
   (clobber (reg:CC CC_REGNUM))]
2069 
  ""
2070 
  "srst\t%0,%1\;jo\t.-4"
2071 
  [(set_attr "length" "8")
2072 
   (set_attr "type" "vs")])
2073 
 
2074 
;
2075 
; cmpstrM instruction pattern(s).
2076 
;
2077 
 
2078 
(define_expand "cmpstrsi"
2079 
  [(set (reg:SI 0) (const_int 0))
2080 
   (parallel
2081 
    [(clobber (match_operand 3 "" ""))
2082 
     (clobber (match_dup 4))
2083 
     (set (reg:CCU CC_REGNUM)
2084 
          (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2085 
                       (match_operand:BLK 2 "memory_operand" "")))
2086 
     (use (reg:SI 0))])
2087 
   (parallel
2088 
    [(set (match_operand:SI 0 "register_operand" "=d")
2089 
          (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
2090 
     (clobber (reg:CC CC_REGNUM))])]
2091 
  ""
2092 
{
2093 
  /* As the result of CMPINT is inverted compared to what we need,
2094 
     we have to swap the operands.  */
2095 
  rtx op1 = operands[2];
2096 
  rtx op2 = operands[1];
2097 
  rtx addr1 = gen_reg_rtx (Pmode);
2098 
  rtx addr2 = gen_reg_rtx (Pmode);
2099 
 
2100 
  emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2101 
  emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2102 
  operands[1] = replace_equiv_address_nv (op1, addr1);
2103 
  operands[2] = replace_equiv_address_nv (op2, addr2);
2104 
  operands[3] = addr1;
2105 
  operands[4] = addr2;
2106 
})
2107 
 
2108 
(define_insn "*cmpstr"
2109 
  [(clobber (match_operand:P 0 "register_operand" "=d"))
2110 
   (clobber (match_operand:P 1 "register_operand" "=d"))
2111 
   (set (reg:CCU CC_REGNUM)
2112 
        (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2113 
                     (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2114 
   (use (reg:SI 0))]
2115 
  ""
2116 
  "clst\t%0,%1\;jo\t.-4"
2117 
  [(set_attr "length" "8")
2118 
   (set_attr "type" "vs")])
2119 
 
2120 
;
2121 
; movstr instruction pattern.
2122 
;
2123 
 
2124 
(define_expand "movstr"
2125 
  [(set (reg:SI 0) (const_int 0))
2126 
   (parallel
2127 
    [(clobber (match_dup 3))
2128 
     (set (match_operand:BLK 1 "memory_operand" "")
2129 
          (match_operand:BLK 2 "memory_operand" ""))
2130 
     (set (match_operand 0 "register_operand" "")
2131 
          (unspec [(match_dup 1)
2132 
                   (match_dup 2)
2133 
                   (reg:SI 0)] UNSPEC_MVST))
2134 
     (clobber (reg:CC CC_REGNUM))])]
2135 
  ""
2136 
{
2137 
  rtx addr1 = gen_reg_rtx (Pmode);
2138 
  rtx addr2 = gen_reg_rtx (Pmode);
2139 
 
2140 
  emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2141 
  emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2142 
  operands[1] = replace_equiv_address_nv (operands[1], addr1);
2143 
  operands[2] = replace_equiv_address_nv (operands[2], addr2);
2144 
  operands[3] = addr2;
2145 
})
2146 
 
2147 
(define_insn "*movstr"
2148 
  [(clobber (match_operand:P 2 "register_operand" "=d"))
2149 
   (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2150 
        (mem:BLK (match_operand:P 3 "register_operand" "2")))
2151 
   (set (match_operand:P 0 "register_operand" "=d")
2152 
        (unspec [(mem:BLK (match_dup 1))
2153 
                 (mem:BLK (match_dup 3))
2154 
                 (reg:SI 0)] UNSPEC_MVST))
2155 
   (clobber (reg:CC CC_REGNUM))]
2156 
  ""
2157 
  "mvst\t%1,%2\;jo\t.-4"
2158 
  [(set_attr "length" "8")
2159 
   (set_attr "type" "vs")])
2160 
 
2161 
 
2162 
;
2163 
; movmemM instruction pattern(s).
2164 
;
2165 
 
2166 
(define_expand "movmem"
2167 
  [(set (match_operand:BLK 0 "memory_operand" "")
2168 
        (match_operand:BLK 1 "memory_operand" ""))
2169 
   (use (match_operand:GPR 2 "general_operand" ""))
2170 
   (match_operand 3 "" "")]
2171 
  ""
2172 
  "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2173 
 
2174 
; Move a block that is up to 256 bytes in length.
2175 
; The block length is taken as (operands[2] % 256) + 1.
2176 
 
2177 
(define_expand "movmem_short"
2178 
  [(parallel
2179 
    [(set (match_operand:BLK 0 "memory_operand" "")
2180 
          (match_operand:BLK 1 "memory_operand" ""))
2181 
     (use (match_operand 2 "nonmemory_operand" ""))
2182 
     (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2183 
     (clobber (match_dup 3))])]
2184 
  ""
2185 
  "operands[3] = gen_rtx_SCRATCH (Pmode);")
2186 
 
2187 
(define_insn "*movmem_short"
2188 
  [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2189 
        (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2190 
   (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2191 
   (use (match_operand 3 "immediate_operand" "X,R,X"))
2192 
   (clobber (match_scratch 4 "=X,X,&a"))]
2193 
  "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2194 
   && GET_MODE (operands[4]) == Pmode"
2195 
  "#"
2196 
  [(set_attr "type" "cs")])
2197 
 
2198 
(define_split
2199 
  [(set (match_operand:BLK 0 "memory_operand" "")
2200 
        (match_operand:BLK 1 "memory_operand" ""))
2201 
   (use (match_operand 2 "const_int_operand" ""))
2202 
   (use (match_operand 3 "immediate_operand" ""))
2203 
   (clobber (scratch))]
2204 
  "reload_completed"
2205 
  [(parallel
2206 
    [(set (match_dup 0) (match_dup 1))
2207 
     (use (match_dup 2))])]
2208 
  "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2209 
 
2210 
(define_split
2211 
  [(set (match_operand:BLK 0 "memory_operand" "")
2212 
        (match_operand:BLK 1 "memory_operand" ""))
2213 
   (use (match_operand 2 "register_operand" ""))
2214 
   (use (match_operand 3 "memory_operand" ""))
2215 
   (clobber (scratch))]
2216 
  "reload_completed"
2217 
  [(parallel
2218 
    [(unspec [(match_dup 2) (match_dup 3)
2219 
              (const_int 0)] UNSPEC_EXECUTE)
2220 
     (set (match_dup 0) (match_dup 1))
2221 
     (use (const_int 1))])]
2222 
  "")
2223 
 
2224 
(define_split
2225 
  [(set (match_operand:BLK 0 "memory_operand" "")
2226 
        (match_operand:BLK 1 "memory_operand" ""))
2227 
   (use (match_operand 2 "register_operand" ""))
2228 
   (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2229 
   (clobber (match_operand 3 "register_operand" ""))]
2230 
  "reload_completed && TARGET_CPU_ZARCH"
2231 
  [(set (match_dup 3) (label_ref (match_dup 4)))
2232 
   (parallel
2233 
    [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2234 
              (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2235 
     (set (match_dup 0) (match_dup 1))
2236 
     (use (const_int 1))])]
2237 
  "operands[4] = gen_label_rtx ();")
2238 
 
2239 
; Move a block of arbitrary length.
2240 
 
2241 
(define_expand "movmem_long"
2242 
  [(parallel
2243 
    [(clobber (match_dup 2))
2244 
     (clobber (match_dup 3))
2245 
     (set (match_operand:BLK 0 "memory_operand" "")
2246 
          (match_operand:BLK 1 "memory_operand" ""))
2247 
     (use (match_operand 2 "general_operand" ""))
2248 
     (use (match_dup 3))
2249 
     (clobber (reg:CC CC_REGNUM))])]
2250 
  ""
2251 
{
2252 
  enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2253 
  rtx reg0 = gen_reg_rtx (dword_mode);
2254 
  rtx reg1 = gen_reg_rtx (dword_mode);
2255 
  rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2256 
  rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2257 
  rtx len0 = gen_lowpart (Pmode, reg0);
2258 
  rtx len1 = gen_lowpart (Pmode, reg1);
2259 
 
2260 
  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2261 
  emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2262 
  emit_move_insn (len0, operands[2]);
2263 
 
2264 
  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2265 
  emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2266 
  emit_move_insn (len1, operands[2]);
2267 
 
2268 
  operands[0] = replace_equiv_address_nv (operands[0], addr0);
2269 
  operands[1] = replace_equiv_address_nv (operands[1], addr1);
2270 
  operands[2] = reg0;
2271 
  operands[3] = reg1;
2272 
})
2273 
 
2274 
(define_insn "*movmem_long"
2275 
  [(clobber (match_operand: 0 "register_operand" "=d"))
2276 
   (clobber (match_operand: 1 "register_operand" "=d"))
2277 
   (set (mem:BLK (subreg:P (match_operand: 2 "register_operand" "0") 0))
2278 
        (mem:BLK (subreg:P (match_operand: 3 "register_operand" "1") 0)))
2279 
   (use (match_dup 2))
2280 
   (use (match_dup 3))
2281 
   (clobber (reg:CC CC_REGNUM))]
2282 
  ""
2283 
  "mvcle\t%0,%1,0\;jo\t.-4"
2284 
  [(set_attr "length" "8")
2285 
   (set_attr "type" "vs")])
2286 
 
2287 
;
2288 
; setmemM instruction pattern(s).
2289 
;
2290 
 
2291 
(define_expand "setmem"
2292 
  [(set (match_operand:BLK 0 "memory_operand" "")
2293 
        (match_operand:QI 2 "general_operand" ""))
2294 
   (use (match_operand:GPR 1 "general_operand" ""))
2295 
   (match_operand 3 "" "")]
2296 
  ""
2297 
  "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2298 
 
2299 
; Clear a block that is up to 256 bytes in length.
2300 
; The block length is taken as (operands[1] % 256) + 1.
2301 
 
2302 
(define_expand "clrmem_short"
2303 
  [(parallel
2304 
    [(set (match_operand:BLK 0 "memory_operand" "")
2305 
          (const_int 0))
2306 
     (use (match_operand 1 "nonmemory_operand" ""))
2307 
     (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2308 
     (clobber (match_dup 2))
2309 
     (clobber (reg:CC CC_REGNUM))])]
2310 
  ""
2311 
  "operands[2] = gen_rtx_SCRATCH (Pmode);")
2312 
 
2313 
(define_insn "*clrmem_short"
2314 
  [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2315 
        (const_int 0))
2316 
   (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2317 
   (use (match_operand 2 "immediate_operand" "X,R,X"))
2318 
   (clobber (match_scratch 3 "=X,X,&a"))
2319 
   (clobber (reg:CC CC_REGNUM))]
2320 
  "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2321 
   && GET_MODE (operands[3]) == Pmode"
2322 
  "#"
2323 
  [(set_attr "type" "cs")])
2324 
 
2325 
(define_split
2326 
  [(set (match_operand:BLK 0 "memory_operand" "")
2327 
        (const_int 0))
2328 
   (use (match_operand 1 "const_int_operand" ""))
2329 
   (use (match_operand 2 "immediate_operand" ""))
2330 
   (clobber (scratch))
2331 
   (clobber (reg:CC CC_REGNUM))]
2332 
  "reload_completed"
2333 
  [(parallel
2334 
    [(set (match_dup 0) (const_int 0))
2335 
     (use (match_dup 1))
2336 
     (clobber (reg:CC CC_REGNUM))])]
2337 
  "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2338 
 
2339 
(define_split
2340 
  [(set (match_operand:BLK 0 "memory_operand" "")
2341 
        (const_int 0))
2342 
   (use (match_operand 1 "register_operand" ""))
2343 
   (use (match_operand 2 "memory_operand" ""))
2344 
   (clobber (scratch))
2345 
   (clobber (reg:CC CC_REGNUM))]
2346 
  "reload_completed"
2347 
  [(parallel
2348 
    [(unspec [(match_dup 1) (match_dup 2)
2349 
              (const_int 0)] UNSPEC_EXECUTE)
2350 
     (set (match_dup 0) (const_int 0))
2351 
     (use (const_int 1))
2352 
     (clobber (reg:CC CC_REGNUM))])]
2353 
  "")
2354 
 
2355 
(define_split
2356 
  [(set (match_operand:BLK 0 "memory_operand" "")
2357 
        (const_int 0))
2358 
   (use (match_operand 1 "register_operand" ""))
2359 
   (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2360 
   (clobber (match_operand 2 "register_operand" ""))
2361 
   (clobber (reg:CC CC_REGNUM))]
2362 
  "reload_completed && TARGET_CPU_ZARCH"
2363 
  [(set (match_dup 2) (label_ref (match_dup 3)))
2364 
   (parallel
2365 
    [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2366 
              (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2367 
     (set (match_dup 0) (const_int 0))
2368 
     (use (const_int 1))
2369 
     (clobber (reg:CC CC_REGNUM))])]
2370 
  "operands[3] = gen_label_rtx ();")
2371 
 
2372 
; Initialize a block of arbitrary length with (operands[2] % 256).
2373 
 
2374 
(define_expand "setmem_long"
2375 
  [(parallel
2376 
    [(clobber (match_dup 1))
2377 
     (set (match_operand:BLK 0 "memory_operand" "")
2378 
          (match_operand 2 "shift_count_or_setmem_operand" ""))
2379 
     (use (match_operand 1 "general_operand" ""))
2380 
     (use (match_dup 3))
2381 
     (clobber (reg:CC CC_REGNUM))])]
2382 
  ""
2383 
{
2384 
  enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2385 
  rtx reg0 = gen_reg_rtx (dword_mode);
2386 
  rtx reg1 = gen_reg_rtx (dword_mode);
2387 
  rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2388 
  rtx len0 = gen_lowpart (Pmode, reg0);
2389 
 
2390 
  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2391 
  emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2392 
  emit_move_insn (len0, operands[1]);
2393 
 
2394 
  emit_move_insn (reg1, const0_rtx);
2395 
 
2396 
  operands[0] = replace_equiv_address_nv (operands[0], addr0);
2397 
  operands[1] = reg0;
2398 
  operands[3] = reg1;
2399 
})
2400 
 
2401 
(define_insn "*setmem_long"
2402 
  [(clobber (match_operand: 0 "register_operand" "=d"))
2403 
   (set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0))
2404 
        (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2405 
   (use (match_dup 3))
2406 
   (use (match_operand: 1 "register_operand" "d"))
2407 
   (clobber (reg:CC CC_REGNUM))]
2408 
  ""
2409 
  "mvcle\t%0,%1,%Y2\;jo\t.-4"
2410 
  [(set_attr "length" "8")
2411 
   (set_attr "type" "vs")])
2412 
 
2413 
(define_insn "*setmem_long_and"
2414 
  [(clobber (match_operand: 0 "register_operand" "=d"))
2415 
   (set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0))
2416 
        (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2417 
             (match_operand 4 "const_int_operand"             "n")))
2418 
   (use (match_dup 3))
2419 
   (use (match_operand: 1 "register_operand" "d"))
2420 
   (clobber (reg:CC CC_REGNUM))]
2421 
  "(INTVAL (operands[4]) & 255) == 255"
2422 
  "mvcle\t%0,%1,%Y2\;jo\t.-4"
2423 
  [(set_attr "length" "8")
2424 
   (set_attr "type" "vs")])
2425 
;
2426 
; cmpmemM instruction pattern(s).
2427 
;
2428 
 
2429 
(define_expand "cmpmemsi"
2430 
  [(set (match_operand:SI 0 "register_operand" "")
2431 
        (compare:SI (match_operand:BLK 1 "memory_operand" "")
2432 
                    (match_operand:BLK 2 "memory_operand" "") ) )
2433 
   (use (match_operand:SI 3 "general_operand" ""))
2434 
   (use (match_operand:SI 4 "" ""))]
2435 
  ""
2436 
  "s390_expand_cmpmem (operands[0], operands[1],
2437 
                       operands[2], operands[3]); DONE;")
2438 
 
2439 
; Compare a block that is up to 256 bytes in length.
2440 
; The block length is taken as (operands[2] % 256) + 1.
2441 
 
2442 
(define_expand "cmpmem_short"
2443 
  [(parallel
2444 
    [(set (reg:CCU CC_REGNUM)
2445 
          (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2446 
                       (match_operand:BLK 1 "memory_operand" "")))
2447 
     (use (match_operand 2 "nonmemory_operand" ""))
2448 
     (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2449 
     (clobber (match_dup 3))])]
2450 
  ""
2451 
  "operands[3] = gen_rtx_SCRATCH (Pmode);")
2452 
 
2453 
(define_insn "*cmpmem_short"
2454 
  [(set (reg:CCU CC_REGNUM)
2455 
        (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2456 
                     (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2457 
   (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2458 
   (use (match_operand 3 "immediate_operand" "X,R,X"))
2459 
   (clobber (match_scratch 4 "=X,X,&a"))]
2460 
  "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2461 
   && GET_MODE (operands[4]) == Pmode"
2462 
  "#"
2463 
  [(set_attr "type" "cs")])
2464 
 
2465 
(define_split
2466 
  [(set (reg:CCU CC_REGNUM)
2467 
        (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2468 
                     (match_operand:BLK 1 "memory_operand" "")))
2469 
   (use (match_operand 2 "const_int_operand" ""))
2470 
   (use (match_operand 3 "immediate_operand" ""))
2471 
   (clobber (scratch))]
2472 
  "reload_completed"
2473 
  [(parallel
2474 
    [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2475 
     (use (match_dup 2))])]
2476 
  "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2477 
 
2478 
(define_split
2479 
  [(set (reg:CCU CC_REGNUM)
2480 
        (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2481 
                     (match_operand:BLK 1 "memory_operand" "")))
2482 
   (use (match_operand 2 "register_operand" ""))
2483 
   (use (match_operand 3 "memory_operand" ""))
2484 
   (clobber (scratch))]
2485 
  "reload_completed"
2486 
  [(parallel
2487 
    [(unspec [(match_dup 2) (match_dup 3)
2488 
              (const_int 0)] UNSPEC_EXECUTE)
2489 
     (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2490 
     (use (const_int 1))])]
2491 
  "")
2492 
 
2493 
(define_split
2494 
  [(set (reg:CCU CC_REGNUM)
2495 
        (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2496 
                     (match_operand:BLK 1 "memory_operand" "")))
2497 
   (use (match_operand 2 "register_operand" ""))
2498 
   (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2499 
   (clobber (match_operand 3 "register_operand" ""))]
2500 
  "reload_completed && TARGET_CPU_ZARCH"
2501 
  [(set (match_dup 3) (label_ref (match_dup 4)))
2502 
   (parallel
2503 
    [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2504 
              (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2505 
     (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2506 
     (use (const_int 1))])]
2507 
  "operands[4] = gen_label_rtx ();")
2508 
 
2509 
; Compare a block of arbitrary length.
2510 
 
2511 
(define_expand "cmpmem_long"
2512 
  [(parallel
2513 
    [(clobber (match_dup 2))
2514 
     (clobber (match_dup 3))
2515 
     (set (reg:CCU CC_REGNUM)
2516 
          (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2517 
                       (match_operand:BLK 1 "memory_operand" "")))
2518 
     (use (match_operand 2 "general_operand" ""))
2519 
     (use (match_dup 3))])]
2520 
  ""
2521 
{
2522 
  enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2523 
  rtx reg0 = gen_reg_rtx (dword_mode);
2524 
  rtx reg1 = gen_reg_rtx (dword_mode);
2525 
  rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2526 
  rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2527 
  rtx len0 = gen_lowpart (Pmode, reg0);
2528 
  rtx len1 = gen_lowpart (Pmode, reg1);
2529 
 
2530 
  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2531 
  emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2532 
  emit_move_insn (len0, operands[2]);
2533 
 
2534 
  emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2535 
  emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2536 
  emit_move_insn (len1, operands[2]);
2537 
 
2538 
  operands[0] = replace_equiv_address_nv (operands[0], addr0);
2539 
  operands[1] = replace_equiv_address_nv (operands[1], addr1);
2540 
  operands[2] = reg0;
2541 
  operands[3] = reg1;
2542 
})
2543 
 
2544 
(define_insn "*cmpmem_long"
2545 
  [(clobber (match_operand: 0 "register_operand" "=d"))
2546 
   (clobber (match_operand: 1 "register_operand" "=d"))
2547 
   (set (reg:CCU CC_REGNUM)
2548 
        (compare:CCU (mem:BLK (subreg:P (match_operand: 2 "register_operand" "0") 0))
2549 
                     (mem:BLK (subreg:P (match_operand: 3 "register_operand" "1") 0))))
2550 
   (use (match_dup 2))
2551 
   (use (match_dup 3))]
2552 
  ""
2553 
  "clcle\t%0,%1,0\;jo\t.-4"
2554 
  [(set_attr "length" "8")
2555 
   (set_attr "type" "vs")])
2556 
 
2557 
; Convert CCUmode condition code to integer.
2558 
; Result is zero if EQ, positive if LTU, negative if GTU.
2559 
 
2560 
(define_insn_and_split "cmpint"
2561 
  [(set (match_operand:SI 0 "register_operand" "=d")
2562 
        (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2563 
                   UNSPEC_CMPINT))
2564 
   (clobber (reg:CC CC_REGNUM))]
2565 
  ""
2566 
  "#"
2567 
  "reload_completed"
2568 
  [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2569 
   (parallel
2570 
    [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2571 
     (clobber (reg:CC CC_REGNUM))])])
2572 
 
2573 
(define_insn_and_split "*cmpint_cc"
2574 
  [(set (reg CC_REGNUM)
2575 
        (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2576 
                            UNSPEC_CMPINT)
2577 
                 (const_int 0)))
2578 
   (set (match_operand:SI 0 "register_operand" "=d")
2579 
        (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2580 
  "s390_match_ccmode (insn, CCSmode)"
2581 
  "#"
2582 
  "&& reload_completed"
2583 
  [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2584 
   (parallel
2585 
    [(set (match_dup 2) (match_dup 3))
2586 
     (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2587 
{
2588 
  rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2589 
  operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2590 
  operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2591 
})
2592 
 
2593 
(define_insn_and_split "*cmpint_sign"
2594 
  [(set (match_operand:DI 0 "register_operand" "=d")
2595 
        (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2596 
                                   UNSPEC_CMPINT)))
2597 
   (clobber (reg:CC CC_REGNUM))]
2598 
  "TARGET_64BIT"
2599 
  "#"
2600 
  "&& reload_completed"
2601 
  [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2602 
   (parallel
2603 
    [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2604 
     (clobber (reg:CC CC_REGNUM))])])
2605 
 
2606 
(define_insn_and_split "*cmpint_sign_cc"
2607 
  [(set (reg CC_REGNUM)
2608 
        (compare (ashiftrt:DI (ashift:DI (subreg:DI
2609 
                   (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2610 
                              UNSPEC_CMPINT) 0)
2611 
                   (const_int 32)) (const_int 32))
2612 
                 (const_int 0)))
2613 
   (set (match_operand:DI 0 "register_operand" "=d")
2614 
        (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2615 
  "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2616 
  "#"
2617 
  "&& reload_completed"
2618 
  [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2619 
   (parallel
2620 
    [(set (match_dup 2) (match_dup 3))
2621 
     (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2622 
{
2623 
  rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2624 
  operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2625 
  operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2626 
})
2627 
 
2628 
 
2629 
;;
2630 
;;- Conversion instructions.
2631 
;;
2632 
 
2633 
(define_insn "*sethighpartsi"
2634 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
2635 
        (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2636 
                    (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2637 
   (clobber (reg:CC CC_REGNUM))]
2638 
  ""
2639 
  "@
2640 
   icm\t%0,%2,%S1
2641 
   icmy\t%0,%2,%S1"
2642 
  [(set_attr "op_type" "RS,RSY")])
2643 
 
2644 
(define_insn "*sethighpartdi_64"
2645 
  [(set (match_operand:DI 0 "register_operand" "=d")
2646 
        (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2647 
                    (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2648 
   (clobber (reg:CC CC_REGNUM))]
2649 
  "TARGET_64BIT"
2650 
  "icmh\t%0,%2,%S1"
2651 
  [(set_attr "op_type" "RSY")])
2652 
 
2653 
(define_insn "*sethighpartdi_31"
2654 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
2655 
        (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2656 
                    (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2657 
   (clobber (reg:CC CC_REGNUM))]
2658 
  "!TARGET_64BIT"
2659 
  "@
2660 
   icm\t%0,%2,%S1
2661 
   icmy\t%0,%2,%S1"
2662 
  [(set_attr "op_type" "RS,RSY")])
2663 
 
2664 
(define_insn_and_split "*extzv"
2665 
  [(set (match_operand:GPR 0 "register_operand" "=d")
2666 
        (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2667 
                          (match_operand 2 "const_int_operand" "n")
2668 
                          (const_int 0)))
2669 
   (clobber (reg:CC CC_REGNUM))]
2670 
  "INTVAL (operands[2]) > 0
2671 
   && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2672 
  "#"
2673 
  "&& reload_completed"
2674 
  [(parallel
2675 
    [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2676 
     (clobber (reg:CC CC_REGNUM))])
2677 
   (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2678 
{
2679 
  int bitsize = INTVAL (operands[2]);
2680 
  int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2681 
  int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2682 
 
2683 
  operands[1] = adjust_address (operands[1], BLKmode, 0);
2684 
  set_mem_size (operands[1], GEN_INT (size));
2685 
  operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) - bitsize);
2686 
  operands[3] = GEN_INT (mask);
2687 
})
2688 
 
2689 
(define_insn_and_split "*extv"
2690 
  [(set (match_operand:GPR 0 "register_operand" "=d")
2691 
        (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2692 
                          (match_operand 2 "const_int_operand" "n")
2693 
                          (const_int 0)))
2694 
   (clobber (reg:CC CC_REGNUM))]
2695 
  "INTVAL (operands[2]) > 0
2696 
   && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2697 
  "#"
2698 
  "&& reload_completed"
2699 
  [(parallel
2700 
    [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2701 
     (clobber (reg:CC CC_REGNUM))])
2702 
   (parallel
2703 
    [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2704 
     (clobber (reg:CC CC_REGNUM))])]
2705 
{
2706 
  int bitsize = INTVAL (operands[2]);
2707 
  int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2708 
  int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2709 
 
2710 
  operands[1] = adjust_address (operands[1], BLKmode, 0);
2711 
  set_mem_size (operands[1], GEN_INT (size));
2712 
  operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) - bitsize);
2713 
  operands[3] = GEN_INT (mask);
2714 
})
2715 
 
2716 
;
2717 
; insv instruction patterns
2718 
;
2719 
 
2720 
(define_expand "insv"
2721 
  [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2722 
                      (match_operand 1 "const_int_operand" "")
2723 
                      (match_operand 2 "const_int_operand" ""))
2724 
        (match_operand 3 "general_operand" ""))]
2725 
  ""
2726 
{
2727 
  if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2728 
    DONE;
2729 
  FAIL;
2730 
})
2731 
 
2732 
(define_insn "*insv_mem_reg"
2733 
  [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2734 
                        (match_operand 1 "const_int_operand" "n,n")
2735 
                        (const_int 0))
2736 
        (match_operand:P 2 "register_operand" "d,d"))]
2737 
  "INTVAL (operands[1]) > 0
2738 
   && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2739 
   && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2740 
{
2741 
    int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2742 
 
2743 
    operands[1] = GEN_INT ((1ul << size) - 1);
2744 
    return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2745 
                                    : "stcmy\t%2,%1,%S0";
2746 
}
2747 
  [(set_attr "op_type" "RS,RSY")])
2748 
 
2749 
(define_insn "*insvdi_mem_reghigh"
2750 
  [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2751 
                         (match_operand 1 "const_int_operand" "n")
2752 
                         (const_int 0))
2753 
        (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2754 
                     (const_int 32)))]
2755 
  "TARGET_64BIT
2756 
   && INTVAL (operands[1]) > 0
2757 
   && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2758 
   && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2759 
{
2760 
    int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2761 
 
2762 
    operands[1] = GEN_INT ((1ul << size) - 1);
2763 
    return "stcmh\t%2,%1,%S0";
2764 
}
2765 
[(set_attr "op_type" "RSY")])
2766 
 
2767 
(define_insn "*insv_reg_imm"
2768 
  [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2769 
                        (const_int 16)
2770 
                        (match_operand 1 "const_int_operand" "n"))
2771 
        (match_operand 2 "const_int_operand" "n"))]
2772 
  "TARGET_ZARCH
2773 
   && INTVAL (operands[1]) >= 0
2774 
   && INTVAL (operands[1]) < BITS_PER_WORD
2775 
   && INTVAL (operands[1]) % 16 == 0"
2776 
{
2777 
  switch (BITS_PER_WORD - INTVAL (operands[1]))
2778 
    {
2779 
      case 64: return "iihh\t%0,%x2"; break;
2780 
      case 48: return "iihl\t%0,%x2"; break;
2781 
      case 32: return "iilh\t%0,%x2"; break;
2782 
      case 16: return "iill\t%0,%x2"; break;
2783 
      default: gcc_unreachable();
2784 
    }
2785 
}
2786 
  [(set_attr "op_type" "RI")])
2787 
 
2788 
(define_insn "*insv_reg_extimm"
2789 
  [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2790 
                        (const_int 32)
2791 
                        (match_operand 1 "const_int_operand" "n"))
2792 
        (match_operand 2 "const_int_operand" "n"))]
2793 
  "TARGET_EXTIMM
2794 
   && INTVAL (operands[1]) >= 0
2795 
   && INTVAL (operands[1]) < BITS_PER_WORD
2796 
   && INTVAL (operands[1]) % 32 == 0"
2797 
{
2798 
  switch (BITS_PER_WORD - INTVAL (operands[1]))
2799 
    {
2800 
      case 64: return "iihf\t%0,%o2"; break;
2801 
      case 32: return "iilf\t%0,%o2"; break;
2802 
      default: gcc_unreachable();
2803 
    }
2804 
}
2805 
  [(set_attr "op_type" "RIL")])
2806 
 
2807 
;
2808 
; extendsidi2 instruction pattern(s).
2809 
;
2810 
 
2811 
(define_expand "extendsidi2"
2812 
  [(set (match_operand:DI 0 "register_operand" "")
2813 
        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2814 
  ""
2815 
{
2816 
  if (!TARGET_64BIT)
2817 
    {
2818 
      emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2819 
      emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2820 
      emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2821 
      emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2822 
      DONE;
2823 
    }
2824 
})
2825 
 
2826 
(define_insn "*extendsidi2"
2827 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
2828 
        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2829 
  "TARGET_64BIT"
2830 
  "@
2831 
   lgfr\t%0,%1
2832 
   lgf\t%0,%1"
2833 
  [(set_attr "op_type" "RRE,RXY")])
2834 
 
2835 
;
2836 
; extend(hi|qi)di2 instruction pattern(s).
2837 
;
2838 
 
2839 
(define_expand "extenddi2"
2840 
  [(set (match_operand:DI 0 "register_operand" "")
2841 
        (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2842 
  ""
2843 
{
2844 
  if (!TARGET_64BIT)
2845 
    {
2846 
      rtx tmp = gen_reg_rtx (SImode);
2847 
      emit_insn (gen_extendsi2 (tmp, operands[1]));
2848 
      emit_insn (gen_extendsidi2 (operands[0], tmp));
2849 
      DONE;
2850 
    }
2851 
  else if (!TARGET_EXTIMM)
2852 
    {
2853 
      rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2854 
                              GET_MODE_BITSIZE (mode));
2855 
      operands[1] = gen_lowpart (DImode, operands[1]);
2856 
      emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2857 
      emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2858 
      DONE;
2859 
    }
2860 
})
2861 
 
2862 
(define_insn "*extendhidi2_extimm"
2863 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
2864 
        (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2865 
  "TARGET_64BIT && TARGET_EXTIMM"
2866 
  "@
2867 
   lghr\t%0,%1
2868 
   lgh\t%0,%1"
2869 
  [(set_attr "op_type" "RRE,RXY")])
2870 
 
2871 
(define_insn "*extendhidi2"
2872 
  [(set (match_operand:DI 0 "register_operand" "=d")
2873 
        (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2874 
  "TARGET_64BIT"
2875 
  "lgh\t%0,%1"
2876 
  [(set_attr "op_type" "RXY")])
2877 
 
2878 
(define_insn "*extendqidi2_extimm"
2879 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
2880 
        (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2881 
  "TARGET_64BIT && TARGET_EXTIMM"
2882 
  "@
2883 
   lgbr\t%0,%1
2884 
   lgb\t%0,%1"
2885 
  [(set_attr "op_type" "RRE,RXY")])
2886 
 
2887 
(define_insn "*extendqidi2"
2888 
  [(set (match_operand:DI 0 "register_operand" "=d")
2889 
        (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2890 
  "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2891 
  "lgb\t%0,%1"
2892 
  [(set_attr "op_type" "RXY")])
2893 
 
2894 
(define_insn_and_split "*extendqidi2_short_displ"
2895 
  [(set (match_operand:DI 0 "register_operand" "=d")
2896 
        (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2897 
   (clobber (reg:CC CC_REGNUM))]
2898 
  "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2899 
  "#"
2900 
  "&& reload_completed"
2901 
  [(parallel
2902 
    [(set (match_dup 0) (unspec:DI [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2903 
     (clobber (reg:CC CC_REGNUM))])
2904 
   (parallel
2905 
    [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2906 
     (clobber (reg:CC CC_REGNUM))])]
2907 
{
2908 
  operands[1] = adjust_address (operands[1], BLKmode, 0);
2909 
  set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2910 
})
2911 
 
2912 
;
2913 
; extend(hi|qi)si2 instruction pattern(s).
2914 
;
2915 
 
2916 
(define_expand "extendsi2"
2917 
  [(set (match_operand:SI 0 "register_operand" "")
2918 
        (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2919 
  ""
2920 
{
2921 
 if (!TARGET_EXTIMM)
2922 
   {
2923 
     rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2924 
                             GET_MODE_BITSIZE(mode));
2925 
     operands[1] = gen_lowpart (SImode, operands[1]);
2926 
     emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2927 
     emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2928 
     DONE;
2929 
   }
2930 
})
2931 
 
2932 
(define_insn "*extendhisi2_extimm"
2933 
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2934 
        (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2935 
  "TARGET_EXTIMM"
2936 
  "@
2937 
   lhr\t%0,%1
2938 
   lh\t%0,%1
2939 
   lhy\t%0,%1"
2940 
  [(set_attr "op_type" "RRE,RX,RXY")])
2941 
 
2942 
(define_insn "*extendhisi2"
2943 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
2944 
        (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2945 
  "!TARGET_EXTIMM"
2946 
  "@
2947 
   lh\t%0,%1
2948 
   lhy\t%0,%1"
2949 
  [(set_attr "op_type" "RX,RXY")])
2950 
 
2951 
(define_insn "*extendqisi2_extimm"
2952 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
2953 
        (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2954 
  "TARGET_EXTIMM"
2955 
  "@
2956 
   lbr\t%0,%1
2957 
   lb\t%0,%1"
2958 
  [(set_attr "op_type" "RRE,RXY")])
2959 
 
2960 
(define_insn "*extendqisi2"
2961 
  [(set (match_operand:SI 0 "register_operand" "=d")
2962 
        (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2963 
  "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM"
2964 
  "lb\t%0,%1"
2965 
  [(set_attr "op_type" "RXY")])
2966 
 
2967 
(define_insn_and_split "*extendqisi2_short_displ"
2968 
  [(set (match_operand:SI 0 "register_operand" "=d")
2969 
        (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2970 
   (clobber (reg:CC CC_REGNUM))]
2971 
  "!TARGET_LONG_DISPLACEMENT"
2972 
  "#"
2973 
  "&& reload_completed"
2974 
  [(parallel
2975 
    [(set (match_dup 0) (unspec:SI [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2976 
     (clobber (reg:CC CC_REGNUM))])
2977 
   (parallel
2978 
    [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2979 
     (clobber (reg:CC CC_REGNUM))])]
2980 
{
2981 
  operands[1] = adjust_address (operands[1], BLKmode, 0);
2982 
  set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2983 
})
2984 
 
2985 
;
2986 
; extendqihi2 instruction pattern(s).
2987 
;
2988 
 
2989 
 
2990 
;
2991 
; zero_extendsidi2 instruction pattern(s).
2992 
;
2993 
 
2994 
(define_expand "zero_extendsidi2"
2995 
  [(set (match_operand:DI 0 "register_operand" "")
2996 
        (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2997 
  ""
2998 
{
2999 
  if (!TARGET_64BIT)
3000 
    {
3001 
      emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
3002 
      emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3003 
      emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3004 
      DONE;
3005 
    }
3006 
})
3007 
 
3008 
(define_insn "*zero_extendsidi2"
3009 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
3010 
        (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
3011 
  "TARGET_64BIT"
3012 
  "@
3013 
   llgfr\t%0,%1
3014 
   llgf\t%0,%1"
3015 
  [(set_attr "op_type" "RRE,RXY")])
3016 
 
3017 
;
3018 
; zero_extend(hi|qi)di2 instruction pattern(s).
3019 
;
3020 
 
3021 
(define_expand "zero_extenddi2"
3022 
  [(set (match_operand:DI 0 "register_operand" "")
3023 
        (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3024 
  ""
3025 
{
3026 
  if (!TARGET_64BIT)
3027 
    {
3028 
      rtx tmp = gen_reg_rtx (SImode);
3029 
      emit_insn (gen_zero_extendsi2 (tmp, operands[1]));
3030 
      emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3031 
      DONE;
3032 
    }
3033 
  else if (!TARGET_EXTIMM)
3034 
    {
3035 
      rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3036 
                              GET_MODE_BITSIZE(mode));
3037 
      operands[1] = gen_lowpart (DImode, operands[1]);
3038 
      emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3039 
      emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3040 
      DONE;
3041 
    }
3042 
})
3043 
 
3044 
(define_insn "*zero_extenddi2_extimm"
3045 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
3046 
        (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
3047 
  "TARGET_64BIT && TARGET_EXTIMM"
3048 
  "@
3049 
   llgr\t%0,%1
3050 
   llg\t%0,%1"
3051 
  [(set_attr "op_type" "RRE,RXY")])
3052 
 
3053 
(define_insn "*zero_extenddi2"
3054 
  [(set (match_operand:DI 0 "register_operand" "=d")
3055 
        (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
3056 
  "TARGET_64BIT  && !TARGET_EXTIMM"
3057 
  "llg\t%0,%1"
3058 
  [(set_attr "op_type" "RXY")])
3059 
 
3060 
;
3061 
; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3062 
;
3063 
 
3064 
(define_insn "*llgt_sidi"
3065 
  [(set (match_operand:DI 0 "register_operand" "=d")
3066 
        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
3067 
                (const_int 2147483647)))]
3068 
  "TARGET_64BIT"
3069 
  "llgt\t%0,%1"
3070 
  [(set_attr "op_type"  "RXE")])
3071 
 
3072 
(define_insn_and_split "*llgt_sidi_split"
3073 
  [(set (match_operand:DI 0 "register_operand" "=d")
3074 
        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
3075 
                (const_int 2147483647)))
3076 
   (clobber (reg:CC CC_REGNUM))]
3077 
  "TARGET_64BIT"
3078 
  "#"
3079 
  "&& reload_completed"
3080 
  [(set (match_dup 0)
3081 
        (and:DI (subreg:DI (match_dup 1) 0)
3082 
                (const_int 2147483647)))]
3083 
  "")
3084 
 
3085 
(define_insn "*llgt_sisi"
3086 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
3087 
        (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
3088 
                (const_int 2147483647)))]
3089 
  "TARGET_ZARCH"
3090 
  "@
3091 
   llgtr\t%0,%1
3092 
   llgt\t%0,%1"
3093 
  [(set_attr "op_type"  "RRE,RXE")])
3094 
 
3095 
(define_insn "*llgt_didi"
3096 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
3097 
        (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3098 
                (const_int 2147483647)))]
3099 
  "TARGET_64BIT"
3100 
  "@
3101 
   llgtr\t%0,%1
3102 
   llgt\t%0,%N1"
3103 
  [(set_attr "op_type"  "RRE,RXE")])
3104 
 
3105 
(define_split
3106 
  [(set (match_operand:GPR 0 "register_operand" "")
3107 
        (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3108 
                 (const_int 2147483647)))
3109 
   (clobber (reg:CC CC_REGNUM))]
3110 
  "TARGET_ZARCH && reload_completed"
3111 
  [(set (match_dup 0)
3112 
        (and:GPR (match_dup 1)
3113 
                 (const_int 2147483647)))]
3114 
  "")
3115 
 
3116 
;
3117 
; zero_extend(hi|qi)si2 instruction pattern(s).
3118 
;
3119 
 
3120 
(define_expand "zero_extendsi2"
3121 
  [(set (match_operand:SI 0 "register_operand" "")
3122 
        (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3123 
  ""
3124 
{
3125 
  if (!TARGET_EXTIMM)
3126 
    {
3127 
      operands[1] = gen_lowpart (SImode, operands[1]);
3128 
      emit_insn (gen_andsi3 (operands[0], operands[1],
3129 
                   GEN_INT ((1 << GET_MODE_BITSIZE(mode)) - 1)));
3130 
      DONE;
3131 
}
3132 
})
3133 
 
3134 
(define_insn "*zero_extendsi2_extimm"
3135 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
3136 
        (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
3137 
  "TARGET_EXTIMM"
3138 
  "@
3139 
   llr\t%0,%1
3140 
   ll\t%0,%1"
3141 
  [(set_attr "op_type" "RRE,RXY")])
3142 
 
3143 
(define_insn "*zero_extendsi2_64"
3144 
  [(set (match_operand:SI 0 "register_operand" "=d")
3145 
        (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
3146 
  "TARGET_ZARCH && !TARGET_EXTIMM"
3147 
  "llg\t%0,%1"
3148 
  [(set_attr "op_type" "RXY")])
3149 
 
3150 
(define_insn_and_split "*zero_extendhisi2_31"
3151 
  [(set (match_operand:SI 0 "register_operand" "=&d")
3152 
        (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3153 
   (clobber (reg:CC CC_REGNUM))]
3154 
  "!TARGET_ZARCH"
3155 
  "#"
3156 
  "&& reload_completed"
3157 
  [(set (match_dup 0) (const_int 0))
3158 
   (parallel
3159 
    [(set (strict_low_part (match_dup 2)) (match_dup 1))
3160 
     (clobber (reg:CC CC_REGNUM))])]
3161 
  "operands[2] = gen_lowpart (HImode, operands[0]);")
3162 
 
3163 
(define_insn_and_split "*zero_extendqisi2_31"
3164 
  [(set (match_operand:SI 0 "register_operand" "=&d")
3165 
        (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3166 
  "!TARGET_ZARCH"
3167 
  "#"
3168 
  "&& reload_completed"
3169 
  [(set (match_dup 0) (const_int 0))
3170 
   (set (strict_low_part (match_dup 2)) (match_dup 1))]
3171 
  "operands[2] = gen_lowpart (QImode, operands[0]);")
3172 
 
3173 
;
3174 
; zero_extendqihi2 instruction pattern(s).
3175 
;
3176 
 
3177 
(define_expand "zero_extendqihi2"
3178 
  [(set (match_operand:HI 0 "register_operand" "")
3179 
        (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3180 
  "TARGET_ZARCH && !TARGET_EXTIMM"
3181 
{
3182 
  operands[1] = gen_lowpart (HImode, operands[1]);
3183 
  emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3184 
  DONE;
3185 
})
3186 
 
3187 
(define_insn "*zero_extendqihi2_64"
3188 
  [(set (match_operand:HI 0 "register_operand" "=d")
3189 
        (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3190 
  "TARGET_ZARCH && !TARGET_EXTIMM"
3191 
  "llgc\t%0,%1"
3192 
  [(set_attr "op_type" "RXY")])
3193 
 
3194 
(define_insn_and_split "*zero_extendqihi2_31"
3195 
  [(set (match_operand:HI 0 "register_operand" "=&d")
3196 
        (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3197 
  "!TARGET_ZARCH"
3198 
  "#"
3199 
  "&& reload_completed"
3200 
  [(set (match_dup 0) (const_int 0))
3201 
   (set (strict_low_part (match_dup 2)) (match_dup 1))]
3202 
  "operands[2] = gen_lowpart (QImode, operands[0]);")
3203 
 
3204 
 
3205 
;
3206 
; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
3207 
;
3208 
 
3209 
(define_expand "fixuns_trunc2"
3210 
  [(set (match_operand:GPR 0 "register_operand" "")
3211 
        (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
3212 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3213 
{
3214 
  rtx label1 = gen_label_rtx ();
3215 
  rtx label2 = gen_label_rtx ();
3216 
  rtx temp = gen_reg_rtx (mode);
3217 
  REAL_VALUE_TYPE cmp, sub;
3218 
 
3219 
  operands[1] = force_reg (mode, operands[1]);
3220 
  real_2expN (&cmp, GET_MODE_BITSIZE(mode) - 1);
3221 
  real_2expN (&sub, GET_MODE_BITSIZE(mode));
3222 
 
3223 
  emit_insn (gen_cmp (operands[1],
3224 
        CONST_DOUBLE_FROM_REAL_VALUE (cmp, mode)));
3225 
  emit_jump_insn (gen_blt (label1));
3226 
  emit_insn (gen_sub3 (temp, operands[1],
3227 
        CONST_DOUBLE_FROM_REAL_VALUE (sub, mode)));
3228 
  emit_insn (gen_fix_trunc2_ieee (operands[0], temp,
3229 
        GEN_INT(7)));
3230 
  emit_jump (label2);
3231 
 
3232 
  emit_label (label1);
3233 
  emit_insn (gen_fix_trunc2_ieee (operands[0],
3234 
        operands[1], GEN_INT(5)));
3235 
  emit_label (label2);
3236 
  DONE;
3237 
})
3238 
 
3239 
(define_expand "fix_truncdi2"
3240 
  [(set (match_operand:DI 0 "register_operand" "")
3241 
        (fix:DI (match_operand:DSF 1 "nonimmediate_operand" "")))]
3242 
  "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3243 
{
3244 
  operands[1] = force_reg (mode, operands[1]);
3245 
  emit_insn (gen_fix_truncdi2_ieee (operands[0], operands[1],
3246 
      GEN_INT(5)));
3247 
  DONE;
3248 
})
3249 
 
3250 
(define_insn "fix_trunc2_ieee"
3251 
  [(set (match_operand:GPR 0 "register_operand" "=d")
3252 
        (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
3253 
   (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3254 
   (clobber (reg:CC CC_REGNUM))]
3255 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3256 
  "cbr\t%0,%h2,%1"
3257 
  [(set_attr "op_type" "RRE")
3258 
   (set_attr "type"    "ftoi")])
3259 
 
3260 
;
3261 
; fix_trunctf(si|di)2 instruction pattern(s).
3262 
;
3263 
 
3264 
(define_expand "fix_trunctf2"
3265 
  [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3266 
                   (fix:GPR (match_operand:TF 1 "register_operand" "")))
3267 
              (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3268 
              (clobber (reg:CC CC_REGNUM))])]
3269 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3270 
  "")
3271 
 
3272 
;
3273 
; fix_truncdfsi2 instruction pattern(s).
3274 
;
3275 
 
3276 
(define_expand "fix_truncdfsi2"
3277 
  [(set (match_operand:SI 0 "register_operand" "")
3278 
        (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
3279 
  "TARGET_HARD_FLOAT"
3280 
{
3281 
  if (TARGET_IBM_FLOAT)
3282 
    {
3283 
      /* This is the algorithm from POP chapter A.5.7.2.  */
3284 
 
3285 
      rtx temp   = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3286 
      rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
3287 
      rtx two32  = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
3288 
 
3289 
      operands[1] = force_reg (DFmode, operands[1]);
3290 
      emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
3291 
                                         two31r, two32, temp));
3292 
    }
3293 
  else
3294 
    {
3295 
      operands[1] = force_reg (DFmode, operands[1]);
3296 
      emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3297 
    }
3298 
 
3299 
  DONE;
3300 
})
3301 
 
3302 
(define_insn "fix_truncdfsi2_ibm"
3303 
  [(set (match_operand:SI 0 "register_operand" "=d")
3304 
        (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
3305 
   (use (match_operand:DI 2 "immediate_operand" "m"))
3306 
   (use (match_operand:DI 3 "immediate_operand" "m"))
3307 
   (use (match_operand:BLK 4 "memory_operand" "m"))
3308 
   (clobber (reg:CC CC_REGNUM))]
3309 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3310 
{
3311 
   output_asm_insn ("sd\t%1,%2", operands);
3312 
   output_asm_insn ("aw\t%1,%3", operands);
3313 
   output_asm_insn ("std\t%1,%4", operands);
3314 
   output_asm_insn ("xi\t%N4,128", operands);
3315 
   return "l\t%0,%N4";
3316 
}
3317 
  [(set_attr "length" "20")])
3318 
 
3319 
;
3320 
; fix_truncsfsi2 instruction pattern(s).
3321 
;
3322 
 
3323 
(define_expand "fix_truncsfsi2"
3324 
  [(set (match_operand:SI 0 "register_operand" "")
3325 
        (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3326 
  "TARGET_HARD_FLOAT"
3327 
{
3328 
  if (TARGET_IBM_FLOAT)
3329 
    {
3330 
      /* Convert to DFmode and then use the POP algorithm.  */
3331 
      rtx temp = gen_reg_rtx (DFmode);
3332 
      emit_insn (gen_extendsfdf2 (temp, operands[1]));
3333 
      emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3334 
    }
3335 
  else
3336 
    {
3337 
      operands[1] = force_reg (SFmode, operands[1]);
3338 
      emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3339 
    }
3340 
 
3341 
  DONE;
3342 
})
3343 
 
3344 
;
3345 
; float(si|di)(tf|df|sf)2 instruction pattern(s).
3346 
;
3347 
 
3348 
(define_insn "floatdi2"
3349 
  [(set (match_operand:FPR 0 "register_operand" "=f")
3350 
        (float:FPR (match_operand:DI 1 "register_operand" "d")))]
3351 
  "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3352 
  "cgbr\t%0,%1"
3353 
  [(set_attr "op_type" "RRE")
3354 
   (set_attr "type"    "itof" )])
3355 
 
3356 
(define_insn "floatsi2_ieee"
3357 
  [(set (match_operand:FPR 0 "register_operand" "=f")
3358 
        (float:FPR (match_operand:SI 1 "register_operand" "d")))]
3359 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3360 
  "cfbr\t%0,%1"
3361 
  [(set_attr "op_type" "RRE")
3362 
   (set_attr "type"   "itof" )])
3363 
 
3364 
 
3365 
;
3366 
; floatsi(tf|df)2 instruction pattern(s).
3367 
;
3368 
 
3369 
(define_expand "floatsitf2"
3370 
  [(set (match_operand:TF 0 "register_operand" "")
3371 
        (float:TF (match_operand:SI 1 "register_operand" "")))]
3372 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3373 
  "")
3374 
 
3375 
(define_expand "floatsidf2"
3376 
  [(set (match_operand:DF 0 "register_operand" "")
3377 
        (float:DF (match_operand:SI 1 "register_operand" "")))]
3378 
  "TARGET_HARD_FLOAT"
3379 
{
3380 
  if (TARGET_IBM_FLOAT)
3381 
    {
3382 
      /* This is the algorithm from POP chapter A.5.7.1.  */
3383 
 
3384 
      rtx temp  = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3385 
      rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3386 
 
3387 
      emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3388 
      DONE;
3389 
    }
3390 
})
3391 
 
3392 
(define_insn "floatsidf2_ibm"
3393 
  [(set (match_operand:DF 0 "register_operand" "=f")
3394 
        (float:DF (match_operand:SI 1 "register_operand" "d")))
3395 
   (use (match_operand:DI 2 "immediate_operand" "m"))
3396 
   (use (match_operand:BLK 3 "memory_operand" "m"))
3397 
   (clobber (reg:CC CC_REGNUM))]
3398 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3399 
{
3400 
   output_asm_insn ("st\t%1,%N3", operands);
3401 
   output_asm_insn ("xi\t%N3,128", operands);
3402 
   output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3403 
   output_asm_insn ("ld\t%0,%3", operands);
3404 
   return "sd\t%0,%2";
3405 
}
3406 
  [(set_attr "length" "20")])
3407 
 
3408 
;
3409 
; floatsisf2 instruction pattern(s).
3410 
;
3411 
 
3412 
(define_expand "floatsisf2"
3413 
  [(set (match_operand:SF 0 "register_operand" "")
3414 
        (float:SF (match_operand:SI 1 "register_operand" "")))]
3415 
  "TARGET_HARD_FLOAT"
3416 
{
3417 
  if (TARGET_IBM_FLOAT)
3418 
    {
3419 
      /* Use the POP algorithm to convert to DFmode and then truncate.  */
3420 
      rtx temp = gen_reg_rtx (DFmode);
3421 
      emit_insn (gen_floatsidf2 (temp, operands[1]));
3422 
      emit_insn (gen_truncdfsf2 (operands[0], temp));
3423 
      DONE;
3424 
    }
3425 
})
3426 
 
3427 
;
3428 
; truncdfsf2 instruction pattern(s).
3429 
;
3430 
 
3431 
(define_expand "truncdfsf2"
3432 
  [(set (match_operand:SF 0 "register_operand" "")
3433 
        (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3434 
  "TARGET_HARD_FLOAT"
3435 
  "")
3436 
 
3437 
(define_insn "truncdfsf2_ieee"
3438 
  [(set (match_operand:SF 0 "register_operand" "=f")
3439 
        (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3440 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3441 
  "ledbr\t%0,%1"
3442 
  [(set_attr "op_type"  "RRE")
3443 
   (set_attr "type"   "ftruncdf")])
3444 
 
3445 
(define_insn "truncdfsf2_ibm"
3446 
  [(set (match_operand:SF 0 "register_operand" "=f,f")
3447 
        (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3448 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3449 
  "@
3450 
   ler\t%0,%1
3451 
   le\t%0,%1"
3452 
  [(set_attr "op_type"  "RR,RX")
3453 
   (set_attr "type"   "floadsf")])
3454 
 
3455 
;
3456 
; trunctfdf2 instruction pattern(s).
3457 
;
3458 
 
3459 
(define_expand "trunctfdf2"
3460 
  [(parallel
3461 
    [(set (match_operand:DF 0 "register_operand" "")
3462 
          (float_truncate:DF (match_operand:TF 1 "register_operand" "")))
3463 
     (clobber (match_scratch:TF 2 "=f"))])]
3464 
  "TARGET_HARD_FLOAT"
3465 
  "")
3466 
 
3467 
(define_insn "*trunctfdf2_ieee"
3468 
  [(set (match_operand:DF 0 "register_operand" "=f")
3469 
        (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
3470 
   (clobber (match_scratch:TF 2 "=f"))]
3471 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3472 
  "ldxbr\t%2,%1\;ldr\t%0,%2"
3473 
  [(set_attr "length" "6")
3474 
   (set_attr "type"   "ftrunctf")])
3475 
 
3476 
(define_insn "*trunctfdf2_ibm"
3477 
  [(set (match_operand:DF 0 "register_operand" "=f")
3478 
        (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
3479 
   (clobber (match_scratch:TF 2 "=f"))]
3480 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3481 
  "ldxr\t%2,%1\;ldr\t%0,%2"
3482 
  [(set_attr "length"  "4")
3483 
   (set_attr "type"   "ftrunctf")])
3484 
 
3485 
;
3486 
; trunctfsf2 instruction pattern(s).
3487 
;
3488 
 
3489 
(define_expand "trunctfsf2"
3490 
  [(parallel
3491 
    [(set (match_operand:SF 0 "register_operand" "=f")
3492 
          (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3493 
     (clobber (match_scratch:TF 2 "=f"))])]
3494 
  "TARGET_HARD_FLOAT"
3495 
  "")
3496 
 
3497 
(define_insn "*trunctfsf2_ieee"
3498 
  [(set (match_operand:SF 0 "register_operand" "=f")
3499 
        (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3500 
   (clobber (match_scratch:TF 2 "=f"))]
3501 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3502 
  "lexbr\t%2,%1\;ler\t%0,%2"
3503 
  [(set_attr "length"  "6")
3504 
   (set_attr "type"   "ftrunctf")])
3505 
 
3506 
(define_insn "*trunctfsf2_ibm"
3507 
  [(set (match_operand:SF 0 "register_operand" "=f")
3508 
        (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3509 
   (clobber (match_scratch:TF 2 "=f"))]
3510 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3511 
  "lexr\t%2,%1\;ler\t%0,%2"
3512 
  [(set_attr "length"  "6")
3513 
   (set_attr "type"   "ftrunctf")])
3514 
 
3515 
;
3516 
; extendsfdf2 instruction pattern(s).
3517 
;
3518 
 
3519 
(define_expand "extendsfdf2"
3520 
  [(set (match_operand:DF 0 "register_operand" "")
3521 
        (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3522 
  "TARGET_HARD_FLOAT"
3523 
{
3524 
  if (TARGET_IBM_FLOAT)
3525 
    {
3526 
      emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3527 
      DONE;
3528 
    }
3529 
})
3530 
 
3531 
(define_insn "extendsfdf2_ieee"
3532 
  [(set (match_operand:DF 0 "register_operand" "=f,f")
3533 
        (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R")))]
3534 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3535 
  "@
3536 
   ldebr\t%0,%1
3537 
   ldeb\t%0,%1"
3538 
  [(set_attr "op_type"  "RRE,RXE")
3539 
   (set_attr "type"   "fsimpsf, floadsf")])
3540 
 
3541 
(define_insn "extendsfdf2_ibm"
3542 
  [(set (match_operand:DF 0 "register_operand" "=f,f")
3543 
        (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3544 
   (clobber (reg:CC CC_REGNUM))]
3545 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3546 
  "@
3547 
   sdr\t%0,%0\;ler\t%0,%1
3548 
   sdr\t%0,%0\;le\t%0,%1"
3549 
  [(set_attr "length"   "4,6")
3550 
   (set_attr "type"     "floadsf")])
3551 
 
3552 
;
3553 
; extenddftf2 instruction pattern(s).
3554 
;
3555 
 
3556 
(define_expand "extenddftf2"
3557 
  [(set (match_operand:TF 0 "register_operand" "")
3558 
        (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
3559 
  "TARGET_HARD_FLOAT"
3560 
  "")
3561 
 
3562 
(define_insn "*extenddftf2_ieee"
3563 
  [(set (match_operand:TF 0 "register_operand" "=f,f")
3564 
        (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3565 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3566 
  "@
3567 
   lxdbr\t%0,%1
3568 
   lxdb\t%0,%1"
3569 
  [(set_attr "op_type"  "RRE,RXE")
3570 
   (set_attr "type"   "fsimptf, floadtf")])
3571 
 
3572 
(define_insn "*extenddftf2_ibm"
3573 
  [(set (match_operand:TF 0 "register_operand" "=f,f")
3574 
        (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3575 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3576 
  "@
3577 
   lxdr\t%0,%1
3578 
   lxd\t%0,%1"
3579 
  [(set_attr "op_type"  "RRE,RXE")
3580 
   (set_attr "type"   "fsimptf, floadtf")])
3581 
 
3582 
;
3583 
; extendsftf2 instruction pattern(s).
3584 
;
3585 
 
3586 
(define_expand "extendsftf2"
3587 
  [(set (match_operand:TF 0 "register_operand" "")
3588 
        (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
3589 
  "TARGET_HARD_FLOAT"
3590 
  "")
3591 
 
3592 
(define_insn "*extendsftf2_ieee"
3593 
  [(set (match_operand:TF 0 "register_operand" "=f,f")
3594 
        (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3595 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3596 
  "@
3597 
   lxebr\t%0,%1
3598 
   lxeb\t%0,%1"
3599 
  [(set_attr "op_type"  "RRE,RXE")
3600 
   (set_attr "type"   "fsimptf, floadtf")])
3601 
 
3602 
(define_insn "*extendsftf2_ibm"
3603 
  [(set (match_operand:TF 0 "register_operand" "=f,f")
3604 
        (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3605 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3606 
  "@
3607 
   lxer\t%0,%1
3608 
   lxe\t%0,%1"
3609 
  [(set_attr "op_type"  "RRE,RXE")
3610 
   (set_attr "type"   "fsimptf, floadtf")])
3611 
 
3612 
 
3613 
;;
3614 
;; ARITHMETIC OPERATIONS
3615 
;;
3616 
;  arithmetic operations set the ConditionCode,
3617 
;  because of unpredictable Bits in Register for Halfword and Byte
3618 
;  the ConditionCode can be set wrong in operations for Halfword and Byte
3619 
 
3620 
;;
3621 
;;- Add instructions.
3622 
;;
3623 
 
3624 
;
3625 
; addti3 instruction pattern(s).
3626 
;
3627 
 
3628 
(define_insn_and_split "addti3"
3629 
  [(set (match_operand:TI 0 "register_operand" "=&d")
3630 
        (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3631 
                 (match_operand:TI 2 "general_operand" "do") ) )
3632 
   (clobber (reg:CC CC_REGNUM))]
3633 
  "TARGET_64BIT"
3634 
  "#"
3635 
  "&& reload_completed"
3636 
  [(parallel
3637 
    [(set (reg:CCL1 CC_REGNUM)
3638 
          (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3639 
                        (match_dup 7)))
3640 
     (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3641 
   (parallel
3642 
    [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3643 
                                 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3644 
     (clobber (reg:CC CC_REGNUM))])]
3645 
  "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3646 
   operands[4] = operand_subword (operands[1], 0, 0, TImode);
3647 
   operands[5] = operand_subword (operands[2], 0, 0, TImode);
3648 
   operands[6] = operand_subword (operands[0], 1, 0, TImode);
3649 
   operands[7] = operand_subword (operands[1], 1, 0, TImode);
3650 
   operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3651 
 
3652 
;
3653 
; adddi3 instruction pattern(s).
3654 
;
3655 
 
3656 
(define_insn "*adddi3_sign"
3657 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
3658 
        (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3659 
                 (match_operand:DI 1 "register_operand" "0,0")))
3660 
   (clobber (reg:CC CC_REGNUM))]
3661 
  "TARGET_64BIT"
3662 
  "@
3663 
   agfr\t%0,%2
3664 
   agf\t%0,%2"
3665 
  [(set_attr "op_type"  "RRE,RXY")])
3666 
 
3667 
(define_insn "*adddi3_zero_cc"
3668 
  [(set (reg CC_REGNUM)
3669 
        (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3670 
                          (match_operand:DI 1 "register_operand" "0,0"))
3671 
                 (const_int 0)))
3672 
   (set (match_operand:DI 0 "register_operand" "=d,d")
3673 
        (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3674 
  "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3675 
  "@
3676 
   algfr\t%0,%2
3677 
   algf\t%0,%2"
3678 
  [(set_attr "op_type"  "RRE,RXY")])
3679 
 
3680 
(define_insn "*adddi3_zero_cconly"
3681 
  [(set (reg CC_REGNUM)
3682 
        (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3683 
                          (match_operand:DI 1 "register_operand" "0,0"))
3684 
                 (const_int 0)))
3685 
   (clobber (match_scratch:DI 0 "=d,d"))]
3686 
  "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3687 
  "@
3688 
   algfr\t%0,%2
3689 
   algf\t%0,%2"
3690 
  [(set_attr "op_type"  "RRE,RXY")])
3691 
 
3692 
(define_insn "*adddi3_zero"
3693 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
3694 
        (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3695 
                 (match_operand:DI 1 "register_operand" "0,0")))
3696 
   (clobber (reg:CC CC_REGNUM))]
3697 
  "TARGET_64BIT"
3698 
  "@
3699 
   algfr\t%0,%2
3700 
   algf\t%0,%2"
3701 
  [(set_attr "op_type"  "RRE,RXY")])
3702 
 
3703 
(define_insn "*adddi3_imm_cc"
3704 
  [(set (reg CC_REGNUM)
3705 
        (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
3706 
                          (match_operand:DI 2 "const_int_operand" "K,Os"))
3707 
                 (const_int 0)))
3708 
   (set (match_operand:DI 0 "register_operand" "=d,d")
3709 
        (plus:DI (match_dup 1) (match_dup 2)))]
3710 
  "TARGET_64BIT
3711 
   && s390_match_ccmode (insn, CCAmode)
3712 
   && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3713 
       || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
3714 
  "@
3715 
   aghi\t%0,%h2
3716 
   agfi\t%0,%2"
3717 
  [(set_attr "op_type"  "RI,RIL")])
3718 
 
3719 
(define_insn "*adddi3_carry1_cc"
3720 
  [(set (reg CC_REGNUM)
3721 
        (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3722 
                          (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3723 
                 (match_dup 1)))
3724 
   (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3725 
        (plus:DI (match_dup 1) (match_dup 2)))]
3726 
  "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3727 
  "@
3728 
   algr\t%0,%2
3729 
   algfi\t%0,%2
3730 
   slgfi\t%0,%n2
3731 
   alg\t%0,%2"
3732 
  [(set_attr "op_type"  "RRE,RIL,RIL,RXY")])
3733 
 
3734 
(define_insn "*adddi3_carry1_cconly"
3735 
  [(set (reg CC_REGNUM)
3736 
        (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3737 
                          (match_operand:DI 2 "general_operand" "d,m"))
3738 
                 (match_dup 1)))
3739 
   (clobber (match_scratch:DI 0 "=d,d"))]
3740 
  "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3741 
  "@
3742 
   algr\t%0,%2
3743 
   alg\t%0,%2"
3744 
  [(set_attr "op_type"  "RRE,RXY")])
3745 
 
3746 
(define_insn "*adddi3_carry2_cc"
3747 
  [(set (reg CC_REGNUM)
3748 
        (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3749 
                          (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3750 
                 (match_dup 2)))
3751 
   (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3752 
        (plus:DI (match_dup 1) (match_dup 2)))]
3753 
  "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3754 
  "@
3755 
   algr\t%0,%2
3756 
   algfi\t%0,%2
3757 
   slgfi\t%0,%n2
3758 
   alg\t%0,%2"
3759 
  [(set_attr "op_type"  "RRE,RIL,RIL,RXY")])
3760 
 
3761 
(define_insn "*adddi3_carry2_cconly"
3762 
  [(set (reg CC_REGNUM)
3763 
        (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3764 
                          (match_operand:DI 2 "general_operand" "d,m"))
3765 
                 (match_dup 2)))
3766 
   (clobber (match_scratch:DI 0 "=d,d"))]
3767 
  "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3768 
  "@
3769 
   algr\t%0,%2
3770 
   alg\t%0,%2"
3771 
  [(set_attr "op_type"  "RRE,RXY")])
3772 
 
3773 
(define_insn "*adddi3_cc"
3774 
  [(set (reg CC_REGNUM)
3775 
        (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3776 
                          (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3777 
                 (const_int 0)))
3778 
   (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3779 
        (plus:DI (match_dup 1) (match_dup 2)))]
3780 
  "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3781 
  "@
3782 
   algr\t%0,%2
3783 
   algfi\t%0,%2
3784 
   slgfi\t%0,%n2
3785 
   alg\t%0,%2"
3786 
  [(set_attr "op_type"  "RRE,RIL,RIL,RXY")])
3787 
 
3788 
(define_insn "*adddi3_cconly"
3789 
  [(set (reg CC_REGNUM)
3790 
        (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3791 
                          (match_operand:DI 2 "general_operand" "d,m"))
3792 
                 (const_int 0)))
3793 
   (clobber (match_scratch:DI 0 "=d,d"))]
3794 
  "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3795 
  "@
3796 
   algr\t%0,%2
3797 
   alg\t%0,%2"
3798 
  [(set_attr "op_type"  "RRE,RXY")])
3799 
 
3800 
(define_insn "*adddi3_cconly2"
3801 
  [(set (reg CC_REGNUM)
3802 
        (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3803 
                 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3804 
   (clobber (match_scratch:DI 0 "=d,d"))]
3805 
  "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3806 
  "@
3807 
   algr\t%0,%2
3808 
   alg\t%0,%2"
3809 
  [(set_attr "op_type"  "RRE,RXY")])
3810 
 
3811 
(define_insn "*adddi3_64"
3812 
  [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
3813 
        (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
3814 
                 (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
3815 
   (clobber (reg:CC CC_REGNUM))]
3816 
  "TARGET_64BIT"
3817 
  "@
3818 
   agr\t%0,%2
3819 
   aghi\t%0,%h2
3820 
   algfi\t%0,%2
3821 
   slgfi\t%0,%n2
3822 
   ag\t%0,%2"
3823 
  [(set_attr "op_type"  "RRE,RI,RIL,RIL,RXY")])
3824 
 
3825 
(define_insn_and_split "*adddi3_31z"
3826 
  [(set (match_operand:DI 0 "register_operand" "=&d")
3827 
        (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3828 
                 (match_operand:DI 2 "general_operand" "do") ) )
3829 
   (clobber (reg:CC CC_REGNUM))]
3830 
  "!TARGET_64BIT && TARGET_CPU_ZARCH"
3831 
  "#"
3832 
  "&& reload_completed"
3833 
  [(parallel
3834 
    [(set (reg:CCL1 CC_REGNUM)
3835 
          (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3836 
                        (match_dup 7)))
3837 
     (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3838 
   (parallel
3839 
    [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3840 
                                 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3841 
     (clobber (reg:CC CC_REGNUM))])]
3842 
  "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3843 
   operands[4] = operand_subword (operands[1], 0, 0, DImode);
3844 
   operands[5] = operand_subword (operands[2], 0, 0, DImode);
3845 
   operands[6] = operand_subword (operands[0], 1, 0, DImode);
3846 
   operands[7] = operand_subword (operands[1], 1, 0, DImode);
3847 
   operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3848 
 
3849 
(define_insn_and_split "*adddi3_31"
3850 
  [(set (match_operand:DI 0 "register_operand" "=&d")
3851 
        (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3852 
                 (match_operand:DI 2 "general_operand" "do") ) )
3853 
   (clobber (reg:CC CC_REGNUM))]
3854 
  "!TARGET_CPU_ZARCH"
3855 
  "#"
3856 
  "&& reload_completed"
3857 
  [(parallel
3858 
    [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3859 
     (clobber (reg:CC CC_REGNUM))])
3860 
   (parallel
3861 
    [(set (reg:CCL1 CC_REGNUM)
3862 
          (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3863 
                        (match_dup 7)))
3864 
     (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3865 
   (set (pc)
3866 
        (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3867 
                      (pc)
3868 
                      (label_ref (match_dup 9))))
3869 
   (parallel
3870 
    [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3871 
     (clobber (reg:CC CC_REGNUM))])
3872 
   (match_dup 9)]
3873 
  "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3874 
   operands[4] = operand_subword (operands[1], 0, 0, DImode);
3875 
   operands[5] = operand_subword (operands[2], 0, 0, DImode);
3876 
   operands[6] = operand_subword (operands[0], 1, 0, DImode);
3877 
   operands[7] = operand_subword (operands[1], 1, 0, DImode);
3878 
   operands[8] = operand_subword (operands[2], 1, 0, DImode);
3879 
   operands[9] = gen_label_rtx ();")
3880 
 
3881 
(define_expand "adddi3"
3882 
  [(parallel
3883 
    [(set (match_operand:DI 0 "register_operand" "")
3884 
          (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3885 
                   (match_operand:DI 2 "general_operand" "")))
3886 
     (clobber (reg:CC CC_REGNUM))])]
3887 
  ""
3888 
  "")
3889 
 
3890 
;
3891 
; addsi3 instruction pattern(s).
3892 
;
3893 
 
3894 
(define_insn "*addsi3_imm_cc"
3895 
  [(set (reg CC_REGNUM)
3896 
        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
3897 
                          (match_operand:SI 2 "const_int_operand" "K,Os"))
3898 
                 (const_int 0)))
3899 
   (set (match_operand:SI 0 "register_operand" "=d,d")
3900 
        (plus:SI (match_dup 1) (match_dup 2)))]
3901 
  "s390_match_ccmode (insn, CCAmode)
3902 
   && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3903 
       || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3904 
   && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
3905 
  "@
3906 
   ahi\t%0,%h2
3907 
   afi\t%0,%2"
3908 
  [(set_attr "op_type"  "RI,RIL")])
3909 
 
3910 
(define_insn "*addsi3_carry1_cc"
3911 
  [(set (reg CC_REGNUM)
3912 
        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3913 
                          (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3914 
                 (match_dup 1)))
3915 
   (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3916 
        (plus:SI (match_dup 1) (match_dup 2)))]
3917 
  "s390_match_ccmode (insn, CCL1mode)"
3918 
  "@
3919 
   alr\t%0,%2
3920 
   alfi\t%0,%o2
3921 
   al\t%0,%2
3922 
   aly\t%0,%2"
3923 
  [(set_attr "op_type"  "RR,RIL,RX,RXY")])
3924 
 
3925 
(define_insn "*addsi3_carry1_cconly"
3926 
  [(set (reg CC_REGNUM)
3927 
        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3928 
                          (match_operand:SI 2 "general_operand" "d,R,T"))
3929 
                 (match_dup 1)))
3930 
   (clobber (match_scratch:SI 0 "=d,d,d"))]
3931 
  "s390_match_ccmode (insn, CCL1mode)"
3932 
  "@
3933 
   alr\t%0,%2
3934 
   al\t%0,%2
3935 
   aly\t%0,%2"
3936 
  [(set_attr "op_type"  "RR,RX,RXY")])
3937 
 
3938 
(define_insn "*addsi3_carry2_cc"
3939 
  [(set (reg CC_REGNUM)
3940 
        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3941 
                          (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3942 
                 (match_dup 2)))
3943 
   (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3944 
        (plus:SI (match_dup 1) (match_dup 2)))]
3945 
  "s390_match_ccmode (insn, CCL1mode)"
3946 
  "@
3947 
   alr\t%0,%2
3948 
   alfi\t%0,%o2
3949 
   al\t%0,%2
3950 
   aly\t%0,%2"
3951 
  [(set_attr "op_type"  "RR,RIL,RX,RXY")])
3952 
 
3953 
(define_insn "*addsi3_carry2_cconly"
3954 
  [(set (reg CC_REGNUM)
3955 
        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3956 
                          (match_operand:SI 2 "general_operand" "d,R,T"))
3957 
                 (match_dup 2)))
3958 
   (clobber (match_scratch:SI 0 "=d,d,d"))]
3959 
  "s390_match_ccmode (insn, CCL1mode)"
3960 
  "@
3961 
   alr\t%0,%2
3962 
   al\t%0,%2
3963 
   aly\t%0,%2"
3964 
  [(set_attr "op_type"  "RR,RX,RXY")])
3965 
 
3966 
(define_insn "*addsi3_cc"
3967 
  [(set (reg CC_REGNUM)
3968 
        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3969 
                          (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3970 
                 (const_int 0)))
3971 
   (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3972 
        (plus:SI (match_dup 1) (match_dup 2)))]
3973 
  "s390_match_ccmode (insn, CCLmode)"
3974 
  "@
3975 
   alr\t%0,%2
3976 
   alfi\t%0,%o2
3977 
   al\t%0,%2
3978 
   aly\t%0,%2"
3979 
  [(set_attr "op_type"  "RR,RIL,RX,RXY")])
3980 
 
3981 
(define_insn "*addsi3_cconly"
3982 
  [(set (reg CC_REGNUM)
3983 
        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3984 
                          (match_operand:SI 2 "general_operand" "d,R,T"))
3985 
                 (const_int 0)))
3986 
   (clobber (match_scratch:SI 0 "=d,d,d"))]
3987 
  "s390_match_ccmode (insn, CCLmode)"
3988 
  "@
3989 
   alr\t%0,%2
3990 
   al\t%0,%2
3991 
   aly\t%0,%2"
3992 
  [(set_attr "op_type"  "RR,RX,RXY")])
3993 
 
3994 
(define_insn "*addsi3_cconly2"
3995 
  [(set (reg CC_REGNUM)
3996 
        (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3997 
                 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3998 
   (clobber (match_scratch:SI 0 "=d,d,d"))]
3999 
  "s390_match_ccmode (insn, CCLmode)"
4000 
  "@
4001 
   alr\t%0,%2
4002 
   al\t%0,%2
4003 
   aly\t%0,%2"
4004 
  [(set_attr "op_type"  "RR,RX,RXY")])
4005 
 
4006 
(define_insn "*addsi3_sign"
4007 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
4008 
        (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4009 
                 (match_operand:SI 1 "register_operand" "0,0")))
4010 
   (clobber (reg:CC CC_REGNUM))]
4011 
  ""
4012 
  "@
4013 
   ah\t%0,%2
4014 
   ahy\t%0,%2"
4015 
  [(set_attr "op_type"  "RX,RXY")])
4016 
 
4017 
(define_insn "addsi3"
4018 
  [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
4019 
        (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
4020 
                 (match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
4021 
   (clobber (reg:CC CC_REGNUM))]
4022 
  ""
4023 
  "@
4024 
   ar\t%0,%2
4025 
   ahi\t%0,%h2
4026 
   afi\t%0,%2
4027 
   a\t%0,%2
4028 
   ay\t%0,%2"
4029 
  [(set_attr "op_type"  "RR,RI,RIL,RX,RXY")])
4030 
 
4031 
;
4032 
; add(df|sf)3 instruction pattern(s).
4033 
;
4034 
 
4035 
(define_expand "add3"
4036 
  [(parallel
4037 
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
4038 
          (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4039 
                    (match_operand:FPR 2 "general_operand" "f,")))
4040 
     (clobber (reg:CC CC_REGNUM))])]
4041 
  "TARGET_HARD_FLOAT"
4042 
  "")
4043 
 
4044 
(define_insn "*add3"
4045 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
4046 
        (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4047 
                  (match_operand:FPR 2 "general_operand" "f,")))
4048 
   (clobber (reg:CC CC_REGNUM))]
4049 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4050 
  "@
4051 
   abr\t%0,%2
4052 
   ab\t%0,%2"
4053 
  [(set_attr "op_type"  "RRE,RXE")
4054 
   (set_attr "type"     "fsimp")])
4055 
 
4056 
(define_insn "*add3_cc"
4057 
  [(set (reg CC_REGNUM)
4058 
        (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4059 
                           (match_operand:FPR 2 "general_operand" "f,"))
4060 
                 (match_operand:FPR 3 "const0_operand" "")))
4061 
   (set (match_operand:FPR 0 "register_operand" "=f,f")
4062 
        (plus:FPR (match_dup 1) (match_dup 2)))]
4063 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4064 
  "@
4065 
   abr\t%0,%2
4066 
   ab\t%0,%2"
4067 
  [(set_attr "op_type"  "RRE,RXE")
4068 
   (set_attr "type"     "fsimp")])
4069 
 
4070 
(define_insn "*add3_cconly"
4071 
  [(set (reg CC_REGNUM)
4072 
        (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4073 
                           (match_operand:FPR 2 "general_operand" "f,"))
4074 
                 (match_operand:FPR 3 "const0_operand" "")))
4075 
   (clobber (match_scratch:FPR 0 "=f,f"))]
4076 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4077 
  "@
4078 
   abr\t%0,%2
4079 
   ab\t%0,%2"
4080 
  [(set_attr "op_type"  "RRE,RXE")
4081 
   (set_attr "type"     "fsimp")])
4082 
 
4083 
(define_insn "*add3_ibm"
4084 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
4085 
        (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4086 
                  (match_operand:FPR 2 "general_operand" "f,")))
4087 
   (clobber (reg:CC CC_REGNUM))]
4088 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4089 
  "@
4090 
   ar\t%0,%2
4091 
   a\t%0,%2"
4092 
  [(set_attr "op_type"  ",")
4093 
   (set_attr "type"     "fsimp")])
4094 
 
4095 
 
4096 
;;
4097 
;;- Subtract instructions.
4098 
;;
4099 
 
4100 
;
4101 
; subti3 instruction pattern(s).
4102 
;
4103 
 
4104 
(define_insn_and_split "subti3"
4105 
  [(set (match_operand:TI 0 "register_operand" "=&d")
4106 
        (minus:TI (match_operand:TI 1 "register_operand" "0")
4107 
                  (match_operand:TI 2 "general_operand" "do") ) )
4108 
   (clobber (reg:CC CC_REGNUM))]
4109 
  "TARGET_64BIT"
4110 
  "#"
4111 
  "&& reload_completed"
4112 
  [(parallel
4113 
    [(set (reg:CCL2 CC_REGNUM)
4114 
          (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4115 
                        (match_dup 7)))
4116 
     (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4117 
   (parallel
4118 
    [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4119 
                                  (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4120 
     (clobber (reg:CC CC_REGNUM))])]
4121 
  "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4122 
   operands[4] = operand_subword (operands[1], 0, 0, TImode);
4123 
   operands[5] = operand_subword (operands[2], 0, 0, TImode);
4124 
   operands[6] = operand_subword (operands[0], 1, 0, TImode);
4125 
   operands[7] = operand_subword (operands[1], 1, 0, TImode);
4126 
   operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4127 
 
4128 
;
4129 
; subdi3 instruction pattern(s).
4130 
;
4131 
 
4132 
(define_insn "*subdi3_sign"
4133 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
4134 
        (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4135 
                  (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
4136 
   (clobber (reg:CC CC_REGNUM))]
4137 
  "TARGET_64BIT"
4138 
  "@
4139 
   sgfr\t%0,%2
4140 
   sgf\t%0,%2"
4141 
  [(set_attr "op_type"  "RRE,RXY")])
4142 
 
4143 
(define_insn "*subdi3_zero_cc"
4144 
  [(set (reg CC_REGNUM)
4145 
        (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4146 
                           (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
4147 
                 (const_int 0)))
4148 
   (set (match_operand:DI 0 "register_operand" "=d,d")
4149 
        (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4150 
  "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4151 
  "@
4152 
   slgfr\t%0,%2
4153 
   slgf\t%0,%2"
4154 
  [(set_attr "op_type"  "RRE,RXY")])
4155 
 
4156 
(define_insn "*subdi3_zero_cconly"
4157 
  [(set (reg CC_REGNUM)
4158 
        (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4159 
                           (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
4160 
                 (const_int 0)))
4161 
   (clobber (match_scratch:DI 0 "=d,d"))]
4162 
  "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4163 
  "@
4164 
   slgfr\t%0,%2
4165 
   slgf\t%0,%2"
4166 
  [(set_attr "op_type"  "RRE,RXY")])
4167 
 
4168 
(define_insn "*subdi3_zero"
4169 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
4170 
        (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4171 
                  (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
4172 
   (clobber (reg:CC CC_REGNUM))]
4173 
  "TARGET_64BIT"
4174 
  "@
4175 
   slgfr\t%0,%2
4176 
   slgf\t%0,%2"
4177 
  [(set_attr "op_type"  "RRE,RXY")])
4178 
 
4179 
(define_insn "*subdi3_borrow_cc"
4180 
  [(set (reg CC_REGNUM)
4181 
        (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4182 
                           (match_operand:DI 2 "general_operand" "d,m"))
4183 
                 (match_dup 1)))
4184 
   (set (match_operand:DI 0 "register_operand" "=d,d")
4185 
        (minus:DI (match_dup 1) (match_dup 2)))]
4186 
  "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
4187 
  "@
4188 
   slgr\t%0,%2
4189 
   slg\t%0,%2"
4190 
  [(set_attr "op_type"  "RRE,RXY")])
4191 
 
4192 
(define_insn "*subdi3_borrow_cconly"
4193 
  [(set (reg CC_REGNUM)
4194 
        (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4195 
                           (match_operand:DI 2 "general_operand" "d,m"))
4196 
                 (match_dup 1)))
4197 
   (clobber (match_scratch:DI 0 "=d,d"))]
4198 
  "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
4199 
  "@
4200 
   slgr\t%0,%2
4201 
   slg\t%0,%2"
4202 
  [(set_attr "op_type"  "RRE,RXY")])
4203 
 
4204 
(define_insn "*subdi3_cc"
4205 
  [(set (reg CC_REGNUM)
4206 
        (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4207 
                           (match_operand:DI 2 "general_operand" "d,m"))
4208 
                 (const_int 0)))
4209 
   (set (match_operand:DI 0 "register_operand" "=d,d")
4210 
        (minus:DI (match_dup 1) (match_dup 2)))]
4211 
  "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4212 
  "@
4213 
   slgr\t%0,%2
4214 
   slg\t%0,%2"
4215 
  [(set_attr "op_type"  "RRE,RXY")])
4216 
 
4217 
(define_insn "*subdi3_cc2"
4218 
  [(set (reg CC_REGNUM)
4219 
        (compare (match_operand:DI 1 "register_operand" "0,0")
4220 
                 (match_operand:DI 2 "general_operand" "d,m")))
4221 
   (set (match_operand:DI 0 "register_operand" "=d,d")
4222 
        (minus:DI (match_dup 1) (match_dup 2)))]
4223 
  "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
4224 
  "@
4225 
   slgr\t%0,%2
4226 
   slg\t%0,%2"
4227 
  [(set_attr "op_type"  "RRE,RXY")])
4228 
 
4229 
(define_insn "*subdi3_cconly"
4230 
  [(set (reg CC_REGNUM)
4231 
        (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4232 
                           (match_operand:DI 2 "general_operand" "d,m"))
4233 
                 (const_int 0)))
4234 
   (clobber (match_scratch:DI 0 "=d,d"))]
4235 
  "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4236 
  "@
4237 
   slgr\t%0,%2
4238 
   slg\t%0,%2"
4239 
  [(set_attr "op_type"  "RRE,RXY")])
4240 
 
4241 
(define_insn "*subdi3_cconly2"
4242 
  [(set (reg CC_REGNUM)
4243 
        (compare (match_operand:DI 1 "register_operand" "0,0")
4244 
                 (match_operand:DI 2 "general_operand" "d,m")))
4245 
   (clobber (match_scratch:DI 0 "=d,d"))]
4246 
  "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
4247 
  "@
4248 
   slgr\t%0,%2
4249 
   slg\t%0,%2"
4250 
  [(set_attr "op_type"  "RRE,RXY")])
4251 
 
4252 
(define_insn "*subdi3_64"
4253 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
4254 
        (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4255 
                  (match_operand:DI 2 "general_operand" "d,m") ) )
4256 
   (clobber (reg:CC CC_REGNUM))]
4257 
  "TARGET_64BIT"
4258 
  "@
4259 
   sgr\t%0,%2
4260 
   sg\t%0,%2"
4261 
  [(set_attr "op_type"  "RRE,RRE")])
4262 
 
4263 
(define_insn_and_split "*subdi3_31z"
4264 
  [(set (match_operand:DI 0 "register_operand" "=&d")
4265 
        (minus:DI (match_operand:DI 1 "register_operand" "0")
4266 
                  (match_operand:DI 2 "general_operand" "do") ) )
4267 
   (clobber (reg:CC CC_REGNUM))]
4268 
  "!TARGET_64BIT && TARGET_CPU_ZARCH"
4269 
  "#"
4270 
  "&& reload_completed"
4271 
  [(parallel
4272 
    [(set (reg:CCL2 CC_REGNUM)
4273 
          (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4274 
                        (match_dup 7)))
4275 
     (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4276 
   (parallel
4277 
    [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4278 
                                  (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4279 
     (clobber (reg:CC CC_REGNUM))])]
4280 
  "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4281 
   operands[4] = operand_subword (operands[1], 0, 0, DImode);
4282 
   operands[5] = operand_subword (operands[2], 0, 0, DImode);
4283 
   operands[6] = operand_subword (operands[0], 1, 0, DImode);
4284 
   operands[7] = operand_subword (operands[1], 1, 0, DImode);
4285 
   operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4286 
 
4287 
(define_insn_and_split "*subdi3_31"
4288 
  [(set (match_operand:DI 0 "register_operand" "=&d")
4289 
        (minus:DI (match_operand:DI 1 "register_operand" "0")
4290 
                  (match_operand:DI 2 "general_operand" "do") ) )
4291 
   (clobber (reg:CC CC_REGNUM))]
4292 
  "!TARGET_CPU_ZARCH"
4293 
  "#"
4294 
  "&& reload_completed"
4295 
  [(parallel
4296 
    [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4297 
     (clobber (reg:CC CC_REGNUM))])
4298 
   (parallel
4299 
    [(set (reg:CCL2 CC_REGNUM)
4300 
          (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4301 
                        (match_dup 7)))
4302 
     (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4303 
   (set (pc)
4304 
        (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4305 
                      (pc)
4306 
                      (label_ref (match_dup 9))))
4307 
   (parallel
4308 
    [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4309 
     (clobber (reg:CC CC_REGNUM))])
4310 
   (match_dup 9)]
4311 
  "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4312 
   operands[4] = operand_subword (operands[1], 0, 0, DImode);
4313 
   operands[5] = operand_subword (operands[2], 0, 0, DImode);
4314 
   operands[6] = operand_subword (operands[0], 1, 0, DImode);
4315 
   operands[7] = operand_subword (operands[1], 1, 0, DImode);
4316 
   operands[8] = operand_subword (operands[2], 1, 0, DImode);
4317 
   operands[9] = gen_label_rtx ();")
4318 
 
4319 
(define_expand "subdi3"
4320 
  [(parallel
4321 
    [(set (match_operand:DI 0 "register_operand" "")
4322 
          (minus:DI (match_operand:DI 1 "register_operand" "")
4323 
                    (match_operand:DI 2 "general_operand" "")))
4324 
     (clobber (reg:CC CC_REGNUM))])]
4325 
  ""
4326 
  "")
4327 
 
4328 
;
4329 
; subsi3 instruction pattern(s).
4330 
;
4331 
 
4332 
(define_insn "*subsi3_borrow_cc"
4333 
  [(set (reg CC_REGNUM)
4334 
        (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4335 
                           (match_operand:SI 2 "general_operand" "d,R,T"))
4336 
                 (match_dup 1)))
4337 
   (set (match_operand:SI 0 "register_operand" "=d,d,d")
4338 
        (minus:SI (match_dup 1) (match_dup 2)))]
4339 
  "s390_match_ccmode (insn, CCL2mode)"
4340 
  "@
4341 
   slr\t%0,%2
4342 
   sl\t%0,%2
4343 
   sly\t%0,%2"
4344 
  [(set_attr "op_type"  "RR,RX,RXY")])
4345 
 
4346 
(define_insn "*subsi3_borrow_cconly"
4347 
  [(set (reg CC_REGNUM)
4348 
        (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4349 
                           (match_operand:SI 2 "general_operand" "d,R,T"))
4350 
                 (match_dup 1)))
4351 
   (clobber (match_scratch:SI 0 "=d,d,d"))]
4352 
  "s390_match_ccmode (insn, CCL2mode)"
4353 
  "@
4354 
   slr\t%0,%2
4355 
   sl\t%0,%2
4356 
   sly\t%0,%2"
4357 
  [(set_attr "op_type"  "RR,RX,RXY")])
4358 
 
4359 
(define_insn "*subsi3_cc"
4360 
  [(set (reg CC_REGNUM)
4361 
        (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4362 
                           (match_operand:SI 2 "general_operand" "d,R,T"))
4363 
                 (const_int 0)))
4364 
   (set (match_operand:SI 0 "register_operand" "=d,d,d")
4365 
        (minus:SI (match_dup 1) (match_dup 2)))]
4366 
  "s390_match_ccmode (insn, CCLmode)"
4367 
  "@
4368 
   slr\t%0,%2
4369 
   sl\t%0,%2
4370 
   sly\t%0,%2"
4371 
  [(set_attr "op_type"  "RR,RX,RXY")])
4372 
 
4373 
(define_insn "*subsi3_cc2"
4374 
  [(set (reg CC_REGNUM)
4375 
        (compare (match_operand:SI 1 "register_operand" "0,0,0")
4376 
                 (match_operand:SI 2 "general_operand" "d,R,T")))
4377 
   (set (match_operand:SI 0 "register_operand" "=d,d,d")
4378 
        (minus:SI (match_dup 1) (match_dup 2)))]
4379 
  "s390_match_ccmode (insn, CCL3mode)"
4380 
  "@
4381 
   slr\t%0,%2
4382 
   sl\t%0,%2
4383 
   sly\t%0,%2"
4384 
  [(set_attr "op_type"  "RR,RX,RXY")])
4385 
 
4386 
(define_insn "*subsi3_cconly"
4387 
  [(set (reg CC_REGNUM)
4388 
        (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4389 
                           (match_operand:SI 2 "general_operand" "d,R,T"))
4390 
                 (const_int 0)))
4391 
   (clobber (match_scratch:SI 0 "=d,d,d"))]
4392 
  "s390_match_ccmode (insn, CCLmode)"
4393 
  "@
4394 
   slr\t%0,%2
4395 
   sl\t%0,%2
4396 
   sly\t%0,%2"
4397 
  [(set_attr "op_type"  "RR,RX,RXY")])
4398 
 
4399 
(define_insn "*subsi3_cconly2"
4400 
  [(set (reg CC_REGNUM)
4401 
        (compare (match_operand:SI 1 "register_operand" "0,0,0")
4402 
                 (match_operand:SI 2 "general_operand" "d,R,T")))
4403 
   (clobber (match_scratch:SI 0 "=d,d,d"))]
4404 
  "s390_match_ccmode (insn, CCL3mode)"
4405 
  "@
4406 
   slr\t%0,%2
4407 
   sl\t%0,%2
4408 
   sly\t%0,%2"
4409 
  [(set_attr "op_type"  "RR,RX,RXY")])
4410 
 
4411 
(define_insn "*subsi3_sign"
4412 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
4413 
        (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4414 
                  (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4415 
   (clobber (reg:CC CC_REGNUM))]
4416 
  ""
4417 
  "@
4418 
   sh\t%0,%2
4419 
   shy\t%0,%2"
4420 
  [(set_attr "op_type"  "RX,RXY")])
4421 
 
4422 
(define_insn "subsi3"
4423 
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4424 
        (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4425 
                  (match_operand:SI 2 "general_operand" "d,R,T")))
4426 
   (clobber (reg:CC CC_REGNUM))]
4427 
  ""
4428 
  "@
4429 
   sr\t%0,%2
4430 
   s\t%0,%2
4431 
   sy\t%0,%2"
4432 
  [(set_attr "op_type"  "RR,RX,RXY")])
4433 
 
4434 
 
4435 
;
4436 
; sub(df|sf)3 instruction pattern(s).
4437 
;
4438 
 
4439 
(define_expand "sub3"
4440 
  [(parallel
4441 
    [(set (match_operand:FPR 0 "register_operand" "=f,f")
4442 
          (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4443 
                     (match_operand:FPR 2 "general_operand" "f,R")))
4444 
     (clobber (reg:CC CC_REGNUM))])]
4445 
  "TARGET_HARD_FLOAT"
4446 
  "")
4447 
 
4448 
(define_insn "*sub3"
4449 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
4450 
        (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4451 
                   (match_operand:FPR 2 "general_operand" "f,")))
4452 
   (clobber (reg:CC CC_REGNUM))]
4453 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4454 
  "@
4455 
   sbr\t%0,%2
4456 
   sb\t%0,%2"
4457 
  [(set_attr "op_type"  "RRE,RXE")
4458 
   (set_attr "type"     "fsimp")])
4459 
 
4460 
(define_insn "*sub3_cc"
4461 
  [(set (reg CC_REGNUM)
4462 
        (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4463 
                            (match_operand:FPR 2 "general_operand" "f,"))
4464 
                 (match_operand:FPR 3 "const0_operand" "")))
4465 
   (set (match_operand:FPR 0 "register_operand" "=f,f")
4466 
        (minus:FPR (match_dup 1) (match_dup 2)))]
4467 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4468 
  "@
4469 
   sbr\t%0,%2
4470 
   sb\t%0,%2"
4471 
  [(set_attr "op_type"  "RRE,RXE")
4472 
   (set_attr "type"     "fsimp")])
4473 
 
4474 
(define_insn "*sub3_cconly"
4475 
  [(set (reg CC_REGNUM)
4476 
        (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4477 
                            (match_operand:FPR 2 "general_operand" "f,"))
4478 
                 (match_operand:FPR 3 "const0_operand" "")))
4479 
   (clobber (match_scratch:FPR 0 "=f,f"))]
4480 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4481 
  "@
4482 
   sbr\t%0,%2
4483 
   sb\t%0,%2"
4484 
  [(set_attr "op_type"  "RRE,RXE")
4485 
   (set_attr "type"     "fsimp")])
4486 
 
4487 
(define_insn "*sub3_ibm"
4488 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
4489 
        (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4490 
                   (match_operand:FPR 2 "general_operand" "f,")))
4491 
   (clobber (reg:CC CC_REGNUM))]
4492 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4493 
  "@
4494 
   sr\t%0,%2
4495 
   s\t%0,%2"
4496 
  [(set_attr "op_type"  ",")
4497 
   (set_attr "type"     "fsimp")])
4498 
 
4499 
 
4500 
;;
4501 
;;- Conditional add/subtract instructions.
4502 
;;
4503 
 
4504 
;
4505 
; add(di|si)cc instruction pattern(s).
4506 
;
4507 
 
4508 
(define_insn "*add3_alc_cc"
4509 
  [(set (reg CC_REGNUM)
4510 
        (compare
4511 
          (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4512 
                              (match_operand:GPR 2 "general_operand" "d,m"))
4513 
                    (match_operand:GPR 3 "s390_alc_comparison" ""))
4514 
          (const_int 0)))
4515 
   (set (match_operand:GPR 0 "register_operand" "=d,d")
4516 
        (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4517 
  "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4518 
  "@
4519 
   alcr\t%0,%2
4520 
   alc\t%0,%2"
4521 
  [(set_attr "op_type"  "RRE,RXY")])
4522 
 
4523 
(define_insn "*add3_alc"
4524 
  [(set (match_operand:GPR 0 "register_operand" "=d,d")
4525 
        (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4526 
                            (match_operand:GPR 2 "general_operand" "d,m"))
4527 
                  (match_operand:GPR 3 "s390_alc_comparison" "")))
4528 
   (clobber (reg:CC CC_REGNUM))]
4529 
  "TARGET_CPU_ZARCH"
4530 
  "@
4531 
   alcr\t%0,%2
4532 
   alc\t%0,%2"
4533 
  [(set_attr "op_type"  "RRE,RXY")])
4534 
 
4535 
(define_insn "*sub3_slb_cc"
4536 
  [(set (reg CC_REGNUM)
4537 
        (compare
4538 
          (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4539 
                                (match_operand:GPR 2 "general_operand" "d,m"))
4540 
                     (match_operand:GPR 3 "s390_slb_comparison" ""))
4541 
          (const_int 0)))
4542 
   (set (match_operand:GPR 0 "register_operand" "=d,d")
4543 
        (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4544 
  "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4545 
  "@
4546 
   slbr\t%0,%2
4547 
   slb\t%0,%2"
4548 
  [(set_attr "op_type"  "RRE,RXY")])
4549 
 
4550 
(define_insn "*sub3_slb"
4551 
  [(set (match_operand:GPR 0 "register_operand" "=d,d")
4552 
        (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4553 
                              (match_operand:GPR 2 "general_operand" "d,m"))
4554 
                   (match_operand:GPR 3 "s390_slb_comparison" "")))
4555 
   (clobber (reg:CC CC_REGNUM))]
4556 
  "TARGET_CPU_ZARCH"
4557 
  "@
4558 
   slbr\t%0,%2
4559 
   slb\t%0,%2"
4560 
  [(set_attr "op_type"  "RRE,RXY")])
4561 
 
4562 
(define_expand "addcc"
4563 
  [(match_operand:GPR 0 "register_operand" "")
4564 
   (match_operand 1 "comparison_operator" "")
4565 
   (match_operand:GPR 2 "register_operand" "")
4566 
   (match_operand:GPR 3 "const_int_operand" "")]
4567 
  "TARGET_CPU_ZARCH"
4568 
  "if (!s390_expand_addcc (GET_CODE (operands[1]),
4569 
                           s390_compare_op0, s390_compare_op1,
4570 
                           operands[0], operands[2],
4571 
                           operands[3])) FAIL; DONE;")
4572 
 
4573 
;
4574 
; scond instruction pattern(s).
4575 
;
4576 
 
4577 
(define_insn_and_split "*scond"
4578 
  [(set (match_operand:GPR 0 "register_operand" "=&d")
4579 
        (match_operand:GPR 1 "s390_alc_comparison" ""))
4580 
   (clobber (reg:CC CC_REGNUM))]
4581 
  "TARGET_CPU_ZARCH"
4582 
  "#"
4583 
  "&& reload_completed"
4584 
  [(set (match_dup 0) (const_int 0))
4585 
   (parallel
4586 
    [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4587 
                                  (match_dup 1)))
4588 
     (clobber (reg:CC CC_REGNUM))])]
4589 
  "")
4590 
 
4591 
(define_insn_and_split "*scond_neg"
4592 
  [(set (match_operand:GPR 0 "register_operand" "=&d")
4593 
        (match_operand:GPR 1 "s390_slb_comparison" ""))
4594 
   (clobber (reg:CC CC_REGNUM))]
4595 
  "TARGET_CPU_ZARCH"
4596 
  "#"
4597 
  "&& reload_completed"
4598 
  [(set (match_dup 0) (const_int 0))
4599 
   (parallel
4600 
    [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4601 
                                   (match_dup 1)))
4602 
     (clobber (reg:CC CC_REGNUM))])
4603 
   (parallel
4604 
    [(set (match_dup 0) (neg:GPR (match_dup 0)))
4605 
     (clobber (reg:CC CC_REGNUM))])]
4606 
  "")
4607 
 
4608 
 
4609 
(define_expand "s"
4610 
  [(set (match_operand:SI 0 "register_operand" "")
4611 
        (SCOND (match_dup 0)
4612 
               (match_dup 0)))]
4613 
  "TARGET_CPU_ZARCH"
4614 
  "if (!s390_expand_addcc (, s390_compare_op0, s390_compare_op1,
4615 
                           operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4616 
 
4617 
(define_expand "seq"
4618 
  [(parallel
4619 
    [(set (match_operand:SI 0 "register_operand" "=d")
4620 
          (match_dup 1))
4621 
     (clobber (reg:CC CC_REGNUM))])
4622 
   (parallel
4623 
    [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4624 
     (clobber (reg:CC CC_REGNUM))])]
4625 
  ""
4626 
{
4627 
  if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4628 
    FAIL;
4629 
  operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4630 
  PUT_MODE (operands[1], SImode);
4631 
})
4632 
 
4633 
(define_insn_and_split "*sne"
4634 
  [(set (match_operand:SI 0 "register_operand" "=d")
4635 
        (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4636 
               (const_int 0)))
4637 
   (clobber (reg:CC CC_REGNUM))]
4638 
  ""
4639 
  "#"
4640 
  "reload_completed"
4641 
  [(parallel
4642 
    [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4643 
     (clobber (reg:CC CC_REGNUM))])])
4644 
 
4645 
 
4646 
;;
4647 
;;- Multiply instructions.
4648 
;;
4649 
 
4650 
;
4651 
; muldi3 instruction pattern(s).
4652 
;
4653 
 
4654 
(define_insn "*muldi3_sign"
4655 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
4656 
        (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4657 
                 (match_operand:DI 1 "register_operand" "0,0")))]
4658 
  "TARGET_64BIT"
4659 
  "@
4660 
   msgfr\t%0,%2
4661 
   msgf\t%0,%2"
4662 
  [(set_attr "op_type"  "RRE,RXY")
4663 
   (set_attr "type"     "imuldi")])
4664 
 
4665 
(define_insn "muldi3"
4666 
  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4667 
        (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4668 
                 (match_operand:DI 2 "general_operand" "d,K,m")))]
4669 
  "TARGET_64BIT"
4670 
  "@
4671 
   msgr\t%0,%2
4672 
   mghi\t%0,%h2
4673 
   msg\t%0,%2"
4674 
  [(set_attr "op_type"  "RRE,RI,RXY")
4675 
   (set_attr "type"     "imuldi")])
4676 
 
4677 
;
4678 
; mulsi3 instruction pattern(s).
4679 
;
4680 
 
4681 
(define_insn "*mulsi3_sign"
4682 
  [(set (match_operand:SI 0 "register_operand" "=d")
4683 
        (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4684 
                 (match_operand:SI 1 "register_operand" "0")))]
4685 
  ""
4686 
  "mh\t%0,%2"
4687 
  [(set_attr "op_type"  "RX")
4688 
   (set_attr "type"     "imulhi")])
4689 
 
4690 
(define_insn "mulsi3"
4691 
  [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4692 
        (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4693 
                  (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4694 
  ""
4695 
  "@
4696 
   msr\t%0,%2
4697 
   mhi\t%0,%h2
4698 
   ms\t%0,%2
4699 
   msy\t%0,%2"
4700 
  [(set_attr "op_type"  "RRE,RI,RX,RXY")
4701 
   (set_attr "type"     "imulsi,imulhi,imulsi,imulsi")])
4702 
 
4703 
;
4704 
; mulsidi3 instruction pattern(s).
4705 
;
4706 
 
4707 
(define_insn "mulsidi3"
4708 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
4709 
        (mult:DI (sign_extend:DI
4710 
                   (match_operand:SI 1 "register_operand" "%0,0"))
4711 
                 (sign_extend:DI
4712 
                   (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4713 
  "!TARGET_64BIT"
4714 
  "@
4715 
   mr\t%0,%2
4716 
   m\t%0,%2"
4717 
  [(set_attr "op_type"  "RR,RX")
4718 
   (set_attr "type"     "imulsi")])
4719 
 
4720 
;
4721 
; umulsidi3 instruction pattern(s).
4722 
;
4723 
 
4724 
(define_insn "umulsidi3"
4725 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
4726 
        (mult:DI (zero_extend:DI
4727 
                   (match_operand:SI 1 "register_operand" "%0,0"))
4728 
                 (zero_extend:DI
4729 
                   (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4730 
  "!TARGET_64BIT && TARGET_CPU_ZARCH"
4731 
  "@
4732 
   mlr\t%0,%2
4733 
   ml\t%0,%2"
4734 
  [(set_attr "op_type"  "RRE,RXY")
4735 
   (set_attr "type"     "imulsi")])
4736 
 
4737 
;
4738 
; mul(df|sf)3 instruction pattern(s).
4739 
;
4740 
 
4741 
(define_expand "mul3"
4742 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
4743 
        (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4744 
                  (match_operand:FPR 2 "general_operand" "f,")))]
4745 
  "TARGET_HARD_FLOAT"
4746 
  "")
4747 
 
4748 
(define_insn "*mul3"
4749 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
4750 
        (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4751 
                  (match_operand:FPR 2 "general_operand" "f,")))]
4752 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4753 
  "@
4754 
   mbr\t%0,%2
4755 
   mb\t%0,%2"
4756 
  [(set_attr "op_type"  "RRE,RXE")
4757 
   (set_attr "type"     "fmul")])
4758 
 
4759 
(define_insn "*mul3_ibm"
4760 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
4761 
        (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4762 
                  (match_operand:FPR 2 "general_operand" "f,")))]
4763 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4764 
  "@
4765 
   mr\t%0,%2
4766 
   m\t%0,%2"
4767 
  [(set_attr "op_type"  ",")
4768 
   (set_attr "type"     "fmul")])
4769 
 
4770 
(define_insn "*fmadd"
4771 
  [(set (match_operand:DSF 0 "register_operand" "=f,f")
4772 
        (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
4773 
                            (match_operand:DSF 2 "nonimmediate_operand"  "f,R"))
4774 
                 (match_operand:DSF 3 "register_operand" "0,0")))]
4775 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4776 
  "@
4777 
   mabr\t%0,%1,%2
4778 
   mab\t%0,%1,%2"
4779 
  [(set_attr "op_type"  "RRE,RXE")
4780 
   (set_attr "type"     "fmul")])
4781 
 
4782 
(define_insn "*fmsub"
4783 
  [(set (match_operand:DSF 0 "register_operand" "=f,f")
4784 
        (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
4785 
                             (match_operand:DSF 2 "nonimmediate_operand"  "f,R"))
4786 
                 (match_operand:DSF 3 "register_operand" "0,0")))]
4787 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4788 
  "@
4789 
   msbr\t%0,%1,%2
4790 
   msb\t%0,%1,%2"
4791 
  [(set_attr "op_type"  "RRE,RXE")
4792 
   (set_attr "type"     "fmul")])
4793 
 
4794 
;;
4795 
;;- Divide and modulo instructions.
4796 
;;
4797 
 
4798 
;
4799 
; divmoddi4 instruction pattern(s).
4800 
;
4801 
 
4802 
(define_expand "divmoddi4"
4803 
  [(parallel [(set (match_operand:DI 0 "general_operand" "")
4804 
                   (div:DI (match_operand:DI 1 "register_operand" "")
4805 
                           (match_operand:DI 2 "general_operand" "")))
4806 
              (set (match_operand:DI 3 "general_operand" "")
4807 
                   (mod:DI (match_dup 1) (match_dup 2)))])
4808 
   (clobber (match_dup 4))]
4809 
  "TARGET_64BIT"
4810 
{
4811 
  rtx insn, div_equal, mod_equal;
4812 
 
4813 
  div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4814 
  mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4815 
 
4816 
  operands[4] = gen_reg_rtx(TImode);
4817 
  emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4818 
 
4819 
  insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4820 
  REG_NOTES (insn) =
4821 
        gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4822 
 
4823 
  insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4824 
  REG_NOTES (insn) =
4825 
        gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4826 
 
4827 
  DONE;
4828 
})
4829 
 
4830 
(define_insn "divmodtidi3"
4831 
  [(set (match_operand:TI 0 "register_operand" "=d,d")
4832 
        (ior:TI
4833 
          (ashift:TI
4834 
            (zero_extend:TI
4835 
              (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4836 
                      (match_operand:DI 2 "general_operand" "d,m")))
4837 
            (const_int 64))
4838 
          (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4839 
  "TARGET_64BIT"
4840 
  "@
4841 
   dsgr\t%0,%2
4842 
   dsg\t%0,%2"
4843 
  [(set_attr "op_type"  "RRE,RXY")
4844 
   (set_attr "type"     "idiv")])
4845 
 
4846 
(define_insn "divmodtisi3"
4847 
  [(set (match_operand:TI 0 "register_operand" "=d,d")
4848 
        (ior:TI
4849 
          (ashift:TI
4850 
            (zero_extend:TI
4851 
              (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4852 
                      (sign_extend:DI
4853 
                        (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4854 
            (const_int 64))
4855 
          (zero_extend:TI
4856 
            (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4857 
  "TARGET_64BIT"
4858 
  "@
4859 
   dsgfr\t%0,%2
4860 
   dsgf\t%0,%2"
4861 
  [(set_attr "op_type"  "RRE,RXY")
4862 
   (set_attr "type"     "idiv")])
4863 
 
4864 
;
4865 
; udivmoddi4 instruction pattern(s).
4866 
;
4867 
 
4868 
(define_expand "udivmoddi4"
4869 
  [(parallel [(set (match_operand:DI 0 "general_operand" "")
4870 
                   (udiv:DI (match_operand:DI 1 "general_operand" "")
4871 
                            (match_operand:DI 2 "nonimmediate_operand" "")))
4872 
              (set (match_operand:DI 3 "general_operand" "")
4873 
                   (umod:DI (match_dup 1) (match_dup 2)))])
4874 
   (clobber (match_dup 4))]
4875 
  "TARGET_64BIT"
4876 
{
4877 
  rtx insn, div_equal, mod_equal, equal;
4878 
 
4879 
  div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4880 
  mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4881 
  equal = gen_rtx_IOR (TImode,
4882 
                       gen_rtx_ASHIFT (TImode,
4883 
                                       gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4884 
                                       GEN_INT (64)),
4885 
                       gen_rtx_ZERO_EXTEND (TImode, div_equal));
4886 
 
4887 
  operands[4] = gen_reg_rtx(TImode);
4888 
  emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4889 
  emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4890 
  emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4891 
  insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4892 
  REG_NOTES (insn) =
4893 
        gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4894 
 
4895 
  insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4896 
  REG_NOTES (insn) =
4897 
        gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4898 
 
4899 
  insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4900 
  REG_NOTES (insn) =
4901 
        gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4902 
 
4903 
  DONE;
4904 
})
4905 
 
4906 
(define_insn "udivmodtidi3"
4907 
  [(set (match_operand:TI 0 "register_operand" "=d,d")
4908 
        (ior:TI
4909 
          (ashift:TI
4910 
            (zero_extend:TI
4911 
              (truncate:DI
4912 
                (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4913 
                         (zero_extend:TI
4914 
                           (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4915 
            (const_int 64))
4916 
          (zero_extend:TI
4917 
            (truncate:DI
4918 
              (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4919 
  "TARGET_64BIT"
4920 
  "@
4921 
   dlgr\t%0,%2
4922 
   dlg\t%0,%2"
4923 
  [(set_attr "op_type"  "RRE,RXY")
4924 
   (set_attr "type"     "idiv")])
4925 
 
4926 
;
4927 
; divmodsi4 instruction pattern(s).
4928 
;
4929 
 
4930 
(define_expand "divmodsi4"
4931 
  [(parallel [(set (match_operand:SI 0 "general_operand" "")
4932 
                   (div:SI (match_operand:SI 1 "general_operand" "")
4933 
                           (match_operand:SI 2 "nonimmediate_operand" "")))
4934 
              (set (match_operand:SI 3 "general_operand" "")
4935 
                   (mod:SI (match_dup 1) (match_dup 2)))])
4936 
   (clobber (match_dup 4))]
4937 
  "!TARGET_64BIT"
4938 
{
4939 
  rtx insn, div_equal, mod_equal, equal;
4940 
 
4941 
  div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4942 
  mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4943 
  equal = gen_rtx_IOR (DImode,
4944 
                       gen_rtx_ASHIFT (DImode,
4945 
                                       gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4946 
                                       GEN_INT (32)),
4947 
                       gen_rtx_ZERO_EXTEND (DImode, div_equal));
4948 
 
4949 
  operands[4] = gen_reg_rtx(DImode);
4950 
  emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4951 
  insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4952 
  REG_NOTES (insn) =
4953 
        gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4954 
 
4955 
  insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4956 
  REG_NOTES (insn) =
4957 
        gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4958 
 
4959 
  insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4960 
  REG_NOTES (insn) =
4961 
        gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4962 
 
4963 
  DONE;
4964 
})
4965 
 
4966 
(define_insn "divmoddisi3"
4967 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
4968 
        (ior:DI
4969 
          (ashift:DI
4970 
            (zero_extend:DI
4971 
              (truncate:SI
4972 
                (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4973 
                        (sign_extend:DI
4974 
                          (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4975 
            (const_int 32))
4976 
          (zero_extend:DI
4977 
            (truncate:SI
4978 
              (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4979 
  "!TARGET_64BIT"
4980 
  "@
4981 
   dr\t%0,%2
4982 
   d\t%0,%2"
4983 
  [(set_attr "op_type"  "RR,RX")
4984 
   (set_attr "type"     "idiv")])
4985 
 
4986 
;
4987 
; udivsi3 and umodsi3 instruction pattern(s).
4988 
;
4989 
 
4990 
(define_expand "udivmodsi4"
4991 
  [(parallel [(set (match_operand:SI 0 "general_operand" "")
4992 
                   (udiv:SI (match_operand:SI 1 "general_operand" "")
4993 
                            (match_operand:SI 2 "nonimmediate_operand" "")))
4994 
              (set (match_operand:SI 3 "general_operand" "")
4995 
                   (umod:SI (match_dup 1) (match_dup 2)))])
4996 
   (clobber (match_dup 4))]
4997 
  "!TARGET_64BIT && TARGET_CPU_ZARCH"
4998 
{
4999 
  rtx insn, div_equal, mod_equal, equal;
5000 
 
5001 
  div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5002 
  mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5003 
  equal = gen_rtx_IOR (DImode,
5004 
                       gen_rtx_ASHIFT (DImode,
5005 
                                       gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5006 
                                       GEN_INT (32)),
5007 
                       gen_rtx_ZERO_EXTEND (DImode, div_equal));
5008 
 
5009 
  operands[4] = gen_reg_rtx(DImode);
5010 
  emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
5011 
  emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5012 
  emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5013 
  insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5014 
  REG_NOTES (insn) =
5015 
        gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5016 
 
5017 
  insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5018 
  REG_NOTES (insn) =
5019 
        gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
5020 
 
5021 
  insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5022 
  REG_NOTES (insn) =
5023 
        gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
5024 
 
5025 
  DONE;
5026 
})
5027 
 
5028 
(define_insn "udivmoddisi3"
5029 
  [(set (match_operand:DI 0 "register_operand" "=d,d")
5030 
        (ior:DI
5031 
          (ashift:DI
5032 
            (zero_extend:DI
5033 
              (truncate:SI
5034 
                (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5035 
                         (zero_extend:DI
5036 
                           (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
5037 
            (const_int 32))
5038 
          (zero_extend:DI
5039 
            (truncate:SI
5040 
              (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5041 
  "!TARGET_64BIT && TARGET_CPU_ZARCH"
5042 
  "@
5043 
   dlr\t%0,%2
5044 
   dl\t%0,%2"
5045 
  [(set_attr "op_type"  "RRE,RXY")
5046 
   (set_attr "type"     "idiv")])
5047 
 
5048 
(define_expand "udivsi3"
5049 
  [(set (match_operand:SI 0 "register_operand" "=d")
5050 
        (udiv:SI (match_operand:SI 1 "general_operand" "")
5051 
                 (match_operand:SI 2 "general_operand" "")))
5052 
   (clobber (match_dup 3))]
5053 
  "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5054 
{
5055 
  rtx insn, udiv_equal, umod_equal, equal;
5056 
 
5057 
  udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5058 
  umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5059 
  equal = gen_rtx_IOR (DImode,
5060 
                       gen_rtx_ASHIFT (DImode,
5061 
                                       gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5062 
                                       GEN_INT (32)),
5063 
                       gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5064 
 
5065 
  operands[3] = gen_reg_rtx (DImode);
5066 
 
5067 
  if (CONSTANT_P (operands[2]))
5068 
    {
5069 
      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5070 
        {
5071 
          rtx label1 = gen_label_rtx ();
5072 
 
5073 
          operands[1] = make_safe_from (operands[1], operands[0]);
5074 
          emit_move_insn (operands[0], const0_rtx);
5075 
          emit_insn (gen_cmpsi (operands[1], operands[2]));
5076 
          emit_jump_insn (gen_bltu (label1));
5077 
          emit_move_insn (operands[0], const1_rtx);
5078 
          emit_label (label1);
5079 
        }
5080 
      else
5081 
        {
5082 
          operands[2] = force_reg (SImode, operands[2]);
5083 
          operands[2] = make_safe_from (operands[2], operands[0]);
5084 
 
5085 
          emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5086 
          insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5087 
                                             operands[2]));
5088 
          REG_NOTES (insn) =
5089 
            gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5090 
 
5091 
          insn = emit_move_insn (operands[0],
5092 
                                 gen_lowpart (SImode, operands[3]));
5093 
          REG_NOTES (insn) =
5094 
            gen_rtx_EXPR_LIST (REG_EQUAL,
5095 
                               udiv_equal, REG_NOTES (insn));
5096 
        }
5097 
    }
5098 
  else
5099 
    {
5100 
      rtx label1 = gen_label_rtx ();
5101 
      rtx label2 = gen_label_rtx ();
5102 
      rtx label3 = gen_label_rtx ();
5103 
 
5104 
      operands[1] = force_reg (SImode, operands[1]);
5105 
      operands[1] = make_safe_from (operands[1], operands[0]);
5106 
      operands[2] = force_reg (SImode, operands[2]);
5107 
      operands[2] = make_safe_from (operands[2], operands[0]);
5108 
 
5109 
      emit_move_insn (operands[0], const0_rtx);
5110 
      emit_insn (gen_cmpsi (operands[2], operands[1]));
5111 
      emit_jump_insn (gen_bgtu (label3));
5112 
      emit_insn (gen_cmpsi (operands[2], const0_rtx));
5113 
      emit_jump_insn (gen_blt (label2));
5114 
      emit_insn (gen_cmpsi (operands[2], const1_rtx));
5115 
      emit_jump_insn (gen_beq (label1));
5116 
      emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5117 
      insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5118 
                                         operands[2]));
5119 
      REG_NOTES (insn) =
5120 
      gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5121 
 
5122 
      insn = emit_move_insn (operands[0],
5123 
                             gen_lowpart (SImode, operands[3]));
5124 
      REG_NOTES (insn) =
5125 
      gen_rtx_EXPR_LIST (REG_EQUAL,
5126 
                               udiv_equal, REG_NOTES (insn));
5127 
      emit_jump (label3);
5128 
      emit_label (label1);
5129 
      emit_move_insn (operands[0], operands[1]);
5130 
      emit_jump (label3);
5131 
      emit_label (label2);
5132 
      emit_move_insn (operands[0], const1_rtx);
5133 
      emit_label (label3);
5134 
    }
5135 
  emit_move_insn (operands[0], operands[0]);
5136 
  DONE;
5137 
})
5138 
 
5139 
(define_expand "umodsi3"
5140 
  [(set (match_operand:SI 0 "register_operand" "=d")
5141 
        (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5142 
                 (match_operand:SI 2 "nonimmediate_operand" "")))
5143 
   (clobber (match_dup 3))]
5144 
  "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5145 
{
5146 
  rtx insn, udiv_equal, umod_equal, equal;
5147 
 
5148 
  udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5149 
  umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5150 
  equal = gen_rtx_IOR (DImode,
5151 
                       gen_rtx_ASHIFT (DImode,
5152 
                                       gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5153 
                                       GEN_INT (32)),
5154 
                       gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5155 
 
5156 
  operands[3] = gen_reg_rtx (DImode);
5157 
 
5158 
  if (CONSTANT_P (operands[2]))
5159 
    {
5160 
      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5161 
        {
5162 
          rtx label1 = gen_label_rtx ();
5163 
 
5164 
          operands[1] = make_safe_from (operands[1], operands[0]);
5165 
          emit_move_insn (operands[0], operands[1]);
5166 
          emit_insn (gen_cmpsi (operands[0], operands[2]));
5167 
          emit_jump_insn (gen_bltu (label1));
5168 
          emit_insn (gen_abssi2 (operands[0], operands[2]));
5169 
          emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5170 
          emit_label (label1);
5171 
        }
5172 
      else
5173 
        {
5174 
          operands[2] = force_reg (SImode, operands[2]);
5175 
          operands[2] = make_safe_from (operands[2], operands[0]);
5176 
 
5177 
          emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5178 
          insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5179 
                                             operands[2]));
5180 
          REG_NOTES (insn) =
5181 
            gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5182 
 
5183 
          insn = emit_move_insn (operands[0],
5184 
                                 gen_highpart (SImode, operands[3]));
5185 
          REG_NOTES (insn) =
5186 
            gen_rtx_EXPR_LIST (REG_EQUAL,
5187 
                               umod_equal, REG_NOTES (insn));
5188 
        }
5189 
    }
5190 
  else
5191 
    {
5192 
      rtx label1 = gen_label_rtx ();
5193 
      rtx label2 = gen_label_rtx ();
5194 
      rtx label3 = gen_label_rtx ();
5195 
 
5196 
      operands[1] = force_reg (SImode, operands[1]);
5197 
      operands[1] = make_safe_from (operands[1], operands[0]);
5198 
      operands[2] = force_reg (SImode, operands[2]);
5199 
      operands[2] = make_safe_from (operands[2], operands[0]);
5200 
 
5201 
      emit_move_insn(operands[0], operands[1]);
5202 
      emit_insn (gen_cmpsi (operands[2], operands[1]));
5203 
      emit_jump_insn (gen_bgtu (label3));
5204 
      emit_insn (gen_cmpsi (operands[2], const0_rtx));
5205 
      emit_jump_insn (gen_blt (label2));
5206 
      emit_insn (gen_cmpsi (operands[2], const1_rtx));
5207 
      emit_jump_insn (gen_beq (label1));
5208 
      emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5209 
      insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5210 
                                         operands[2]));
5211 
      REG_NOTES (insn) =
5212 
      gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5213 
 
5214 
      insn = emit_move_insn (operands[0],
5215 
                             gen_highpart (SImode, operands[3]));
5216 
      REG_NOTES (insn) =
5217 
      gen_rtx_EXPR_LIST (REG_EQUAL,
5218 
                         umod_equal, REG_NOTES (insn));
5219 
      emit_jump (label3);
5220 
      emit_label (label1);
5221 
      emit_move_insn (operands[0], const0_rtx);
5222 
      emit_jump (label3);
5223 
      emit_label (label2);
5224 
      emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5225 
      emit_label (label3);
5226 
    }
5227 
  DONE;
5228 
})
5229 
 
5230 
;
5231 
; div(df|sf)3 instruction pattern(s).
5232 
;
5233 
 
5234 
(define_expand "div3"
5235 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
5236 
        (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
5237 
                 (match_operand:FPR 2 "general_operand" "f,")))]
5238 
  "TARGET_HARD_FLOAT"
5239 
  "")
5240 
 
5241 
(define_insn "*div3"
5242 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
5243 
        (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
5244 
                 (match_operand:FPR 2 "general_operand" "f,")))]
5245 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5246 
  "@
5247 
   dbr\t%0,%2
5248 
   db\t%0,%2"
5249 
  [(set_attr "op_type"  "RRE,RXE")
5250 
   (set_attr "type"     "fdiv")])
5251 
 
5252 
(define_insn "*div3_ibm"
5253 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
5254 
        (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
5255 
                 (match_operand:FPR 2 "general_operand" "f,")))]
5256 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5257 
  "@
5258 
   dr\t%0,%2
5259 
   d\t%0,%2"
5260 
  [(set_attr "op_type"  ",")
5261 
   (set_attr "type"     "fdiv")])
5262 
 
5263 
 
5264 
;;
5265 
;;- And instructions.
5266 
;;
5267 
 
5268 
(define_expand "and3"
5269 
  [(set (match_operand:INT 0 "nonimmediate_operand" "")
5270 
        (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5271 
                 (match_operand:INT 2 "general_operand" "")))
5272 
   (clobber (reg:CC CC_REGNUM))]
5273 
  ""
5274 
  "s390_expand_logical_operator (AND, mode, operands); DONE;")
5275 
 
5276 
;
5277 
; anddi3 instruction pattern(s).
5278 
;
5279 
 
5280 
(define_insn "*anddi3_cc"
5281 
  [(set (reg CC_REGNUM)
5282 
        (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5283 
                         (match_operand:DI 2 "general_operand" "d,m"))
5284 
                 (const_int 0)))
5285 
   (set (match_operand:DI 0 "register_operand" "=d,d")
5286 
        (and:DI (match_dup 1) (match_dup 2)))]
5287 
  "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5288 
  "@
5289 
   ngr\t%0,%2
5290 
   ng\t%0,%2"
5291 
  [(set_attr "op_type"  "RRE,RXY")])
5292 
 
5293 
(define_insn "*anddi3_cconly"
5294 
  [(set (reg CC_REGNUM)
5295 
        (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5296 
                         (match_operand:DI 2 "general_operand" "d,m"))
5297 
                 (const_int 0)))
5298 
   (clobber (match_scratch:DI 0 "=d,d"))]
5299 
  "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5300 
   /* Do not steal TM patterns.  */
5301 
   && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5302 
  "@
5303 
   ngr\t%0,%2
5304 
   ng\t%0,%2"
5305 
  [(set_attr "op_type"  "RRE,RXY")])
5306 
 
5307 
(define_insn "*anddi3_extimm"
5308 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5309 
        (and:DI (match_operand:DI 1 "nonimmediate_operand"
5310 
                                    "%d,o,0,0,0,0,0,0,0,0,0,0")
5311 
                (match_operand:DI 2 "general_operand"
5312 
                                    "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
5313 
   (clobber (reg:CC CC_REGNUM))]
5314 
  "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5315 
  "@
5316 
   #
5317 
   #
5318 
   nihh\t%0,%j2
5319 
   nihl\t%0,%j2
5320 
   nilh\t%0,%j2
5321 
   nill\t%0,%j2
5322 
   nihf\t%0,%m2
5323 
   nilf\t%0,%m2
5324 
   ngr\t%0,%2
5325 
   ng\t%0,%2
5326 
   #
5327 
   #"
5328 
  [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5329 
 
5330 
(define_insn "*anddi3"
5331 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5332 
        (and:DI (match_operand:DI 1 "nonimmediate_operand"
5333 
                                    "%d,o,0,0,0,0,0,0,0,0")
5334 
                (match_operand:DI 2 "general_operand"
5335 
                                    "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5336 
   (clobber (reg:CC CC_REGNUM))]
5337 
  "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5338 
  "@
5339 
   #
5340 
   #
5341 
   nihh\t%0,%j2
5342 
   nihl\t%0,%j2
5343 
   nilh\t%0,%j2
5344 
   nill\t%0,%j2
5345 
   ngr\t%0,%2
5346 
   ng\t%0,%2
5347 
   #
5348 
   #"
5349 
  [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5350 
 
5351 
(define_split
5352 
  [(set (match_operand:DI 0 "s_operand" "")
5353 
        (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5354 
   (clobber (reg:CC CC_REGNUM))]
5355 
  "reload_completed"
5356 
  [(parallel
5357 
    [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5358 
     (clobber (reg:CC CC_REGNUM))])]
5359 
  "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5360 
 
5361 
 
5362 
;
5363 
; andsi3 instruction pattern(s).
5364 
;
5365 
 
5366 
(define_insn "*andsi3_cc"
5367 
  [(set (reg CC_REGNUM)
5368 
        (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5369 
                         (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5370 
                 (const_int 0)))
5371 
   (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5372 
        (and:SI (match_dup 1) (match_dup 2)))]
5373 
  "s390_match_ccmode(insn, CCTmode)"
5374 
  "@
5375 
   nilf\t%0,%o2
5376 
   nr\t%0,%2
5377 
   n\t%0,%2
5378 
   ny\t%0,%2"
5379 
  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
5380 
 
5381 
(define_insn "*andsi3_cconly"
5382 
  [(set (reg CC_REGNUM)
5383 
        (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5384 
                         (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5385 
                 (const_int 0)))
5386 
   (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5387 
  "s390_match_ccmode(insn, CCTmode)
5388 
   /* Do not steal TM patterns.  */
5389 
   && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5390 
  "@
5391 
   nilf\t%0,%o2
5392 
   nr\t%0,%2
5393 
   n\t%0,%2
5394 
   ny\t%0,%2"
5395 
  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
5396 
 
5397 
(define_insn "*andsi3_zarch"
5398 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5399 
        (and:SI (match_operand:SI 1 "nonimmediate_operand"
5400 
                                    "%d,o,0,0,0,0,0,0,0,0")
5401 
                (match_operand:SI 2 "general_operand"
5402 
                                    "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5403 
   (clobber (reg:CC CC_REGNUM))]
5404 
  "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5405 
  "@
5406 
   #
5407 
   #
5408 
   nilh\t%0,%j2
5409 
   nill\t%0,%j2
5410 
   nilf\t%0,%o2
5411 
   nr\t%0,%2
5412 
   n\t%0,%2
5413 
   ny\t%0,%2
5414 
   #
5415 
   #"
5416 
  [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5417 
 
5418 
(define_insn "*andsi3_esa"
5419 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5420 
        (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5421 
                (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5422 
   (clobber (reg:CC CC_REGNUM))]
5423 
  "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5424 
  "@
5425 
   nr\t%0,%2
5426 
   n\t%0,%2
5427 
   #
5428 
   #"
5429 
  [(set_attr "op_type"  "RR,RX,SI,SS")])
5430 
 
5431 
(define_split
5432 
  [(set (match_operand:SI 0 "s_operand" "")
5433 
        (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5434 
   (clobber (reg:CC CC_REGNUM))]
5435 
  "reload_completed"
5436 
  [(parallel
5437 
    [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5438 
     (clobber (reg:CC CC_REGNUM))])]
5439 
  "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5440 
 
5441 
;
5442 
; andhi3 instruction pattern(s).
5443 
;
5444 
 
5445 
(define_insn "*andhi3_zarch"
5446 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5447 
        (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5448 
                (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5449 
   (clobber (reg:CC CC_REGNUM))]
5450 
  "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5451 
  "@
5452 
   nr\t%0,%2
5453 
   nill\t%0,%x2
5454 
   #
5455 
   #"
5456 
  [(set_attr "op_type"  "RR,RI,SI,SS")])
5457 
 
5458 
(define_insn "*andhi3_esa"
5459 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5460 
        (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5461 
                (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5462 
   (clobber (reg:CC CC_REGNUM))]
5463 
  "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5464 
  "@
5465 
   nr\t%0,%2
5466 
   #
5467 
   #"
5468 
  [(set_attr "op_type"  "RR,SI,SS")])
5469 
 
5470 
(define_split
5471 
  [(set (match_operand:HI 0 "s_operand" "")
5472 
        (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5473 
   (clobber (reg:CC CC_REGNUM))]
5474 
  "reload_completed"
5475 
  [(parallel
5476 
    [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5477 
     (clobber (reg:CC CC_REGNUM))])]
5478 
  "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5479 
 
5480 
;
5481 
; andqi3 instruction pattern(s).
5482 
;
5483 
 
5484 
(define_insn "*andqi3_zarch"
5485 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5486 
        (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5487 
                (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5488 
   (clobber (reg:CC CC_REGNUM))]
5489 
  "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5490 
  "@
5491 
   nr\t%0,%2
5492 
   nill\t%0,%b2
5493 
   ni\t%S0,%b2
5494 
   niy\t%S0,%b2
5495 
   #"
5496 
  [(set_attr "op_type"  "RR,RI,SI,SIY,SS")])
5497 
 
5498 
(define_insn "*andqi3_esa"
5499 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5500 
        (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5501 
                (match_operand:QI 2 "general_operand" "d,n,Q")))
5502 
   (clobber (reg:CC CC_REGNUM))]
5503 
  "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5504 
  "@
5505 
   nr\t%0,%2
5506 
   ni\t%S0,%b2
5507 
   #"
5508 
  [(set_attr "op_type"  "RR,SI,SS")])
5509 
 
5510 
;
5511 
; Block and (NC) patterns.
5512 
;
5513 
 
5514 
(define_insn "*nc"
5515 
  [(set (match_operand:BLK 0 "memory_operand" "=Q")
5516 
        (and:BLK (match_dup 0)
5517 
                 (match_operand:BLK 1 "memory_operand" "Q")))
5518 
   (use (match_operand 2 "const_int_operand" "n"))
5519 
   (clobber (reg:CC CC_REGNUM))]
5520 
  "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5521 
  "nc\t%O0(%2,%R0),%S1"
5522 
  [(set_attr "op_type" "SS")])
5523 
 
5524 
(define_split
5525 
  [(set (match_operand 0 "memory_operand" "")
5526 
        (and (match_dup 0)
5527 
             (match_operand 1 "memory_operand" "")))
5528 
   (clobber (reg:CC CC_REGNUM))]
5529 
  "reload_completed
5530 
   && GET_MODE (operands[0]) == GET_MODE (operands[1])
5531 
   && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5532 
  [(parallel
5533 
    [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5534 
     (use (match_dup 2))
5535 
     (clobber (reg:CC CC_REGNUM))])]
5536 
{
5537 
  operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5538 
  operands[0] = adjust_address (operands[0], BLKmode, 0);
5539 
  operands[1] = adjust_address (operands[1], BLKmode, 0);
5540 
})
5541 
 
5542 
(define_peephole2
5543 
  [(parallel
5544 
    [(set (match_operand:BLK 0 "memory_operand" "")
5545 
          (and:BLK (match_dup 0)
5546 
                   (match_operand:BLK 1 "memory_operand" "")))
5547 
     (use (match_operand 2 "const_int_operand" ""))
5548 
     (clobber (reg:CC CC_REGNUM))])
5549 
   (parallel
5550 
    [(set (match_operand:BLK 3 "memory_operand" "")
5551 
          (and:BLK (match_dup 3)
5552 
                   (match_operand:BLK 4 "memory_operand" "")))
5553 
     (use (match_operand 5 "const_int_operand" ""))
5554 
     (clobber (reg:CC CC_REGNUM))])]
5555 
  "s390_offset_p (operands[0], operands[3], operands[2])
5556 
   && s390_offset_p (operands[1], operands[4], operands[2])
5557 
   && !s390_overlap_p (operands[0], operands[1],
5558 
                       INTVAL (operands[2]) + INTVAL (operands[5]))
5559 
   && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5560 
  [(parallel
5561 
    [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5562 
     (use (match_dup 8))
5563 
     (clobber (reg:CC CC_REGNUM))])]
5564 
  "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5565 
   operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5566 
   operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5567 
 
5568 
 
5569 
;;
5570 
;;- Bit set (inclusive or) instructions.
5571 
;;
5572 
 
5573 
(define_expand "ior3"
5574 
  [(set (match_operand:INT 0 "nonimmediate_operand" "")
5575 
        (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5576 
                 (match_operand:INT 2 "general_operand" "")))
5577 
   (clobber (reg:CC CC_REGNUM))]
5578 
  ""
5579 
  "s390_expand_logical_operator (IOR, mode, operands); DONE;")
5580 
 
5581 
;
5582 
; iordi3 instruction pattern(s).
5583 
;
5584 
 
5585 
(define_insn "*iordi3_cc"
5586 
  [(set (reg CC_REGNUM)
5587 
        (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5588 
                         (match_operand:DI 2 "general_operand" "d,m"))
5589 
                 (const_int 0)))
5590 
   (set (match_operand:DI 0 "register_operand" "=d,d")
5591 
        (ior:DI (match_dup 1) (match_dup 2)))]
5592 
  "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5593 
  "@
5594 
   ogr\t%0,%2
5595 
   og\t%0,%2"
5596 
  [(set_attr "op_type"  "RRE,RXY")])
5597 
 
5598 
(define_insn "*iordi3_cconly"
5599 
  [(set (reg CC_REGNUM)
5600 
        (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5601 
                         (match_operand:DI 2 "general_operand" "d,m"))
5602 
                 (const_int 0)))
5603 
   (clobber (match_scratch:DI 0 "=d,d"))]
5604 
  "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5605 
  "@
5606 
   ogr\t%0,%2
5607 
   og\t%0,%2"
5608 
  [(set_attr "op_type"  "RRE,RXY")])
5609 
 
5610 
(define_insn "*iordi3_extimm"
5611 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5612 
        (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5613 
                (match_operand:DI 2 "general_operand"
5614 
                                    "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5615 
   (clobber (reg:CC CC_REGNUM))]
5616 
  "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5617 
  "@
5618 
   oihh\t%0,%i2
5619 
   oihl\t%0,%i2
5620 
   oilh\t%0,%i2
5621 
   oill\t%0,%i2
5622 
   oihf\t%0,%k2
5623 
   oilf\t%0,%k2
5624 
   ogr\t%0,%2
5625 
   og\t%0,%2
5626 
   #
5627 
   #"
5628 
  [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5629 
 
5630 
(define_insn "*iordi3"
5631 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5632 
        (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5633 
                (match_operand:DI 2 "general_operand"
5634 
                                    "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5635 
   (clobber (reg:CC CC_REGNUM))]
5636 
  "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5637 
  "@
5638 
   oihh\t%0,%i2
5639 
   oihl\t%0,%i2
5640 
   oilh\t%0,%i2
5641 
   oill\t%0,%i2
5642 
   ogr\t%0,%2
5643 
   og\t%0,%2
5644 
   #
5645 
   #"
5646 
  [(set_attr "op_type"  "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5647 
 
5648 
(define_split
5649 
  [(set (match_operand:DI 0 "s_operand" "")
5650 
        (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5651 
   (clobber (reg:CC CC_REGNUM))]
5652 
  "reload_completed"
5653 
  [(parallel
5654 
    [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5655 
     (clobber (reg:CC CC_REGNUM))])]
5656 
  "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5657 
 
5658 
;
5659 
; iorsi3 instruction pattern(s).
5660 
;
5661 
 
5662 
(define_insn "*iorsi3_cc"
5663 
  [(set (reg CC_REGNUM)
5664 
        (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5665 
                         (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5666 
                 (const_int 0)))
5667 
   (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5668 
        (ior:SI (match_dup 1) (match_dup 2)))]
5669 
  "s390_match_ccmode(insn, CCTmode)"
5670 
  "@
5671 
   oilf\t%0,%o2
5672 
   or\t%0,%2
5673 
   o\t%0,%2
5674 
   oy\t%0,%2"
5675 
  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
5676 
 
5677 
(define_insn "*iorsi3_cconly"
5678 
  [(set (reg CC_REGNUM)
5679 
        (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5680 
                         (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5681 
                 (const_int 0)))
5682 
   (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5683 
  "s390_match_ccmode(insn, CCTmode)"
5684 
  "@
5685 
   oilf\t%0,%o2
5686 
   or\t%0,%2
5687 
   o\t%0,%2
5688 
   oy\t%0,%2"
5689 
  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
5690 
 
5691 
(define_insn "*iorsi3_zarch"
5692 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5693 
        (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5694 
                (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5695 
   (clobber (reg:CC CC_REGNUM))]
5696 
  "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5697 
  "@
5698 
   oilh\t%0,%i2
5699 
   oill\t%0,%i2
5700 
   oilf\t%0,%o2
5701 
   or\t%0,%2
5702 
   o\t%0,%2
5703 
   oy\t%0,%2
5704 
   #
5705 
   #"
5706 
  [(set_attr "op_type"  "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5707 
 
5708 
(define_insn "*iorsi3_esa"
5709 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5710 
        (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5711 
                (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5712 
   (clobber (reg:CC CC_REGNUM))]
5713 
  "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5714 
  "@
5715 
   or\t%0,%2
5716 
   o\t%0,%2
5717 
   #
5718 
   #"
5719 
  [(set_attr "op_type"  "RR,RX,SI,SS")])
5720 
 
5721 
(define_split
5722 
  [(set (match_operand:SI 0 "s_operand" "")
5723 
        (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5724 
   (clobber (reg:CC CC_REGNUM))]
5725 
  "reload_completed"
5726 
  [(parallel
5727 
    [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5728 
     (clobber (reg:CC CC_REGNUM))])]
5729 
  "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5730 
 
5731 
;
5732 
; iorhi3 instruction pattern(s).
5733 
;
5734 
 
5735 
(define_insn "*iorhi3_zarch"
5736 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5737 
        (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5738 
                (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5739 
   (clobber (reg:CC CC_REGNUM))]
5740 
  "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5741 
  "@
5742 
   or\t%0,%2
5743 
   oill\t%0,%x2
5744 
   #
5745 
   #"
5746 
  [(set_attr "op_type"  "RR,RI,SI,SS")])
5747 
 
5748 
(define_insn "*iorhi3_esa"
5749 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5750 
        (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5751 
                (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5752 
   (clobber (reg:CC CC_REGNUM))]
5753 
  "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5754 
  "@
5755 
   or\t%0,%2
5756 
   #
5757 
   #"
5758 
  [(set_attr "op_type"  "RR,SI,SS")])
5759 
 
5760 
(define_split
5761 
  [(set (match_operand:HI 0 "s_operand" "")
5762 
        (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5763 
   (clobber (reg:CC CC_REGNUM))]
5764 
  "reload_completed"
5765 
  [(parallel
5766 
    [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5767 
     (clobber (reg:CC CC_REGNUM))])]
5768 
  "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5769 
 
5770 
;
5771 
; iorqi3 instruction pattern(s).
5772 
;
5773 
 
5774 
(define_insn "*iorqi3_zarch"
5775 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5776 
        (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5777 
                (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5778 
   (clobber (reg:CC CC_REGNUM))]
5779 
  "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5780 
  "@
5781 
   or\t%0,%2
5782 
   oill\t%0,%b2
5783 
   oi\t%S0,%b2
5784 
   oiy\t%S0,%b2
5785 
   #"
5786 
  [(set_attr "op_type"  "RR,RI,SI,SIY,SS")])
5787 
 
5788 
(define_insn "*iorqi3_esa"
5789 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5790 
        (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5791 
                (match_operand:QI 2 "general_operand" "d,n,Q")))
5792 
   (clobber (reg:CC CC_REGNUM))]
5793 
  "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5794 
  "@
5795 
   or\t%0,%2
5796 
   oi\t%S0,%b2
5797 
   #"
5798 
  [(set_attr "op_type"  "RR,SI,SS")])
5799 
 
5800 
;
5801 
; Block inclusive or (OC) patterns.
5802 
;
5803 
 
5804 
(define_insn "*oc"
5805 
  [(set (match_operand:BLK 0 "memory_operand" "=Q")
5806 
        (ior:BLK (match_dup 0)
5807 
                 (match_operand:BLK 1 "memory_operand" "Q")))
5808 
   (use (match_operand 2 "const_int_operand" "n"))
5809 
   (clobber (reg:CC CC_REGNUM))]
5810 
  "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5811 
  "oc\t%O0(%2,%R0),%S1"
5812 
  [(set_attr "op_type" "SS")])
5813 
 
5814 
(define_split
5815 
  [(set (match_operand 0 "memory_operand" "")
5816 
        (ior (match_dup 0)
5817 
             (match_operand 1 "memory_operand" "")))
5818 
   (clobber (reg:CC CC_REGNUM))]
5819 
  "reload_completed
5820 
   && GET_MODE (operands[0]) == GET_MODE (operands[1])
5821 
   && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5822 
  [(parallel
5823 
    [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5824 
     (use (match_dup 2))
5825 
     (clobber (reg:CC CC_REGNUM))])]
5826 
{
5827 
  operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5828 
  operands[0] = adjust_address (operands[0], BLKmode, 0);
5829 
  operands[1] = adjust_address (operands[1], BLKmode, 0);
5830 
})
5831 
 
5832 
(define_peephole2
5833 
  [(parallel
5834 
    [(set (match_operand:BLK 0 "memory_operand" "")
5835 
          (ior:BLK (match_dup 0)
5836 
                   (match_operand:BLK 1 "memory_operand" "")))
5837 
     (use (match_operand 2 "const_int_operand" ""))
5838 
     (clobber (reg:CC CC_REGNUM))])
5839 
   (parallel
5840 
    [(set (match_operand:BLK 3 "memory_operand" "")
5841 
          (ior:BLK (match_dup 3)
5842 
                   (match_operand:BLK 4 "memory_operand" "")))
5843 
     (use (match_operand 5 "const_int_operand" ""))
5844 
     (clobber (reg:CC CC_REGNUM))])]
5845 
  "s390_offset_p (operands[0], operands[3], operands[2])
5846 
   && s390_offset_p (operands[1], operands[4], operands[2])
5847 
   && !s390_overlap_p (operands[0], operands[1],
5848 
                       INTVAL (operands[2]) + INTVAL (operands[5]))
5849 
   && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5850 
  [(parallel
5851 
    [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5852 
     (use (match_dup 8))
5853 
     (clobber (reg:CC CC_REGNUM))])]
5854 
  "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5855 
   operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5856 
   operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5857 
 
5858 
 
5859 
;;
5860 
;;- Xor instructions.
5861 
;;
5862 
 
5863 
(define_expand "xor3"
5864 
  [(set (match_operand:INT 0 "nonimmediate_operand" "")
5865 
        (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5866 
                 (match_operand:INT 2 "general_operand" "")))
5867 
   (clobber (reg:CC CC_REGNUM))]
5868 
  ""
5869 
  "s390_expand_logical_operator (XOR, mode, operands); DONE;")
5870 
 
5871 
;
5872 
; xordi3 instruction pattern(s).
5873 
;
5874 
 
5875 
(define_insn "*xordi3_cc"
5876 
  [(set (reg CC_REGNUM)
5877 
        (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5878 
                         (match_operand:DI 2 "general_operand" "d,m"))
5879 
                 (const_int 0)))
5880 
   (set (match_operand:DI 0 "register_operand" "=d,d")
5881 
        (xor:DI (match_dup 1) (match_dup 2)))]
5882 
  "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5883 
  "@
5884 
   xgr\t%0,%2
5885 
   xg\t%0,%2"
5886 
  [(set_attr "op_type"  "RRE,RXY")])
5887 
 
5888 
(define_insn "*xordi3_cconly"
5889 
  [(set (reg CC_REGNUM)
5890 
        (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5891 
                         (match_operand:DI 2 "general_operand" "d,m"))
5892 
                 (const_int 0)))
5893 
   (clobber (match_scratch:DI 0 "=d,d"))]
5894 
  "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5895 
  "@
5896 
   xgr\t%0,%2
5897 
   xr\t%0,%2"
5898 
  [(set_attr "op_type"  "RRE,RXY")])
5899 
 
5900 
(define_insn "*xordi3_extimm"
5901 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5902 
        (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5903 
                (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5904 
   (clobber (reg:CC CC_REGNUM))]
5905 
  "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5906 
  "@
5907 
   xihf\t%0,%k2
5908 
   xilf\t%0,%k2
5909 
   xgr\t%0,%2
5910 
   xg\t%0,%2
5911 
   #
5912 
   #"
5913 
  [(set_attr "op_type"  "RIL,RIL,RRE,RXY,SI,SS")])
5914 
 
5915 
(define_insn "*xordi3"
5916 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5917 
        (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5918 
                (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5919 
   (clobber (reg:CC CC_REGNUM))]
5920 
  "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5921 
  "@
5922 
   xgr\t%0,%2
5923 
   xg\t%0,%2
5924 
   #
5925 
   #"
5926 
  [(set_attr "op_type"  "RRE,RXY,SI,SS")])
5927 
 
5928 
(define_split
5929 
  [(set (match_operand:DI 0 "s_operand" "")
5930 
        (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5931 
   (clobber (reg:CC CC_REGNUM))]
5932 
  "reload_completed"
5933 
  [(parallel
5934 
    [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5935 
     (clobber (reg:CC CC_REGNUM))])]
5936 
  "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5937 
 
5938 
;
5939 
; xorsi3 instruction pattern(s).
5940 
;
5941 
 
5942 
(define_insn "*xorsi3_cc"
5943 
  [(set (reg CC_REGNUM)
5944 
        (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5945 
                         (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5946 
                 (const_int 0)))
5947 
   (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5948 
        (xor:SI (match_dup 1) (match_dup 2)))]
5949 
  "s390_match_ccmode(insn, CCTmode)"
5950 
  "@
5951 
   xilf\t%0,%o2
5952 
   xr\t%0,%2
5953 
   x\t%0,%2
5954 
   xy\t%0,%2"
5955 
  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
5956 
 
5957 
(define_insn "*xorsi3_cconly"
5958 
  [(set (reg CC_REGNUM)
5959 
        (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5960 
                         (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5961 
                 (const_int 0)))
5962 
   (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5963 
  "s390_match_ccmode(insn, CCTmode)"
5964 
  "@
5965 
   xilf\t%0,%o2
5966 
   xr\t%0,%2
5967 
   x\t%0,%2
5968 
   xy\t%0,%2"
5969 
  [(set_attr "op_type"  "RIL,RR,RX,RXY")])
5970 
 
5971 
(define_insn "*xorsi3"
5972 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5973 
        (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5974 
                (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5975 
   (clobber (reg:CC CC_REGNUM))]
5976 
  "s390_logical_operator_ok_p (operands)"
5977 
  "@
5978 
   xilf\t%0,%o2
5979 
   xr\t%0,%2
5980 
   x\t%0,%2
5981 
   xy\t%0,%2
5982 
   #
5983 
   #"
5984 
  [(set_attr "op_type"  "RIL,RR,RX,RXY,SI,SS")])
5985 
 
5986 
(define_split
5987 
  [(set (match_operand:SI 0 "s_operand" "")
5988 
        (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5989 
   (clobber (reg:CC CC_REGNUM))]
5990 
  "reload_completed"
5991 
  [(parallel
5992 
    [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5993 
     (clobber (reg:CC CC_REGNUM))])]
5994 
  "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5995 
 
5996 
;
5997 
; xorhi3 instruction pattern(s).
5998 
;
5999 
 
6000 
(define_insn "*xorhi3"
6001 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6002 
        (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6003 
                (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
6004 
   (clobber (reg:CC CC_REGNUM))]
6005 
  "s390_logical_operator_ok_p (operands)"
6006 
  "@
6007 
   xilf\t%0,%x2
6008 
   xr\t%0,%2
6009 
   #
6010 
   #"
6011 
  [(set_attr "op_type"  "RIL,RR,SI,SS")])
6012 
 
6013 
(define_split
6014 
  [(set (match_operand:HI 0 "s_operand" "")
6015 
        (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6016 
   (clobber (reg:CC CC_REGNUM))]
6017 
  "reload_completed"
6018 
  [(parallel
6019 
    [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6020 
     (clobber (reg:CC CC_REGNUM))])]
6021 
  "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6022 
 
6023 
;
6024 
; xorqi3 instruction pattern(s).
6025 
;
6026 
 
6027 
(define_insn "*xorqi3"
6028 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6029 
        (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6030 
                (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
6031 
   (clobber (reg:CC CC_REGNUM))]
6032 
  "s390_logical_operator_ok_p (operands)"
6033 
  "@
6034 
   xilf\t%0,%b2
6035 
   xr\t%0,%2
6036 
   xi\t%S0,%b2
6037 
   xiy\t%S0,%b2
6038 
   #"
6039 
  [(set_attr "op_type"  "RIL,RR,SI,SIY,SS")])
6040 
 
6041 
;
6042 
; Block exclusive or (XC) patterns.
6043 
;
6044 
 
6045 
(define_insn "*xc"
6046 
  [(set (match_operand:BLK 0 "memory_operand" "=Q")
6047 
        (xor:BLK (match_dup 0)
6048 
                 (match_operand:BLK 1 "memory_operand" "Q")))
6049 
   (use (match_operand 2 "const_int_operand" "n"))
6050 
   (clobber (reg:CC CC_REGNUM))]
6051 
  "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6052 
  "xc\t%O0(%2,%R0),%S1"
6053 
  [(set_attr "op_type" "SS")])
6054 
 
6055 
(define_split
6056 
  [(set (match_operand 0 "memory_operand" "")
6057 
        (xor (match_dup 0)
6058 
             (match_operand 1 "memory_operand" "")))
6059 
   (clobber (reg:CC CC_REGNUM))]
6060 
  "reload_completed
6061 
   && GET_MODE (operands[0]) == GET_MODE (operands[1])
6062 
   && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6063 
  [(parallel
6064 
    [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6065 
     (use (match_dup 2))
6066 
     (clobber (reg:CC CC_REGNUM))])]
6067 
{
6068 
  operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6069 
  operands[0] = adjust_address (operands[0], BLKmode, 0);
6070 
  operands[1] = adjust_address (operands[1], BLKmode, 0);
6071 
})
6072 
 
6073 
(define_peephole2
6074 
  [(parallel
6075 
    [(set (match_operand:BLK 0 "memory_operand" "")
6076 
          (xor:BLK (match_dup 0)
6077 
                   (match_operand:BLK 1 "memory_operand" "")))
6078 
     (use (match_operand 2 "const_int_operand" ""))
6079 
     (clobber (reg:CC CC_REGNUM))])
6080 
   (parallel
6081 
    [(set (match_operand:BLK 3 "memory_operand" "")
6082 
          (xor:BLK (match_dup 3)
6083 
                   (match_operand:BLK 4 "memory_operand" "")))
6084 
     (use (match_operand 5 "const_int_operand" ""))
6085 
     (clobber (reg:CC CC_REGNUM))])]
6086 
  "s390_offset_p (operands[0], operands[3], operands[2])
6087 
   && s390_offset_p (operands[1], operands[4], operands[2])
6088 
   && !s390_overlap_p (operands[0], operands[1],
6089 
                       INTVAL (operands[2]) + INTVAL (operands[5]))
6090 
   && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6091 
  [(parallel
6092 
    [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6093 
     (use (match_dup 8))
6094 
     (clobber (reg:CC CC_REGNUM))])]
6095 
  "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6096 
   operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6097 
   operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6098 
 
6099 
;
6100 
; Block xor (XC) patterns with src == dest.
6101 
;
6102 
 
6103 
(define_insn "*xc_zero"
6104 
  [(set (match_operand:BLK 0 "memory_operand" "=Q")
6105 
        (const_int 0))
6106 
   (use (match_operand 1 "const_int_operand" "n"))
6107 
   (clobber (reg:CC CC_REGNUM))]
6108 
  "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6109 
  "xc\t%O0(%1,%R0),%S0"
6110 
  [(set_attr "op_type" "SS")])
6111 
 
6112 
(define_peephole2
6113 
  [(parallel
6114 
    [(set (match_operand:BLK 0 "memory_operand" "")
6115 
          (const_int 0))
6116 
     (use (match_operand 1 "const_int_operand" ""))
6117 
     (clobber (reg:CC CC_REGNUM))])
6118 
   (parallel
6119 
    [(set (match_operand:BLK 2 "memory_operand" "")
6120 
          (const_int 0))
6121 
     (use (match_operand 3 "const_int_operand" ""))
6122 
     (clobber (reg:CC CC_REGNUM))])]
6123 
  "s390_offset_p (operands[0], operands[2], operands[1])
6124 
   && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6125 
  [(parallel
6126 
    [(set (match_dup 4) (const_int 0))
6127 
     (use (match_dup 5))
6128 
     (clobber (reg:CC CC_REGNUM))])]
6129 
  "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6130 
   operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6131 
 
6132 
 
6133 
;;
6134 
;;- Negate instructions.
6135 
;;
6136 
 
6137 
;
6138 
; neg(di|si)2 instruction pattern(s).
6139 
;
6140 
 
6141 
(define_expand "neg2"
6142 
  [(parallel
6143 
    [(set (match_operand:DSI 0 "register_operand" "=d")
6144 
          (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6145 
     (clobber (reg:CC CC_REGNUM))])]
6146 
  ""
6147 
  "")
6148 
 
6149 
(define_insn "*negdi2_sign_cc"
6150 
  [(set (reg CC_REGNUM)
6151 
        (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6152 
                           (match_operand:SI 1 "register_operand" "d") 0)
6153 
                           (const_int 32)) (const_int 32)))
6154 
                 (const_int 0)))
6155 
   (set (match_operand:DI 0 "register_operand" "=d")
6156 
        (neg:DI (sign_extend:DI (match_dup 1))))]
6157 
  "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6158 
  "lcgfr\t%0,%1"
6159 
  [(set_attr "op_type"  "RRE")])
6160 
 
6161 
(define_insn "*negdi2_sign"
6162 
  [(set (match_operand:DI 0 "register_operand" "=d")
6163 
        (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6164 
   (clobber (reg:CC CC_REGNUM))]
6165 
  "TARGET_64BIT"
6166 
  "lcgfr\t%0,%1"
6167 
  [(set_attr "op_type"  "RRE")])
6168 
 
6169 
(define_insn "*neg2_cc"
6170 
  [(set (reg CC_REGNUM)
6171 
        (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6172 
                 (const_int 0)))
6173 
   (set (match_operand:GPR 0 "register_operand" "=d")
6174 
        (neg:GPR (match_dup 1)))]
6175 
  "s390_match_ccmode (insn, CCAmode)"
6176 
  "lcr\t%0,%1"
6177 
  [(set_attr "op_type"  "RR")])
6178 
 
6179 
(define_insn "*neg2_cconly"
6180 
  [(set (reg CC_REGNUM)
6181 
        (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6182 
                 (const_int 0)))
6183 
   (clobber (match_scratch:GPR 0 "=d"))]
6184 
  "s390_match_ccmode (insn, CCAmode)"
6185 
  "lcr\t%0,%1"
6186 
  [(set_attr "op_type"  "RR")])
6187 
 
6188 
(define_insn "*neg2"
6189 
  [(set (match_operand:GPR 0 "register_operand" "=d")
6190 
        (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6191 
   (clobber (reg:CC CC_REGNUM))]
6192 
  ""
6193 
  "lcr\t%0,%1"
6194 
  [(set_attr "op_type"  "RR")])
6195 
 
6196 
(define_insn_and_split "*negdi2_31"
6197 
  [(set (match_operand:DI 0 "register_operand" "=d")
6198 
        (neg:DI (match_operand:DI 1 "register_operand" "d")))
6199 
   (clobber (reg:CC CC_REGNUM))]
6200 
  "!TARGET_64BIT"
6201 
  "#"
6202 
  "&& reload_completed"
6203 
  [(parallel
6204 
    [(set (match_dup 2) (neg:SI (match_dup 3)))
6205 
     (clobber (reg:CC CC_REGNUM))])
6206 
   (parallel
6207 
    [(set (reg:CCAP CC_REGNUM)
6208 
          (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6209 
     (set (match_dup 4) (neg:SI (match_dup 5)))])
6210 
   (set (pc)
6211 
        (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6212 
                      (pc)
6213 
                      (label_ref (match_dup 6))))
6214 
   (parallel
6215 
    [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6216 
     (clobber (reg:CC CC_REGNUM))])
6217 
   (match_dup 6)]
6218 
  "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6219 
   operands[3] = operand_subword (operands[1], 0, 0, DImode);
6220 
   operands[4] = operand_subword (operands[0], 1, 0, DImode);
6221 
   operands[5] = operand_subword (operands[1], 1, 0, DImode);
6222 
   operands[6] = gen_label_rtx ();")
6223 
 
6224 
;
6225 
; neg(df|sf)2 instruction pattern(s).
6226 
;
6227 
 
6228 
(define_expand "neg2"
6229 
  [(parallel
6230 
    [(set (match_operand:FPR 0 "register_operand" "=f")
6231 
          (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
6232 
     (clobber (reg:CC CC_REGNUM))])]
6233 
  "TARGET_HARD_FLOAT"
6234 
  "")
6235 
 
6236 
(define_insn "*neg2_cc"
6237 
  [(set (reg CC_REGNUM)
6238 
        (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
6239 
                 (match_operand:FPR 2 "const0_operand" "")))
6240 
   (set (match_operand:FPR 0 "register_operand" "=f")
6241 
        (neg:FPR (match_dup 1)))]
6242 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6243 
  "lcbr\t%0,%1"
6244 
  [(set_attr "op_type"  "RRE")
6245 
   (set_attr "type"     "fsimp")])
6246 
 
6247 
(define_insn "*neg2_cconly"
6248 
  [(set (reg CC_REGNUM)
6249 
        (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
6250 
                 (match_operand:FPR 2 "const0_operand" "")))
6251 
   (clobber (match_scratch:FPR 0 "=f"))]
6252 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6253 
  "lcbr\t%0,%1"
6254 
  [(set_attr "op_type"  "RRE")
6255 
   (set_attr "type"     "fsimp")])
6256 
 
6257 
(define_insn "*neg2"
6258 
  [(set (match_operand:FPR 0 "register_operand" "=f")
6259 
        (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
6260 
   (clobber (reg:CC CC_REGNUM))]
6261 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6262 
  "lcbr\t%0,%1"
6263 
  [(set_attr "op_type"  "RRE")
6264 
   (set_attr "type"     "fsimp")])
6265 
 
6266 
(define_insn "*neg2_ibm"
6267 
  [(set (match_operand:FPR 0 "register_operand" "=f")
6268 
        (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
6269 
   (clobber (reg:CC CC_REGNUM))]
6270 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6271 
  "lcr\t%0,%1"
6272 
  [(set_attr "op_type"  "")
6273 
   (set_attr "type"     "fsimp")])
6274 
 
6275 
 
6276 
;;
6277 
;;- Absolute value instructions.
6278 
;;
6279 
 
6280 
;
6281 
; abs(di|si)2 instruction pattern(s).
6282 
;
6283 
 
6284 
(define_insn "*absdi2_sign_cc"
6285 
  [(set (reg CC_REGNUM)
6286 
        (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6287 
                           (match_operand:SI 1 "register_operand" "d") 0)
6288 
                           (const_int 32)) (const_int 32)))
6289 
                 (const_int 0)))
6290 
   (set (match_operand:DI 0 "register_operand" "=d")
6291 
        (abs:DI (sign_extend:DI (match_dup 1))))]
6292 
  "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6293 
  "lpgfr\t%0,%1"
6294 
  [(set_attr "op_type"  "RRE")])
6295 
 
6296 
(define_insn "*absdi2_sign"
6297 
  [(set (match_operand:DI 0 "register_operand" "=d")
6298 
        (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6299 
   (clobber (reg:CC CC_REGNUM))]
6300 
  "TARGET_64BIT"
6301 
  "lpgfr\t%0,%1"
6302 
  [(set_attr "op_type"  "RRE")])
6303 
 
6304 
(define_insn "*abs2_cc"
6305 
  [(set (reg CC_REGNUM)
6306 
        (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6307 
                 (const_int 0)))
6308 
   (set (match_operand:GPR 0 "register_operand" "=d")
6309 
        (abs:GPR (match_dup 1)))]
6310 
  "s390_match_ccmode (insn, CCAmode)"
6311 
  "lpr\t%0,%1"
6312 
  [(set_attr "op_type"  "RR")])
6313 
 
6314 
(define_insn "*abs2_cconly"
6315 
  [(set (reg CC_REGNUM)
6316 
        (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6317 
                 (const_int 0)))
6318 
   (clobber (match_scratch:GPR 0 "=d"))]
6319 
  "s390_match_ccmode (insn, CCAmode)"
6320 
  "lpr\t%0,%1"
6321 
  [(set_attr "op_type"  "RR")])
6322 
 
6323 
(define_insn "abs2"
6324 
  [(set (match_operand:GPR 0 "register_operand" "=d")
6325 
        (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6326 
   (clobber (reg:CC CC_REGNUM))]
6327 
  ""
6328 
  "lpr\t%0,%1"
6329 
  [(set_attr "op_type"  "RR")])
6330 
 
6331 
;
6332 
; abs(df|sf)2 instruction pattern(s).
6333 
;
6334 
 
6335 
(define_expand "abs2"
6336 
  [(parallel
6337 
    [(set (match_operand:FPR 0 "register_operand" "=f")
6338 
          (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6339 
     (clobber (reg:CC CC_REGNUM))])]
6340 
  "TARGET_HARD_FLOAT"
6341 
  "")
6342 
 
6343 
(define_insn "*abs2_cc"
6344 
  [(set (reg CC_REGNUM)
6345 
        (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6346 
                 (match_operand:FPR 2 "const0_operand" "")))
6347 
   (set (match_operand:FPR 0 "register_operand" "=f")
6348 
        (abs:FPR (match_dup 1)))]
6349 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6350 
  "lpbr\t%0,%1"
6351 
  [(set_attr "op_type"  "RRE")
6352 
   (set_attr "type"     "fsimp")])
6353 
 
6354 
(define_insn "*abs2_cconly"
6355 
  [(set (reg CC_REGNUM)
6356 
        (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6357 
                 (match_operand:FPR 2 "const0_operand" "")))
6358 
   (clobber (match_scratch:FPR 0 "=f"))]
6359 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6360 
  "lpbr\t%0,%1"
6361 
  [(set_attr "op_type"  "RRE")
6362 
   (set_attr "type"     "fsimp")])
6363 
 
6364 
(define_insn "*abs2"
6365 
  [(set (match_operand:FPR 0 "register_operand" "=f")
6366 
        (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6367 
   (clobber (reg:CC CC_REGNUM))]
6368 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6369 
  "lpbr\t%0,%1"
6370 
  [(set_attr "op_type"  "RRE")
6371 
   (set_attr "type"     "fsimp")])
6372 
 
6373 
(define_insn "*abs2_ibm"
6374 
  [(set (match_operand:FPR 0 "register_operand" "=f")
6375 
        (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6376 
   (clobber (reg:CC CC_REGNUM))]
6377 
  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6378 
  "lpr\t%0,%1"
6379 
  [(set_attr "op_type"  "")
6380 
   (set_attr "type"     "fsimp")])
6381 
 
6382 
;;
6383 
;;- Negated absolute value instructions
6384 
;;
6385 
 
6386 
;
6387 
; Integer
6388 
;
6389 
 
6390 
(define_insn "*negabsdi2_sign_cc"
6391 
  [(set (reg CC_REGNUM)
6392 
        (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6393 
                           (match_operand:SI 1 "register_operand" "d") 0)
6394 
                           (const_int 32)) (const_int 32))))
6395 
                 (const_int 0)))
6396 
   (set (match_operand:DI 0 "register_operand" "=d")
6397 
        (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6398 
  "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6399 
  "lngfr\t%0,%1"
6400 
  [(set_attr "op_type"  "RRE")])
6401 
 
6402 
(define_insn "*negabsdi2_sign"
6403 
  [(set (match_operand:DI 0 "register_operand" "=d")
6404 
        (neg:DI (abs:DI (sign_extend:DI
6405 
                          (match_operand:SI 1 "register_operand" "d")))))
6406 
   (clobber (reg:CC CC_REGNUM))]
6407 
  "TARGET_64BIT"
6408 
  "lngfr\t%0,%1"
6409 
  [(set_attr "op_type" "RRE")])
6410 
 
6411 
(define_insn "*negabs2_cc"
6412 
  [(set (reg CC_REGNUM)
6413 
        (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6414 
                 (const_int 0)))
6415 
   (set (match_operand:GPR 0 "register_operand" "=d")
6416 
        (neg:GPR (abs:GPR (match_dup 1))))]
6417 
  "s390_match_ccmode (insn, CCAmode)"
6418 
  "lnr\t%0,%1"
6419 
  [(set_attr "op_type"  "RR")])
6420 
 
6421 
(define_insn "*negabs2_cconly"
6422 
  [(set (reg CC_REGNUM)
6423 
        (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6424 
                 (const_int 0)))
6425 
   (clobber (match_scratch:GPR 0 "=d"))]
6426 
  "s390_match_ccmode (insn, CCAmode)"
6427 
  "lnr\t%0,%1"
6428 
  [(set_attr "op_type"  "RR")])
6429 
 
6430 
(define_insn "*negabs2"
6431 
  [(set (match_operand:GPR 0 "register_operand" "=d")
6432 
        (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6433 
   (clobber (reg:CC CC_REGNUM))]
6434 
  ""
6435 
  "lnr\t%0,%1"
6436 
  [(set_attr "op_type" "RR")])
6437 
 
6438 
;
6439 
; Floating point
6440 
;
6441 
 
6442 
(define_insn "*negabs2_cc"
6443 
  [(set (reg CC_REGNUM)
6444 
        (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6445 
                 (match_operand:FPR 2 "const0_operand" "")))
6446 
   (set (match_operand:FPR 0 "register_operand" "=f")
6447 
        (neg:FPR (abs:FPR (match_dup 1))))]
6448 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6449 
  "lnbr\t%0,%1"
6450 
  [(set_attr "op_type"  "RRE")
6451 
   (set_attr "type"     "fsimp")])
6452 
 
6453 
(define_insn "*negabs2_cconly"
6454 
  [(set (reg CC_REGNUM)
6455 
        (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6456 
                 (match_operand:FPR 2 "const0_operand" "")))
6457 
   (clobber (match_scratch:FPR 0 "=f"))]
6458 
  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6459 
  "lnbr\t%0,%1"
6460 
  [(set_attr "op_type"  "RRE")
6461 
   (set_attr "type"     "fsimp")])
6462 
 
6463 
(define_insn "*negabs2"
6464 
  [(set (match_operand:FPR 0 "register_operand" "=f")
6465 
        (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
6466 
   (clobber (reg:CC CC_REGNUM))]
6467 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6468 
  "lnbr\t%0,%1"
6469 
  [(set_attr "op_type"  "RRE")
6470 
   (set_attr "type"     "fsimp")])
6471 
 
6472 
;;
6473 
;;- Square root instructions.
6474 
;;
6475 
 
6476 
;
6477 
; sqrt(df|sf)2 instruction pattern(s).
6478 
;
6479 
 
6480 
(define_insn "sqrt2"
6481 
  [(set (match_operand:FPR 0 "register_operand" "=f,f")
6482 
        (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,")))]
6483 
  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6484 
  "@
6485 
   sqbr\t%0,%1
6486 
   sqb\t%0,%1"
6487 
  [(set_attr "op_type" "RRE,RXE")
6488 
   (set_attr "type" "fsqrt")])
6489 
 
6490 
 
6491 
;;
6492 
;;- One complement instructions.
6493 
;;
6494 
 
6495 
;
6496 
; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6497 
;
6498 
 
6499 
(define_expand "one_cmpl2"
6500 
  [(parallel
6501 
    [(set (match_operand:INT 0 "register_operand" "")
6502 
          (xor:INT (match_operand:INT 1 "register_operand" "")
6503 
                   (const_int -1)))
6504 
     (clobber (reg:CC CC_REGNUM))])]
6505 
  ""
6506 
  "")
6507 
 
6508 
 
6509 
;;
6510 
;; Find leftmost bit instructions.
6511 
;;
6512 
 
6513 
(define_expand "clzdi2"
6514 
  [(set (match_operand:DI 0 "register_operand" "=d")
6515 
        (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6516 
  "TARGET_EXTIMM && TARGET_64BIT"
6517 
{
6518 
  rtx insn, clz_equal;
6519 
  rtx wide_reg = gen_reg_rtx (TImode);
6520 
  rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6521 
 
6522 
  clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6523 
 
6524 
  emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6525 
 
6526 
  insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6527 
  REG_NOTES (insn) =
6528 
        gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
6529 
 
6530 
  DONE;
6531 
})
6532 
 
6533 
(define_insn "clztidi2"
6534 
  [(set (match_operand:TI 0 "register_operand" "=d")
6535 
        (ior:TI
6536 
          (ashift:TI
6537 
            (zero_extend:TI
6538 
              (xor:DI (match_operand:DI 1 "register_operand" "d")
6539 
                      (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6540 
                                (subreg:SI (clz:DI (match_dup 1)) 4))))
6541 
 
6542 
            (const_int 64))
6543 
          (zero_extend:TI (clz:DI (match_dup 1)))))
6544 
   (clobber (reg:CC CC_REGNUM))]
6545 
  "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6546 
   == (unsigned HOST_WIDE_INT) 1 << 63
6547 
   && TARGET_EXTIMM && TARGET_64BIT"
6548 
  "flogr\t%0,%1"
6549 
  [(set_attr "op_type"  "RRE")])
6550 
 
6551 
 
6552 
;;
6553 
;;- Rotate instructions.
6554 
;;
6555 
 
6556 
;
6557 
; rotl(di|si)3 instruction pattern(s).
6558 
;
6559 
 
6560 
(define_insn "rotl3"
6561 
  [(set (match_operand:GPR 0 "register_operand" "=d")
6562 
        (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6563 
                    (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6564 
  "TARGET_CPU_ZARCH"
6565 
  "rll\t%0,%1,%Y2"
6566 
  [(set_attr "op_type"  "RSE")
6567 
   (set_attr "atype"    "reg")])
6568 
 
6569 
(define_insn "*rotl3_and"
6570 
  [(set (match_operand:GPR 0 "register_operand" "=d")
6571 
        (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6572 
                    (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6573 
                            (match_operand:SI 3 "const_int_operand"   "n"))))]
6574 
  "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
6575 
  "rll\t%0,%1,%Y2"
6576 
  [(set_attr "op_type"  "RSE")
6577 
   (set_attr "atype"    "reg")])
6578 
 
6579 
 
6580 
;;
6581 
;;- Shift instructions.
6582 
;;
6583 
 
6584 
;
6585 
; (ashl|lshr)di3 instruction pattern(s).
6586 
;
6587 
 
6588 
(define_expand "di3"
6589 
  [(set (match_operand:DI 0 "register_operand" "")
6590 
        (SHIFT:DI (match_operand:DI 1 "register_operand" "")
6591 
                  (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
6592 
  ""
6593 
  "")
6594 
 
6595 
(define_insn "*di3_31"
6596 
  [(set (match_operand:DI 0 "register_operand" "=d")
6597 
        (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6598 
                  (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6599 
  "!TARGET_64BIT"
6600 
  "sdl\t%0,%Y2"
6601 
  [(set_attr "op_type"  "RS")
6602 
   (set_attr "atype"    "reg")])
6603 
 
6604 
(define_insn "*di3_64"
6605 
  [(set (match_operand:DI 0 "register_operand" "=d")
6606 
        (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
6607 
                  (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6608 
  "TARGET_64BIT"
6609 
  "slg\t%0,%1,%Y2"
6610 
  [(set_attr "op_type"  "RSE")
6611 
   (set_attr "atype"    "reg")])
6612 
 
6613 
(define_insn "*di3_31_and"
6614 
  [(set (match_operand:DI 0 "register_operand" "=d")
6615 
        (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6616 
                  (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6617 
                          (match_operand:SI 3 "const_int_operand"   "n"))))]
6618 
  "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6619 
  "sdl\t%0,%Y2"
6620 
  [(set_attr "op_type"  "RS")
6621 
   (set_attr "atype"    "reg")])
6622 
 
6623 
(define_insn "*di3_64_and"
6624 
  [(set (match_operand:DI 0 "register_operand" "=d")
6625 
        (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
6626 
                  (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6627 
                          (match_operand:SI 3 "const_int_operand"   "n"))))]
6628 
  "TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6629 
  "slg\t%0,%1,%Y2"
6630 
  [(set_attr "op_type"  "RSE")
6631 
   (set_attr "atype"    "reg")])
6632 
 
6633 
;
6634 
; ashrdi3 instruction pattern(s).
6635 
;
6636 
 
6637 
(define_expand "ashrdi3"
6638 
  [(parallel
6639 
    [(set (match_operand:DI 0 "register_operand" "")
6640 
          (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6641 
                       (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
6642 
     (clobber (reg:CC CC_REGNUM))])]
6643 
  ""
6644 
  "")
6645 
 
6646 
(define_insn "*ashrdi3_cc_31"
6647 
  [(set (reg CC_REGNUM)
6648 
        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6649 
                              (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6650 
                 (const_int 0)))
6651 
   (set (match_operand:DI 0 "register_operand" "=d")
6652 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6653 
  "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6654 
  "srda\t%0,%Y2"
6655 
  [(set_attr "op_type"  "RS")
6656 
   (set_attr "atype"    "reg")])
6657 
 
6658 
(define_insn "*ashrdi3_cconly_31"
6659 
  [(set (reg CC_REGNUM)
6660 
        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6661 
                              (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6662 
                 (const_int 0)))
6663 
   (clobber (match_scratch:DI 0 "=d"))]
6664 
  "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6665 
  "srda\t%0,%Y2"
6666 
  [(set_attr "op_type"  "RS")
6667 
   (set_attr "atype"    "reg")])
6668 
 
6669 
(define_insn "*ashrdi3_31"
6670 
  [(set (match_operand:DI 0 "register_operand" "=d")
6671 
        (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6672 
                     (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6673 
   (clobber (reg:CC CC_REGNUM))]
6674 
  "!TARGET_64BIT"
6675 
  "srda\t%0,%Y2"
6676 
  [(set_attr "op_type"  "RS")
6677 
   (set_attr "atype"    "reg")])
6678 
 
6679 
(define_insn "*ashrdi3_cc_64"
6680 
  [(set (reg CC_REGNUM)
6681 
        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6682 
                              (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6683 
                 (const_int 0)))
6684 
   (set (match_operand:DI 0 "register_operand" "=d")
6685 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6686 
  "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6687 
  "srag\t%0,%1,%Y2"
6688 
  [(set_attr "op_type"  "RSE")
6689 
   (set_attr "atype"    "reg")])
6690 
 
6691 
(define_insn "*ashrdi3_cconly_64"
6692 
  [(set (reg CC_REGNUM)
6693 
        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6694 
                              (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6695 
                 (const_int 0)))
6696 
   (clobber (match_scratch:DI 0 "=d"))]
6697 
  "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6698 
  "srag\t%0,%1,%Y2"
6699 
  [(set_attr "op_type"  "RSE")
6700 
   (set_attr "atype"    "reg")])
6701 
 
6702 
(define_insn "*ashrdi3_64"
6703 
  [(set (match_operand:DI 0 "register_operand" "=d")
6704 
        (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6705 
                     (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6706 
   (clobber (reg:CC CC_REGNUM))]
6707 
  "TARGET_64BIT"
6708 
  "srag\t%0,%1,%Y2"
6709 
  [(set_attr "op_type"  "RSE")
6710 
   (set_attr "atype"    "reg")])
6711 
 
6712 
 
6713 
; shift pattern with implicit ANDs
6714 
 
6715 
(define_insn "*ashrdi3_cc_31_and"
6716 
  [(set (reg CC_REGNUM)
6717 
        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6718 
                              (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6719 
                                      (match_operand:SI 3 "const_int_operand"   "n")))
6720 
                 (const_int 0)))
6721 
   (set (match_operand:DI 0 "register_operand" "=d")
6722 
        (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6723 
  "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6724 
   && (INTVAL (operands[3]) & 63) == 63"
6725 
  "srda\t%0,%Y2"
6726 
  [(set_attr "op_type"  "RS")
6727 
   (set_attr "atype"    "reg")])
6728 
 
6729 
(define_insn "*ashrdi3_cconly_31_and"
6730 
  [(set (reg CC_REGNUM)
6731 
        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6732 
                              (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6733 
                                      (match_operand:SI 3 "const_int_operand"   "n")))
6734 
                 (const_int 0)))
6735 
   (clobber (match_scratch:DI 0 "=d"))]
6736 
  "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6737 
   && (INTVAL (operands[3]) & 63) == 63"
6738 
  "srda\t%0,%Y2"
6739 
  [(set_attr "op_type"  "RS")
6740 
   (set_attr "atype"    "reg")])
6741 
 
6742 
(define_insn "*ashrdi3_31_and"
6743 
  [(set (match_operand:DI 0 "register_operand" "=d")
6744 
        (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6745 
                     (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6746 
                             (match_operand:SI 3 "const_int_operand"   "n"))))
6747 
   (clobber (reg:CC CC_REGNUM))]
6748 
  "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6749 
  "srda\t%0,%Y2"
6750 
  [(set_attr "op_type"  "RS")
6751 
   (set_attr "atype"    "reg")])
6752 
 
6753 
(define_insn "*ashrdi3_cc_64_and"
6754 
  [(set (reg CC_REGNUM)
6755 
        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6756 
                              (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6757 
                                      (match_operand:SI 3 "const_int_operand"   "n")))
6758 
                 (const_int 0)))
6759 
   (set (match_operand:DI 0 "register_operand" "=d")
6760 
        (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6761 
  "TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6762 
   && (INTVAL (operands[3]) & 63) == 63"
6763 
  "srag\t%0,%1,%Y2"
6764 
  [(set_attr "op_type"  "RSE")
6765 
   (set_attr "atype"    "reg")])
6766 
 
6767 
(define_insn "*ashrdi3_cconly_64_and"
6768 
  [(set (reg CC_REGNUM)
6769 
        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6770 
                              (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6771 
                                      (match_operand:SI 3 "const_int_operand"   "n")))
6772 
                 (const_int 0)))
6773 
   (clobber (match_scratch:DI 0 "=d"))]
6774 
  "TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6775 
   && (INTVAL (operands[3]) & 63) == 63"
6776 
  "srag\t%0,%1,%Y2"
6777 
  [(set_attr "op_type"  "RSE")
6778 
   (set_attr "atype"    "reg")])
6779 
 
6780 
(define_insn "*ashrdi3_64_and"
6781 
  [(set (match_operand:DI 0 "register_operand" "=d")
6782 
        (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6783 
                     (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6784 
                             (match_operand:SI 3 "const_int_operand"   "n"))))
6785 
   (clobber (reg:CC CC_REGNUM))]
6786 
  "TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6787 
  "srag\t%0,%1,%Y2"
6788 
  [(set_attr "op_type"  "RSE")
6789 
   (set_attr "atype"    "reg")])
6790 
 
6791 
;
6792 
; (ashl|lshr)si3 instruction pattern(s).
6793 
;
6794 
 
6795 
(define_insn "si3"
6796 
  [(set (match_operand:SI 0 "register_operand" "=d")
6797 
        (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
6798 
                  (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6799 
  ""
6800 
  "sl\t%0,%Y2"
6801 
  [(set_attr "op_type"  "RS")
6802 
   (set_attr "atype"    "reg")])
6803 
 
6804 
(define_insn "*si3_and"
6805 
  [(set (match_operand:SI 0 "register_operand" "=d")
6806 
        (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
6807 
                  (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6808 
                          (match_operand:SI 3 "const_int_operand"   "n"))))]
6809 
  "(INTVAL (operands[3]) & 63) == 63"
6810 
  "sl\t%0,%Y2"
6811 
  [(set_attr "op_type"  "RS")
6812 
   (set_attr "atype"    "reg")])
6813 
 
6814 
;
6815 
; ashrsi3 instruction pattern(s).
6816 
;
6817 
 
6818 
(define_insn "*ashrsi3_cc"
6819 
  [(set (reg CC_REGNUM)
6820 
        (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6821 
                              (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6822 
                 (const_int 0)))
6823 
   (set (match_operand:SI 0 "register_operand" "=d")
6824 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6825 
  "s390_match_ccmode(insn, CCSmode)"
6826 
  "sra\t%0,%Y2"
6827 
  [(set_attr "op_type"  "RS")
6828 
   (set_attr "atype"    "reg")])
6829 
 
6830 
 
6831 
(define_insn "*ashrsi3_cconly"
6832 
  [(set (reg CC_REGNUM)
6833 
        (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6834 
                              (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6835 
                 (const_int 0)))
6836 
   (clobber (match_scratch:SI 0 "=d"))]
6837 
  "s390_match_ccmode(insn, CCSmode)"
6838 
  "sra\t%0,%Y2"
6839 
  [(set_attr "op_type"  "RS")
6840 
   (set_attr "atype"    "reg")])
6841 
 
6842 
(define_insn "ashrsi3"
6843 
  [(set (match_operand:SI 0 "register_operand" "=d")
6844 
        (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6845 
                     (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6846 
   (clobber (reg:CC CC_REGNUM))]
6847 
  ""
6848 
  "sra\t%0,%Y2"
6849 
  [(set_attr "op_type"  "RS")
6850 
   (set_attr "atype"    "reg")])
6851 
 
6852 
; with implicit ANDs
6853 
 
6854 
(define_insn "*ashrsi3_cc_and"
6855 
  [(set (reg CC_REGNUM)
6856 
        (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6857 
                              (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6858 
                                      (match_operand:SI 3 "const_int_operand"   "n")))
6859 
                 (const_int 0)))
6860 
   (set (match_operand:SI 0 "register_operand" "=d")
6861 
        (ashiftrt:SI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6862 
  "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6863 
  "sra\t%0,%Y2"
6864 
  [(set_attr "op_type"  "RS")
6865 
   (set_attr "atype"    "reg")])
6866 
 
6867 
 
6868 
(define_insn "*ashrsi3_cconly_and"
6869 
  [(set (reg CC_REGNUM)
6870 
        (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6871 
                              (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6872 
                                      (match_operand:SI 3 "const_int_operand"   "n")))
6873 
                 (const_int 0)))
6874 
   (clobber (match_scratch:SI 0 "=d"))]
6875 
  "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6876 
  "sra\t%0,%Y2"
6877 
  [(set_attr "op_type"  "RS")
6878 
   (set_attr "atype"    "reg")])
6879 
 
6880 
(define_insn "*ashrsi3_and"
6881 
  [(set (match_operand:SI 0 "register_operand" "=d")
6882 
        (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6883 
                     (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6884 
                             (match_operand:SI 3 "const_int_operand"   "n"))))
6885 
   (clobber (reg:CC CC_REGNUM))]
6886 
  "(INTVAL (operands[3]) & 63) == 63"
6887 
  "sra\t%0,%Y2"
6888 
  [(set_attr "op_type"  "RS")
6889 
   (set_attr "atype"    "reg")])
6890 
 
6891 
 
6892 
;;
6893 
;; Branch instruction patterns.
6894 
;;
6895 
 
6896 
(define_expand "b"
6897 
  [(set (pc)
6898 
        (if_then_else (COMPARE (match_operand 0 "" "")
6899 
                               (const_int 0))
6900 
                      (match_dup 0)
6901 
                      (pc)))]
6902 
  ""
6903 
  "s390_emit_jump (operands[0],
6904 
    s390_emit_compare (, s390_compare_op0, s390_compare_op1)); DONE;")
6905 
 
6906 
 
6907 
;;
6908 
;;- Conditional jump instructions.
6909 
;;
6910 
 
6911 
(define_insn "*cjump_64"
6912 
  [(set (pc)
6913 
        (if_then_else
6914 
          (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6915 
          (label_ref (match_operand 0 "" ""))
6916 
          (pc)))]
6917 
  "TARGET_CPU_ZARCH"
6918 
{
6919 
  if (get_attr_length (insn) == 4)
6920 
    return "j%C1\t%l0";
6921 
  else
6922 
    return "jg%C1\t%l0";
6923 
}
6924 
  [(set_attr "op_type" "RI")
6925 
   (set_attr "type"    "branch")
6926 
   (set (attr "length")
6927 
        (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6928 
                      (const_int 4) (const_int 6)))])
6929 
 
6930 
(define_insn "*cjump_31"
6931 
  [(set (pc)
6932 
        (if_then_else
6933 
          (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6934 
          (label_ref (match_operand 0 "" ""))
6935 
          (pc)))]
6936 
  "!TARGET_CPU_ZARCH"
6937 
{
6938 
  gcc_assert (get_attr_length (insn) == 4);
6939 
  return "j%C1\t%l0";
6940 
}
6941 
  [(set_attr "op_type" "RI")
6942 
   (set_attr "type"    "branch")
6943 
   (set (attr "length")
6944 
        (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6945 
          (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6946 
                        (const_int 4) (const_int 6))
6947 
          (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6948 
                        (const_int 4) (const_int 8))))])
6949 
 
6950 
(define_insn "*cjump_long"
6951 
  [(set (pc)
6952 
        (if_then_else
6953 
          (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6954 
          (match_operand 0 "address_operand" "U")
6955 
          (pc)))]
6956 
  ""
6957 
{
6958 
  if (get_attr_op_type (insn) == OP_TYPE_RR)
6959 
    return "b%C1r\t%0";
6960 
  else
6961 
    return "b%C1\t%a0";
6962 
}
6963 
  [(set (attr "op_type")
6964 
        (if_then_else (match_operand 0 "register_operand" "")
6965 
                      (const_string "RR") (const_string "RX")))
6966 
   (set_attr "type"  "branch")
6967 
   (set_attr "atype" "agen")])
6968 
 
6969 
 
6970 
;;
6971 
;;- Negated conditional jump instructions.
6972 
;;
6973 
 
6974 
(define_insn "*icjump_64"
6975 
  [(set (pc)
6976 
        (if_then_else
6977 
          (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6978 
          (pc)
6979 
          (label_ref (match_operand 0 "" ""))))]
6980 
  "TARGET_CPU_ZARCH"
6981 
{
6982 
  if (get_attr_length (insn) == 4)
6983 
    return "j%D1\t%l0";
6984 
  else
6985 
    return "jg%D1\t%l0";
6986 
}
6987 
  [(set_attr "op_type" "RI")
6988 
   (set_attr "type"    "branch")
6989 
   (set (attr "length")
6990 
        (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6991 
                      (const_int 4) (const_int 6)))])
6992 
 
6993 
(define_insn "*icjump_31"
6994 
  [(set (pc)
6995 
        (if_then_else
6996 
          (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6997 
          (pc)
6998 
          (label_ref (match_operand 0 "" ""))))]
6999 
  "!TARGET_CPU_ZARCH"
7000 
{
7001 
  gcc_assert (get_attr_length (insn) == 4);
7002 
  return "j%D1\t%l0";
7003 
}
7004 
  [(set_attr "op_type" "RI")
7005 
   (set_attr "type"    "branch")
7006 
   (set (attr "length")
7007 
        (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7008 
          (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7009 
                        (const_int 4) (const_int 6))
7010 
          (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7011 
                        (const_int 4) (const_int 8))))])
7012 
 
7013 
(define_insn "*icjump_long"
7014 
  [(set (pc)
7015 
        (if_then_else
7016 
          (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7017 
          (pc)
7018 
          (match_operand 0 "address_operand" "U")))]
7019 
  ""
7020 
{
7021 
  if (get_attr_op_type (insn) == OP_TYPE_RR)
7022 
    return "b%D1r\t%0";
7023 
  else
7024 
    return "b%D1\t%a0";
7025 
}
7026 
  [(set (attr "op_type")
7027 
        (if_then_else (match_operand 0 "register_operand" "")
7028 
                      (const_string "RR") (const_string "RX")))
7029 
   (set_attr "type"  "branch")
7030 
   (set_attr "atype" "agen")])
7031 
 
7032 
;;
7033 
;;- Trap instructions.
7034 
;;
7035 
 
7036 
(define_insn "trap"
7037 
  [(trap_if (const_int 1) (const_int 0))]
7038 
  ""
7039 
  "j\t.+2"
7040 
  [(set_attr "op_type" "RI")
7041 
   (set_attr "type"  "branch")])
7042 
 
7043 
(define_expand "conditional_trap"
7044 
  [(trap_if (match_operand 0 "comparison_operator" "")
7045 
            (match_operand 1 "general_operand" ""))]
7046 
  ""
7047 
{
7048 
  if (operands[1] != const0_rtx) FAIL;
7049 
  operands[0] = s390_emit_compare (GET_CODE (operands[0]),
7050 
                                   s390_compare_op0, s390_compare_op1);
7051 
})
7052 
 
7053 
(define_insn "*trap"
7054 
  [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7055 
            (const_int 0))]
7056 
  ""
7057 
  "j%C0\t.+2";
7058 
  [(set_attr "op_type" "RI")
7059 
   (set_attr "type"  "branch")])
7060 
 
7061 
;;
7062 
;;- Loop instructions.
7063 
;;
7064 
;;  This is all complicated by the fact that since this is a jump insn
7065 
;;  we must handle our own output reloads.
7066 
 
7067 
(define_expand "doloop_end"
7068 
  [(use (match_operand 0 "" ""))        ; loop pseudo
7069 
   (use (match_operand 1 "" ""))        ; iterations; zero if unknown
7070 
   (use (match_operand 2 "" ""))        ; max iterations
7071 
   (use (match_operand 3 "" ""))        ; loop level
7072 
   (use (match_operand 4 "" ""))]       ; label
7073 
  ""
7074 
{
7075 
  if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7076 
    emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7077 
  else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7078 
    emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7079 
  else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7080 
    emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7081 
  else
7082 
    FAIL;
7083 
 
7084 
  DONE;
7085 
})
7086 
 
7087 
(define_insn_and_split "doloop_si64"
7088 
  [(set (pc)
7089 
        (if_then_else
7090 
          (ne (match_operand:SI 1 "register_operand" "d,d")
7091 
              (const_int 1))
7092 
          (label_ref (match_operand 0 "" ""))
7093 
          (pc)))
7094 
   (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7095 
        (plus:SI (match_dup 1) (const_int -1)))
7096 
   (clobber (match_scratch:SI 3 "=X,&1"))
7097 
   (clobber (reg:CC CC_REGNUM))]
7098 
  "TARGET_CPU_ZARCH"
7099 
{
7100 
  if (which_alternative != 0)
7101 
    return "#";
7102 
  else if (get_attr_length (insn) == 4)
7103 
    return "brct\t%1,%l0";
7104 
  else
7105 
    return "ahi\t%1,-1\;jgne\t%l0";
7106 
}
7107 
  "&& reload_completed
7108 
   && (! REG_P (operands[2])
7109 
       || ! rtx_equal_p (operands[1], operands[2]))"
7110 
  [(parallel [(set (reg:CCAN CC_REGNUM)
7111 
                   (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7112 
                                 (const_int 0)))
7113 
              (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7114 
   (set (match_dup 2) (match_dup 3))
7115 
   (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7116 
                           (label_ref (match_dup 0))
7117 
                           (pc)))]
7118 
  ""
7119 
  [(set_attr "op_type"  "RI")
7120 
   (set_attr "type"  "branch")
7121 
   (set (attr "length")
7122 
        (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7123 
                      (const_int 4) (const_int 10)))])
7124 
 
7125 
(define_insn_and_split "doloop_si31"
7126 
  [(set (pc)
7127 
        (if_then_else
7128 
          (ne (match_operand:SI 1 "register_operand" "d,d")
7129 
              (const_int 1))
7130 
          (label_ref (match_operand 0 "" ""))
7131 
          (pc)))
7132 
   (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7133 
        (plus:SI (match_dup 1) (const_int -1)))
7134 
   (clobber (match_scratch:SI 3 "=X,&1"))
7135 
   (clobber (reg:CC CC_REGNUM))]
7136 
  "!TARGET_CPU_ZARCH"
7137 
{
7138 
  if (which_alternative != 0)
7139 
    return "#";
7140 
  else if (get_attr_length (insn) == 4)
7141 
    return "brct\t%1,%l0";
7142 
  else
7143 
    gcc_unreachable ();
7144 
}
7145 
  "&& reload_completed
7146 
   && (! REG_P (operands[2])
7147 
       || ! rtx_equal_p (operands[1], operands[2]))"
7148 
  [(parallel [(set (reg:CCAN CC_REGNUM)
7149 
                   (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7150 
                                 (const_int 0)))
7151 
              (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7152 
   (set (match_dup 2) (match_dup 3))
7153 
   (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7154 
                           (label_ref (match_dup 0))
7155 
                           (pc)))]
7156 
  ""
7157 
  [(set_attr "op_type"  "RI")
7158 
   (set_attr "type"  "branch")
7159 
   (set (attr "length")
7160 
        (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7161 
          (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7162 
                        (const_int 4) (const_int 6))
7163 
          (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7164 
                        (const_int 4) (const_int 8))))])
7165 
 
7166 
(define_insn "*doloop_si_long"
7167 
  [(set (pc)
7168 
        (if_then_else
7169 
          (ne (match_operand:SI 1 "register_operand" "d,d")
7170 
              (const_int 1))
7171 
          (match_operand 0 "address_operand" "U,U")
7172 
          (pc)))
7173 
   (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
7174 
        (plus:SI (match_dup 1) (const_int -1)))
7175 
   (clobber (match_scratch:SI 3 "=X,&1"))
7176 
   (clobber (reg:CC CC_REGNUM))]
7177 
  "!TARGET_CPU_ZARCH"
7178 
{
7179 
  if (get_attr_op_type (insn) == OP_TYPE_RR)
7180 
    return "bctr\t%1,%0";
7181 
  else
7182 
    return "bct\t%1,%a0";
7183 
}
7184 
  [(set (attr "op_type")
7185 
        (if_then_else (match_operand 0 "register_operand" "")
7186 
                      (const_string "RR") (const_string "RX")))
7187 
   (set_attr "type"  "branch")
7188 
   (set_attr "atype" "agen")])
7189 
 
7190 
(define_insn_and_split "doloop_di"
7191 
  [(set (pc)
7192 
        (if_then_else
7193 
          (ne (match_operand:DI 1 "register_operand" "d,d")
7194 
              (const_int 1))
7195 
          (label_ref (match_operand 0 "" ""))
7196 
          (pc)))
7197 
   (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
7198 
        (plus:DI (match_dup 1) (const_int -1)))
7199 
   (clobber (match_scratch:DI 3 "=X,&1"))
7200 
   (clobber (reg:CC CC_REGNUM))]
7201 
  "TARGET_64BIT"
7202 
{
7203 
  if (which_alternative != 0)
7204 
    return "#";
7205 
  else if (get_attr_length (insn) == 4)
7206 
    return "brctg\t%1,%l0";
7207 
  else
7208 
    return "aghi\t%1,-1\;jgne\t%l0";
7209 
}
7210 
  "&& reload_completed
7211 
   && (! REG_P (operands[2])
7212 
       || ! rtx_equal_p (operands[1], operands[2]))"
7213 
  [(parallel [(set (reg:CCAN CC_REGNUM)
7214 
                   (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7215 
                                 (const_int 0)))
7216 
              (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7217 
   (set (match_dup 2) (match_dup 3))
7218 
   (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7219 
                           (label_ref (match_dup 0))
7220 
                           (pc)))]
7221 
  ""
7222 
  [(set_attr "op_type"  "RI")
7223 
   (set_attr "type"  "branch")
7224 
   (set (attr "length")
7225 
        (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7226 
                      (const_int 4) (const_int 10)))])
7227 
 
7228 
;;
7229 
;;- Unconditional jump instructions.
7230 
;;
7231 
 
7232 
;
7233 
; jump instruction pattern(s).
7234 
;
7235 
 
7236 
(define_expand "jump"
7237 
  [(match_operand 0 "" "")]
7238 
  ""
7239 
  "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7240 
 
7241 
(define_insn "*jump64"
7242 
  [(set (pc) (label_ref (match_operand 0 "" "")))]
7243 
  "TARGET_CPU_ZARCH"
7244 
{
7245 
  if (get_attr_length (insn) == 4)
7246 
    return "j\t%l0";
7247 
  else
7248 
    return "jg\t%l0";
7249 
}
7250 
  [(set_attr "op_type" "RI")
7251 
   (set_attr "type"  "branch")
7252 
   (set (attr "length")
7253 
        (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7254 
                      (const_int 4) (const_int 6)))])
7255 
 
7256 
(define_insn "*jump31"
7257 
  [(set (pc) (label_ref (match_operand 0 "" "")))]
7258 
  "!TARGET_CPU_ZARCH"
7259 
{
7260 
  gcc_assert (get_attr_length (insn) == 4);
7261 
  return "j\t%l0";
7262 
}
7263 
  [(set_attr "op_type" "RI")
7264 
   (set_attr "type"  "branch")
7265 
   (set (attr "length")
7266 
        (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7267 
          (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7268 
                        (const_int 4) (const_int 6))
7269 
          (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7270 
                        (const_int 4) (const_int 8))))])
7271 
 
7272 
;
7273 
; indirect-jump instruction pattern(s).
7274 
;
7275 
 
7276 
(define_insn "indirect_jump"
7277 
 [(set (pc) (match_operand 0 "address_operand" "U"))]
7278 
  ""
7279 
{
7280 
  if (get_attr_op_type (insn) == OP_TYPE_RR)
7281 
    return "br\t%0";
7282 
  else
7283 
    return "b\t%a0";
7284 
}
7285 
  [(set (attr "op_type")
7286 
        (if_then_else (match_operand 0 "register_operand" "")
7287 
                      (const_string "RR") (const_string "RX")))
7288 
   (set_attr "type"  "branch")
7289 
   (set_attr "atype" "agen")])
7290 
 
7291 
;
7292 
; casesi instruction pattern(s).
7293 
;
7294 
 
7295 
(define_insn "casesi_jump"
7296 
 [(set (pc) (match_operand 0 "address_operand" "U"))
7297 
   (use (label_ref (match_operand 1 "" "")))]
7298 
  ""
7299 
{
7300 
  if (get_attr_op_type (insn) == OP_TYPE_RR)
7301 
    return "br\t%0";
7302 
  else
7303 
    return "b\t%a0";
7304 
}
7305 
  [(set (attr "op_type")
7306 
        (if_then_else (match_operand 0 "register_operand" "")
7307 
                      (const_string "RR") (const_string "RX")))
7308 
   (set_attr "type"  "branch")
7309 
   (set_attr "atype" "agen")])
7310 
 
7311 
(define_expand "casesi"
7312 
  [(match_operand:SI 0 "general_operand" "")
7313 
   (match_operand:SI 1 "general_operand" "")
7314 
   (match_operand:SI 2 "general_operand" "")
7315 
   (label_ref (match_operand 3 "" ""))
7316 
   (label_ref (match_operand 4 "" ""))]
7317 
  ""
7318 
{
7319 
   rtx index  = gen_reg_rtx (SImode);
7320 
   rtx base   = gen_reg_rtx (Pmode);
7321 
   rtx target = gen_reg_rtx (Pmode);
7322 
 
7323 
   emit_move_insn (index, operands[0]);
7324 
   emit_insn (gen_subsi3 (index, index, operands[1]));
7325 
   emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7326 
                            operands[4]);
7327 
 
7328 
   if (Pmode != SImode)
7329 
     index = convert_to_mode (Pmode, index, 1);
7330 
   if (GET_CODE (index) != REG)
7331 
     index = copy_to_mode_reg (Pmode, index);
7332 
 
7333 
   if (TARGET_64BIT)
7334 
       emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7335 
   else
7336 
       emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7337 
 
7338 
   emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7339 
 
7340 
   index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7341 
   emit_move_insn (target, index);
7342 
 
7343 
   if (flag_pic)
7344 
     target = gen_rtx_PLUS (Pmode, base, target);
7345 
   emit_jump_insn (gen_casesi_jump (target, operands[3]));
7346 
 
7347 
   DONE;
7348 
})
7349 
 
7350 
 
7351 
;;
7352 
;;- Jump to subroutine.
7353 
;;
7354 
;;
7355 
 
7356 
;
7357 
; untyped call instruction pattern(s).
7358 
;
7359 
 
7360 
;; Call subroutine returning any type.
7361 
(define_expand "untyped_call"
7362 
  [(parallel [(call (match_operand 0 "" "")
7363 
                    (const_int 0))
7364 
              (match_operand 1 "" "")
7365 
              (match_operand 2 "" "")])]
7366 
  ""
7367 
{
7368 
  int i;
7369 
 
7370 
  emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7371 
 
7372 
  for (i = 0; i < XVECLEN (operands[2], 0); i++)
7373 
    {
7374 
      rtx set = XVECEXP (operands[2], 0, i);
7375 
      emit_move_insn (SET_DEST (set), SET_SRC (set));
7376 
    }
7377 
 
7378 
  /* The optimizer does not know that the call sets the function value
7379 
     registers we stored in the result block.  We avoid problems by
7380 
     claiming that all hard registers are used and clobbered at this
7381 
     point.  */
7382 
  emit_insn (gen_blockage ());
7383 
 
7384 
  DONE;
7385 
})
7386 
 
7387 
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7388 
;; all of memory.  This blocks insns from being moved across this point.
7389 
 
7390 
(define_insn "blockage"
7391 
  [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7392 
  ""
7393 
  ""
7394 
  [(set_attr "type"    "none")
7395 
   (set_attr "length"  "0")])
7396 
 
7397 
;
7398 
; sibcall patterns
7399 
;
7400 
 
7401 
(define_expand "sibcall"
7402 
  [(call (match_operand 0 "" "")
7403 
         (match_operand 1 "" ""))]
7404 
  ""
7405 
{
7406 
  s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7407 
  DONE;
7408 
})
7409 
 
7410 
(define_insn "*sibcall_br"
7411 
  [(call (mem:QI (reg SIBCALL_REGNUM))
7412 
         (match_operand 0 "const_int_operand" "n"))]
7413 
  "SIBLING_CALL_P (insn)
7414 
   && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7415 
  "br\t%%r1"
7416 
  [(set_attr "op_type" "RR")
7417 
   (set_attr "type"  "branch")
7418 
   (set_attr "atype" "agen")])
7419 
 
7420 
(define_insn "*sibcall_brc"
7421 
  [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7422 
         (match_operand 1 "const_int_operand" "n"))]
7423 
  "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7424 
  "j\t%0"
7425 
  [(set_attr "op_type" "RI")
7426 
   (set_attr "type"    "branch")])
7427 
 
7428 
(define_insn "*sibcall_brcl"
7429 
  [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7430 
         (match_operand 1 "const_int_operand" "n"))]
7431 
  "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7432 
  "jg\t%0"
7433 
  [(set_attr "op_type" "RIL")
7434 
   (set_attr "type"    "branch")])
7435 
 
7436 
;
7437 
; sibcall_value patterns
7438 
;
7439 
 
7440 
(define_expand "sibcall_value"
7441 
  [(set (match_operand 0 "" "")
7442 
        (call (match_operand 1 "" "")
7443 
              (match_operand 2 "" "")))]
7444 
  ""
7445 
{
7446 
  s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7447 
  DONE;
7448 
})
7449 
 
7450 
(define_insn "*sibcall_value_br"
7451 
  [(set (match_operand 0 "" "")
7452 
        (call (mem:QI (reg SIBCALL_REGNUM))
7453 
              (match_operand 1 "const_int_operand" "n")))]
7454 
  "SIBLING_CALL_P (insn)
7455 
   && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7456 
  "br\t%%r1"
7457 
  [(set_attr "op_type" "RR")
7458 
   (set_attr "type"  "branch")
7459 
   (set_attr "atype" "agen")])
7460 
 
7461 
(define_insn "*sibcall_value_brc"
7462 
  [(set (match_operand 0 "" "")
7463 
        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7464 
              (match_operand 2 "const_int_operand" "n")))]
7465 
  "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7466 
  "j\t%1"
7467 
  [(set_attr "op_type" "RI")
7468 
   (set_attr "type"    "branch")])
7469 
 
7470 
(define_insn "*sibcall_value_brcl"
7471 
  [(set (match_operand 0 "" "")
7472 
        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7473 
              (match_operand 2 "const_int_operand" "n")))]
7474 
  "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7475 
  "jg\t%1"
7476 
  [(set_attr "op_type" "RIL")
7477 
   (set_attr "type"    "branch")])
7478 
 
7479 
 
7480 
;
7481 
; call instruction pattern(s).
7482 
;
7483 
 
7484 
(define_expand "call"
7485 
  [(call (match_operand 0 "" "")
7486 
         (match_operand 1 "" ""))
7487 
   (use (match_operand 2 "" ""))]
7488 
  ""
7489 
{
7490 
  s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7491 
                  gen_rtx_REG (Pmode, RETURN_REGNUM));
7492 
  DONE;
7493 
})
7494 
 
7495 
(define_insn "*bras"
7496 
  [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7497 
         (match_operand 1 "const_int_operand" "n"))
7498 
   (clobber (match_operand 2 "register_operand" "=r"))]
7499 
  "!SIBLING_CALL_P (insn)
7500 
   && TARGET_SMALL_EXEC
7501 
   && GET_MODE (operands[2]) == Pmode"
7502 
  "bras\t%2,%0"
7503 
  [(set_attr "op_type" "RI")
7504 
   (set_attr "type"    "jsr")])
7505 
 
7506 
(define_insn "*brasl"
7507 
  [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7508 
         (match_operand 1 "const_int_operand" "n"))
7509 
   (clobber (match_operand 2 "register_operand" "=r"))]
7510 
  "!SIBLING_CALL_P (insn)
7511 
   && TARGET_CPU_ZARCH
7512 
   && GET_MODE (operands[2]) == Pmode"
7513 
  "brasl\t%2,%0"
7514 
  [(set_attr "op_type" "RIL")
7515 
   (set_attr "type"    "jsr")])
7516 
 
7517 
(define_insn "*basr"
7518 
  [(call (mem:QI (match_operand 0 "address_operand" "U"))
7519 
         (match_operand 1 "const_int_operand" "n"))
7520 
   (clobber (match_operand 2 "register_operand" "=r"))]
7521 
  "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7522 
{
7523 
  if (get_attr_op_type (insn) == OP_TYPE_RR)
7524 
    return "basr\t%2,%0";
7525 
  else
7526 
    return "bas\t%2,%a0";
7527 
}
7528 
  [(set (attr "op_type")
7529 
        (if_then_else (match_operand 0 "register_operand" "")
7530 
                      (const_string "RR") (const_string "RX")))
7531 
   (set_attr "type"  "jsr")
7532 
   (set_attr "atype" "agen")])
7533 
 
7534 
;
7535 
; call_value instruction pattern(s).
7536 
;
7537 
 
7538 
(define_expand "call_value"
7539 
  [(set (match_operand 0 "" "")
7540 
        (call (match_operand 1 "" "")
7541 
              (match_operand 2 "" "")))
7542 
   (use (match_operand 3 "" ""))]
7543 
  ""
7544 
{
7545 
  s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7546 
                  gen_rtx_REG (Pmode, RETURN_REGNUM));
7547 
  DONE;
7548 
})
7549 
 
7550 
(define_insn "*bras_r"
7551 
  [(set (match_operand 0 "" "")
7552 
        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7553 
              (match_operand:SI 2 "const_int_operand" "n")))
7554 
   (clobber (match_operand 3 "register_operand" "=r"))]
7555 
  "!SIBLING_CALL_P (insn)
7556 
   && TARGET_SMALL_EXEC
7557 
   && GET_MODE (operands[3]) == Pmode"
7558 
  "bras\t%3,%1"
7559 
  [(set_attr "op_type" "RI")
7560 
   (set_attr "type"    "jsr")])
7561 
 
7562 
(define_insn "*brasl_r"
7563 
  [(set (match_operand 0 "" "")
7564 
        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7565 
              (match_operand 2 "const_int_operand" "n")))
7566 
   (clobber (match_operand 3 "register_operand" "=r"))]
7567 
  "!SIBLING_CALL_P (insn)
7568 
   && TARGET_CPU_ZARCH
7569 
   && GET_MODE (operands[3]) == Pmode"
7570 
  "brasl\t%3,%1"
7571 
  [(set_attr "op_type" "RIL")
7572 
   (set_attr "type"    "jsr")])
7573 
 
7574 
(define_insn "*basr_r"
7575 
  [(set (match_operand 0 "" "")
7576 
        (call (mem:QI (match_operand 1 "address_operand" "U"))
7577 
              (match_operand 2 "const_int_operand" "n")))
7578 
   (clobber (match_operand 3 "register_operand" "=r"))]
7579 
  "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7580 
{
7581 
  if (get_attr_op_type (insn) == OP_TYPE_RR)
7582 
    return "basr\t%3,%1";
7583 
  else
7584 
    return "bas\t%3,%a1";
7585 
}
7586 
  [(set (attr "op_type")
7587 
        (if_then_else (match_operand 1 "register_operand" "")
7588 
                      (const_string "RR") (const_string "RX")))
7589 
   (set_attr "type"  "jsr")
7590 
   (set_attr "atype" "agen")])
7591 
 
7592 
;;
7593 
;;- Thread-local storage support.
7594 
;;
7595 
 
7596 
(define_expand "get_tp_64"
7597 
  [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7598 
  "TARGET_64BIT"
7599 
  "")
7600 
 
7601 
(define_expand "get_tp_31"
7602 
  [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7603 
  "!TARGET_64BIT"
7604 
  "")
7605 
 
7606 
(define_expand "set_tp_64"
7607 
  [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7608 
   (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7609 
  "TARGET_64BIT"
7610 
  "")
7611 
 
7612 
(define_expand "set_tp_31"
7613 
  [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7614 
   (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7615 
  "!TARGET_64BIT"
7616 
  "")
7617 
 
7618 
(define_insn "*set_tp"
7619 
  [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7620 
  ""
7621 
  ""
7622 
  [(set_attr "type" "none")
7623 
   (set_attr "length" "0")])
7624 
 
7625 
(define_insn "*tls_load_64"
7626 
  [(set (match_operand:DI 0 "register_operand" "=d")
7627 
        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7628 
                    (match_operand:DI 2 "" "")]
7629 
                   UNSPEC_TLS_LOAD))]
7630 
  "TARGET_64BIT"
7631 
  "lg\t%0,%1%J2"
7632 
  [(set_attr "op_type" "RXE")])
7633 
 
7634 
(define_insn "*tls_load_31"
7635 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
7636 
        (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7637 
                    (match_operand:SI 2 "" "")]
7638 
                   UNSPEC_TLS_LOAD))]
7639 
  "!TARGET_64BIT"
7640 
  "@
7641 
   l\t%0,%1%J2
7642 
   ly\t%0,%1%J2"
7643 
  [(set_attr "op_type" "RX,RXY")])
7644 
 
7645 
(define_insn "*bras_tls"
7646 
  [(set (match_operand 0 "" "")
7647 
        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7648 
              (match_operand 2 "const_int_operand" "n")))
7649 
   (clobber (match_operand 3 "register_operand" "=r"))
7650 
   (use (match_operand 4 "" ""))]
7651 
  "!SIBLING_CALL_P (insn)
7652 
   && TARGET_SMALL_EXEC
7653 
   && GET_MODE (operands[3]) == Pmode"
7654 
  "bras\t%3,%1%J4"
7655 
  [(set_attr "op_type" "RI")
7656 
   (set_attr "type"    "jsr")])
7657 
 
7658 
(define_insn "*brasl_tls"
7659 
  [(set (match_operand 0 "" "")
7660 
        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7661 
              (match_operand 2 "const_int_operand" "n")))
7662 
   (clobber (match_operand 3 "register_operand" "=r"))
7663 
   (use (match_operand 4 "" ""))]
7664 
  "!SIBLING_CALL_P (insn)
7665 
   && TARGET_CPU_ZARCH
7666 
   && GET_MODE (operands[3]) == Pmode"
7667 
  "brasl\t%3,%1%J4"
7668 
  [(set_attr "op_type" "RIL")
7669 
   (set_attr "type"    "jsr")])
7670 
 
7671 
(define_insn "*basr_tls"
7672 
  [(set (match_operand 0 "" "")
7673 
        (call (mem:QI (match_operand 1 "address_operand" "U"))
7674 
              (match_operand 2 "const_int_operand" "n")))
7675 
   (clobber (match_operand 3 "register_operand" "=r"))
7676 
   (use (match_operand 4 "" ""))]
7677 
  "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7678 
{
7679 
  if (get_attr_op_type (insn) == OP_TYPE_RR)
7680 
    return "basr\t%3,%1%J4";
7681 
  else
7682 
    return "bas\t%3,%a1%J4";
7683 
}
7684 
  [(set (attr "op_type")
7685 
        (if_then_else (match_operand 1 "register_operand" "")
7686 
                      (const_string "RR") (const_string "RX")))
7687 
   (set_attr "type"  "jsr")
7688 
   (set_attr "atype" "agen")])
7689 
 
7690 
;;
7691 
;;- Atomic operations
7692 
;;
7693 
 
7694 
;
7695 
; memory barrier pattern.
7696 
;
7697 
 
7698 
(define_expand "memory_barrier"
7699 
  [(set (mem:BLK (match_dup 0))
7700 
        (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7701 
  ""
7702 
{
7703 
  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7704 
  MEM_VOLATILE_P (operands[0]) = 1;
7705 
})
7706 
 
7707 
(define_insn "*memory_barrier"
7708 
  [(set (match_operand:BLK 0 "" "")
7709 
        (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7710 
  ""
7711 
  "bcr\t15,0"
7712 
  [(set_attr "op_type" "RR")])
7713 
 
7714 
;
7715 
; compare and swap patterns.
7716 
;
7717 
 
7718 
(define_expand "sync_compare_and_swap"
7719 
  [(parallel
7720 
    [(set (match_operand:TDSI 0 "register_operand" "")
7721 
          (match_operand:TDSI 1 "memory_operand" ""))
7722 
     (set (match_dup 1)
7723 
          (unspec_volatile:TDSI
7724 
            [(match_dup 1)
7725 
             (match_operand:TDSI 2 "register_operand" "")
7726 
             (match_operand:TDSI 3 "register_operand" "")]
7727 
            UNSPECV_CAS))
7728 
     (set (reg:CCZ1 CC_REGNUM)
7729 
          (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7730 
  "")
7731 
 
7732 
(define_expand "sync_compare_and_swap"
7733 
  [(parallel
7734 
    [(set (match_operand:HQI 0 "register_operand" "")
7735 
          (match_operand:HQI 1 "memory_operand" ""))
7736 
     (set (match_dup 1)
7737 
          (unspec_volatile:HQI
7738 
            [(match_dup 1)
7739 
             (match_operand:HQI 2 "general_operand" "")
7740 
             (match_operand:HQI 3 "general_operand" "")]
7741 
            UNSPECV_CAS))
7742 
     (set (reg:CCZ1 CC_REGNUM)
7743 
          (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7744 
  ""
7745 
  "s390_expand_cs_hqi (mode, operands[0], operands[1],
7746 
                       operands[2], operands[3]); DONE;")
7747 
 
7748 
(define_expand "sync_compare_and_swap_cc"
7749 
  [(parallel
7750 
    [(set (match_operand:TDSI 0 "register_operand" "")
7751 
          (match_operand:TDSI 1 "memory_operand" ""))
7752 
     (set (match_dup 1)
7753 
          (unspec_volatile:TDSI
7754 
            [(match_dup 1)
7755 
             (match_operand:TDSI 2 "register_operand" "")
7756 
             (match_operand:TDSI 3 "register_operand" "")]
7757 
            UNSPECV_CAS))
7758 
     (set (match_dup 4)
7759 
          (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7760 
  ""
7761 
{
7762 
  /* Emulate compare.  */
7763 
  operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7764 
  s390_compare_op0 = operands[1];
7765 
  s390_compare_op1 = operands[2];
7766 
  s390_compare_emitted = operands[4];
7767 
})
7768 
 
7769 
(define_insn "*sync_compare_and_swap"
7770 
  [(set (match_operand:DP 0 "register_operand" "=r")
7771 
        (match_operand:DP 1 "memory_operand" "+Q"))
7772 
   (set (match_dup 1)
7773 
        (unspec_volatile:DP
7774 
          [(match_dup 1)
7775 
           (match_operand:DP 2 "register_operand" "0")
7776 
           (match_operand:DP 3 "register_operand" "r")]
7777 
          UNSPECV_CAS))
7778 
   (set (reg:CCZ1 CC_REGNUM)
7779 
        (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7780 
  ""
7781 
  "cds\t%0,%3,%S1"
7782 
  [(set_attr "op_type" "RS")
7783 
   (set_attr "type"   "sem")])
7784 
 
7785 
(define_insn "*sync_compare_and_swap"
7786 
  [(set (match_operand:GPR 0 "register_operand" "=r")
7787 
        (match_operand:GPR 1 "memory_operand" "+Q"))
7788 
   (set (match_dup 1)
7789 
        (unspec_volatile:GPR
7790 
          [(match_dup 1)
7791 
           (match_operand:GPR 2 "register_operand" "0")
7792 
           (match_operand:GPR 3 "register_operand" "r")]
7793 
          UNSPECV_CAS))
7794 
   (set (reg:CCZ1 CC_REGNUM)
7795 
        (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7796 
  ""
7797 
  "cs\t%0,%3,%S1"
7798 
  [(set_attr "op_type" "RS")
7799 
   (set_attr "type"   "sem")])
7800 
 
7801 
 
7802 
;
7803 
; Other atomic instruction patterns.
7804 
;
7805 
 
7806 
(define_expand "sync_lock_test_and_set"
7807 
  [(match_operand:HQI 0 "register_operand")
7808 
   (match_operand:HQI 1 "memory_operand")
7809 
   (match_operand:HQI 2 "general_operand")]
7810 
  ""
7811 
  "s390_expand_atomic (mode, SET, operands[0], operands[1],
7812 
                       operands[2], false); DONE;")
7813 
 
7814 
(define_expand "sync_"
7815 
  [(set (match_operand:HQI 0 "memory_operand")
7816 
        (ATOMIC:HQI (match_dup 0)
7817 
                    (match_operand:HQI 1 "general_operand")))]
7818 
  ""
7819 
  "s390_expand_atomic (mode, , NULL_RTX, operands[0],
7820 
                       operands[1], false); DONE;")
7821 
 
7822 
(define_expand "sync_old_"
7823 
  [(set (match_operand:HQI 0 "register_operand")
7824 
        (match_operand:HQI 1 "memory_operand"))
7825 
   (set (match_dup 1)
7826 
        (ATOMIC:HQI (match_dup 1)
7827 
                    (match_operand:HQI 2 "general_operand")))]
7828 
  ""
7829 
  "s390_expand_atomic (mode, , operands[0], operands[1],
7830 
                       operands[2], false); DONE;")
7831 
 
7832 
(define_expand "sync_new_"
7833 
  [(set (match_operand:HQI 0 "register_operand")
7834 
        (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
7835 
                    (match_operand:HQI 2 "general_operand")))
7836 
   (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
7837 
  ""
7838 
  "s390_expand_atomic (mode, , operands[0], operands[1],
7839 
                       operands[2], true); DONE;")
7840 
 
7841 
;;
7842 
;;- Miscellaneous instructions.
7843 
;;
7844 
 
7845 
;
7846 
; allocate stack instruction pattern(s).
7847 
;
7848 
 
7849 
(define_expand "allocate_stack"
7850 
  [(match_operand 0 "general_operand" "")
7851 
   (match_operand 1 "general_operand" "")]
7852 
 "TARGET_BACKCHAIN"
7853 
{
7854 
  rtx temp = gen_reg_rtx (Pmode);
7855 
 
7856 
  emit_move_insn (temp, s390_back_chain_rtx ());
7857 
  anti_adjust_stack (operands[1]);
7858 
  emit_move_insn (s390_back_chain_rtx (), temp);
7859 
 
7860 
  emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7861 
  DONE;
7862 
})
7863 
 
7864 
 
7865 
;
7866 
; setjmp instruction pattern.
7867 
;
7868 
 
7869 
(define_expand "builtin_setjmp_receiver"
7870 
  [(match_operand 0 "" "")]
7871 
  "flag_pic"
7872 
{
7873 
  emit_insn (s390_load_got ());
7874 
  emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7875 
  DONE;
7876 
})
7877 
 
7878 
;; These patterns say how to save and restore the stack pointer.  We need not
7879 
;; save the stack pointer at function level since we are careful to
7880 
;; preserve the backchain.  At block level, we have to restore the backchain
7881 
;; when we restore the stack pointer.
7882 
;;
7883 
;; For nonlocal gotos, we must save both the stack pointer and its
7884 
;; backchain and restore both.  Note that in the nonlocal case, the
7885 
;; save area is a memory location.
7886 
 
7887 
(define_expand "save_stack_function"
7888 
  [(match_operand 0 "general_operand" "")
7889 
   (match_operand 1 "general_operand" "")]
7890 
  ""
7891 
  "DONE;")
7892 
 
7893 
(define_expand "restore_stack_function"
7894 
  [(match_operand 0 "general_operand" "")
7895 
   (match_operand 1 "general_operand" "")]
7896 
  ""
7897 
  "DONE;")
7898 
 
7899 
(define_expand "restore_stack_block"
7900 
  [(match_operand 0 "register_operand" "")
7901 
   (match_operand 1 "register_operand" "")]
7902 
  "TARGET_BACKCHAIN"
7903 
{
7904 
  rtx temp = gen_reg_rtx (Pmode);
7905 
 
7906 
  emit_move_insn (temp, s390_back_chain_rtx ());
7907 
  emit_move_insn (operands[0], operands[1]);
7908 
  emit_move_insn (s390_back_chain_rtx (), temp);
7909 
 
7910 
  DONE;
7911 
})
7912 
 
7913 
(define_expand "save_stack_nonlocal"
7914 
  [(match_operand 0 "memory_operand" "")
7915 
   (match_operand 1 "register_operand" "")]
7916 
  ""
7917 
{
7918 
  enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7919 
  rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7920 
 
7921 
  /* Copy the backchain to the first word, sp to the second and the
7922 
     literal pool base to the third.  */
7923 
 
7924 
  if (TARGET_BACKCHAIN)
7925 
    {
7926 
      rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7927 
      emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7928 
    }
7929 
 
7930 
  emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7931 
  emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7932 
 
7933 
  DONE;
7934 
})
7935 
 
7936 
(define_expand "restore_stack_nonlocal"
7937 
  [(match_operand 0 "register_operand" "")
7938 
   (match_operand 1 "memory_operand" "")]
7939 
  ""
7940 
{
7941 
  enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7942 
  rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7943 
  rtx temp = NULL_RTX;
7944 
 
7945 
  /* Restore the backchain from the first word, sp from the second and the
7946 
     literal pool base from the third.  */
7947 
 
7948 
  if (TARGET_BACKCHAIN)
7949 
    temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7950 
 
7951 
  emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7952 
  emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7953 
 
7954 
  if (temp)
7955 
    emit_move_insn (s390_back_chain_rtx (), temp);
7956 
 
7957 
  emit_insn (gen_rtx_USE (VOIDmode, base));
7958 
  DONE;
7959 
})
7960 
 
7961 
(define_expand "exception_receiver"
7962 
  [(const_int 0)]
7963 
  ""
7964 
{
7965 
  s390_set_has_landing_pad_p (true);
7966 
  DONE;
7967 
})
7968 
 
7969 
;
7970 
; nop instruction pattern(s).
7971 
;
7972 
 
7973 
(define_insn "nop"
7974 
  [(const_int 0)]
7975 
  ""
7976 
  "lr\t0,0"
7977 
  [(set_attr "op_type" "RR")])
7978 
 
7979 
 
7980 
;
7981 
; Special literal pool access instruction pattern(s).
7982 
;
7983 
 
7984 
(define_insn "*pool_entry"
7985 
  [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7986 
                    UNSPECV_POOL_ENTRY)]
7987 
  ""
7988 
{
7989 
  enum machine_mode mode = GET_MODE (PATTERN (insn));
7990 
  unsigned int align = GET_MODE_BITSIZE (mode);
7991 
  s390_output_pool_entry (operands[0], mode, align);
7992 
  return "";
7993 
}
7994 
  [(set (attr "length")
7995 
        (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7996 
 
7997 
(define_insn "pool_align"
7998 
  [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7999 
                    UNSPECV_POOL_ALIGN)]
8000 
  ""
8001 
  ".align\t%0"
8002 
  [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8003 
 
8004 
(define_insn "pool_section_start"
8005 
  [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8006 
  ""
8007 
  ".section\t.rodata"
8008 
  [(set_attr "length" "0")])
8009 
 
8010 
(define_insn "pool_section_end"
8011 
  [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8012 
  ""
8013 
  ".previous"
8014 
  [(set_attr "length" "0")])
8015 
 
8016 
(define_insn "main_base_31_small"
8017 
  [(set (match_operand 0 "register_operand" "=a")
8018 
        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8019 
  "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8020 
  "basr\t%0,0"
8021 
  [(set_attr "op_type" "RR")
8022 
   (set_attr "type"    "la")])
8023 
 
8024 
(define_insn "main_base_31_large"
8025 
  [(set (match_operand 0 "register_operand" "=a")
8026 
        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8027 
   (set (pc) (label_ref (match_operand 2 "" "")))]
8028 
  "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8029 
  "bras\t%0,%2"
8030 
  [(set_attr "op_type" "RI")])
8031 
 
8032 
(define_insn "main_base_64"
8033 
  [(set (match_operand 0 "register_operand" "=a")
8034 
        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8035 
  "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8036 
  "larl\t%0,%1"
8037 
  [(set_attr "op_type" "RIL")
8038 
   (set_attr "type"    "larl")])
8039 
 
8040 
(define_insn "main_pool"
8041 
  [(set (match_operand 0 "register_operand" "=a")
8042 
        (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8043 
  "GET_MODE (operands[0]) == Pmode"
8044 
{
8045 
  gcc_unreachable ();
8046 
}
8047 
  [(set (attr "type")
8048 
        (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8049 
                      (const_string "larl") (const_string "la")))])
8050 
 
8051 
(define_insn "reload_base_31"
8052 
  [(set (match_operand 0 "register_operand" "=a")
8053 
        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8054 
  "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8055 
  "basr\t%0,0\;la\t%0,%1-.(%0)"
8056 
  [(set_attr "length" "6")
8057 
   (set_attr "type" "la")])
8058 
 
8059 
(define_insn "reload_base_64"
8060 
  [(set (match_operand 0 "register_operand" "=a")
8061 
        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8062 
  "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8063 
  "larl\t%0,%1"
8064 
  [(set_attr "op_type" "RIL")
8065 
   (set_attr "type"    "larl")])
8066 
 
8067 
(define_insn "pool"
8068 
  [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8069 
  ""
8070 
{
8071 
  gcc_unreachable ();
8072 
}
8073 
  [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8074 
 
8075 
;;
8076 
;; Insns related to generating the function prologue and epilogue.
8077 
;;
8078 
 
8079 
 
8080 
(define_expand "prologue"
8081 
  [(use (const_int 0))]
8082 
  ""
8083 
  "s390_emit_prologue (); DONE;")
8084 
 
8085 
(define_expand "epilogue"
8086 
  [(use (const_int 1))]
8087 
  ""
8088 
  "s390_emit_epilogue (false); DONE;")
8089 
 
8090 
(define_expand "sibcall_epilogue"
8091 
  [(use (const_int 0))]
8092 
  ""
8093 
  "s390_emit_epilogue (true); DONE;")
8094 
 
8095 
(define_insn "*return"
8096 
  [(return)
8097 
   (use (match_operand 0 "register_operand" "a"))]
8098 
  "GET_MODE (operands[0]) == Pmode"
8099 
  "br\t%0"
8100 
  [(set_attr "op_type" "RR")
8101 
   (set_attr "type"    "jsr")
8102 
   (set_attr "atype"   "agen")])
8103 
 
8104 
 
8105 
;; Instruction definition to extend a 31-bit pointer into a 64-bit
8106 
;; pointer. This is used for compatibility.
8107 
 
8108 
(define_expand "ptr_extend"
8109 
  [(set (match_operand:DI 0 "register_operand" "=r")
8110 
        (match_operand:SI 1 "register_operand" "r"))]
8111 
  "TARGET_64BIT"
8112 
{
8113 
  emit_insn (gen_anddi3 (operands[0],
8114 
                         gen_lowpart (DImode, operands[1]),
8115 
                         GEN_INT (0x7fffffff)));
8116 
  DONE;
8117 
})
8118 
 
8119 
;; Instruction definition to expand eh_return macro to support
8120 
;; swapping in special linkage return addresses.
8121 
 
8122 
(define_expand "eh_return"
8123 
  [(use (match_operand 0 "register_operand" ""))]
8124 
  "TARGET_TPF"
8125 
{
8126 
  s390_emit_tpf_eh_return (operands[0]);
8127 
  DONE;
8128 
})
8129 
 
8130 
;
8131 
; Stack Protector Patterns
8132 
;
8133 
 
8134 
(define_expand "stack_protect_set"
8135 
  [(set (match_operand 0 "memory_operand" "")
8136 
        (match_operand 1 "memory_operand" ""))]
8137 
  ""
8138 
{
8139 
#ifdef TARGET_THREAD_SSP_OFFSET
8140 
  operands[1]
8141 
    = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8142 
                                        GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8143 
#endif
8144 
  if (TARGET_64BIT)
8145 
    emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8146 
  else
8147 
    emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8148 
 
8149 
  DONE;
8150 
})
8151 
 
8152 
(define_insn "stack_protect_set"
8153 
  [(set (match_operand:DSI 0 "memory_operand" "=Q")
8154 
        (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
8155 
  ""
8156 
  "mvc\t%O0(%G0,%R0),%S1"
8157 
  [(set_attr "op_type" "SS")])
8158 
 
8159 
(define_expand "stack_protect_test"
8160 
  [(set (reg:CC CC_REGNUM)
8161 
        (compare (match_operand 0 "memory_operand" "")
8162 
                 (match_operand 1 "memory_operand" "")))
8163 
   (match_operand 2 "" "")]
8164 
  ""
8165 
{
8166 
#ifdef TARGET_THREAD_SSP_OFFSET
8167 
  operands[1]
8168 
    = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8169 
                                        GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8170 
#endif
8171 
  s390_compare_op0 = operands[0];
8172 
  s390_compare_op1 = operands[1];
8173 
  s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
8174 
 
8175 
  if (TARGET_64BIT)
8176 
    emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
8177 
  else
8178 
    emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8179 
 
8180 
  emit_jump_insn (gen_beq (operands[2]));
8181 
 
8182 
  DONE;
8183 
})
8184 
 
8185 
(define_insn "stack_protect_test"
8186 
  [(set (reg:CCZ CC_REGNUM)
8187 
        (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
8188 
                     (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
8189 
  ""
8190 
  "clc\t%O0(%G0,%R0),%S1"
8191 
  [(set_attr "op_type" "SS")])

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