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[/] [scarts/] [trunk/] [toolchain/] [scarts-gcc/] [gcc-4.1.1/] [gcc/] [config/] [scarts16/] [scarts16.md] - Blame information for rev 12

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1 12 jlechner 
;; -*- Mode: Scheme -*-
2 
;;   Machine description for GNU compiler,
3 
;;   for SCARTS16 micro controllers.
4 
;;   Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005 Free Software Foundation, Inc.
5 
;;   Contributed by Wolfgang Puffitsch
6 
 
7 
;;   This file is part of the SCARTS16 port of GCC
8 
 
9 
;; GNU CC is free software; you can redistribute it and/or modify
10 
;; it under the terms of the GNU General Public License as published by
11 
;; the Free Software Foundation; either version 2, or (at your option)
12 
;; any later version.
13 
 
14 
;; GNU CC is distributed in the hope that it will be useful,
15 
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
;; GNU General Public License for more details.
18 
 
19 
;; You should have received a copy of the GNU General Public License
20 
;; along with GNU CC; see the file COPYING.  If not, write to
21 
;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 
;; Boston, MA 02111-1307, USA.
23 
 
24 
;; Special characters after '%':
25 
;;  A  No effect (add 0).
26 
;;  B  Add 1 to REG number, MEM address or CONST_INT.
27 
;;  C  Add 2.
28 
;;  D  Add 3.
29 
 
30 
;; The size of instructions in bytes.
31 
(define_attr "length" "" (const_int 1))
32 
 
33 
;; Register numbers.
34 
(define_constants
35 
  [(RET_REGNO 0)
36 
   (ARG0_REGNO 1)
37 
   (ARG1_REGNO 2)
38 
   (ARG2_REGNO 3)
39 
   (ARG3_REGNO 4)
40 
   (TMP_REGNO 13)
41 
   (RA_REGNO 14)
42 
   (CC_REGNO 20)])
43 
 
44 
;; Possible conditions
45 
(define_code_macro any_cond [eq ne gt gtu lt ltu ge geu le leu])
46 
(define_code_macro straight_cond [eq gt gtu lt ltu])
47 
(define_code_macro inverted_cond [ne le leu ge geu])
48 
 
49 
;; **************************************************************************
50 
;; calls
51 
 
52 
(define_expand "call"
53 
  [(parallel [(call (match_operand:HI 0 "call_insn_operand" "")
54 
                    (match_operand:HI 1 "general_operand" ""))
55 
              (clobber (reg:HI RA_REGNO))])]
56 
  ""
57 
  "{
58 
     if (GET_CODE (operands[0]) == MEM
59 
         && !register_operand (XEXP (operands[0], 0), HImode))
60 
       operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
61 
                                  force_reg (HImode, XEXP (operands[0], 0)));
62 
}")
63 
 
64 
(define_expand "call_value"
65 
  [(parallel [(set (match_operand 0 "register_operand" "")
66 
                   (call (match_operand:HI 1 "call_insn_operand" "")
67 
                         (match_operand:HI 2 "general_operand" "")))
68 
              (clobber (reg:HI RA_REGNO))])]
69 
  ""
70 
  "{
71 
     if (GET_CODE (operands[1]) == MEM
72 
         && !register_operand (XEXP (operands[1], 0), HImode))
73 
       operands[1] = gen_rtx_MEM (GET_MODE (operands[1]),
74 
                                  force_reg (HImode, XEXP (operands[1], 0)));
75 
}")
76 
 
77 
(define_insn "call_insn"
78 
   [(call (mem:HI (match_operand:HI 0 "register_operand" "r"))
79 
          (match_operand:HI 1 "general_operand" "X"))
80 
    (clobber (reg:HI RA_REGNO))]
81 
  ""
82 
  "jsr %0"
83 
  [(set_attr "length" "1")])
84 
 
85 
(define_insn "call_insn"
86 
  [(cond_exec
87 
    (straight_cond:CC (reg:CC CC_REGNO)
88 
                      (const_int 0))
89 
    (parallel [(call (mem:HI (match_operand:HI 0 "register_operand" "r"))
90 
                     (match_operand:HI 1 "general_operand" "X"))
91 
               (clobber (reg:HI RA_REGNO))]))]
92 
  ""
93 
  "jsr_ct %0"
94 
  [(set_attr "length" "1")])
95 
 
96 
(define_insn "call_insn"
97 
  [(cond_exec
98 
    (inverted_cond:CC (reg:CC CC_REGNO)
99 
                      (const_int 0))
100 
    (parallel [(call (mem:HI (match_operand:HI 0 "register_operand" "r"))
101 
                     (match_operand:HI 1 "general_operand" "X"))
102 
               (clobber (reg:HI RA_REGNO))]))]
103 
  ""
104 
  "jsr_cf %0"
105 
  [(set_attr "length" "1")])
106 
 
107 
(define_insn "call_value_insn"
108 
  [(set (match_operand 0 "register_operand" "=r")
109 
        (call (mem:HI (match_operand:HI 1 "register_operand" "r"))
110 
              (match_operand:HI 2 "general_operand" "X")))
111 
   (clobber (reg:HI RA_REGNO))]
112 
  ""
113 
  "jsr %1"
114 
  [(set_attr "length" "1")])
115 
 
116 
(define_insn "call_value_insn"
117 
  [(cond_exec
118 
    (straight_cond:CC (reg:CC CC_REGNO)
119 
                      (const_int 0))
120 
    (parallel [(set (match_operand 0 "register_operand" "=r")
121 
                    (call (mem:HI (match_operand:HI 1 "register_operand" "r"))
122 
                          (match_operand:HI 2 "general_operand" "X")))
123 
               (clobber (reg:HI RA_REGNO))]))]
124 
  ""
125 
  "jsr_ct %1"
126 
  [(set_attr "length" "1")])
127 
 
128 
(define_insn "call_value_insn"
129 
  [(cond_exec
130 
    (inverted_cond:CC (reg:CC CC_REGNO)
131 
                      (const_int 0))
132 
    (parallel [(set (match_operand 0 "register_operand" "=r")
133 
                    (call (mem:HI (match_operand:HI 1 "register_operand" "r"))
134 
                          (match_operand:HI 2 "general_operand" "X")))
135 
               (clobber (reg:HI RA_REGNO))]))]
136 
  ""
137 
  "jsr_cf %1"
138 
  [(set_attr "length" "1")])
139 
 
140 
;; return
141 
 
142 
(define_insn "return"
143 
  [(return)]
144 
  "reload_completed && scarts16_simple_epilogue ()"
145 
  "rts"
146 
  [(set_attr "length" "1")])
147 
 
148 
;;==========================================================================
149 
;; push
150 
 
151 
(define_insn "pushqi2"
152 
  [(set (mem:QI (pre_modify:HI (match_operand:HI 0 "register_operand" "+q")
153 
                               (plus:HI (match_dup 0) (const_int -2))))
154 
        (match_operand:QI 1 "register_operand" "r"))]
155 
  ""
156 
  "st%0_dec %1,-1"
157 
  [(set_attr "length" "1")])
158 
 
159 
(define_insn "pushhi2"
160 
  [(set (mem:HI (pre_dec:HI (match_operand:HI 0 "register_operand" "+q")))
161 
        (match_operand:HI 1 "register_operand" "r"))]
162 
  ""
163 
  "st%0_dec %1,-1"
164 
  [(set_attr "length" "1")])
165 
 
166 
(define_insn "pushsi2"
167 
  [(set (mem:SI (pre_dec:HI (match_operand:HI 0 "register_operand" "+q")))
168 
        (match_operand:SI 1 "register_operand" "r"))]
169 
  ""
170 
  "st%0_dec %B1,-1\;st%0_dec %A1,-1"
171 
  [(set_attr "length" "2")])
172 
 
173 
(define_insn "pushdi2"
174 
  [(set (mem:DI (pre_dec:HI (match_operand:HI 0 "register_operand" "+q")))
175 
        (match_operand:DI 1 "register_operand" "r"))]
176 
  ""
177 
  "st%0_dec %D1,-1\;st%0_dec %C1,-1\;st%0_dec %B1,-1\;st%0_dec %A1,-1"
178 
  [(set_attr "length" "4")])
179 
 
180 
;; =========================================================================
181 
;; postdec
182 
 
183 
(define_insn "st_postdechi2"
184 
  [(set (mem:HI (post_dec:HI (match_operand:HI 0 "register_operand" "+q")))
185 
        (match_operand:HI 1 "register_operand" "r"))]
186 
   ""
187 
   "st%0_dec %1,0"
188 
   [(set_attr "length" "1")])
189 
 
190 
(define_insn "st_postdecsi2"
191 
  [(set (mem:SI (post_dec:HI (match_operand:HI 0 "register_operand" "+q")))
192 
        (match_operand:SI 1 "register_operand" "r"))]
193 
   ""
194 
   "st%0_dec %B1,1\;st%0_dec %A1,1"
195 
   [(set_attr "length" "2")])
196 
 
197 
(define_insn "st_postdecdi2"
198 
  [(set (mem:DI (post_dec:HI (match_operand:HI 0 "register_operand" "+q")))
199 
        (match_operand:DI 1 "register_operand" "r"))]
200 
   ""
201 
   "st%0_dec %D1,3\;st%0_dec %C1,3\;st%0_dec %B1,3\;st%0_dec %A1,3"
202 
   [(set_attr "length" "4")])
203 
 
204 
(define_insn "ld_postdechi2"
205 
  [(set (match_operand:HI 1 "register_operand" "=r")
206 
        (mem:HI (post_dec:HI (match_operand:HI 0 "register_operand" "+q"))))]
207 
   ""
208 
   "ld%0_dec %1,0"
209 
   [(set_attr "length" "1")])
210 
 
211 
(define_insn "ld_postdecsi2"
212 
  [(set (match_operand:SI 1 "register_operand" "=r")
213 
        (mem:SI (post_dec:HI (match_operand:HI 0 "register_operand" "+q"))))]
214 
   ""
215 
   "ld%0_dec %B1,1\;ld%0_dec %A1,1"
216 
   [(set_attr "length" "2")])
217 
 
218 
(define_insn "ld_postdecdi2"
219 
  [(set (match_operand:DI 1 "register_operand" "=r")
220 
        (mem:DI (post_dec:HI (match_operand:HI 0 "register_operand" "+q"))))]
221 
   ""
222 
   "ld%0_dec %D1,3\;ld%0_dec %C1,3\;ld%0_dec %B1,3\;ld%0_dec %A1,3"
223 
   [(set_attr "length" "4")])
224 
 
225 
;; =========================================================================
226 
;; postinc
227 
 
228 
(define_insn "st_postinchi2"
229 
  [(set (mem:HI (post_inc:HI (match_operand:HI 0 "register_operand" "+q")))
230 
        (match_operand:HI 1 "register_operand" "r"))]
231 
   ""
232 
   "st%0_inc %1,0"
233 
   [(set_attr "length" "1")])
234 
 
235 
(define_insn "st_postincsi2"
236 
  [(set (mem:SI (post_inc:HI (match_operand:HI 0 "register_operand" "+q")))
237 
        (match_operand:SI 1 "register_operand" "r"))]
238 
   ""
239 
   "st%0_inc %A1,0\;st%0_inc %B1,0"
240 
   [(set_attr "length" "2")])
241 
 
242 
(define_insn "st_postincdi2"
243 
  [(set (mem:DI (post_inc:HI (match_operand:HI 0 "register_operand" "+q")))
244 
        (match_operand:DI 1 "register_operand" "r"))]
245 
   ""
246 
   "st%0_inc %A1,0\;st%0_inc %B1,0\;st%0_inc %C1,0\;st%0_inc %D1,0"
247 
   [(set_attr "length" "4")])
248 
 
249 
(define_insn "ld_postinchi2"
250 
  [(set (match_operand:HI 1 "register_operand" "=r")
251 
        (mem:HI (post_inc:HI (match_operand:HI 0 "register_operand" "+q"))))]
252 
   ""
253 
   "ld%0_inc %1,0"
254 
   [(set_attr "length" "1")])
255 
 
256 
(define_insn "ld_postincsi2"
257 
  [(set (match_operand:SI 1 "register_operand" "=r")
258 
        (mem:SI (post_inc:HI (match_operand:HI 0 "register_operand" "+q"))))]
259 
   ""
260 
   "ld%0_inc %A1,0\;ld%0_inc %B1,0"
261 
   [(set_attr "length" "2")])
262 
 
263 
(define_insn "ld_postincdi2"
264 
  [(set (match_operand:DI 1 "register_operand" "=r")
265 
        (mem:DI (post_inc:HI (match_operand:HI 0 "register_operand" "+q"))))]
266 
   ""
267 
   "ld%0_inc %A1,0\;ld%0_inc %B1,0\;ld%0_inc %C1,0\;ld%0_inc %D1,0"
268 
   [(set_attr "length" "4")])
269 
 
270 
;;==========================================================================
271 
;; move byte (8 bit)
272 
 
273 
(define_expand "movqi"
274 
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
275 
        (match_operand:QI 1 "general_operand"  ""))]
276 
  ""
277 
  "{
278 
 /* One of the ops has to be in a register.  */
279 
 if (!register_operand (operand0, QImode)
280 
     && !(register_operand (operand1, QImode)))
281 
   {
282 
     operands[1] = copy_to_mode_reg (QImode, operand1);
283 
   }
284 
}
285 
  ")
286 
 
287 
(define_insn "*movqi3"
288 
  [(cond_exec
289 
    (straight_cond:CC (reg:CC CC_REGNO)
290 
                      (const_int 0))
291 
    (set (match_operand:QI 0 "register_operand"    "=r")
292 
         (match_operand:QI 1 "register_operand"     "r")))]
293 
  ""
294 
  "mov_ct %0,%1"
295 
  [(set_attr "length" "1")])
296 
 
297 
(define_insn "*movqi3"
298 
  [(cond_exec
299 
    (inverted_cond:CC (reg:CC CC_REGNO)
300 
                      (const_int 0))
301 
    (set (match_operand:QI 0 "register_operand"    "=r")
302 
         (match_operand:QI 1 "register_operand"     "r")))]
303 
  ""
304 
  "mov_cf %0,%1"
305 
  [(set_attr "length" "1")])
306 
 
307 
(define_insn "*movqi"
308 
  [(set (match_operand:QI 0 "nonimmediate_operand"   "=r,r,m,r")
309 
        (match_operand:QI 1 "general_operand"         "r,L,r,m"))]
310 
  ""
311 
  "* return scarts16_out_movqi (insn, operands, which_alternative);"
312 
  [(set_attr "length" "1,1,3,3")])
313 
 
314 
;;==========================================================================
315 
;; move word (16 bit)
316 
 
317 
(define_expand "movhi"
318 
  [(set (match_operand:HI 0 "nonimmediate_operand" "")
319 
        (match_operand:HI 1 "general_operand"  ""))]
320 
  ""
321 
  "{
322 
 /* One of the ops has to be in a register.  */
323 
 if (!register_operand (operand0, HImode)
324 
     && !(register_operand (operand1, HImode)))
325 
   {
326 
     operands[1] = copy_to_mode_reg (HImode, operand1);
327 
   }
328 
}
329 
  ")
330 
 
331 
(define_insn "*ld_qihi2"
332 
  [(set (match_operand:HI 0 "register_operand" "=r")
333 
        (sign_extend:HI
334 
         (mem:QI (match_operand:HI 1 "register_operand" "r"))))]
335 
  ""
336 
  "ldb %0,%1"
337 
  [(set_attr "length" "1")])
338 
 
339 
(define_insn "*ldu_qihi2"
340 
  [(set (match_operand:HI 0 "register_operand" "=r")
341 
        (zero_extend:HI
342 
         (mem:QI (match_operand:HI 1 "register_operand" "r"))))]
343 
  ""
344 
  "ldbu %0,%1"
345 
  [(set_attr "length" "1")])
346 
 
347 
(define_insn "*movhi3"
348 
  [(cond_exec
349 
    (straight_cond:CC (reg:CC CC_REGNO)
350 
                      (const_int 0))
351 
    (set (match_operand:HI 0 "register_operand"    "=r")
352 
         (match_operand:HI 1 "register_operand"     "r")))]
353 
  ""
354 
  "mov_ct %0,%1"
355 
  [(set_attr "length" "1")])
356 
 
357 
(define_insn "*movhi3"
358 
  [(cond_exec
359 
    (inverted_cond:CC (reg:CC CC_REGNO)
360 
                      (const_int 0))
361 
    (set (match_operand:HI 0 "register_operand"    "=r")
362 
         (match_operand:HI 1 "register_operand"     "r")))]
363 
  ""
364 
  "mov_cf %0,%1"
365 
  [(set_attr "length" "1")])
366 
 
367 
(define_insn "*movhi"
368 
  [(set (match_operand:HI 0 "nonimmediate_operand"   "=r,r,r,r, m,rq,rq")
369 
        (match_operand:HI 1 "general_operand"         "r,L,n,s,rq, m,rq"))]
370 
  ""
371 
  "* return scarts16_out_movhi (insn, operands, which_alternative);"
372 
  [(set_attr "length" "1,1,2,2,5,5,6")])
373 
 
374 
;;==========================================================================
375 
;; move double-word (32 bit)
376 
 
377 
(define_expand "movsi"
378 
  [(set (match_operand:SI 0 "nonimmediate_operand" "")
379 
        (match_operand:SI 1 "general_operand"  ""))]
380 
  ""
381 
  "{
382 
 /* One of the ops has to be in a register.  */
383 
 if (!register_operand (operand0, SImode)
384 
     && !register_operand (operand1, SImode))
385 
   {
386 
     operands[1] = copy_to_mode_reg (SImode, operand1);
387 
   }
388 
}
389 
  ")
390 
 
391 
(define_insn "*movsi3"
392 
  [(cond_exec
393 
    (straight_cond:CC (reg:CC CC_REGNO)
394 
                      (const_int 0))
395 
    (set (match_operand:SI 0 "register_operand"    "=r")
396 
         (match_operand:SI 1 "register_operand"     "r")))]
397 
  ""
398 
  "* {
399 
      if (true_regnum(operands[0]) < true_regnum(operands[1]))
400 
        {
401 
          output_asm_insn (\"mov_ct %A0,%A1\", operands);
402 
          output_asm_insn (\"mov_ct %B0,%B1\", operands);
403 
        }
404 
      else
405 
        {
406 
          output_asm_insn (\"mov_ct %B0,%B1\", operands);
407 
          output_asm_insn (\"mov_ct %A0,%A1\", operands);
408 
        }
409 
     return \"\";
410 
}"
411 
  [(set_attr "length" "2")])
412 
 
413 
(define_insn "*movsi3"
414 
  [(cond_exec
415 
    (inverted_cond:CC (reg:CC CC_REGNO)
416 
                      (const_int 0))
417 
    (set (match_operand:SI 0 "register_operand"    "=r")
418 
         (match_operand:SI 1 "register_operand"     "r")))]
419 
  ""
420 
  "* {
421 
      if (true_regnum(operands[0]) < true_regnum(operands[1]))
422 
        {
423 
          output_asm_insn (\"mov_cf %A0,%A1\", operands);
424 
          output_asm_insn (\"mov_cf %B0,%B1\", operands);
425 
        }
426 
      else
427 
        {
428 
          output_asm_insn (\"mov_cf %B0,%B1\", operands);
429 
          output_asm_insn (\"mov_cf %A0,%A1\", operands);
430 
        }
431 
     return \"\";
432 
}"
433 
  [(set_attr "length" "2")])
434 
 
435 
(define_insn "*movsi"
436 
  [(set (match_operand:SI 0 "nonimmediate_operand"    "=r,r,r,m,r")
437 
        (match_operand:SI 1 "general_operand"          "r,L,n,r,m"))]
438 
  ""
439 
  "* return scarts16_out_movsi (insn, operands, which_alternative);"
440 
  [(set_attr "length" "2,2,4,4,4")])
441 
 
442 
;;==========================================================================
443 
;; move quad-word (64 bit)
444 
 
445 
(define_expand "movdi"
446 
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
447 
        (match_operand:DI 1 "general_operand"  ""))]
448 
  ""
449 
  "{
450 
 /* One of the ops has to be in a register.  */
451 
 if (!register_operand (operand0, DImode)
452 
     && !(register_operand (operand1, DImode)))
453 
   {
454 
     operands[1] = copy_to_mode_reg (DImode, operand1);
455 
   }
456 
}
457 
  ")
458 
 
459 
(define_insn "*movdi3"
460 
  [(cond_exec
461 
    (straight_cond:CC (reg:CC CC_REGNO)
462 
                      (const_int 0))
463 
    (set (match_operand:DI 0 "register_operand"    "=r")
464 
         (match_operand:DI 1 "register_operand"     "r")))]
465 
  ""
466 
  "* {
467 
      if (true_regnum(operands[0]) < true_regnum(operands[1]))
468 
        {
469 
          output_asm_insn (\"mov_ct %A0,%A1\", operands);
470 
          output_asm_insn (\"mov_ct %B0,%B1\", operands);
471 
          output_asm_insn (\"mov_ct %C0,%C1\", operands);
472 
          output_asm_insn (\"mov_ct %D0,%D1\", operands);
473 
        }
474 
      else
475 
        {
476 
          output_asm_insn (\"mov_ct %D0,%D1\", operands);
477 
          output_asm_insn (\"mov_ct %C0,%C1\", operands);
478 
          output_asm_insn (\"mov_ct %B0,%B1\", operands);
479 
          output_asm_insn (\"mov_ct %A0,%A1\", operands);
480 
        }
481 
     return \"\";
482 
}"
483 
  [(set_attr "length" "2")])
484 
 
485 
(define_insn "*movdi3"
486 
  [(cond_exec
487 
    (inverted_cond:CC (reg:CC CC_REGNO)
488 
                      (const_int 0))
489 
    (set (match_operand:DI 0 "register_operand"    "=r")
490 
         (match_operand:DI 1 "register_operand"     "r")))]
491 
  ""
492 
  "* {
493 
      if (true_regnum(operands[0]) < true_regnum(operands[1]))
494 
        {
495 
          output_asm_insn (\"mov_ct %A0,%A1\", operands);
496 
          output_asm_insn (\"mov_ct %B0,%B1\", operands);
497 
          output_asm_insn (\"mov_cf %C0,%C1\", operands);
498 
          output_asm_insn (\"mov_cf %D0,%D1\", operands);
499 
        }
500 
      else
501 
        {
502 
          output_asm_insn (\"mov_cf %D0,%D1\", operands);
503 
          output_asm_insn (\"mov_cf %C0,%C1\", operands);
504 
          output_asm_insn (\"mov_ct %B0,%B1\", operands);
505 
          output_asm_insn (\"mov_ct %A0,%A1\", operands);
506 
        }
507 
     return \"\";
508 
}"
509 
  [(set_attr "length" "2")])
510 
 
511 
(define_insn "*movdi"
512 
  [(set (match_operand:DI 0 "nonimmediate_operand"    "=r,r,r,m,r")
513 
        (match_operand:DI 1 "general_operand"          "r,L,n,r,m"))]
514 
  ""
515 
  "* return scarts16_out_movdi (insn, operands, which_alternative);"
516 
  [(set_attr "length" "4,4,8,5,5")])
517 
 
518 
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
519 
; add bytes
520 
 
521 
(define_insn "addhi3"
522 
  [(set (match_operand:HI 0 "register_operand"            "=r,r")
523 
        (plus:HI (match_operand:HI 1 "register_operand"   "%0,0")
524 
                 (match_operand:HI 2 "nonmemory_operand"  "rq,O")))]
525 
  ""
526 
  "* return scarts16_out_addhi (insn, operands, which_alternative);"
527 
  [(set_attr "length" "3,1")])
528 
 
529 
(define_insn "addhi3"
530 
  [(cond_exec
531 
    (straight_cond:CC (reg:CC CC_REGNO)
532 
                      (const_int 0))
533 
    (set (match_operand:HI 0 "register_operand"          "=r,r")
534 
         (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
535 
                  (match_operand:HI 2 "nonmemory_operand" "r,O"))))]
536 
  ""
537 
  "@
538 
     add_ct %0,%2
539 
     addi_ct %0,%2"
540 
  [(set_attr "length" "1,1")])
541 
 
542 
(define_insn "addhi3"
543 
  [(cond_exec
544 
    (inverted_cond:CC (reg:CC CC_REGNO)
545 
                      (const_int 0))
546 
    (set (match_operand:HI 0 "register_operand"          "=r,r")
547 
         (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
548 
                  (match_operand:HI 2 "nonmemory_operand" "r,O"))))]
549 
  ""
550 
  "@
551 
     add_cf %0,%2
552 
     addi_cf %0,%2"
553 
  [(set_attr "length" "1,1")])
554 
 
555 
(define_insn "addsi3"
556 
  [(set (match_operand:SI 0 "register_operand"          "=&r")
557 
        (plus:SI (match_operand:SI 1 "register_operand"  "%0")
558 
                 (match_operand:SI 2 "register_operand"   "r")))]
559 
  ""
560 
  "add %A0,%A2\;addc %B0,%B2"
561 
  [(set_attr "length" "2")])
562 
 
563 
(define_insn "addsi3"
564 
  [(cond_exec
565 
    (straight_cond:CC (reg:CC CC_REGNO)
566 
                      (const_int 0))
567 
    (set (match_operand:SI 0 "register_operand"         "=&r")
568 
         (plus:SI (match_operand:SI 1 "register_operand" "%0")
569 
                  (match_operand:SI 2 "register_operand"  "r"))))]
570 
  ""
571 
  "add_ct %A0,%A2\;addc_ct %B0,%B2"
572 
  [(set_attr "length" "2")])
573 
 
574 
(define_insn "addsi3"
575 
  [(cond_exec
576 
    (inverted_cond:CC (reg:CC CC_REGNO)
577 
                      (const_int 0))
578 
    (set (match_operand:SI 0 "register_operand"         "=&r")
579 
         (plus:SI (match_operand:SI 1 "register_operand" "%0")
580 
                  (match_operand:SI 2 "register_operand"  "r"))))]
581 
  ""
582 
  "add_cf %A0,%A2\;addc_cf %B0,%B2"
583 
  [(set_attr "length" "2")])
584 
 
585 
(define_insn "adddi3"
586 
  [(set (match_operand:DI 0 "register_operand"          "=&r")
587 
        (plus:DI (match_operand:DI 1 "register_operand"  "%0")
588 
                 (match_operand:DI 2 "register_operand"   "r")))]
589 
  ""
590 
  "add %A0,%A2\;addc %B0,%B2\;addc %C0,%C2\;addc %D0,%D2"
591 
  [(set_attr "length" "4")])
592 
 
593 
(define_insn "adddi3"
594 
  [(cond_exec
595 
    (straight_cond:CC (reg:CC CC_REGNO)
596 
                      (const_int 0))
597 
    (set (match_operand:DI 0 "register_operand"         "=&r")
598 
         (plus:DI (match_operand:DI 1 "register_operand" "%0")
599 
                  (match_operand:DI 2 "register_operand"  "r"))))]
600 
  ""
601 
  "add_ct %A0,%A2\;addc_ct %B0,%B2\;addc_ct %C0,%C2\;addc_ct %D0,%D2"
602 
  [(set_attr "length" "4")])
603 
 
604 
(define_insn "adddi3"
605 
  [(cond_exec
606 
    (inverted_cond:CC (reg:CC CC_REGNO)
607 
                      (const_int 0))
608 
    (set (match_operand:DI 0 "register_operand"         "=&r")
609 
         (plus:DI (match_operand:DI 1 "register_operand" "%0")
610 
                  (match_operand:DI 2 "register_operand"  "r"))))]
611 
  ""
612 
  "add_cf %A0,%A2\;addc_cf %B0,%B2\;addc_cf %C0,%C2\;addc_cf %D0,%D2"
613 
  [(set_attr "length" "4")])
614 
 
615 
;-----------------------------------------------------------------------------
616 
; sub bytes
617 
 
618 
(define_insn "subhi3"
619 
  [(set (match_operand:HI 0 "register_operand"           "=r")
620 
        (minus:HI (match_operand:HI 1 "register_operand"  "0")
621 
                  (match_operand:HI 2 "register_operand"  "r")))]
622 
  ""
623 
  "sub %0,%2"
624 
  [(set_attr "length" "1")])
625 
 
626 
(define_insn "subhi3"
627 
  [(cond_exec
628 
    (straight_cond:CC (reg:CC CC_REGNO)
629 
                      (const_int 0))
630 
    (set (match_operand:HI 0 "register_operand"           "=r")
631 
         (minus:HI (match_operand:HI 1 "register_operand"  "0")
632 
                   (match_operand:HI 2 "register_operand"  "r"))))]
633 
  ""
634 
  "sub_ct %0,%2"
635 
  [(set_attr "length" "1")])
636 
 
637 
(define_insn "subhi3"
638 
  [(cond_exec
639 
    (inverted_cond:CC (reg:CC CC_REGNO)
640 
                      (const_int 0))
641 
    (set (match_operand:HI 0 "register_operand"           "=r")
642 
         (minus:HI (match_operand:HI 1 "register_operand"  "0")
643 
                   (match_operand:HI 2 "register_operand"  "r"))))]
644 
  ""
645 
  "sub_cf %0,%2"
646 
  [(set_attr "length" "1")])
647 
 
648 
(define_insn "subsi3"
649 
  [(set (match_operand:SI 0 "register_operand"           "=&r")
650 
        (minus:SI (match_operand:SI 1 "register_operand"   "0")
651 
                  (match_operand:SI 2 "register_operand"   "r")))]
652 
  ""
653 
  "sub %A0,%A2\;subc %B0,%B2"
654 
  [(set_attr "length" "2")])
655 
 
656 
(define_insn "subsi3"
657 
  [(cond_exec
658 
    (straight_cond:CC (reg:CC CC_REGNO)
659 
                      (const_int 0))
660 
    (set (match_operand:SI 0 "register_operand"          "=&r")
661 
         (minus:SI (match_operand:SI 1 "register_operand"  "0")
662 
                   (match_operand:SI 2 "register_operand"  "r"))))]
663 
  ""
664 
  "sub_ct %A0,%A2\;subc_ct %B0,%B2"
665 
  [(set_attr "length" "2")])
666 
 
667 
(define_insn "subsi3"
668 
  [(cond_exec
669 
    (inverted_cond:CC (reg:CC CC_REGNO)
670 
                      (const_int 0))
671 
    (set (match_operand:SI 0 "register_operand"          "=&r")
672 
         (minus:SI (match_operand:SI 1 "register_operand"  "0")
673 
                   (match_operand:SI 2 "register_operand"  "r"))))]
674 
  ""
675 
  "sub_cf %A0,%A2\;subc_cf %B0,%B2"
676 
  [(set_attr "length" "2")])
677 
 
678 
(define_insn "subdi3"
679 
  [(set (match_operand:DI 0 "register_operand"          "=&r")
680 
        (minus:DI (match_operand:DI 1 "register_operand"  "0")
681 
                  (match_operand:DI 2 "register_operand"  "r")))]
682 
  ""
683 
  "sub %A0,%A2\;subc %B0,%B2\;subc %C0,%C2\;subc %D0,%D2"
684 
  [(set_attr "length" "4")])
685 
 
686 
(define_insn "subdi3"
687 
  [(cond_exec
688 
    (straight_cond:CC (reg:CC CC_REGNO)
689 
                      (const_int 0))
690 
    (set (match_operand:DI 0 "register_operand"         "=&r")
691 
         (minus:DI (match_operand:DI 1 "register_operand" "0")
692 
                   (match_operand:DI 2 "register_operand" "r"))))]
693 
  ""
694 
  "sub_ct %A0,%A2\;subc_ct %B0,%B2\;subc_ct %C0,%C2\;subc_ct %D0,%D2"
695 
  [(set_attr "length" "4")])
696 
 
697 
(define_insn "subdi3"
698 
  [(cond_exec
699 
    (inverted_cond:CC (reg:CC CC_REGNO)
700 
                      (const_int 0))
701 
    (set (match_operand:DI 0 "register_operand"         "=&r")
702 
         (minus:DI (match_operand:DI 1 "register_operand" "0")
703 
                   (match_operand:DI 2 "register_operand" "r"))))]
704 
  ""
705 
  "sub_cf %A0,%A2\;subc_cf %B0,%B2\;subc_cf %C0,%C2\;subc_cf %D0,%D2"
706 
  [(set_attr "length" "4")])
707 
 
708 
;******************************************************************************
709 
; mul
710 
 
711 
(define_expand "mulhi3"
712 
  [(set (match_operand:HI 0 "register_operand" "")
713 
        (mult:HI (match_operand:HI 1 "register_operand" "")
714 
                 (match_operand:HI 2 "register_operand" "")))]
715 
  ""
716 
  "{
717 
     operands[3] = force_reg (HImode, gen_rtx_SYMBOL_REF (HImode, \"__mulhi3\"));
718 
     emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2], operands[3]));
719 
     DONE;
720 
}")
721 
 
722 
(define_expand "mulhi3_call"
723 
  [(set (reg:HI ARG0_REGNO) (match_operand:HI 1 "register_operand" ""))
724 
   (set (reg:HI ARG1_REGNO) (match_operand:HI 2 "register_operand" ""))
725 
   (parallel [(set (reg:HI RET_REGNO)
726 
                   (mult:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
727 
              (use (match_operand:HI 3 "register_operand" ""))
728 
              (use (reg:HI ARG0_REGNO))
729 
              (use (reg:HI ARG1_REGNO))
730 
              (clobber (reg:HI ARG0_REGNO))
731 
              (clobber (reg:HI ARG1_REGNO))
732 
              (clobber (reg:HI RA_REGNO))])
733 
   (set (match_operand:HI 0 "register_operand" "") (reg:HI RET_REGNO))]
734 
  ""
735 
  "")
736 
 
737 
(define_insn "*mulhi3_call"
738 
  [(set (reg:HI RET_REGNO)
739 
        (mult:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
740 
   (use (match_operand:HI 0 "register_operand" "r"))
741 
   (use (reg:HI ARG0_REGNO))
742 
   (use (reg:HI ARG1_REGNO))
743 
   (clobber (reg:HI ARG0_REGNO))
744 
   (clobber (reg:HI ARG1_REGNO))
745 
   (clobber (reg:HI RA_REGNO))]
746 
  ""
747 
  "jsr %0"
748 
  [(set_attr "length" "1")])
749 
 
750 
;//////////////////////////////////////////////////////////////////////////////
751 
; div
752 
 
753 
(define_expand "divhi3"
754 
  [(set (match_operand:HI 0 "register_operand" "")
755 
        (div:HI (match_operand:HI 1 "register_operand" "")
756 
                 (match_operand:HI 2 "register_operand" "")))]
757 
  ""
758 
  "{
759 
     operands[3] = force_reg (HImode, gen_rtx_SYMBOL_REF (HImode, \"__divhi3\"));
760 
     emit_insn (gen_divhi3_call (operands[0], operands[1], operands[2], operands[3]));
761 
     DONE;
762 
}")
763 
 
764 
(define_expand "divhi3_call"
765 
  [(set (reg:HI ARG0_REGNO) (match_operand:HI 1 "register_operand" ""))
766 
   (set (reg:HI ARG1_REGNO) (match_operand:HI 2 "register_operand" ""))
767 
   (parallel [(set (reg:HI RET_REGNO)
768 
                   (div:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
769 
              (use (match_operand:HI 3 "register_operand" ""))
770 
              (use (reg:HI ARG0_REGNO))
771 
              (use (reg:HI ARG1_REGNO))
772 
              (clobber (reg:HI ARG0_REGNO))
773 
              (clobber (reg:HI ARG1_REGNO))
774 
              (clobber (reg:HI ARG2_REGNO))
775 
              (clobber (reg:HI RA_REGNO))])
776 
   (set (match_operand:HI 0 "register_operand" "") (reg:HI RET_REGNO))]
777 
  ""
778 
  "")
779 
 
780 
(define_insn "*divhi3_call"
781 
  [(set (reg:HI RET_REGNO)
782 
        (div:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
783 
   (use (match_operand:HI 0 "register_operand" "r"))
784 
   (use (reg:HI ARG0_REGNO))
785 
   (use (reg:HI ARG1_REGNO))
786 
   (clobber (reg:HI ARG0_REGNO))
787 
   (clobber (reg:HI ARG1_REGNO))
788 
   (clobber (reg:HI ARG2_REGNO))
789 
   (clobber (reg:HI RA_REGNO))]
790 
  ""
791 
  "jsr %0"
792 
  [(set_attr "length" "1")])
793 
 
794 
;//////////////////////////////////////////////////////////////////////////////
795 
; udiv
796 
 
797 
(define_expand "udivhi3"
798 
  [(set (match_operand:HI 0 "register_operand" "")
799 
        (udiv:HI (match_operand:HI 1 "register_operand" "")
800 
                 (match_operand:HI 2 "register_operand" "")))]
801 
  ""
802 
  "{
803 
     operands[3] = force_reg (HImode, gen_rtx_SYMBOL_REF (HImode, \"__udivhi3\"));
804 
     emit_insn (gen_udivhi3_call (operands[0], operands[1], operands[2], operands[3]));
805 
     DONE;
806 
}")
807 
 
808 
(define_expand "udivhi3_call"
809 
  [(set (reg:HI ARG0_REGNO) (match_operand:HI 1 "register_operand" ""))
810 
   (set (reg:HI ARG1_REGNO) (match_operand:HI 2 "register_operand" ""))
811 
   (parallel [(set (reg:HI RET_REGNO)
812 
                   (udiv:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
813 
              (use (match_operand:HI 3 "register_operand" ""))
814 
              (use (reg:HI ARG0_REGNO))
815 
              (use (reg:HI ARG1_REGNO))
816 
              (clobber (reg:HI ARG0_REGNO))
817 
              (clobber (reg:HI ARG1_REGNO))
818 
              (clobber (reg:HI RA_REGNO))])
819 
   (set (match_operand:HI 0 "register_operand" "") (reg:HI RET_REGNO))]
820 
  ""
821 
  "")
822 
 
823 
(define_insn "*udivhi3_call"
824 
  [(set (reg:HI RET_REGNO)
825 
        (udiv:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
826 
   (use (match_operand:HI 0 "register_operand" "r"))
827 
   (use (reg:HI ARG0_REGNO))
828 
   (use (reg:HI ARG1_REGNO))
829 
   (clobber (reg:HI ARG0_REGNO))
830 
   (clobber (reg:HI ARG1_REGNO))
831 
   (clobber (reg:HI RA_REGNO))]
832 
  ""
833 
  "jsr %0"
834 
  [(set_attr "length" "1")])
835 
 
836 
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
837 
; mod
838 
 
839 
(define_expand "modhi3"
840 
  [(set (match_operand:HI 0 "register_operand" "")
841 
        (mod:HI (match_operand:HI 1 "register_operand" "")
842 
                 (match_operand:HI 2 "register_operand" "")))]
843 
  ""
844 
  "{
845 
     operands[3] = force_reg (HImode, gen_rtx_SYMBOL_REF (HImode, \"__modhi3\"));
846 
     emit_insn (gen_modhi3_call (operands[0], operands[1], operands[2], operands[3]));
847 
     DONE;
848 
}")
849 
 
850 
(define_expand "modhi3_call"
851 
  [(set (reg:HI ARG0_REGNO) (match_operand:HI 1 "register_operand" ""))
852 
   (set (reg:HI ARG1_REGNO) (match_operand:HI 2 "register_operand" ""))
853 
   (parallel [(set (reg:HI RET_REGNO)
854 
                   (mod:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
855 
              (use (match_operand:HI 3 "register_operand" ""))
856 
              (use (reg:HI ARG0_REGNO))
857 
              (use (reg:HI ARG1_REGNO))
858 
              (clobber (reg:HI ARG0_REGNO))
859 
              (clobber (reg:HI ARG1_REGNO))
860 
              (clobber (reg:HI ARG2_REGNO))
861 
              (clobber (reg:HI RA_REGNO))])
862 
   (set (match_operand:HI 0 "register_operand" "") (reg:HI RET_REGNO))]
863 
  ""
864 
  "")
865 
 
866 
(define_insn "*modhi3_call"
867 
  [(set (reg:HI RET_REGNO)
868 
        (mod:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
869 
   (use (match_operand:HI 0 "register_operand" "r"))
870 
   (use (reg:HI ARG0_REGNO))
871 
   (use (reg:HI ARG1_REGNO))
872 
   (clobber (reg:HI ARG0_REGNO))
873 
   (clobber (reg:HI ARG1_REGNO))
874 
   (clobber (reg:HI ARG2_REGNO))
875 
   (clobber (reg:HI RA_REGNO))]
876 
  ""
877 
  "jsr %0"
878 
  [(set_attr "length" "1")])
879 
 
880 
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
881 
; umod
882 
 
883 
(define_expand "umodhi3"
884 
  [(set (match_operand:HI 0 "register_operand" "")
885 
        (umod:HI (match_operand:HI 1 "register_operand" "")
886 
                 (match_operand:HI 2 "register_operand" "")))]
887 
  ""
888 
  "{
889 
     operands[3] = force_reg (HImode, gen_rtx_SYMBOL_REF (HImode, \"__umodhi3\"));
890 
     emit_insn (gen_umodhi3_call (operands[0], operands[1], operands[2], operands[3]));
891 
     DONE;
892 
}")
893 
 
894 
(define_expand "umodhi3_call"
895 
  [(set (reg:HI ARG0_REGNO) (match_operand:HI 1 "register_operand" ""))
896 
   (set (reg:HI ARG1_REGNO) (match_operand:HI 2 "register_operand" ""))
897 
   (parallel [(set (reg:HI RET_REGNO)
898 
                   (umod:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
899 
              (use (match_operand:HI 3 "register_operand" ""))
900 
              (use (reg:HI ARG0_REGNO))
901 
              (use (reg:HI ARG1_REGNO))
902 
              (clobber (reg:HI ARG0_REGNO))
903 
              (clobber (reg:HI ARG1_REGNO))
904 
              (clobber (reg:HI RA_REGNO))])
905 
   (set (match_operand:HI 0 "register_operand" "") (reg:HI RET_REGNO))]
906 
  ""
907 
  "")
908 
 
909 
(define_insn "*umodhi3_call"
910 
  [(set (reg:HI RET_REGNO)
911 
        (umod:HI (reg:HI ARG0_REGNO) (reg:HI ARG1_REGNO)))
912 
   (use (match_operand:HI 0 "register_operand" "r"))
913 
   (use (reg:HI ARG0_REGNO))
914 
   (use (reg:HI ARG1_REGNO))
915 
   (clobber (reg:HI ARG0_REGNO))
916 
   (clobber (reg:HI ARG1_REGNO))
917 
   (clobber (reg:HI RA_REGNO))]
918 
  ""
919 
  "jsr %0"
920 
  [(set_attr "length" "1")])
921 
 
922 
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
923 
; and
924 
 
925 
(define_insn "andhi3"
926 
  [(set (match_operand:HI 0 "register_operand"          "=r,r")
927 
        (and:HI (match_operand:HI 1 "register_operand"  "%0,0")
928 
                (match_operand:HI 2 "nonmemory_operand"  "r,I")))]
929 
  ""
930 
  "*{
931 
      switch (which_alternative)
932 
        {
933 
          case 0: output_asm_insn (\"and %0, %2\", operands);
934 
            break;
935 
          case 1: operands[2] = gen_rtx_CONST_INT (HImode, exact_log2(~INTVAL(operands[2])));
936 
                  output_asm_insn (\"bclr %0, %2\", operands);
937 
            break;
938 
          default: gcc_unreachable();
939 
        }
940 
      return \"\";
941 
}"
942 
  [(set_attr "length" "1,1")])
943 
 
944 
(define_insn "andhi3"
945 
  [(cond_exec
946 
    (straight_cond:CC (reg:CC CC_REGNO)
947 
                      (const_int 0))
948 
    (set (match_operand:HI 0 "register_operand"           "=r,r")
949 
         (and:HI (match_operand:HI 1 "register_operand"   "%0,0")
950 
                  (match_operand:HI 2 "nonmemory_operand"  "r,I"))))]
951 
  ""
952 
  "*{
953 
      switch (which_alternative)
954 
        {
955 
          case 0: output_asm_insn (\"and_ct %0, %2\", operands);
956 
            break;
957 
          case 1: operands[2] = gen_rtx_CONST_INT (HImode, exact_log2(~INTVAL(operands[2])));
958 
                  output_asm_insn (\"bclr_ct %0, %2\", operands);
959 
            break;
960 
          default: gcc_unreachable();
961 
        }
962 
      return \"\";
963 
}"
964 
  [(set_attr "length" "1,1")])
965 
 
966 
(define_insn "andhi3"
967 
  [(cond_exec
968 
    (inverted_cond:CC (reg:CC CC_REGNO)
969 
                      (const_int 0))
970 
    (set (match_operand:HI 0 "register_operand"           "=r,r")
971 
         (and:HI (match_operand:HI 1 "register_operand"   "%0,0")
972 
                  (match_operand:HI 2 "nonmemory_operand"  "r,I"))))]
973 
  ""
974 
  "*{
975 
      switch (which_alternative)
976 
        {
977 
          case 0: output_asm_insn (\"and_cf %0, %2\", operands);
978 
            break;
979 
          case 1: operands[2] = gen_rtx_CONST_INT (HImode, exact_log2(~INTVAL(operands[2])));
980 
                  output_asm_insn (\"bclr_cf %0, %2\", operands);
981 
            break;
982 
          default: gcc_unreachable();
983 
        }
984 
      return \"\";
985 
}"
986 
  [(set_attr "length" "1,1")])
987 
 
988 
(define_insn "andsi3"
989 
  [(set (match_operand:SI 0 "register_operand"         "=&r")
990 
        (and:SI (match_operand:SI 1 "register_operand"  "%0")
991 
                (match_operand:SI 2 "register_operand"   "r")))]
992 
  ""
993 
  "and %A0,%A2\;and %B0,%B2"
994 
  [(set_attr "length" "2")])
995 
 
996 
(define_insn "andsi3"
997 
  [(cond_exec
998 
    (straight_cond:CC (reg:CC CC_REGNO)
999 
                      (const_int 0))
1000 
    (set (match_operand:SI 0 "register_operand"         "=&r")
1001 
         (and:SI (match_operand:SI 1 "register_operand"  "%0")
1002 
                  (match_operand:SI 2 "register_operand"  "r"))))]
1003 
  ""
1004 
  "and_ct %A0,%A2\;and_ct %B0,%B2"
1005 
  [(set_attr "length" "2")])
1006 
 
1007 
(define_insn "andsi3"
1008 
  [(cond_exec
1009 
    (inverted_cond:CC (reg:CC CC_REGNO)
1010 
                      (const_int 0))
1011 
    (set (match_operand:SI 0 "register_operand"         "=&r")
1012 
         (and:SI (match_operand:SI 1 "register_operand"  "%0")
1013 
                  (match_operand:SI 2 "register_operand"  "r"))))]
1014 
  ""
1015 
  "and_cf %A0,%A2\;and_cf %B0,%B2"
1016 
  [(set_attr "length" "2")])
1017 
 
1018 
(define_insn "anddi3"
1019 
  [(set (match_operand:DI 0 "register_operand"         "=&r")
1020 
        (and:DI (match_operand:DI 1 "register_operand"  "%0")
1021 
                (match_operand:DI 2 "register_operand"   "r")))]
1022 
  ""
1023 
  "and %A0,%A2\;and %B0,%B2\;and %C0,%C2\;and %D0,%D2"
1024 
  [(set_attr "length" "4")])
1025 
 
1026 
(define_insn "anddi3"
1027 
  [(cond_exec
1028 
    (straight_cond:CC (reg:CC CC_REGNO)
1029 
                      (const_int 0))
1030 
    (set (match_operand:DI 0 "register_operand"         "=&r")
1031 
         (and:DI (match_operand:DI 1 "register_operand"  "%0")
1032 
                  (match_operand:DI 2 "register_operand"  "r"))))]
1033 
  ""
1034 
  "and_ct %A0,%A2\;and_ct %B0,%B2\;and_ct %C0,%C2\;and_ct %D0,%D2"
1035 
  [(set_attr "length" "4")])
1036 
 
1037 
(define_insn "anddi3"
1038 
  [(cond_exec
1039 
    (inverted_cond:CC (reg:CC CC_REGNO)
1040 
                      (const_int 0))
1041 
    (set (match_operand:DI 0 "register_operand"         "=&r")
1042 
         (and:DI (match_operand:DI 1 "register_operand"  "%0")
1043 
                  (match_operand:DI 2 "register_operand"  "r"))))]
1044 
  ""
1045 
  "and_cf %A0,%A2\;and_cf %B0,%B2\;and_cf %C0,%C2\;and_cf %D0,%D2"
1046 
  [(set_attr "length" "4")])
1047 
 
1048 
;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1049 
;; ior
1050 
 
1051 
(define_insn "iorhi3"
1052 
  [(set (match_operand:HI 0 "register_operand"          "=r,r")
1053 
        (ior:HI (match_operand:HI 1 "register_operand"  "%0,0")
1054 
                (match_operand:HI 2 "nonmemory_operand"  "r,J")))]
1055 
  ""
1056 
  "*{
1057 
      switch (which_alternative)
1058 
        {
1059 
          case 0: output_asm_insn (\"or %0, %2\", operands);
1060 
            break;
1061 
          case 1: operands[2] = gen_rtx_CONST_INT (HImode, exact_log2(INTVAL(operands[2])));
1062 
                  output_asm_insn (\"bset %0, %2\", operands);
1063 
            break;
1064 
          default: gcc_unreachable();
1065 
        }
1066 
      return \"\";
1067 
}"
1068 
  [(set_attr "length" "1,1")])
1069 
 
1070 
(define_insn "iorhi3"
1071 
  [(cond_exec
1072 
    (straight_cond:CC (reg:CC CC_REGNO)
1073 
                      (const_int 0))
1074 
    (set (match_operand:HI 0 "register_operand"          "=r,r")
1075 
         (ior:HI (match_operand:HI 1 "register_operand"  "%0,0")
1076 
                  (match_operand:HI 2 "nonmemory_operand" "r,J"))))]
1077 
  ""
1078 
  "*{
1079 
      switch (which_alternative)
1080 
        {
1081 
          case 0: output_asm_insn (\"or_ct %0, %2\", operands);
1082 
            break;
1083 
          case 1: operands[2] = gen_rtx_CONST_INT (HImode, exact_log2(INTVAL(operands[2])));
1084 
                  output_asm_insn (\"bset_ct %0, %2\", operands);
1085 
            break;
1086 
          default: gcc_unreachable();
1087 
        }
1088 
      return \"\";
1089 
}"
1090 
  [(set_attr "length" "1,1")])
1091 
 
1092 
(define_insn "iorhi3"
1093 
  [(cond_exec
1094 
    (inverted_cond:CC (reg:CC CC_REGNO)
1095 
                      (const_int 0))
1096 
    (set (match_operand:HI 0 "register_operand"          "=r,r")
1097 
         (ior:HI (match_operand:HI 1 "register_operand"  "%0,0")
1098 
                  (match_operand:HI 2 "nonmemory_operand" "r,J"))))]
1099 
  ""
1100 
  "*{
1101 
      switch (which_alternative)
1102 
        {
1103 
          case 0: output_asm_insn (\"or_cf %0, %2\", operands);
1104 
            break;
1105 
          case 1: operands[2] = gen_rtx_CONST_INT (HImode, exact_log2(INTVAL(operands[2])));
1106 
                  output_asm_insn (\"bset_cf %0, %2\", operands);
1107 
            break;
1108 
          default: gcc_unreachable();
1109 
        }
1110 
      return \"\";
1111 
}"
1112 
  [(set_attr "length" "1,1")])
1113 
 
1114 
(define_insn "iorsi3"
1115 
  [(set (match_operand:SI 0 "register_operand"         "=&r")
1116 
        (ior:SI (match_operand:SI 1 "register_operand"  "%0")
1117 
                (match_operand:SI 2 "register_operand"   "r")))]
1118 
  ""
1119 
  "or %A0,%A2\;or %B0,%B2"
1120 
  [(set_attr "length" "2")])
1121 
 
1122 
(define_insn "iorsi3"
1123 
  [(cond_exec
1124 
    (straight_cond:CC (reg:CC CC_REGNO)
1125 
                      (const_int 0))
1126 
    (set (match_operand:SI 0 "register_operand"         "=&r")
1127 
         (ior:SI (match_operand:SI 1 "register_operand"  "%0")
1128 
                 (match_operand:SI 2 "register_operand"   "r"))))]
1129 
  ""
1130 
  "or_ct %A0,%A2\;or_ct %B0,%B2"
1131 
  [(set_attr "length" "2")])
1132 
 
1133 
(define_insn "iorsi3"
1134 
  [(cond_exec
1135 
    (inverted_cond:CC (reg:CC CC_REGNO)
1136 
                      (const_int 0))
1137 
    (set (match_operand:SI 0 "register_operand"         "=&r")
1138 
         (ior:SI (match_operand:SI 1 "register_operand"  "%0")
1139 
                 (match_operand:SI 2 "register_operand"   "r"))))]
1140 
  ""
1141 
  "or_cf %A0,%A2\;or_cf %B0,%B2"
1142 
  [(set_attr "length" "2")])
1143 
 
1144 
(define_insn "iordi3"
1145 
  [(set (match_operand:DI 0 "register_operand"         "=&r")
1146 
        (ior:DI (match_operand:DI 1 "register_operand"  "%0")
1147 
                (match_operand:DI 2 "register_operand"   "r")))]
1148 
  ""
1149 
  "or %A0,%A2\;or %B0,%B2\;or %C0,%C2\;or %D0,%D2"
1150 
  [(set_attr "length" "4")])
1151 
 
1152 
(define_insn "iordi3"
1153 
  [(cond_exec
1154 
    (straight_cond:CC (reg:CC CC_REGNO)
1155 
                      (const_int 0))
1156 
    (set (match_operand:DI 0 "register_operand"         "=&r")
1157 
         (ior:DI (match_operand:DI 1 "register_operand"  "%0")
1158 
                 (match_operand:DI 2 "register_operand"   "r"))))]
1159 
  ""
1160 
  "or_ct %A0,%A2\;or_ct %B0,%B2\;or_ct %C0,%C2\;or_ct %D0,%D2"
1161 
  [(set_attr "length" "4")])
1162 
 
1163 
(define_insn "iordi3"
1164 
  [(cond_exec
1165 
    (inverted_cond:CC (reg:CC CC_REGNO)
1166 
                      (const_int 0))
1167 
    (set (match_operand:DI 0 "register_operand"         "=&r")
1168 
         (ior:DI (match_operand:DI 1 "register_operand"  "%0")
1169 
                 (match_operand:DI 2 "register_operand"   "r"))))]
1170 
  ""
1171 
  "or_cf %A0,%A2\;or_cf %B0,%B2\;or_cf %C0,%C2\;or_cf %D0,%D2"
1172 
  [(set_attr "length" "4")])
1173 
 
1174 
;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1175 
;; xor
1176 
 
1177 
(define_insn "xorhi3"
1178 
  [(set (match_operand:HI 0 "register_operand"         "=r")
1179 
        (xor:HI (match_operand:HI 1 "register_operand" "%0")
1180 
                (match_operand:HI 2 "register_operand"  "r")))]
1181 
  ""
1182 
  "eor %0,%2"
1183 
  [(set_attr "length" "1")])
1184 
 
1185 
(define_insn "xorhi3"
1186 
  [(cond_exec
1187 
    (straight_cond:CC (reg:CC CC_REGNO)
1188 
                      (const_int 0))
1189 
    (set (match_operand:HI 0 "register_operand"          "=r")
1190 
         (xor:HI (match_operand:HI 1 "register_operand"  "%0")
1191 
                 (match_operand:HI 2 "register_operand"   "r"))))]
1192 
  ""
1193 
  "eor_ct %0,%2"
1194 
  [(set_attr "length" "1")])
1195 
 
1196 
(define_insn "xorhi3"
1197 
  [(cond_exec
1198 
    (inverted_cond:CC (reg:CC CC_REGNO)
1199 
                      (const_int 0))
1200 
    (set (match_operand:HI 0 "register_operand"          "=r")
1201 
         (xor:HI (match_operand:HI 1 "register_operand"  "%0")
1202 
                 (match_operand:HI 2 "register_operand"   "r"))))]
1203 
  ""
1204 
  "eor_cf %0,%2"
1205 
  [(set_attr "length" "1")])
1206 
 
1207 
(define_insn "xorsi3"
1208 
  [(set (match_operand:SI 0 "register_operand"        "=&r")
1209 
        (xor:SI (match_operand:SI 1 "register_operand" "%0")
1210 
                (match_operand:SI 2 "register_operand"  "r")))]
1211 
  ""
1212 
  "eor %A0,%A2\;eor %B0,%B2"
1213 
  [(set_attr "length" "1")])
1214 
 
1215 
(define_insn "xorsi3"
1216 
  [(cond_exec
1217 
    (straight_cond:CC (reg:CC CC_REGNO)
1218 
                      (const_int 0))
1219 
    (set (match_operand:SI 0 "register_operand"         "=&r")
1220 
         (xor:SI (match_operand:SI 1 "register_operand"  "%0")
1221 
                  (match_operand:SI 2 "register_operand"  "r"))))]
1222 
  ""
1223 
  "eor_ct %A0,%A2\;eor_ct %B0,%B2"
1224 
  [(set_attr "length" "2")])
1225 
 
1226 
(define_insn "xorsi3"
1227 
  [(cond_exec
1228 
    (inverted_cond:CC (reg:CC CC_REGNO)
1229 
                      (const_int 0))
1230 
    (set (match_operand:SI 0 "register_operand"         "=&r")
1231 
         (xor:SI (match_operand:SI 1 "register_operand"  "%0")
1232 
                  (match_operand:SI 2 "register_operand"  "r"))))]
1233 
  ""
1234 
  "eor_cf %A0,%A2\;eor_cf %B0,%B2"
1235 
  [(set_attr "length" "2")])
1236 
 
1237 
(define_insn "xordi3"
1238 
  [(set (match_operand:DI 0 "register_operand"        "=&r")
1239 
        (xor:DI (match_operand:DI 1 "register_operand" "%0")
1240 
                (match_operand:DI 2 "register_operand"  "r")))]
1241 
  ""
1242 
  "eor %A0,%A2\;eor %B0,%B2\;eor %C0,%C2\;eor %D0,%D2"
1243 
  [(set_attr "length" "4")])
1244 
 
1245 
(define_insn "xordi3"
1246 
  [(cond_exec
1247 
    (straight_cond:CC (reg:CC CC_REGNO)
1248 
                      (const_int 0))
1249 
    (set (match_operand:DI 0 "register_operand"         "=&r")
1250 
         (xor:DI (match_operand:DI 1 "register_operand"  "%0")
1251 
                  (match_operand:DI 2 "register_operand"  "r"))))]
1252 
  ""
1253 
  "eor_ct %A0,%A2\;eor_ct %B0,%B2\;eor_ct %C0,%C2\;eor_ct %D0,%D2"
1254 
  [(set_attr "length" "4")])
1255 
 
1256 
(define_insn "xordi3"
1257 
  [(cond_exec
1258 
    (inverted_cond:CC (reg:CC CC_REGNO)
1259 
                      (const_int 0))
1260 
    (set (match_operand:DI 0 "register_operand"         "=&r")
1261 
         (xor:DI (match_operand:DI 1 "register_operand"  "%0")
1262 
                  (match_operand:DI 2 "register_operand"  "r"))))]
1263 
  ""
1264 
  "eor_cf %A0,%A2\;eor_cf %B0,%B2\;eor_cf %C0,%C2\;eor_cf %D0,%D2"
1265 
  [(set_attr "length" "4")])
1266 
 
1267 
;;>>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>>
1268 
;; lshr
1269 
 
1270 
(define_insn "lshrhi3"
1271 
  [(set (match_operand:HI 0 "register_operand"              "=r,r")
1272 
        (lshiftrt:HI (match_operand:HI 1 "register_operand"  "0,0")
1273 
                     (match_operand:HI 2 "nonmemory_operand" "r,P")))]
1274 
  ""
1275 
  "@
1276 
      sr %0, %2
1277 
      sri %0, %2"
1278 
  [(set_attr "length" "1,1")])
1279 
 
1280 
(define_insn "lshrhi3"
1281 
  [(cond_exec
1282 
    (straight_cond:CC (reg:CC CC_REGNO)
1283 
                      (const_int 0))
1284 
    (set (match_operand:HI 0 "register_operand"              "=r,r")
1285 
         (lshiftrt:HI (match_operand:HI 1 "register_operand"  "0,0")
1286 
                      (match_operand:HI 2 "nonmemory_operand" "r,P"))))]
1287 
  ""
1288 
  "@
1289 
      sr_ct %0,%2
1290 
      sri_ct %0,%2"
1291 
  [(set_attr "length" "1,1")])
1292 
 
1293 
(define_insn "lshrhi3"
1294 
  [(cond_exec
1295 
    (inverted_cond:CC (reg:CC CC_REGNO)
1296 
                      (const_int 0))
1297 
    (set (match_operand:HI 0 "register_operand"              "=r,r")
1298 
         (lshiftrt:HI (match_operand:HI 1 "register_operand"  "0,0")
1299 
                      (match_operand:HI 2 "nonmemory_operand" "r,P"))))]
1300 
  ""
1301 
  "@
1302 
      sr_cf %0,%2
1303 
      sri_cf %0,%2"
1304 
  [(set_attr "length" "1,1")])
1305 
 
1306 
(define_expand "lshrsi3"
1307 
  [(set (match_operand:SI 0 "register_operand" "")
1308 
        (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1309 
                     (match_operand:HI 2 "nonmemory_operand" "")))]
1310 
  ""
1311 
  "{
1312 
     if ((GET_CODE (operand2) == CONST_INT) && (INTVAL (operand2) <= 3))
1313 
       {
1314 
         int i;
1315 
         int k = INTVAL (operand2);
1316 
         emit_move_insn (operands[0], operands[1]);
1317 
         for (i = 0; i < k; i++)
1318 
           {
1319 
             emit_insn (gen_lshrsi1 (operands[0], operands[0]));
1320 
           }
1321 
         DONE;
1322 
       }
1323 
     else
1324 
       {
1325 
         FAIL;
1326 
       }
1327 
}")
1328 
 
1329 
(define_insn "lshrsi1"
1330 
  [(set (match_operand:SI 0 "register_operand"              "=r,r")
1331 
        (lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,0")
1332 
                     (const_int 1)))]
1333 
  ""
1334 
  "sri %B0, 1\;rrc %A0"
1335 
  [(set_attr "length" "2")])
1336 
 
1337 
(define_insn "lshrsi1"
1338 
  [(cond_exec
1339 
    (straight_cond:CC (reg:CC CC_REGNO)
1340 
                      (const_int 0))
1341 
    (set (match_operand:SI 0 "register_operand"              "=r,r")
1342 
         (lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,0")
1343 
                      (const_int 1))))]
1344 
  ""
1345 
  "sri_ct %B0, 1\;rrc_ct %A0"
1346 
  [(set_attr "length" "2")])
1347 
 
1348 
(define_insn "lshrsi1"
1349 
  [(cond_exec
1350 
    (inverted_cond:CC (reg:CC CC_REGNO)
1351 
                      (const_int 0))
1352 
    (set (match_operand:SI 0 "register_operand"              "=r,r")
1353 
         (lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,0")
1354 
                      (const_int 1))))]
1355 
  ""
1356 
  "sri_cf %B0, 1\;rrc_cf %A0"
1357 
  [(set_attr "length" "2")])
1358 
 
1359 
(define_insn "lshrdi1"
1360 
  [(set (match_operand:DI 0 "register_operand"              "=r,r")
1361 
        (lshiftrt:DI (match_operand:DI 1 "register_operand"  "0,0")
1362 
                   (const_int 1)))]
1363 
  ""
1364 
  "sri %D0, 1\;rrc %C0\;rrc %B0\;rrc %A0"
1365 
  [(set_attr "length" "4")])
1366 
 
1367 
(define_insn "lshrdi1"
1368 
  [(cond_exec
1369 
    (straight_cond:CC (reg:CC CC_REGNO)
1370 
                      (const_int 0))
1371 
    (set (match_operand:DI 0 "register_operand"              "=r,r")
1372 
         (lshiftrt:DI (match_operand:DI 1 "register_operand"  "0,0")
1373 
                    (const_int 1))))]
1374 
  ""
1375 
  "sri_ct %D0, 1\;rrc_ct %C0\;rrc_ct %B0\;rrc_ct %A0"
1376 
  [(set_attr "length" "4")])
1377 
 
1378 
(define_insn "lshrdi1"
1379 
  [(cond_exec
1380 
    (inverted_cond:CC (reg:CC CC_REGNO)
1381 
                      (const_int 0))
1382 
    (set (match_operand:DI 0 "register_operand"              "=r,r")
1383 
         (lshiftrt:DI (match_operand:DI 1 "register_operand"  "0,0")
1384 
                    (const_int 1))))]
1385 
  ""
1386 
  "sri_cf %D0, 1\;rrc_cf %C0\;rrc_cf %B0\;rrc_cf %A0"
1387 
  [(set_attr "length" "4")])
1388 
 
1389 
;;>> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1390 
;; ashr
1391 
 
1392 
(define_insn "ashrhi3"
1393 
  [(set (match_operand:HI 0 "register_operand"              "=r,r")
1394 
        (ashiftrt:HI (match_operand:HI 1 "register_operand"  "0,0")
1395 
                     (match_operand:HI 2 "nonmemory_operand" "r,P")))]
1396 
  ""
1397 
  "@
1398 
      sra %0, %2
1399 
      srai %0, %2"
1400 
  [(set_attr "length" "1,1")])
1401 
 
1402 
(define_insn "ashrhi3"
1403 
  [(cond_exec
1404 
    (straight_cond:CC (reg:CC CC_REGNO)
1405 
                      (const_int 0))
1406 
    (set (match_operand:HI 0 "register_operand"              "=r,r")
1407 
         (ashiftrt:HI (match_operand:HI 1 "register_operand"  "0,0")
1408 
                      (match_operand:HI 2 "nonmemory_operand" "r,P"))))]
1409 
  ""
1410 
  "@
1411 
      sra_ct %0,%2
1412 
      srai_ct %0,%2"
1413 
  [(set_attr "length" "1,1")])
1414 
 
1415 
(define_insn "ashrhi3"
1416 
  [(cond_exec
1417 
    (inverted_cond:CC (reg:CC CC_REGNO)
1418 
                      (const_int 0))
1419 
    (set (match_operand:HI 0 "register_operand"              "=r,r")
1420 
         (ashiftrt:HI (match_operand:HI 1 "register_operand"  "0,0")
1421 
                      (match_operand:HI 2 "nonmemory_operand" "r,P"))))]
1422 
  ""
1423 
  "@
1424 
      sra_cf %0,%2
1425 
      srai_cf %0,%2"
1426 
  [(set_attr "length" "1,1")])
1427 
 
1428 
(define_expand "ashrsi3"
1429 
  [(set (match_operand:SI 0 "register_operand" "")
1430 
        (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1431 
                     (match_operand:HI 2 "nonmemory_operand" "")))]
1432 
  ""
1433 
  "{
1434 
     if ((GET_CODE (operand2) == CONST_INT) && (INTVAL (operand2) <= 3))
1435 
       {
1436 
         int i;
1437 
         int k = INTVAL (operand2);
1438 
         emit_move_insn (operands[0], operands[1]);
1439 
         for (i = 0; i < k; i++)
1440 
           {
1441 
             emit_insn (gen_ashrsi1 (operands[0], operands[0]));
1442 
           }
1443 
         DONE;
1444 
       }
1445 
     else
1446 
       {
1447 
         FAIL;
1448 
       }
1449 
}")
1450 
 
1451 
(define_insn "ashrsi1"
1452 
  [(set (match_operand:SI 0 "register_operand"              "=r,r")
1453 
        (ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,0")
1454 
                     (const_int 1)))]
1455 
  ""
1456 
  "srai %B0, 1\;rrc %A0"
1457 
  [(set_attr "length" "2")])
1458 
 
1459 
(define_insn "ashrsi1"
1460 
  [(cond_exec
1461 
    (straight_cond:CC (reg:CC CC_REGNO)
1462 
                      (const_int 0))
1463 
    (set (match_operand:SI 0 "register_operand"              "=r,r")
1464 
         (ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,0")
1465 
                      (const_int 1))))]
1466 
  ""
1467 
  "srai_ct %B0, 1\;rrc_ct %A0"
1468 
  [(set_attr "length" "2")])
1469 
 
1470 
(define_insn "ashrsi1"
1471 
  [(cond_exec
1472 
    (inverted_cond:CC (reg:CC CC_REGNO)
1473 
                      (const_int 0))
1474 
    (set (match_operand:SI 0 "register_operand"              "=r,r")
1475 
         (ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,0")
1476 
                      (const_int 1))))]
1477 
  ""
1478 
  "srai_cf %B0, 1\;rrc_cf %A0"
1479 
  [(set_attr "length" "2")])
1480 
 
1481 
(define_insn "ashrdi1"
1482 
  [(set (match_operand:DI 0 "register_operand"              "=r,r")
1483 
        (ashiftrt:DI (match_operand:DI 1 "register_operand"  "0,0")
1484 
                   (const_int 1)))]
1485 
  ""
1486 
  "srai %D0, 1\;rrc %C0\;rrc %B0\;rrc %A0"
1487 
  [(set_attr "length" "4")])
1488 
(define_insn "ashrdi1"
1489 
  [(cond_exec
1490 
    (straight_cond:CC (reg:CC CC_REGNO)
1491 
                      (const_int 0))
1492 
    (set (match_operand:DI 0 "register_operand"              "=r,r")
1493 
         (ashiftrt:DI (match_operand:DI 1 "register_operand"  "0,0")
1494 
                    (const_int 1))))]
1495 
  ""
1496 
  "srai_ct %D0, 1\;rrc_ct %C0\;rrc_ct %B0\;rrc_ct %A0"
1497 
  [(set_attr "length" "4")])
1498 
 
1499 
(define_insn "ashrdi1"
1500 
  [(cond_exec
1501 
    (inverted_cond:CC (reg:CC CC_REGNO)
1502 
                      (const_int 0))
1503 
    (set (match_operand:DI 0 "register_operand"              "=r,r")
1504 
         (ashiftrt:DI (match_operand:DI 1 "register_operand"  "0,0")
1505 
                    (const_int 1))))]
1506 
  ""
1507 
  "srai_cf %D0, 1\;rrc_cf %C0\;rrc_cf %B0\;rrc_cf %A0"
1508 
  [(set_attr "length" "4")])
1509 
 
1510 
;;<< << << << << << << << << << << << << << << << << << << << << << << <<
1511 
;; ashl
1512 
 
1513 
(define_insn "ashlhi3"
1514 
  [(set (match_operand:HI 0 "register_operand"            "=r,r")
1515 
        (ashift:HI (match_operand:HI 1 "register_operand"  "0,0")
1516 
                   (match_operand:HI 2 "nonmemory_operand" "r,P")))]
1517 
  ""
1518 
  "@
1519 
      sl %0, %2
1520 
      sli %0, %2"
1521 
  [(set_attr "length" "1,1")])
1522 
 
1523 
(define_insn "ashlhi3"
1524 
  [(cond_exec
1525 
    (straight_cond:CC (reg:CC CC_REGNO)
1526 
                      (const_int 0))
1527 
    (set (match_operand:HI 0 "register_operand"            "=r,r")
1528 
         (ashift:HI (match_operand:HI 1 "register_operand"  "0,0")
1529 
                    (match_operand:HI 2 "nonmemory_operand" "r,P"))))]
1530 
  ""
1531 
  "@
1532 
      sl_ct %0,%2
1533 
      sli_ct %0,%2"
1534 
  [(set_attr "length" "1,1")])
1535 
 
1536 
(define_insn "ashlhi3"
1537 
  [(cond_exec
1538 
    (inverted_cond:CC (reg:CC CC_REGNO)
1539 
                      (const_int 0))
1540 
    (set (match_operand:HI 0 "register_operand"            "=r,r")
1541 
         (ashift:HI (match_operand:HI 1 "register_operand"  "0,0")
1542 
                    (match_operand:HI 2 "nonmemory_operand" "r,P"))))]
1543 
  ""
1544 
  "@
1545 
      sl_cf %0,%2
1546 
      sli_cf %0,%2"
1547 
  [(set_attr "length" "1,1")])
1548 
 
1549 
(define_expand "ashlsi3"
1550 
  [(set (match_operand:SI 0 "register_operand" "")
1551 
        (ashift:SI (match_operand:SI 1 "register_operand" "")
1552 
                   (match_operand:HI 2 "nonmemory_operand" "")))]
1553 
  ""
1554 
  "{
1555 
     if ((GET_CODE (operand2) == CONST_INT) && (INTVAL (operand2) <= 3))
1556 
       {
1557 
         int i;
1558 
         int k = INTVAL (operand2);
1559 
         emit_move_insn (operands[0], operands[1]);
1560 
         for (i = 0; i < k; i++)
1561 
           {
1562 
             emit_insn (gen_ashlsi1 (operands[0], operands[0]));
1563 
           }
1564 
         DONE;
1565 
       }
1566 
     else
1567 
       {
1568 
         FAIL;
1569 
       }
1570 
}")
1571 
 
1572 
(define_insn "ashlsi1"
1573 
  [(set (match_operand:SI 0 "register_operand"            "=r,r")
1574 
        (ashift:SI (match_operand:SI 1 "register_operand"  "0,0")
1575 
                   (const_int 1)))]
1576 
  ""
1577 
  "sli %A0, 1\;addc %B0, %B0"
1578 
  [(set_attr "length" "2")])
1579 
 
1580 
(define_insn "ashlsi1"
1581 
  [(cond_exec
1582 
    (straight_cond:CC (reg:CC CC_REGNO)
1583 
                      (const_int 0))
1584 
    (set (match_operand:SI 0 "register_operand"            "=r,r")
1585 
         (ashift:SI (match_operand:SI 1 "register_operand"  "0,0")
1586 
                    (const_int 1))))]
1587 
  ""
1588 
  "sli_ct %A0, 1\;addc_ct %B0, %B0"
1589 
  [(set_attr "length" "2")])
1590 
 
1591 
(define_insn "ashlsi1"
1592 
  [(cond_exec
1593 
    (inverted_cond:CC (reg:CC CC_REGNO)
1594 
                      (const_int 0))
1595 
    (set (match_operand:SI 0 "register_operand"            "=r,r")
1596 
         (ashift:SI (match_operand:SI 1 "register_operand"  "0,0")
1597 
                    (const_int 1))))]
1598 
  ""
1599 
  "sli_cf %A0, 1\;addc_cf %B0, %B0"
1600 
  [(set_attr "length" "4")])
1601 
 
1602 
(define_insn "ashldi1"
1603 
  [(set (match_operand:DI 0 "register_operand"            "=r,r")
1604 
        (ashift:DI (match_operand:DI 1 "register_operand"  "0,0")
1605 
                   (const_int 1)))]
1606 
  ""
1607 
  "sli %A0, 1\;addc %B0, %B0\;addc %C0, %C0\;addc %D0, %D0"
1608 
  [(set_attr "length" "4")])
1609 
 
1610 
(define_insn "ashldi1"
1611 
  [(cond_exec
1612 
    (straight_cond:CC (reg:CC CC_REGNO)
1613 
                      (const_int 0))
1614 
    (set (match_operand:DI 0 "register_operand"            "=r,r")
1615 
         (ashift:DI (match_operand:DI 1 "register_operand"  "0,0")
1616 
                    (const_int 1))))]
1617 
  ""
1618 
  "sli_ct %A0, 1\;addc_ct %B0, %B0\;addc_ct %C0, %C0\;addc_ct %D0, %D0"
1619 
  [(set_attr "length" "4")])
1620 
 
1621 
(define_insn "ashldi1"
1622 
  [(cond_exec
1623 
    (inverted_cond:CC (reg:CC CC_REGNO)
1624 
                      (const_int 0))
1625 
    (set (match_operand:DI 0 "register_operand"            "=r,r")
1626 
         (ashift:DI (match_operand:DI 1 "register_operand"  "0,0")
1627 
                    (const_int 1))))]
1628 
  ""
1629 
  "sli_cf %A0, 1\;addc_cf %B0, %B0\;addc_cf %C0, %C0\;addc_cf %D0, %D0"
1630 
  [(set_attr "length" "4")])
1631 
 
1632 
;; 0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x  0 - x
1633 
;; neg
1634 
 
1635 
(define_insn "neghi2"
1636 
  [(set (match_operand:HI 0 "register_operand"         "=r")
1637 
        (neg:HI (match_operand:HI 1 "register_operand"  "0")))]
1638 
  ""
1639 
  "neg %0"
1640 
  [(set_attr "length" "1")])
1641 
 
1642 
(define_insn "neghi3"
1643 
  [(cond_exec
1644 
    (straight_cond:CC (reg:CC CC_REGNO)
1645 
                      (const_int 0))
1646 
    (set (match_operand:HI 0 "register_operand"          "=r")
1647 
         (neg:HI (match_operand:HI 1 "register_operand"   "0"))))]
1648 
  ""
1649 
  "neg_ct %0"
1650 
  [(set_attr "length" "1")])
1651 
 
1652 
(define_insn "neghi3"
1653 
  [(cond_exec
1654 
    (inverted_cond:CC (reg:CC CC_REGNO)
1655 
                      (const_int 0))
1656 
    (set (match_operand:HI 0 "register_operand"          "=r")
1657 
         (neg:HI (match_operand:HI 1 "register_operand"   "0"))))]
1658 
  ""
1659 
  "neg_cf %0"
1660 
  [(set_attr "length" "1")])
1661 
 
1662 
;; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1663 
;; not
1664 
 
1665 
(define_insn "one_cmplhi2"
1666 
  [(set (match_operand:HI 0 "register_operand"         "=r")
1667 
        (not:HI (match_operand:HI 1 "register_operand"  "0")))]
1668 
  ""
1669 
  "not %0"
1670 
  [(set_attr "length" "1")])
1671 
 
1672 
(define_insn "one_cmplhi3"
1673 
  [(cond_exec
1674 
    (straight_cond:CC (reg:CC CC_REGNO)
1675 
                      (const_int 0))
1676 
    (set (match_operand:HI 0 "register_operand"          "=r")
1677 
         (not:HI (match_operand:HI 1 "register_operand"   "0"))))]
1678 
  ""
1679 
  "not_ct %0"
1680 
  [(set_attr "length" "1")])
1681 
 
1682 
(define_insn "one_cmplhi3"
1683 
  [(cond_exec
1684 
    (inverted_cond:CC (reg:CC CC_REGNO)
1685 
                      (const_int 0))
1686 
    (set (match_operand:HI 0 "register_operand"          "=r")
1687 
         (not:HI (match_operand:HI 1 "register_operand"   "0"))))]
1688 
  ""
1689 
  "not_cf %0"
1690 
  [(set_attr "length" "1")])
1691 
 
1692 
(define_insn "one_cmplsi2"
1693 
  [(set (match_operand:SI 0 "register_operand"         "=r")
1694 
        (not:SI (match_operand:SI 1 "register_operand"  "0")))]
1695 
  ""
1696 
  "not %A0\;not %B0"
1697 
  [(set_attr "length" "2")])
1698 
 
1699 
(define_insn "one_cmplsi3"
1700 
  [(cond_exec
1701 
    (straight_cond:CC (reg:CC CC_REGNO)
1702 
                      (const_int 0))
1703 
    (set (match_operand:SI 0 "register_operand"          "=r")
1704 
         (not:SI (match_operand:SI 1 "register_operand"   "0"))))]
1705 
  ""
1706 
  "not_ct %A0\;not_ct %B0"
1707 
  [(set_attr "length" "2")])
1708 
 
1709 
(define_insn "one_cmplsi3"
1710 
  [(cond_exec
1711 
    (inverted_cond:CC (reg:CC CC_REGNO)
1712 
                      (const_int 0))
1713 
    (set (match_operand:SI 0 "register_operand"          "=r")
1714 
         (not:SI (match_operand:SI 1 "register_operand"   "0"))))]
1715 
  ""
1716 
  "not_cf %A0\;not_cf %B0"
1717 
  [(set_attr "length" "2")])
1718 
 
1719 
(define_insn "one_cmpldi2"
1720 
  [(set (match_operand:DI 0 "register_operand"         "=r")
1721 
        (not:DI (match_operand:DI 1 "register_operand"  "0")))]
1722 
  ""
1723 
  "not %A0\;not %B0\;not %C0\;not %D0"
1724 
  [(set_attr "length" "4")])
1725 
 
1726 
(define_insn "one_cmpldi3"
1727 
  [(cond_exec
1728 
    (straight_cond:CC (reg:CC CC_REGNO)
1729 
                      (const_int 0))
1730 
    (set (match_operand:DI 0 "register_operand"          "=r")
1731 
         (not:DI (match_operand:DI 1 "register_operand"   "0"))))]
1732 
  ""
1733 
  "not_ct %A0\;not_ct %B0\;not_ct %C0\;not_ct %D0"
1734 
  [(set_attr "length" "4")])
1735 
 
1736 
(define_insn "one_cmpldi3"
1737 
  [(cond_exec
1738 
    (inverted_cond:CC (reg:CC CC_REGNO)
1739 
                      (const_int 0))
1740 
    (set (match_operand:DI 0 "register_operand"          "=r")
1741 
         (not:DI (match_operand:DI 1 "register_operand"   "0"))))]
1742 
  ""
1743 
  "not_cf %A0\;not_cf %B0\;not_cf %C0\;not_cf %D0"
1744 
  [(set_attr "length" "4")])
1745 
 
1746 
;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
1747 
;; compare
1748 
 
1749 
(define_insn "cmphi"
1750 
  [(set (reg:CC CC_REGNO)
1751 
        (compare:CC (match_operand:HI 0 "register_operand" "r,r")
1752 
                    (match_operand:HI 1 "nonmemory_operand" "r,K")))]
1753 
  ""
1754 
  "* return scarts16_out_compare(insn, operands);"
1755 
  [(set_attr "length" "1,2")])
1756 
 
1757 
 
1758 
(define_insn "cmpsi"
1759 
  [(set (reg:CC CC_REGNO)
1760 
        (compare:CC (match_operand:SI 0 "register_operand" "r")
1761 
                    (match_operand:SI 1 "register_operand" "r")))]
1762 
  ""
1763 
  "* return scarts16_out_compare(insn, operands);"
1764 
  [(set_attr "length" "7")])
1765 
 
1766 
(define_insn "cmpdi"
1767 
  [(set (reg:CC CC_REGNO)
1768 
        (compare:CC (match_operand:DI 0 "register_operand" "r")
1769 
                    (match_operand:DI 1 "register_operand" "r")))]
1770 
  ""
1771 
  "* return scarts16_out_compare(insn, operands);"
1772 
  [(set_attr "length" "15")])
1773 
 
1774 
(define_insn "btsthi"
1775 
  [(set (reg:CC CC_REGNO)
1776 
        (compare:CC (zero_extract:HI (match_operand:HI 0 "register_operand"  "r")
1777 
                                     (const_int 1)
1778 
                                     (match_operand:HI 1 "immediate_operand" "N"))
1779 
                    (const_int 0)))]
1780 
  ""
1781 
  "* return scarts16_out_bittest(insn, operands);"
1782 
  [(set_attr "length" "1")])
1783 
 
1784 
;; ----------------------------------------------------------------------
1785 
;; CONDITIONAL INSTRUCTIONS
1786 
;; ----------------------------------------------------------------------
1787 
 
1788 
;; ----------------------------------------------------------------------
1789 
;; Conditional jump instructions
1790 
 
1791 
(define_insn "b"
1792 
  [(set (pc)
1793 
        (if_then_else (any_cond:CC (reg:CC CC_REGNO)
1794 
                                   (const_int 0))
1795 
                      (label_ref (match_operand 0 "" ""))
1796 
                      (pc)))]
1797 
  ""
1798 
  "* return scarts16_out_branch(insn, operands, );"
1799 
  [(set (attr "length")
1800 
        (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -512))
1801 
                           (lt (minus (match_dup 0) (pc)) (const_int 511)))
1802 
                      (const_int 1)
1803 
                      (const_int 3)))])
1804 
 
1805 
;; ----------------------------------------------------------------------
1806 
;; Unconditional jump instructions
1807 
 
1808 
;; jump
1809 
 
1810 
(define_insn "jump"
1811 
  [(set (pc)
1812 
        (label_ref (match_operand 0 "" "")))]
1813 
  ""
1814 
  "* return scarts16_out_jump(insn, operands);"
1815 
  [(set (attr "length")
1816 
        (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -512))
1817 
                           (lt (minus (match_dup 0) (pc)) (const_int 511)))
1818 
                      (const_int 1)
1819 
                      (const_int 3)))])
1820 
 
1821 
; indirect jump
1822 
(define_insn "indirect_jump"
1823 
  [(set (pc) (match_operand:HI 0 "register_operand" "r"))]
1824 
  ""
1825 
  "jmp %0"
1826 
  [(set_attr "length" "1")])
1827 
 
1828 
;; **************************************************************************
1829 
;; NOP
1830 
 
1831 
(define_insn "nop"
1832 
  [(const_int 0)]
1833 
  ""
1834 
  "nop"
1835 
  [(set_attr "length" "1")])

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