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jlechner |
/* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
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Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
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2003, 2004, 2005, 2006 Free Software Foundation, Inc.
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Contributed by Steve Chamberlain (sac@cygnus.com).
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Improved by Jim Wilson (wilson@cygnus.com).
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#ifndef GCC_SH_H
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#define GCC_SH_H
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#define TARGET_VERSION \
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fputs (" (Hitachi SH)", stderr);
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/* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
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include it here, because bconfig.h is also included by gencodes.c . */
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/* ??? No longer true. */
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extern int code_for_indirect_jump_scratch;
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#define TARGET_CPU_CPP_BUILTINS() \
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do { \
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builtin_define ("__sh__"); \
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builtin_assert ("cpu=sh"); \
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builtin_assert ("machine=sh"); \
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switch ((int) sh_cpu) \
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{ \
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case PROCESSOR_SH1: \
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builtin_define ("__sh1__"); \
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break; \
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case PROCESSOR_SH2: \
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builtin_define ("__sh2__"); \
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break; \
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case PROCESSOR_SH2E: \
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builtin_define ("__SH2E__"); \
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break; \
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case PROCESSOR_SH2A: \
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builtin_define ("__SH2A__"); \
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builtin_define (TARGET_SH2A_DOUBLE \
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? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
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: TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
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: "__SH2A_NOFPU__"); \
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break; \
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case PROCESSOR_SH3: \
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builtin_define ("__sh3__"); \
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builtin_define ("__SH3__"); \
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if (TARGET_HARD_SH4) \
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builtin_define ("__SH4_NOFPU__"); \
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break; \
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case PROCESSOR_SH3E: \
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builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
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break; \
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case PROCESSOR_SH4: \
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builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
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break; \
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case PROCESSOR_SH4A: \
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builtin_define ("__SH4A__"); \
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builtin_define (TARGET_SH4 \
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? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
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: TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
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: "__SH4_NOFPU__"); \
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break; \
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case PROCESSOR_SH5: \
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{ \
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builtin_define_with_value ("__SH5__", \
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TARGET_SHMEDIA64 ? "64" : "32", 0); \
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builtin_define_with_value ("__SHMEDIA__", \
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TARGET_SHMEDIA ? "1" : "0", 0); \
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if (! TARGET_FPU_DOUBLE) \
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builtin_define ("__SH4_NOFPU__"); \
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} \
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} \
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if (TARGET_FPU_ANY) \
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builtin_define ("__SH_FPU_ANY__"); \
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if (TARGET_FPU_DOUBLE) \
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builtin_define ("__SH_FPU_DOUBLE__"); \
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if (TARGET_HITACHI) \
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builtin_define ("__HITACHI__"); \
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builtin_define (TARGET_LITTLE_ENDIAN \
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? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
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if (flag_pic) \
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{ \
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builtin_define ("__pic__"); \
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builtin_define ("__PIC__"); \
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} \
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} while (0)
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/* We can not debug without a frame pointer. */
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/* #define CAN_DEBUG_WITHOUT_FP */
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#define CONDITIONAL_REGISTER_USAGE do \
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{ \
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int regno; \
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for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
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if (! VALID_REGISTER_P (regno)) \
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fixed_regs[regno] = call_used_regs[regno] = 1; \
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/* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
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if (TARGET_SH5) \
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{ \
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call_used_regs[FIRST_GENERAL_REG + 8] \
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= call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
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call_really_used_regs[FIRST_GENERAL_REG + 8] \
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= call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
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} \
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if (TARGET_SHMEDIA) \
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{ \
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regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
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CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
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regno_reg_class[FIRST_FP_REG] = FP_REGS; \
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} \
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if (flag_pic) \
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{ \
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fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
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call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
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} \
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/* Renesas saves and restores mac registers on call. */ \
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if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
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{ \
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call_really_used_regs[MACH_REG] = 0; \
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call_really_used_regs[MACL_REG] = 0; \
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} \
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for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
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regno <= LAST_FP_REG; regno += 2) \
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SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
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if (TARGET_SHMEDIA) \
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{ \
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for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
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if (! fixed_regs[regno] && call_really_used_regs[regno]) \
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SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
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} \
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else \
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for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
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if (! fixed_regs[regno] && call_really_used_regs[regno]) \
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SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
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} while (0)
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/* Nonzero if this is an ELF target - compile time only */
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#define TARGET_ELF 0
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/* Nonzero if we should generate code using type 2E insns. */
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#define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
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/* Nonzero if we should generate code using type 2A insns. */
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#define TARGET_SH2A TARGET_HARD_SH2A
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/* Nonzero if we should generate code using type 2A SF insns. */
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#define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
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/* Nonzero if we should generate code using type 2A DF insns. */
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#define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
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/* Nonzero if we should generate code using type 3E insns. */
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#define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
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/* Nonzero if the cache line size is 32. */
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#define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
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/* Nonzero if we schedule for a superscalar implementation. */
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#define TARGET_SUPERSCALAR TARGET_HARD_SH4
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/* Nonzero if the target has separate instruction and data caches. */
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#define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
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/* Nonzero if a double-precision FPU is available. */
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#define TARGET_FPU_DOUBLE \
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((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
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/* Nonzero if an FPU is available. */
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#define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
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| 183 |
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/* Nonzero if we should generate code using type 4 insns. */
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#undef TARGET_SH4
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#define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
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/* Nonzero if we're generating code for the common subset of
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instructions present on both SH4a and SH4al-dsp. */
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#define TARGET_SH4A_ARCH TARGET_SH4A
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/* Nonzero if we're generating code for SH4a, unless the use of the
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FPU is disabled (which makes it compatible with SH4al-dsp). */
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#define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
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/* Nonzero if we should generate code using the SHcompact instruction
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set and 32-bit ABI. */
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#define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
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/* Nonzero if we should generate code using the SHmedia instruction
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set and ABI. */
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#define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
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| 203 |
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/* Nonzero if we should generate code using the SHmedia ISA and 32-bit
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ABI. */
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#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
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| 207 |
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/* Nonzero if we should generate code using the SHmedia ISA and 64-bit
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ABI. */
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#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
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| 211 |
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/* Nonzero if we should generate code using SHmedia FPU instructions. */
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#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
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| 213 |
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| 214 |
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/* This is not used by the SH2E calling convention */
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| 215 |
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#define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
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(TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
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&& ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
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| 219 |
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#ifndef TARGET_CPU_DEFAULT
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#define TARGET_CPU_DEFAULT SELECT_SH1
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#define SUPPORT_SH1 1
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#define SUPPORT_SH2E 1
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#define SUPPORT_SH4 1
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| 224 |
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#define SUPPORT_SH4_SINGLE 1
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#define SUPPORT_SH2A 1
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#define SUPPORT_SH2A_SINGLE 1
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#endif
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| 228 |
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| 229 |
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#define TARGET_DIVIDE_INV \
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(sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
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|| sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
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|| sh_div_strategy == SH_DIV_INV_CALL \
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|| sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
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#define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
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#define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
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| 236 |
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#define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
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| 237 |
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#define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
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| 238 |
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#define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
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| 239 |
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#define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
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| 240 |
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#define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
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| 241 |
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#define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
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| 242 |
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| 243 |
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#define SELECT_SH1 (MASK_SH1)
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| 244 |
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#define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
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| 245 |
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#define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
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| 246 |
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| MASK_FPU_SINGLE)
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| 247 |
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#define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
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| 248 |
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| MASK_HARD_SH2A_DOUBLE \
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| 249 |
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| MASK_SH2 | MASK_SH1)
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| 250 |
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#define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
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| 251 |
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#define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
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| 252 |
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| MASK_SH1 | MASK_FPU_SINGLE)
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| 253 |
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#define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
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| 254 |
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| MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
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| 255 |
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| MASK_SH2 | MASK_SH1)
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| 256 |
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#define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
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| 257 |
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#define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
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| 258 |
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#define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
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| 259 |
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#define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
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| 260 |
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#define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
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| 261 |
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| SELECT_SH3)
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| 262 |
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#define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
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| 263 |
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#define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
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| 264 |
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#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
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| 265 |
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#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
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| 266 |
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#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
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| 267 |
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#define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
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| 268 |
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#define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
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| 269 |
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#define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
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| 270 |
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#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
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| 271 |
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#define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
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| 272 |
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#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
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| 273 |
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| 274 |
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#if SUPPORT_SH1
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| 275 |
|
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#define SUPPORT_SH2 1
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| 276 |
|
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#endif
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| 277 |
|
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#if SUPPORT_SH2
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| 278 |
|
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#define SUPPORT_SH3 1
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| 279 |
|
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#endif
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| 280 |
|
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#if SUPPORT_SH3
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| 281 |
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#define SUPPORT_SH4_NOFPU 1
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| 282 |
|
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#endif
|
| 283 |
|
|
#if SUPPORT_SH4_NOFPU
|
| 284 |
|
|
#define SUPPORT_SH4A_NOFPU 1
|
| 285 |
|
|
#define SUPPORT_SH4AL 1
|
| 286 |
|
|
#define SUPPORT_SH2A_NOFPU 1
|
| 287 |
|
|
#endif
|
| 288 |
|
|
|
| 289 |
|
|
#if SUPPORT_SH2E
|
| 290 |
|
|
#define SUPPORT_SH3E 1
|
| 291 |
|
|
#endif
|
| 292 |
|
|
#if SUPPORT_SH3E
|
| 293 |
|
|
#define SUPPORT_SH4_SINGLE_ONLY 1
|
| 294 |
|
|
#define SUPPORT_SH4A_SINGLE_ONLY 1
|
| 295 |
|
|
#define SUPPORT_SH2A_SINGLE_ONLY 1
|
| 296 |
|
|
#endif
|
| 297 |
|
|
|
| 298 |
|
|
#if SUPPORT_SH4
|
| 299 |
|
|
#define SUPPORT_SH4A 1
|
| 300 |
|
|
#endif
|
| 301 |
|
|
|
| 302 |
|
|
#if SUPPORT_SH4_SINGLE
|
| 303 |
|
|
#define SUPPORT_SH4A_SINGLE 1
|
| 304 |
|
|
#endif
|
| 305 |
|
|
|
| 306 |
|
|
#if SUPPORT_SH5_COMPAT
|
| 307 |
|
|
#define SUPPORT_SH5_32MEDIA 1
|
| 308 |
|
|
#endif
|
| 309 |
|
|
|
| 310 |
|
|
#if SUPPORT_SH5_COMPACT_NOFPU
|
| 311 |
|
|
#define SUPPORT_SH5_32MEDIA_NOFPU 1
|
| 312 |
|
|
#endif
|
| 313 |
|
|
|
| 314 |
|
|
#define SUPPORT_ANY_SH5_32MEDIA \
|
| 315 |
|
|
(SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
|
| 316 |
|
|
#define SUPPORT_ANY_SH5_64MEDIA \
|
| 317 |
|
|
(SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
|
| 318 |
|
|
#define SUPPORT_ANY_SH5 \
|
| 319 |
|
|
(SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
|
| 320 |
|
|
|
| 321 |
|
|
/* Reset all target-selection flags. */
|
| 322 |
|
|
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
|
| 323 |
|
|
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
|
| 324 |
|
|
| MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
|
| 325 |
|
|
|
| 326 |
|
|
/* This defaults us to big-endian. */
|
| 327 |
|
|
#ifndef TARGET_ENDIAN_DEFAULT
|
| 328 |
|
|
#define TARGET_ENDIAN_DEFAULT 0
|
| 329 |
|
|
#endif
|
| 330 |
|
|
|
| 331 |
|
|
#ifndef TARGET_OPT_DEFAULT
|
| 332 |
|
|
#define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
|
| 333 |
|
|
#endif
|
| 334 |
|
|
|
| 335 |
|
|
#define TARGET_DEFAULT \
|
| 336 |
|
|
(TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
|
| 337 |
|
|
|
| 338 |
|
|
#ifndef SH_MULTILIB_CPU_DEFAULT
|
| 339 |
|
|
#define SH_MULTILIB_CPU_DEFAULT "m1"
|
| 340 |
|
|
#endif
|
| 341 |
|
|
|
| 342 |
|
|
#if TARGET_ENDIAN_DEFAULT
|
| 343 |
|
|
#define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
|
| 344 |
|
|
#else
|
| 345 |
|
|
#define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
|
| 346 |
|
|
#endif
|
| 347 |
|
|
|
| 348 |
|
|
#define CPP_SPEC " %(subtarget_cpp_spec) "
|
| 349 |
|
|
|
| 350 |
|
|
#ifndef SUBTARGET_CPP_SPEC
|
| 351 |
|
|
#define SUBTARGET_CPP_SPEC ""
|
| 352 |
|
|
#endif
|
| 353 |
|
|
|
| 354 |
|
|
#ifndef SUBTARGET_EXTRA_SPECS
|
| 355 |
|
|
#define SUBTARGET_EXTRA_SPECS
|
| 356 |
|
|
#endif
|
| 357 |
|
|
|
| 358 |
|
|
#define EXTRA_SPECS \
|
| 359 |
|
|
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
|
| 360 |
|
|
{ "link_emul_prefix", LINK_EMUL_PREFIX }, \
|
| 361 |
|
|
{ "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
|
| 362 |
|
|
{ "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
|
| 363 |
|
|
{ "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
|
| 364 |
|
|
{ "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
|
| 365 |
|
|
{ "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
|
| 366 |
|
|
{ "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
|
| 367 |
|
|
{ "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
|
| 368 |
|
|
SUBTARGET_EXTRA_SPECS
|
| 369 |
|
|
|
| 370 |
|
|
#if TARGET_CPU_DEFAULT & MASK_HARD_SH4
|
| 371 |
|
|
#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
|
| 372 |
|
|
#else
|
| 373 |
|
|
#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
|
| 374 |
|
|
#endif
|
| 375 |
|
|
|
| 376 |
|
|
#define SH_ASM_SPEC \
|
| 377 |
|
|
"%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
|
| 378 |
|
|
%(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
|
| 379 |
|
|
%{m2a:--isa=sh2a} \
|
| 380 |
|
|
%{m2a-single:--isa=sh2a} \
|
| 381 |
|
|
%{m2a-single-only:--isa=sh2a} \
|
| 382 |
|
|
%{m2a-nofpu:--isa=sh2a-nofpu} \
|
| 383 |
|
|
%{m5-compact*:--isa=SHcompact} \
|
| 384 |
|
|
%{m5-32media*:--isa=SHmedia --abi=32} \
|
| 385 |
|
|
%{m5-64media*:--isa=SHmedia --abi=64} \
|
| 386 |
|
|
%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
|
| 387 |
|
|
|
| 388 |
|
|
#define ASM_SPEC SH_ASM_SPEC
|
| 389 |
|
|
|
| 390 |
|
|
#ifndef SUBTARGET_ASM_ENDIAN_SPEC
|
| 391 |
|
|
#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
|
| 392 |
|
|
#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
|
| 393 |
|
|
#else
|
| 394 |
|
|
#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
|
| 395 |
|
|
#endif
|
| 396 |
|
|
#endif
|
| 397 |
|
|
|
| 398 |
|
|
#if STRICT_NOFPU == 1
|
| 399 |
|
|
/* Strict nofpu means that the compiler should tell the assembler
|
| 400 |
|
|
to reject FPU instructions. E.g. from ASM inserts. */
|
| 401 |
|
|
#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
|
| 402 |
|
|
#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
|
| 403 |
|
|
#else
|
| 404 |
|
|
/* If there were an -isa option for sh5-nofpu then it would also go here. */
|
| 405 |
|
|
#define SUBTARGET_ASM_ISA_SPEC \
|
| 406 |
|
|
"%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
|
| 407 |
|
|
#endif
|
| 408 |
|
|
#else /* ! STRICT_NOFPU */
|
| 409 |
|
|
#define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
|
| 410 |
|
|
#endif
|
| 411 |
|
|
|
| 412 |
|
|
#ifndef SUBTARGET_ASM_SPEC
|
| 413 |
|
|
#define SUBTARGET_ASM_SPEC ""
|
| 414 |
|
|
#endif
|
| 415 |
|
|
|
| 416 |
|
|
#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
|
| 417 |
|
|
#define LINK_EMUL_PREFIX "sh%{!mb:l}"
|
| 418 |
|
|
#else
|
| 419 |
|
|
#define LINK_EMUL_PREFIX "sh%{ml:l}"
|
| 420 |
|
|
#endif
|
| 421 |
|
|
|
| 422 |
|
|
#if TARGET_CPU_DEFAULT & MASK_SH5
|
| 423 |
|
|
#if TARGET_CPU_DEFAULT & MASK_SH_E
|
| 424 |
|
|
#define LINK_DEFAULT_CPU_EMUL "32"
|
| 425 |
|
|
#if TARGET_CPU_DEFAULT & MASK_SH1
|
| 426 |
|
|
#define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
|
| 427 |
|
|
#else
|
| 428 |
|
|
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
|
| 429 |
|
|
#endif /* MASK_SH1 */
|
| 430 |
|
|
#else /* !MASK_SH_E */
|
| 431 |
|
|
#define LINK_DEFAULT_CPU_EMUL "64"
|
| 432 |
|
|
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
|
| 433 |
|
|
#endif /* MASK_SH_E */
|
| 434 |
|
|
#define ASM_ISA_DEFAULT_SPEC \
|
| 435 |
|
|
" %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
|
| 436 |
|
|
#else /* !MASK_SH5 */
|
| 437 |
|
|
#define LINK_DEFAULT_CPU_EMUL ""
|
| 438 |
|
|
#define ASM_ISA_DEFAULT_SPEC ""
|
| 439 |
|
|
#endif /* MASK_SH5 */
|
| 440 |
|
|
|
| 441 |
|
|
#define SUBTARGET_LINK_EMUL_SUFFIX ""
|
| 442 |
|
|
#define SUBTARGET_LINK_SPEC ""
|
| 443 |
|
|
|
| 444 |
|
|
/* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
|
| 445 |
|
|
so that we can undo the damage without code replication. */
|
| 446 |
|
|
#define LINK_SPEC SH_LINK_SPEC
|
| 447 |
|
|
|
| 448 |
|
|
#define SH_LINK_SPEC "\
|
| 449 |
|
|
-m %(link_emul_prefix)\
|
| 450 |
|
|
%{m5-compact*|m5-32media*:32}\
|
| 451 |
|
|
%{m5-64media*:64}\
|
| 452 |
|
|
%{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
|
| 453 |
|
|
%(subtarget_link_emul_suffix) \
|
| 454 |
|
|
%{mrelax:-relax} %(subtarget_link_spec)"
|
| 455 |
|
|
|
| 456 |
|
|
#ifndef SH_DIV_STR_FOR_SIZE
|
| 457 |
|
|
#define SH_DIV_STR_FOR_SIZE "call"
|
| 458 |
|
|
#endif
|
| 459 |
|
|
|
| 460 |
|
|
#define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
|
| 461 |
|
|
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
|
| 462 |
|
|
do { \
|
| 463 |
|
|
if (LEVEL) \
|
| 464 |
|
|
{ \
|
| 465 |
|
|
flag_omit_frame_pointer = -1; \
|
| 466 |
|
|
if (! SIZE) \
|
| 467 |
|
|
sh_div_str = "inv:minlat"; \
|
| 468 |
|
|
} \
|
| 469 |
|
|
if (SIZE) \
|
| 470 |
|
|
{ \
|
| 471 |
|
|
target_flags |= MASK_SMALLCODE; \
|
| 472 |
|
|
sh_div_str = SH_DIV_STR_FOR_SIZE ; \
|
| 473 |
|
|
} \
|
| 474 |
|
|
/* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
|
| 475 |
|
|
haven't been parsed yet, hence we';d read only the default. \
|
| 476 |
|
|
sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
|
| 477 |
|
|
it's OK to always set flag_branch_target_load_optimize. */ \
|
| 478 |
|
|
if (LEVEL > 1) \
|
| 479 |
|
|
{ \
|
| 480 |
|
|
flag_branch_target_load_optimize = 1; \
|
| 481 |
|
|
if (! (SIZE)) \
|
| 482 |
|
|
target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
|
| 483 |
|
|
} \
|
| 484 |
|
|
/* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
|
| 485 |
|
|
here, so leave it to OVERRIDE_OPTIONS to set \
|
| 486 |
|
|
flag_finite_math_only. We set it to 2 here so we know if the user \
|
| 487 |
|
|
explicitly requested this to be on or off. */ \
|
| 488 |
|
|
flag_finite_math_only = 2; \
|
| 489 |
|
|
/* If flag_schedule_insns is 1, we set it to 2 here so we know if \
|
| 490 |
|
|
the user explicitly requested this to be on or off. */ \
|
| 491 |
|
|
if (flag_schedule_insns > 0) \
|
| 492 |
|
|
flag_schedule_insns = 2; \
|
| 493 |
|
|
} while (0)
|
| 494 |
|
|
|
| 495 |
|
|
#define ASSEMBLER_DIALECT assembler_dialect
|
| 496 |
|
|
|
| 497 |
|
|
extern int assembler_dialect;
|
| 498 |
|
|
|
| 499 |
|
|
enum sh_divide_strategy_e {
|
| 500 |
|
|
SH_DIV_CALL,
|
| 501 |
|
|
SH_DIV_CALL2,
|
| 502 |
|
|
SH_DIV_FP,
|
| 503 |
|
|
SH_DIV_INV,
|
| 504 |
|
|
SH_DIV_INV_MINLAT,
|
| 505 |
|
|
SH_DIV_INV20U,
|
| 506 |
|
|
SH_DIV_INV20L,
|
| 507 |
|
|
SH_DIV_INV_CALL,
|
| 508 |
|
|
SH_DIV_INV_CALL2,
|
| 509 |
|
|
SH_DIV_INV_FP
|
| 510 |
|
|
};
|
| 511 |
|
|
|
| 512 |
|
|
extern enum sh_divide_strategy_e sh_div_strategy;
|
| 513 |
|
|
|
| 514 |
|
|
#ifndef SH_DIV_STRATEGY_DEFAULT
|
| 515 |
|
|
#define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
|
| 516 |
|
|
#endif
|
| 517 |
|
|
|
| 518 |
|
|
#define OVERRIDE_OPTIONS \
|
| 519 |
|
|
do { \
|
| 520 |
|
|
int regno; \
|
| 521 |
|
|
\
|
| 522 |
|
|
if (flag_finite_math_only == 2) \
|
| 523 |
|
|
flag_finite_math_only \
|
| 524 |
|
|
= !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
|
| 525 |
|
|
if (TARGET_SH2E && !flag_finite_math_only) \
|
| 526 |
|
|
target_flags |= MASK_IEEE; \
|
| 527 |
|
|
sh_cpu = CPU_SH1; \
|
| 528 |
|
|
assembler_dialect = 0; \
|
| 529 |
|
|
if (TARGET_SH2) \
|
| 530 |
|
|
sh_cpu = CPU_SH2; \
|
| 531 |
|
|
if (TARGET_SH2E) \
|
| 532 |
|
|
sh_cpu = CPU_SH2E; \
|
| 533 |
|
|
if (TARGET_SH2A) \
|
| 534 |
|
|
{ \
|
| 535 |
|
|
sh_cpu = CPU_SH2A; \
|
| 536 |
|
|
if (TARGET_SH2A_DOUBLE) \
|
| 537 |
|
|
target_flags |= MASK_FMOVD; \
|
| 538 |
|
|
} \
|
| 539 |
|
|
if (TARGET_SH3) \
|
| 540 |
|
|
sh_cpu = CPU_SH3; \
|
| 541 |
|
|
if (TARGET_SH3E) \
|
| 542 |
|
|
sh_cpu = CPU_SH3E; \
|
| 543 |
|
|
if (TARGET_SH4) \
|
| 544 |
|
|
{ \
|
| 545 |
|
|
assembler_dialect = 1; \
|
| 546 |
|
|
sh_cpu = CPU_SH4; \
|
| 547 |
|
|
} \
|
| 548 |
|
|
if (TARGET_SH4A_ARCH) \
|
| 549 |
|
|
{ \
|
| 550 |
|
|
assembler_dialect = 1; \
|
| 551 |
|
|
sh_cpu = CPU_SH4A; \
|
| 552 |
|
|
} \
|
| 553 |
|
|
if (TARGET_SH5) \
|
| 554 |
|
|
{ \
|
| 555 |
|
|
sh_cpu = CPU_SH5; \
|
| 556 |
|
|
target_flags |= MASK_ALIGN_DOUBLE; \
|
| 557 |
|
|
if (TARGET_SHMEDIA_FPU) \
|
| 558 |
|
|
target_flags |= MASK_FMOVD; \
|
| 559 |
|
|
if (TARGET_SHMEDIA) \
|
| 560 |
|
|
{ \
|
| 561 |
|
|
/* There are no delay slots on SHmedia. */ \
|
| 562 |
|
|
flag_delayed_branch = 0; \
|
| 563 |
|
|
/* Relaxation isn't yet supported for SHmedia */ \
|
| 564 |
|
|
target_flags &= ~MASK_RELAX; \
|
| 565 |
|
|
/* After reload, if conversion does little good but can cause \
|
| 566 |
|
|
ICEs: \
|
| 567 |
|
|
- find_if_block doesn't do anything for SH because we don't\
|
| 568 |
|
|
have conditional execution patterns. (We use conditional\
|
| 569 |
|
|
move patterns, which are handled differently, and only \
|
| 570 |
|
|
before reload). \
|
| 571 |
|
|
- find_cond_trap doesn't do anything for the SH because we \
|
| 572 |
|
|
don't have conditional traps. \
|
| 573 |
|
|
- find_if_case_1 uses redirect_edge_and_branch_force in \
|
| 574 |
|
|
the only path that does an optimization, and this causes \
|
| 575 |
|
|
an ICE when branch targets are in registers. \
|
| 576 |
|
|
- find_if_case_2 doesn't do anything for the SHmedia after \
|
| 577 |
|
|
reload except when it can redirect a tablejump - and \
|
| 578 |
|
|
that's rather rare. */ \
|
| 579 |
|
|
flag_if_conversion2 = 0; \
|
| 580 |
|
|
if (! strcmp (sh_div_str, "call")) \
|
| 581 |
|
|
sh_div_strategy = SH_DIV_CALL; \
|
| 582 |
|
|
else if (! strcmp (sh_div_str, "call2")) \
|
| 583 |
|
|
sh_div_strategy = SH_DIV_CALL2; \
|
| 584 |
|
|
if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
|
| 585 |
|
|
sh_div_strategy = SH_DIV_FP; \
|
| 586 |
|
|
else if (! strcmp (sh_div_str, "inv")) \
|
| 587 |
|
|
sh_div_strategy = SH_DIV_INV; \
|
| 588 |
|
|
else if (! strcmp (sh_div_str, "inv:minlat")) \
|
| 589 |
|
|
sh_div_strategy = SH_DIV_INV_MINLAT; \
|
| 590 |
|
|
else if (! strcmp (sh_div_str, "inv20u")) \
|
| 591 |
|
|
sh_div_strategy = SH_DIV_INV20U; \
|
| 592 |
|
|
else if (! strcmp (sh_div_str, "inv20l")) \
|
| 593 |
|
|
sh_div_strategy = SH_DIV_INV20L; \
|
| 594 |
|
|
else if (! strcmp (sh_div_str, "inv:call2")) \
|
| 595 |
|
|
sh_div_strategy = SH_DIV_INV_CALL2; \
|
| 596 |
|
|
else if (! strcmp (sh_div_str, "inv:call")) \
|
| 597 |
|
|
sh_div_strategy = SH_DIV_INV_CALL; \
|
| 598 |
|
|
else if (! strcmp (sh_div_str, "inv:fp")) \
|
| 599 |
|
|
{ \
|
| 600 |
|
|
if (TARGET_FPU_ANY) \
|
| 601 |
|
|
sh_div_strategy = SH_DIV_INV_FP; \
|
| 602 |
|
|
else \
|
| 603 |
|
|
sh_div_strategy = SH_DIV_INV; \
|
| 604 |
|
|
} \
|
| 605 |
|
|
} \
|
| 606 |
|
|
/* -fprofile-arcs needs a working libgcov . In unified tree \
|
| 607 |
|
|
configurations with newlib, this requires to configure with \
|
| 608 |
|
|
--with-newlib --with-headers. But there is no way to check \
|
| 609 |
|
|
here we have a working libgcov, so just assume that we have. */\
|
| 610 |
|
|
if (profile_flag) \
|
| 611 |
|
|
warning (0, "profiling is still experimental for this target");\
|
| 612 |
|
|
} \
|
| 613 |
|
|
else \
|
| 614 |
|
|
{ \
|
| 615 |
|
|
/* Only the sh64-elf assembler fully supports .quad properly. */\
|
| 616 |
|
|
targetm.asm_out.aligned_op.di = NULL; \
|
| 617 |
|
|
targetm.asm_out.unaligned_op.di = NULL; \
|
| 618 |
|
|
} \
|
| 619 |
|
|
if (sh_divsi3_libfunc[0]) \
|
| 620 |
|
|
; /* User supplied - leave it alone. */ \
|
| 621 |
|
|
else if (TARGET_HARD_SH4 && TARGET_SH2E) \
|
| 622 |
|
|
sh_divsi3_libfunc = "__sdivsi3_i4"; \
|
| 623 |
|
|
else if (TARGET_SH5) \
|
| 624 |
|
|
{ \
|
| 625 |
|
|
if (TARGET_FPU_ANY && TARGET_SH1) \
|
| 626 |
|
|
sh_divsi3_libfunc = "__sdivsi3_i4"; \
|
| 627 |
|
|
else \
|
| 628 |
|
|
sh_divsi3_libfunc = "__sdivsi3_1"; \
|
| 629 |
|
|
} \
|
| 630 |
|
|
else \
|
| 631 |
|
|
sh_divsi3_libfunc = "__sdivsi3"; \
|
| 632 |
|
|
if (TARGET_FMOVD) \
|
| 633 |
|
|
reg_class_from_letter['e' - 'a'] = NO_REGS; \
|
| 634 |
|
|
\
|
| 635 |
|
|
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
|
| 636 |
|
|
if (! VALID_REGISTER_P (regno)) \
|
| 637 |
|
|
sh_register_names[regno][0] = '\0'; \
|
| 638 |
|
|
\
|
| 639 |
|
|
for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
|
| 640 |
|
|
if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
|
| 641 |
|
|
sh_additional_register_names[regno][0] = '\0'; \
|
| 642 |
|
|
\
|
| 643 |
|
|
if (flag_omit_frame_pointer < 0) \
|
| 644 |
|
|
{ \
|
| 645 |
|
|
/* The debugging information is sufficient, \
|
| 646 |
|
|
but gdb doesn't implement this yet */ \
|
| 647 |
|
|
if (0) \
|
| 648 |
|
|
flag_omit_frame_pointer \
|
| 649 |
|
|
= (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
|
| 650 |
|
|
else \
|
| 651 |
|
|
flag_omit_frame_pointer = 0; \
|
| 652 |
|
|
} \
|
| 653 |
|
|
\
|
| 654 |
|
|
if ((flag_pic && ! TARGET_PREFERGOT) \
|
| 655 |
|
|
|| (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
|
| 656 |
|
|
flag_no_function_cse = 1; \
|
| 657 |
|
|
\
|
| 658 |
|
|
if (SMALL_REGISTER_CLASSES) \
|
| 659 |
|
|
{ \
|
| 660 |
|
|
/* Never run scheduling before reload, since that can \
|
| 661 |
|
|
break global alloc, and generates slower code anyway due \
|
| 662 |
|
|
to the pressure on R0. */ \
|
| 663 |
|
|
/* Enable sched1 for SH4; ready queue will be reordered by \
|
| 664 |
|
|
the target hooks when pressure is high. We can not do this for \
|
| 665 |
|
|
SH3 and lower as they give spill failures for R0. */ \
|
| 666 |
|
|
if (!TARGET_HARD_SH4) \
|
| 667 |
|
|
flag_schedule_insns = 0; \
|
| 668 |
|
|
/* ??? Current exception handling places basic block boundaries \
|
| 669 |
|
|
after call_insns. It causes the high pressure on R0 and gives \
|
| 670 |
|
|
spill failures for R0 in reload. See PR 22553 and the thread \
|
| 671 |
|
|
on gcc-patches \
|
| 672 |
|
|
<http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
|
| 673 |
|
|
else if (flag_exceptions) \
|
| 674 |
|
|
{ \
|
| 675 |
|
|
if (flag_schedule_insns == 1) \
|
| 676 |
|
|
warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
|
| 677 |
|
|
flag_schedule_insns = 0; \
|
| 678 |
|
|
} \
|
| 679 |
|
|
} \
|
| 680 |
|
|
\
|
| 681 |
|
|
if (align_loops == 0) \
|
| 682 |
|
|
align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
|
| 683 |
|
|
if (align_jumps == 0) \
|
| 684 |
|
|
align_jumps = 1 << CACHE_LOG; \
|
| 685 |
|
|
else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
|
| 686 |
|
|
align_jumps = TARGET_SHMEDIA ? 4 : 2; \
|
| 687 |
|
|
\
|
| 688 |
|
|
/* Allocation boundary (in *bytes*) for the code of a function. \
|
| 689 |
|
|
SH1: 32 bit alignment is faster, because instructions are always \
|
| 690 |
|
|
fetched as a pair from a longword boundary. \
|
| 691 |
|
|
SH2 .. SH5 : align to cache line start. */ \
|
| 692 |
|
|
if (align_functions == 0) \
|
| 693 |
|
|
align_functions \
|
| 694 |
|
|
= TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
|
| 695 |
|
|
/* The linker relaxation code breaks when a function contains \
|
| 696 |
|
|
alignments that are larger than that at the start of a \
|
| 697 |
|
|
compilation unit. */ \
|
| 698 |
|
|
if (TARGET_RELAX) \
|
| 699 |
|
|
{ \
|
| 700 |
|
|
int min_align \
|
| 701 |
|
|
= align_loops > align_jumps ? align_loops : align_jumps; \
|
| 702 |
|
|
\
|
| 703 |
|
|
/* Also take possible .long constants / mova tables int account. */\
|
| 704 |
|
|
if (min_align < 4) \
|
| 705 |
|
|
min_align = 4; \
|
| 706 |
|
|
if (align_functions < min_align) \
|
| 707 |
|
|
align_functions = min_align; \
|
| 708 |
|
|
} \
|
| 709 |
|
|
} while (0)
|
| 710 |
|
|
|
| 711 |
|
|
/* Target machine storage layout. */
|
| 712 |
|
|
|
| 713 |
|
|
/* Define this if most significant bit is lowest numbered
|
| 714 |
|
|
in instructions that operate on numbered bit-fields. */
|
| 715 |
|
|
|
| 716 |
|
|
#define BITS_BIG_ENDIAN 0
|
| 717 |
|
|
|
| 718 |
|
|
/* Define this if most significant byte of a word is the lowest numbered. */
|
| 719 |
|
|
#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
|
| 720 |
|
|
|
| 721 |
|
|
/* Define this if most significant word of a multiword number is the lowest
|
| 722 |
|
|
numbered. */
|
| 723 |
|
|
#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
|
| 724 |
|
|
|
| 725 |
|
|
/* Define this to set the endianness to use in libgcc2.c, which can
|
| 726 |
|
|
not depend on target_flags. */
|
| 727 |
|
|
#if defined(__LITTLE_ENDIAN__)
|
| 728 |
|
|
#define LIBGCC2_WORDS_BIG_ENDIAN 0
|
| 729 |
|
|
#else
|
| 730 |
|
|
#define LIBGCC2_WORDS_BIG_ENDIAN 1
|
| 731 |
|
|
#endif
|
| 732 |
|
|
|
| 733 |
|
|
#define MAX_BITS_PER_WORD 64
|
| 734 |
|
|
|
| 735 |
|
|
/* Width in bits of an `int'. We want just 32-bits, even if words are
|
| 736 |
|
|
longer. */
|
| 737 |
|
|
#define INT_TYPE_SIZE 32
|
| 738 |
|
|
|
| 739 |
|
|
/* Width in bits of a `long'. */
|
| 740 |
|
|
#define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
|
| 741 |
|
|
|
| 742 |
|
|
/* Width in bits of a `long long'. */
|
| 743 |
|
|
#define LONG_LONG_TYPE_SIZE 64
|
| 744 |
|
|
|
| 745 |
|
|
/* Width in bits of a `long double'. */
|
| 746 |
|
|
#define LONG_DOUBLE_TYPE_SIZE 64
|
| 747 |
|
|
|
| 748 |
|
|
/* Width of a word, in units (bytes). */
|
| 749 |
|
|
#define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
|
| 750 |
|
|
#define MIN_UNITS_PER_WORD 4
|
| 751 |
|
|
|
| 752 |
|
|
/* Scaling factor for Dwarf data offsets for CFI information.
|
| 753 |
|
|
The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
|
| 754 |
|
|
SHmedia; however, since we do partial register saves for the registers
|
| 755 |
|
|
visible to SHcompact, and for target registers for SHMEDIA32, we have
|
| 756 |
|
|
to allow saves that are only 4-byte aligned. */
|
| 757 |
|
|
#define DWARF_CIE_DATA_ALIGNMENT -4
|
| 758 |
|
|
|
| 759 |
|
|
/* Width in bits of a pointer.
|
| 760 |
|
|
See also the macro `Pmode' defined below. */
|
| 761 |
|
|
#define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
|
| 762 |
|
|
|
| 763 |
|
|
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
|
| 764 |
|
|
#define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
|
| 765 |
|
|
|
| 766 |
|
|
/* Boundary (in *bits*) on which stack pointer should be aligned. */
|
| 767 |
|
|
#define STACK_BOUNDARY BIGGEST_ALIGNMENT
|
| 768 |
|
|
|
| 769 |
|
|
/* The log (base 2) of the cache line size, in bytes. Processors prior to
|
| 770 |
|
|
SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
|
| 771 |
|
|
The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
|
| 772 |
|
|
#define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
|
| 773 |
|
|
|
| 774 |
|
|
/* ABI given & required minimum allocation boundary (in *bits*) for the
|
| 775 |
|
|
code of a function. */
|
| 776 |
|
|
#define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
|
| 777 |
|
|
|
| 778 |
|
|
/* On SH5, the lowest bit is used to indicate SHmedia functions, so
|
| 779 |
|
|
the vbit must go into the delta field of
|
| 780 |
|
|
pointers-to-member-functions. */
|
| 781 |
|
|
#define TARGET_PTRMEMFUNC_VBIT_LOCATION \
|
| 782 |
|
|
(TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
|
| 783 |
|
|
|
| 784 |
|
|
/* Alignment of field after `int : 0' in a structure. */
|
| 785 |
|
|
#define EMPTY_FIELD_BOUNDARY 32
|
| 786 |
|
|
|
| 787 |
|
|
/* No data type wants to be aligned rounder than this. */
|
| 788 |
|
|
#define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
|
| 789 |
|
|
|
| 790 |
|
|
/* The best alignment to use in cases where we have a choice. */
|
| 791 |
|
|
#define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
|
| 792 |
|
|
|
| 793 |
|
|
/* Make strings word-aligned so strcpy from constants will be faster. */
|
| 794 |
|
|
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
|
| 795 |
|
|
((TREE_CODE (EXP) == STRING_CST \
|
| 796 |
|
|
&& (ALIGN) < FASTEST_ALIGNMENT) \
|
| 797 |
|
|
? FASTEST_ALIGNMENT : (ALIGN))
|
| 798 |
|
|
|
| 799 |
|
|
/* get_mode_alignment assumes complex values are always held in multiple
|
| 800 |
|
|
registers, but that is not the case on the SH; CQImode and CHImode are
|
| 801 |
|
|
held in a single integer register. SH5 also holds CSImode and SCmode
|
| 802 |
|
|
values in integer registers. This is relevant for argument passing on
|
| 803 |
|
|
SHcompact as we use a stack temp in order to pass CSImode by reference. */
|
| 804 |
|
|
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
|
| 805 |
|
|
((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
|
| 806 |
|
|
|| GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
|
| 807 |
|
|
? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
|
| 808 |
|
|
: (unsigned) ALIGN)
|
| 809 |
|
|
|
| 810 |
|
|
/* Make arrays of chars word-aligned for the same reasons. */
|
| 811 |
|
|
#define DATA_ALIGNMENT(TYPE, ALIGN) \
|
| 812 |
|
|
(TREE_CODE (TYPE) == ARRAY_TYPE \
|
| 813 |
|
|
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
|
| 814 |
|
|
&& (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
|
| 815 |
|
|
|
| 816 |
|
|
/* Number of bits which any structure or union's size must be a
|
| 817 |
|
|
multiple of. Each structure or union's size is rounded up to a
|
| 818 |
|
|
multiple of this. */
|
| 819 |
|
|
#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
|
| 820 |
|
|
|
| 821 |
|
|
/* Set this nonzero if move instructions will actually fail to work
|
| 822 |
|
|
when given unaligned data. */
|
| 823 |
|
|
#define STRICT_ALIGNMENT 1
|
| 824 |
|
|
|
| 825 |
|
|
/* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
|
| 826 |
|
|
#define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
|
| 827 |
|
|
barrier_align (LABEL_AFTER_BARRIER)
|
| 828 |
|
|
|
| 829 |
|
|
#define LOOP_ALIGN(A_LABEL) \
|
| 830 |
|
|
((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
|
| 831 |
|
|
? 0 : sh_loop_align (A_LABEL))
|
| 832 |
|
|
|
| 833 |
|
|
#define LABEL_ALIGN(A_LABEL) \
|
| 834 |
|
|
( \
|
| 835 |
|
|
(PREV_INSN (A_LABEL) \
|
| 836 |
|
|
&& GET_CODE (PREV_INSN (A_LABEL)) == INSN \
|
| 837 |
|
|
&& GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
|
| 838 |
|
|
&& XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
|
| 839 |
|
|
/* explicit alignment insn in constant tables. */ \
|
| 840 |
|
|
? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
|
| 841 |
|
|
: 0)
|
| 842 |
|
|
|
| 843 |
|
|
/* Jump tables must be 32 bit aligned, no matter the size of the element. */
|
| 844 |
|
|
#define ADDR_VEC_ALIGN(ADDR_VEC) 2
|
| 845 |
|
|
|
| 846 |
|
|
/* The base two logarithm of the known minimum alignment of an insn length. */
|
| 847 |
|
|
#define INSN_LENGTH_ALIGNMENT(A_INSN) \
|
| 848 |
|
|
(GET_CODE (A_INSN) == INSN \
|
| 849 |
|
|
? 1 << TARGET_SHMEDIA \
|
| 850 |
|
|
: GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
|
| 851 |
|
|
? 1 << TARGET_SHMEDIA \
|
| 852 |
|
|
: CACHE_LOG)
|
| 853 |
|
|
|
| 854 |
|
|
/* Standard register usage. */
|
| 855 |
|
|
|
| 856 |
|
|
/* Register allocation for the Renesas calling convention:
|
| 857 |
|
|
|
| 858 |
|
|
r0 arg return
|
| 859 |
|
|
r1..r3 scratch
|
| 860 |
|
|
r4..r7 args in
|
| 861 |
|
|
r8..r13 call saved
|
| 862 |
|
|
r14 frame pointer/call saved
|
| 863 |
|
|
r15 stack pointer
|
| 864 |
|
|
ap arg pointer (doesn't really exist, always eliminated)
|
| 865 |
|
|
pr subroutine return address
|
| 866 |
|
|
t t bit
|
| 867 |
|
|
mach multiply/accumulate result, high part
|
| 868 |
|
|
macl multiply/accumulate result, low part.
|
| 869 |
|
|
fpul fp/int communication register
|
| 870 |
|
|
rap return address pointer register
|
| 871 |
|
|
fr0 fp arg return
|
| 872 |
|
|
fr1..fr3 scratch floating point registers
|
| 873 |
|
|
fr4..fr11 fp args in
|
| 874 |
|
|
fr12..fr15 call saved floating point registers */
|
| 875 |
|
|
|
| 876 |
|
|
#define MAX_REGISTER_NAME_LENGTH 5
|
| 877 |
|
|
extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
|
| 878 |
|
|
|
| 879 |
|
|
#define SH_REGISTER_NAMES_INITIALIZER \
|
| 880 |
|
|
{ \
|
| 881 |
|
|
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
|
| 882 |
|
|
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
|
| 883 |
|
|
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
|
| 884 |
|
|
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
|
| 885 |
|
|
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
|
| 886 |
|
|
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
|
| 887 |
|
|
"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
|
| 888 |
|
|
"r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
|
| 889 |
|
|
"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
|
| 890 |
|
|
"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
|
| 891 |
|
|
"fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
|
| 892 |
|
|
"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
|
| 893 |
|
|
"fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
|
| 894 |
|
|
"fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
|
| 895 |
|
|
"fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
|
| 896 |
|
|
"fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
|
| 897 |
|
|
"tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
|
| 898 |
|
|
"xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
|
| 899 |
|
|
"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
|
| 900 |
|
|
"rap", "sfp" \
|
| 901 |
|
|
}
|
| 902 |
|
|
|
| 903 |
|
|
#define REGNAMES_ARR_INDEX_1(index) \
|
| 904 |
|
|
(sh_register_names[index])
|
| 905 |
|
|
#define REGNAMES_ARR_INDEX_2(index) \
|
| 906 |
|
|
REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
|
| 907 |
|
|
#define REGNAMES_ARR_INDEX_4(index) \
|
| 908 |
|
|
REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
|
| 909 |
|
|
#define REGNAMES_ARR_INDEX_8(index) \
|
| 910 |
|
|
REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
|
| 911 |
|
|
#define REGNAMES_ARR_INDEX_16(index) \
|
| 912 |
|
|
REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
|
| 913 |
|
|
#define REGNAMES_ARR_INDEX_32(index) \
|
| 914 |
|
|
REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
|
| 915 |
|
|
#define REGNAMES_ARR_INDEX_64(index) \
|
| 916 |
|
|
REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
|
| 917 |
|
|
|
| 918 |
|
|
#define REGISTER_NAMES \
|
| 919 |
|
|
{ \
|
| 920 |
|
|
REGNAMES_ARR_INDEX_64 (0), \
|
| 921 |
|
|
REGNAMES_ARR_INDEX_64 (64), \
|
| 922 |
|
|
REGNAMES_ARR_INDEX_8 (128), \
|
| 923 |
|
|
REGNAMES_ARR_INDEX_8 (136), \
|
| 924 |
|
|
REGNAMES_ARR_INDEX_8 (144), \
|
| 925 |
|
|
REGNAMES_ARR_INDEX_2 (152) \
|
| 926 |
|
|
}
|
| 927 |
|
|
|
| 928 |
|
|
#define ADDREGNAMES_SIZE 32
|
| 929 |
|
|
#define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
|
| 930 |
|
|
extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
|
| 931 |
|
|
[MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
|
| 932 |
|
|
|
| 933 |
|
|
#define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
|
| 934 |
|
|
{ \
|
| 935 |
|
|
"dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
|
| 936 |
|
|
"dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
|
| 937 |
|
|
"dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
|
| 938 |
|
|
"dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
|
| 939 |
|
|
}
|
| 940 |
|
|
|
| 941 |
|
|
#define ADDREGNAMES_REGNO(index) \
|
| 942 |
|
|
((index < 32) ? (FIRST_FP_REG + (index) * 2) \
|
| 943 |
|
|
: (-1))
|
| 944 |
|
|
|
| 945 |
|
|
#define ADDREGNAMES_ARR_INDEX_1(index) \
|
| 946 |
|
|
{ (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
|
| 947 |
|
|
#define ADDREGNAMES_ARR_INDEX_2(index) \
|
| 948 |
|
|
ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
|
| 949 |
|
|
#define ADDREGNAMES_ARR_INDEX_4(index) \
|
| 950 |
|
|
ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
|
| 951 |
|
|
#define ADDREGNAMES_ARR_INDEX_8(index) \
|
| 952 |
|
|
ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
|
| 953 |
|
|
#define ADDREGNAMES_ARR_INDEX_16(index) \
|
| 954 |
|
|
ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
|
| 955 |
|
|
#define ADDREGNAMES_ARR_INDEX_32(index) \
|
| 956 |
|
|
ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
|
| 957 |
|
|
|
| 958 |
|
|
#define ADDITIONAL_REGISTER_NAMES \
|
| 959 |
|
|
{ \
|
| 960 |
|
|
ADDREGNAMES_ARR_INDEX_32 (0) \
|
| 961 |
|
|
}
|
| 962 |
|
|
|
| 963 |
|
|
/* Number of actual hardware registers.
|
| 964 |
|
|
The hardware registers are assigned numbers for the compiler
|
| 965 |
|
|
from 0 to just below FIRST_PSEUDO_REGISTER.
|
| 966 |
|
|
All registers that the compiler knows about must be given numbers,
|
| 967 |
|
|
even those that are not normally considered general registers. */
|
| 968 |
|
|
|
| 969 |
|
|
/* There are many other relevant definitions in sh.md's md_constants. */
|
| 970 |
|
|
|
| 971 |
|
|
#define FIRST_GENERAL_REG R0_REG
|
| 972 |
|
|
#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
|
| 973 |
|
|
#define FIRST_FP_REG DR0_REG
|
| 974 |
|
|
#define LAST_FP_REG (FIRST_FP_REG + \
|
| 975 |
|
|
(TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
|
| 976 |
|
|
#define FIRST_XD_REG XD0_REG
|
| 977 |
|
|
#define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
|
| 978 |
|
|
#define FIRST_TARGET_REG TR0_REG
|
| 979 |
|
|
#define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
|
| 980 |
|
|
|
| 981 |
|
|
#define GENERAL_REGISTER_P(REGNO) \
|
| 982 |
|
|
IN_RANGE ((REGNO), \
|
| 983 |
|
|
(unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
|
| 984 |
|
|
(unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
|
| 985 |
|
|
|
| 986 |
|
|
#define GENERAL_OR_AP_REGISTER_P(REGNO) \
|
| 987 |
|
|
(GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
|
| 988 |
|
|
|| ((REGNO) == FRAME_POINTER_REGNUM))
|
| 989 |
|
|
|
| 990 |
|
|
#define FP_REGISTER_P(REGNO) \
|
| 991 |
|
|
((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
|
| 992 |
|
|
|
| 993 |
|
|
#define XD_REGISTER_P(REGNO) \
|
| 994 |
|
|
((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
|
| 995 |
|
|
|
| 996 |
|
|
#define FP_OR_XD_REGISTER_P(REGNO) \
|
| 997 |
|
|
(FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
|
| 998 |
|
|
|
| 999 |
|
|
#define FP_ANY_REGISTER_P(REGNO) \
|
| 1000 |
|
|
(FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
|
| 1001 |
|
|
|
| 1002 |
|
|
#define SPECIAL_REGISTER_P(REGNO) \
|
| 1003 |
|
|
((REGNO) == GBR_REG || (REGNO) == T_REG \
|
| 1004 |
|
|
|| (REGNO) == MACH_REG || (REGNO) == MACL_REG)
|
| 1005 |
|
|
|
| 1006 |
|
|
#define TARGET_REGISTER_P(REGNO) \
|
| 1007 |
|
|
((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
|
| 1008 |
|
|
|
| 1009 |
|
|
#define SHMEDIA_REGISTER_P(REGNO) \
|
| 1010 |
|
|
(GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
|
| 1011 |
|
|
|| TARGET_REGISTER_P (REGNO))
|
| 1012 |
|
|
|
| 1013 |
|
|
/* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
|
| 1014 |
|
|
that should be fixed. */
|
| 1015 |
|
|
#define VALID_REGISTER_P(REGNO) \
|
| 1016 |
|
|
(SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
|
| 1017 |
|
|
|| (REGNO) == AP_REG || (REGNO) == RAP_REG \
|
| 1018 |
|
|
|| (REGNO) == FRAME_POINTER_REGNUM \
|
| 1019 |
|
|
|| (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
|
| 1020 |
|
|
|| (TARGET_SH2E && (REGNO) == FPUL_REG))
|
| 1021 |
|
|
|
| 1022 |
|
|
/* The mode that should be generally used to store a register by
|
| 1023 |
|
|
itself in the stack, or to load it back. */
|
| 1024 |
|
|
#define REGISTER_NATURAL_MODE(REGNO) \
|
| 1025 |
|
|
(FP_REGISTER_P (REGNO) ? SFmode \
|
| 1026 |
|
|
: XD_REGISTER_P (REGNO) ? DFmode \
|
| 1027 |
|
|
: TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
|
| 1028 |
|
|
? DImode \
|
| 1029 |
|
|
: SImode)
|
| 1030 |
|
|
|
| 1031 |
|
|
#define FIRST_PSEUDO_REGISTER 154
|
| 1032 |
|
|
|
| 1033 |
|
|
/* Don't count soft frame pointer. */
|
| 1034 |
|
|
#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
|
| 1035 |
|
|
|
| 1036 |
|
|
/* 1 for registers that have pervasive standard uses
|
| 1037 |
|
|
and are not available for the register allocator.
|
| 1038 |
|
|
|
| 1039 |
|
|
Mach register is fixed 'cause it's only 10 bits wide for SH1.
|
| 1040 |
|
|
It is 32 bits wide for SH2. */
|
| 1041 |
|
|
|
| 1042 |
|
|
#define FIXED_REGISTERS \
|
| 1043 |
|
|
{ \
|
| 1044 |
|
|
/* Regular registers. */ \
|
| 1045 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1046 |
|
|
0, 0, 0, 0, 0, 0, 0, 1, \
|
| 1047 |
|
|
/* r16 is reserved, r18 is the former pr. */ \
|
| 1048 |
|
|
1, 0, 0, 0, 0, 0, 0, 0, \
|
| 1049 |
|
|
/* r24 is reserved for the OS; r25, for the assembler or linker. */ \
|
| 1050 |
|
|
/* r26 is a global variable data pointer; r27 is for constants. */ \
|
| 1051 |
|
|
1, 1, 1, 1, 0, 0, 0, 0, \
|
| 1052 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1053 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1054 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1055 |
|
|
0, 0, 0, 0, 0, 0, 0, 1, \
|
| 1056 |
|
|
/* FP registers. */ \
|
| 1057 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1058 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1059 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1060 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1061 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1062 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1063 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1064 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1065 |
|
|
/* Branch target registers. */ \
|
| 1066 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1067 |
|
|
/* XD registers. */ \
|
| 1068 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1069 |
|
|
/*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
|
| 1070 |
|
|
1, 1, 1, 1, 1, 1, 0, 1, \
|
| 1071 |
|
|
/*"rap", "sfp" */ \
|
| 1072 |
|
|
1, 1, \
|
| 1073 |
|
|
}
|
| 1074 |
|
|
|
| 1075 |
|
|
/* 1 for registers not available across function calls.
|
| 1076 |
|
|
These must include the FIXED_REGISTERS and also any
|
| 1077 |
|
|
registers that can be used without being saved.
|
| 1078 |
|
|
The latter must include the registers where values are returned
|
| 1079 |
|
|
and the register where structure-value addresses are passed.
|
| 1080 |
|
|
Aside from that, you can include as many other registers as you like. */
|
| 1081 |
|
|
|
| 1082 |
|
|
#define CALL_USED_REGISTERS \
|
| 1083 |
|
|
{ \
|
| 1084 |
|
|
/* Regular registers. */ \
|
| 1085 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, \
|
| 1086 |
|
|
/* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
|
| 1087 |
|
|
Only the lower 32bits of R10-R14 are guaranteed to be preserved \
|
| 1088 |
|
|
across SH5 function calls. */ \
|
| 1089 |
|
|
0, 0, 0, 0, 0, 0, 0, 1, \
|
| 1090 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, \
|
| 1091 |
|
|
1, 1, 1, 1, 0, 0, 0, 0, \
|
| 1092 |
|
|
0, 0, 0, 0, 1, 1, 1, 1, \
|
| 1093 |
|
|
1, 1, 1, 1, 0, 0, 0, 0, \
|
| 1094 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1095 |
|
|
0, 0, 0, 0, 1, 1, 1, 1, \
|
| 1096 |
|
|
/* FP registers. */ \
|
| 1097 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, \
|
| 1098 |
|
|
1, 1, 1, 1, 0, 0, 0, 0, \
|
| 1099 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, \
|
| 1100 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, \
|
| 1101 |
|
|
1, 1, 1, 1, 0, 0, 0, 0, \
|
| 1102 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1103 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1104 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
| 1105 |
|
|
/* Branch target registers. */ \
|
| 1106 |
|
|
1, 1, 1, 1, 1, 0, 0, 0, \
|
| 1107 |
|
|
/* XD registers. */ \
|
| 1108 |
|
|
1, 1, 1, 1, 1, 1, 0, 0, \
|
| 1109 |
|
|
/*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
|
| 1110 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, \
|
| 1111 |
|
|
/*"rap", "sfp" */ \
|
| 1112 |
|
|
1, 1, \
|
| 1113 |
|
|
}
|
| 1114 |
|
|
|
| 1115 |
|
|
/* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
|
| 1116 |
|
|
fixed, like PIC_OFFSET_TABLE_REGNUM. */
|
| 1117 |
|
|
#define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
|
| 1118 |
|
|
|
| 1119 |
|
|
/* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
|
| 1120 |
|
|
across SHcompact function calls. We can't tell whether a called
|
| 1121 |
|
|
function is SHmedia or SHcompact, so we assume it may be when
|
| 1122 |
|
|
compiling SHmedia code with the 32-bit ABI, since that's the only
|
| 1123 |
|
|
ABI that can be linked with SHcompact code. */
|
| 1124 |
|
|
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
|
| 1125 |
|
|
(TARGET_SHMEDIA32 \
|
| 1126 |
|
|
&& GET_MODE_SIZE (MODE) > 4 \
|
| 1127 |
|
|
&& (((REGNO) >= FIRST_GENERAL_REG + 10 \
|
| 1128 |
|
|
&& (REGNO) <= FIRST_GENERAL_REG + 15) \
|
| 1129 |
|
|
|| TARGET_REGISTER_P (REGNO) \
|
| 1130 |
|
|
|| (REGNO) == PR_MEDIA_REG))
|
| 1131 |
|
|
|
| 1132 |
|
|
/* Return number of consecutive hard regs needed starting at reg REGNO
|
| 1133 |
|
|
to hold something of mode MODE.
|
| 1134 |
|
|
This is ordinarily the length in words of a value of mode MODE
|
| 1135 |
|
|
but can be less for certain modes in special long registers.
|
| 1136 |
|
|
|
| 1137 |
|
|
On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
|
| 1138 |
|
|
|
| 1139 |
|
|
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
| 1140 |
|
|
(XD_REGISTER_P (REGNO) \
|
| 1141 |
|
|
? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
|
| 1142 |
|
|
: (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
|
| 1143 |
|
|
? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
|
| 1144 |
|
|
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
|
| 1145 |
|
|
|
| 1146 |
|
|
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
|
| 1147 |
|
|
We can allow any mode in any general register. The special registers
|
| 1148 |
|
|
only allow SImode. Don't allow any mode in the PR. */
|
| 1149 |
|
|
|
| 1150 |
|
|
/* We cannot hold DCmode values in the XD registers because alter_reg
|
| 1151 |
|
|
handles subregs of them incorrectly. We could work around this by
|
| 1152 |
|
|
spacing the XD registers like the DR registers, but this would require
|
| 1153 |
|
|
additional memory in every compilation to hold larger register vectors.
|
| 1154 |
|
|
We could hold SFmode / SCmode values in XD registers, but that
|
| 1155 |
|
|
would require a tertiary reload when reloading from / to memory,
|
| 1156 |
|
|
and a secondary reload to reload from / to general regs; that
|
| 1157 |
|
|
seems to be a loosing proposition. */
|
| 1158 |
|
|
/* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
|
| 1159 |
|
|
it won't be ferried through GP registers first. */
|
| 1160 |
|
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
|
| 1161 |
|
|
(SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
|
| 1162 |
|
|
: (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
|
| 1163 |
|
|
: FP_REGISTER_P (REGNO) && (MODE) == SFmode \
|
| 1164 |
|
|
? 1 \
|
| 1165 |
|
|
: (MODE) == V2SFmode \
|
| 1166 |
|
|
? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
|
| 1167 |
|
|
|| GENERAL_REGISTER_P (REGNO)) \
|
| 1168 |
|
|
: (MODE) == V4SFmode \
|
| 1169 |
|
|
? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
|
| 1170 |
|
|
|| GENERAL_REGISTER_P (REGNO)) \
|
| 1171 |
|
|
: (MODE) == V16SFmode \
|
| 1172 |
|
|
? (TARGET_SHMEDIA \
|
| 1173 |
|
|
? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
|
| 1174 |
|
|
: (REGNO) == FIRST_XD_REG) \
|
| 1175 |
|
|
: FP_REGISTER_P (REGNO) \
|
| 1176 |
|
|
? ((MODE) == SFmode || (MODE) == SImode \
|
| 1177 |
|
|
|| ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
|
| 1178 |
|
|
|| ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
|
| 1179 |
|
|
|| (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
|
| 1180 |
|
|
|| (MODE) == V2SFmode || (MODE) == TImode))) \
|
| 1181 |
|
|
&& (((REGNO) - FIRST_FP_REG) & 1) == 0) \
|
| 1182 |
|
|
|| ((TARGET_SH4 || TARGET_SHMEDIA) \
|
| 1183 |
|
|
&& (MODE) == TImode \
|
| 1184 |
|
|
&& (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
|
| 1185 |
|
|
: XD_REGISTER_P (REGNO) \
|
| 1186 |
|
|
? (MODE) == DFmode \
|
| 1187 |
|
|
: TARGET_REGISTER_P (REGNO) \
|
| 1188 |
|
|
? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
|
| 1189 |
|
|
: (REGNO) == PR_REG ? (MODE) == SImode \
|
| 1190 |
|
|
: (REGNO) == FPSCR_REG ? (MODE) == PSImode \
|
| 1191 |
|
|
: 1)
|
| 1192 |
|
|
|
| 1193 |
|
|
/* Value is 1 if it is a good idea to tie two pseudo registers
|
| 1194 |
|
|
when one has mode MODE1 and one has mode MODE2.
|
| 1195 |
|
|
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
|
| 1196 |
|
|
for any hard reg, then this must be 0 for correct output.
|
| 1197 |
|
|
That's the case for xd registers: we don't hold SFmode values in
|
| 1198 |
|
|
them, so we can't tie an SFmode pseudos with one in another
|
| 1199 |
|
|
floating-point mode. */
|
| 1200 |
|
|
|
| 1201 |
|
|
#define MODES_TIEABLE_P(MODE1, MODE2) \
|
| 1202 |
|
|
((MODE1) == (MODE2) \
|
| 1203 |
|
|
|| (TARGET_SHMEDIA \
|
| 1204 |
|
|
&& GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
|
| 1205 |
|
|
&& INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
|
| 1206 |
|
|
|| (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
|
| 1207 |
|
|
&& (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
|
| 1208 |
|
|
&& (GET_MODE_SIZE (MODE2) <= 4)) \
|
| 1209 |
|
|
: ((MODE1) != SFmode && (MODE2) != SFmode))))
|
| 1210 |
|
|
|
| 1211 |
|
|
/* A C expression that is nonzero if hard register NEW_REG can be
|
| 1212 |
|
|
considered for use as a rename register for OLD_REG register */
|
| 1213 |
|
|
|
| 1214 |
|
|
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
|
| 1215 |
|
|
sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
|
| 1216 |
|
|
|
| 1217 |
|
|
/* Specify the registers used for certain standard purposes.
|
| 1218 |
|
|
The values of these macros are register numbers. */
|
| 1219 |
|
|
|
| 1220 |
|
|
/* Define this if the program counter is overloaded on a register. */
|
| 1221 |
|
|
/* #define PC_REGNUM 15*/
|
| 1222 |
|
|
|
| 1223 |
|
|
/* Register to use for pushing function arguments. */
|
| 1224 |
|
|
#define STACK_POINTER_REGNUM SP_REG
|
| 1225 |
|
|
|
| 1226 |
|
|
/* Base register for access to local variables of the function. */
|
| 1227 |
|
|
#define HARD_FRAME_POINTER_REGNUM FP_REG
|
| 1228 |
|
|
|
| 1229 |
|
|
/* Base register for access to local variables of the function. */
|
| 1230 |
|
|
#define FRAME_POINTER_REGNUM 153
|
| 1231 |
|
|
|
| 1232 |
|
|
/* Fake register that holds the address on the stack of the
|
| 1233 |
|
|
current function's return address. */
|
| 1234 |
|
|
#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
|
| 1235 |
|
|
|
| 1236 |
|
|
/* Register to hold the addressing base for position independent
|
| 1237 |
|
|
code access to data items. */
|
| 1238 |
|
|
#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
|
| 1239 |
|
|
|
| 1240 |
|
|
#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
|
| 1241 |
|
|
|
| 1242 |
|
|
/* Value should be nonzero if functions must have frame pointers.
|
| 1243 |
|
|
Zero means the frame pointer need not be set up (and parms may be accessed
|
| 1244 |
|
|
via the stack pointer) in functions that seem suitable. */
|
| 1245 |
|
|
|
| 1246 |
|
|
#define FRAME_POINTER_REQUIRED 0
|
| 1247 |
|
|
|
| 1248 |
|
|
/* Definitions for register eliminations.
|
| 1249 |
|
|
|
| 1250 |
|
|
We have three registers that can be eliminated on the SH. First, the
|
| 1251 |
|
|
frame pointer register can often be eliminated in favor of the stack
|
| 1252 |
|
|
pointer register. Secondly, the argument pointer register can always be
|
| 1253 |
|
|
eliminated; it is replaced with either the stack or frame pointer.
|
| 1254 |
|
|
Third, there is the return address pointer, which can also be replaced
|
| 1255 |
|
|
with either the stack or the frame pointer. */
|
| 1256 |
|
|
|
| 1257 |
|
|
/* This is an array of structures. Each structure initializes one pair
|
| 1258 |
|
|
of eliminable registers. The "from" register number is given first,
|
| 1259 |
|
|
followed by "to". Eliminations of the same "from" register are listed
|
| 1260 |
|
|
in order of preference. */
|
| 1261 |
|
|
|
| 1262 |
|
|
/* If you add any registers here that are not actually hard registers,
|
| 1263 |
|
|
and that have any alternative of elimination that doesn't always
|
| 1264 |
|
|
apply, you need to amend calc_live_regs to exclude it, because
|
| 1265 |
|
|
reload spills all eliminable registers where it sees an
|
| 1266 |
|
|
can_eliminate == 0 entry, thus making them 'live' .
|
| 1267 |
|
|
If you add any hard registers that can be eliminated in different
|
| 1268 |
|
|
ways, you have to patch reload to spill them only when all alternatives
|
| 1269 |
|
|
of elimination fail. */
|
| 1270 |
|
|
|
| 1271 |
|
|
#define ELIMINABLE_REGS \
|
| 1272 |
|
|
{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
| 1273 |
|
|
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
| 1274 |
|
|
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
| 1275 |
|
|
{ RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
| 1276 |
|
|
{ RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
| 1277 |
|
|
{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
| 1278 |
|
|
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
|
| 1279 |
|
|
|
| 1280 |
|
|
/* Given FROM and TO register numbers, say whether this elimination
|
| 1281 |
|
|
is allowed. */
|
| 1282 |
|
|
#define CAN_ELIMINATE(FROM, TO) \
|
| 1283 |
|
|
(!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
|
| 1284 |
|
|
|
| 1285 |
|
|
/* Define the offset between two registers, one to be eliminated, and the other
|
| 1286 |
|
|
its replacement, at the start of a routine. */
|
| 1287 |
|
|
|
| 1288 |
|
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
| 1289 |
|
|
OFFSET = initial_elimination_offset ((FROM), (TO))
|
| 1290 |
|
|
|
| 1291 |
|
|
/* Base register for access to arguments of the function. */
|
| 1292 |
|
|
#define ARG_POINTER_REGNUM AP_REG
|
| 1293 |
|
|
|
| 1294 |
|
|
/* Register in which the static-chain is passed to a function. */
|
| 1295 |
|
|
#define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
|
| 1296 |
|
|
|
| 1297 |
|
|
/* Don't default to pcc-struct-return, because we have already specified
|
| 1298 |
|
|
exactly how to return structures in the TARGET_RETURN_IN_MEMORY
|
| 1299 |
|
|
target hook. */
|
| 1300 |
|
|
|
| 1301 |
|
|
#define DEFAULT_PCC_STRUCT_RETURN 0
|
| 1302 |
|
|
|
| 1303 |
|
|
#define SHMEDIA_REGS_STACK_ADJUST() \
|
| 1304 |
|
|
(TARGET_SHCOMPACT && current_function_has_nonlocal_label \
|
| 1305 |
|
|
? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
|
| 1306 |
|
|
+ (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
|
| 1307 |
|
|
: 0)
|
| 1308 |
|
|
|
| 1309 |
|
|
|
| 1310 |
|
|
/* Define the classes of registers for register constraints in the
|
| 1311 |
|
|
machine description. Also define ranges of constants.
|
| 1312 |
|
|
|
| 1313 |
|
|
One of the classes must always be named ALL_REGS and include all hard regs.
|
| 1314 |
|
|
If there is more than one class, another class must be named NO_REGS
|
| 1315 |
|
|
and contain no registers.
|
| 1316 |
|
|
|
| 1317 |
|
|
The name GENERAL_REGS must be the name of a class (or an alias for
|
| 1318 |
|
|
another name such as ALL_REGS). This is the class of registers
|
| 1319 |
|
|
that is allowed by "g" or "r" in a register constraint.
|
| 1320 |
|
|
Also, registers outside this class are allocated only when
|
| 1321 |
|
|
instructions express preferences for them.
|
| 1322 |
|
|
|
| 1323 |
|
|
The classes must be numbered in nondecreasing order; that is,
|
| 1324 |
|
|
a larger-numbered class must never be contained completely
|
| 1325 |
|
|
in a smaller-numbered class.
|
| 1326 |
|
|
|
| 1327 |
|
|
For any two classes, it is very desirable that there be another
|
| 1328 |
|
|
class that represents their union. */
|
| 1329 |
|
|
|
| 1330 |
|
|
/* The SH has two sorts of general registers, R0 and the rest. R0 can
|
| 1331 |
|
|
be used as the destination of some of the arithmetic ops. There are
|
| 1332 |
|
|
also some special purpose registers; the T bit register, the
|
| 1333 |
|
|
Procedure Return Register and the Multiply Accumulate Registers. */
|
| 1334 |
|
|
/* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
|
| 1335 |
|
|
reg_class_subunion. We don't want to have an actual union class
|
| 1336 |
|
|
of these, because it would only be used when both classes are calculated
|
| 1337 |
|
|
to give the same cost, but there is only one FPUL register.
|
| 1338 |
|
|
Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
|
| 1339 |
|
|
applying to the actual instruction alternative considered. E.g., the
|
| 1340 |
|
|
y/r alternative of movsi_ie is considered to have no more cost that
|
| 1341 |
|
|
the r/r alternative, which is patently untrue. */
|
| 1342 |
|
|
|
| 1343 |
|
|
enum reg_class
|
| 1344 |
|
|
{
|
| 1345 |
|
|
NO_REGS,
|
| 1346 |
|
|
R0_REGS,
|
| 1347 |
|
|
PR_REGS,
|
| 1348 |
|
|
T_REGS,
|
| 1349 |
|
|
MAC_REGS,
|
| 1350 |
|
|
FPUL_REGS,
|
| 1351 |
|
|
SIBCALL_REGS,
|
| 1352 |
|
|
GENERAL_REGS,
|
| 1353 |
|
|
FP0_REGS,
|
| 1354 |
|
|
FP_REGS,
|
| 1355 |
|
|
DF_HI_REGS,
|
| 1356 |
|
|
DF_REGS,
|
| 1357 |
|
|
FPSCR_REGS,
|
| 1358 |
|
|
GENERAL_FP_REGS,
|
| 1359 |
|
|
GENERAL_DF_REGS,
|
| 1360 |
|
|
TARGET_REGS,
|
| 1361 |
|
|
ALL_REGS,
|
| 1362 |
|
|
LIM_REG_CLASSES
|
| 1363 |
|
|
};
|
| 1364 |
|
|
|
| 1365 |
|
|
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
| 1366 |
|
|
|
| 1367 |
|
|
/* Give names of register classes as strings for dump file. */
|
| 1368 |
|
|
#define REG_CLASS_NAMES \
|
| 1369 |
|
|
{ \
|
| 1370 |
|
|
"NO_REGS", \
|
| 1371 |
|
|
"R0_REGS", \
|
| 1372 |
|
|
"PR_REGS", \
|
| 1373 |
|
|
"T_REGS", \
|
| 1374 |
|
|
"MAC_REGS", \
|
| 1375 |
|
|
"FPUL_REGS", \
|
| 1376 |
|
|
"SIBCALL_REGS", \
|
| 1377 |
|
|
"GENERAL_REGS", \
|
| 1378 |
|
|
"FP0_REGS", \
|
| 1379 |
|
|
"FP_REGS", \
|
| 1380 |
|
|
"DF_HI_REGS", \
|
| 1381 |
|
|
"DF_REGS", \
|
| 1382 |
|
|
"FPSCR_REGS", \
|
| 1383 |
|
|
"GENERAL_FP_REGS", \
|
| 1384 |
|
|
"GENERAL_DF_REGS", \
|
| 1385 |
|
|
"TARGET_REGS", \
|
| 1386 |
|
|
"ALL_REGS", \
|
| 1387 |
|
|
}
|
| 1388 |
|
|
|
| 1389 |
|
|
/* Define which registers fit in which classes.
|
| 1390 |
|
|
This is an initializer for a vector of HARD_REG_SET
|
| 1391 |
|
|
of length N_REG_CLASSES. */
|
| 1392 |
|
|
|
| 1393 |
|
|
#define REG_CLASS_CONTENTS \
|
| 1394 |
|
|
{ \
|
| 1395 |
|
|
/* NO_REGS: */ \
|
| 1396 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
|
| 1397 |
|
|
/* R0_REGS: */ \
|
| 1398 |
|
|
{ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
|
| 1399 |
|
|
/* PR_REGS: */ \
|
| 1400 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
|
| 1401 |
|
|
/* T_REGS: */ \
|
| 1402 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
|
| 1403 |
|
|
/* MAC_REGS: */ \
|
| 1404 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
|
| 1405 |
|
|
/* FPUL_REGS: */ \
|
| 1406 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
|
| 1407 |
|
|
/* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
|
| 1408 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
|
| 1409 |
|
|
/* GENERAL_REGS: */ \
|
| 1410 |
|
|
{ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
|
| 1411 |
|
|
/* FP0_REGS: */ \
|
| 1412 |
|
|
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
|
| 1413 |
|
|
/* FP_REGS: */ \
|
| 1414 |
|
|
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
|
| 1415 |
|
|
/* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
|
| 1416 |
|
|
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
|
| 1417 |
|
|
/* DF_REGS: */ \
|
| 1418 |
|
|
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
|
| 1419 |
|
|
/* FPSCR_REGS: */ \
|
| 1420 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
|
| 1421 |
|
|
/* GENERAL_FP_REGS: */ \
|
| 1422 |
|
|
{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
|
| 1423 |
|
|
/* GENERAL_DF_REGS: */ \
|
| 1424 |
|
|
{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
|
| 1425 |
|
|
/* TARGET_REGS: */ \
|
| 1426 |
|
|
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
|
| 1427 |
|
|
/* ALL_REGS: */ \
|
| 1428 |
|
|
{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
|
| 1429 |
|
|
}
|
| 1430 |
|
|
|
| 1431 |
|
|
/* The same information, inverted:
|
| 1432 |
|
|
Return the class number of the smallest class containing
|
| 1433 |
|
|
reg number REGNO. This could be a conditional expression
|
| 1434 |
|
|
or could index an array. */
|
| 1435 |
|
|
|
| 1436 |
|
|
extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
|
| 1437 |
|
|
#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
|
| 1438 |
|
|
|
| 1439 |
|
|
/* When defined, the compiler allows registers explicitly used in the
|
| 1440 |
|
|
rtl to be used as spill registers but prevents the compiler from
|
| 1441 |
|
|
extending the lifetime of these registers. */
|
| 1442 |
|
|
|
| 1443 |
|
|
#define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
|
| 1444 |
|
|
|
| 1445 |
|
|
/* The order in which register should be allocated. */
|
| 1446 |
|
|
/* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
|
| 1447 |
|
|
and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
|
| 1448 |
|
|
spilled or used otherwise, we better have the FP_REGS allocated first. */
|
| 1449 |
|
|
#define REG_ALLOC_ORDER \
|
| 1450 |
|
|
{/* Caller-saved FPRs */ \
|
| 1451 |
|
|
65, 66, 67, 68, 69, 70, 71, 64, \
|
| 1452 |
|
|
72, 73, 74, 75, 80, 81, 82, 83, \
|
| 1453 |
|
|
84, 85, 86, 87, 88, 89, 90, 91, \
|
| 1454 |
|
|
92, 93, 94, 95, 96, 97, 98, 99, \
|
| 1455 |
|
|
/* Callee-saved FPRs */ \
|
| 1456 |
|
|
76, 77, 78, 79,100,101,102,103, \
|
| 1457 |
|
|
104,105,106,107,108,109,110,111, \
|
| 1458 |
|
|
112,113,114,115,116,117,118,119, \
|
| 1459 |
|
|
120,121,122,123,124,125,126,127, \
|
| 1460 |
|
|
136,137,138,139,140,141,142,143, \
|
| 1461 |
|
|
/* FPSCR */ 151, \
|
| 1462 |
|
|
/* Caller-saved GPRs (except 8/9 on SH1-4) */ \
|
| 1463 |
|
|
1, 2, 3, 7, 6, 5, 4, 0, \
|
| 1464 |
|
|
8, 9, 17, 19, 20, 21, 22, 23, \
|
| 1465 |
|
|
36, 37, 38, 39, 40, 41, 42, 43, \
|
| 1466 |
|
|
60, 61, 62, \
|
| 1467 |
|
|
/* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
|
| 1468 |
|
|
10, 11, 12, 13, 14, 18, \
|
| 1469 |
|
|
/* SH5 callee-saved GPRs */ \
|
| 1470 |
|
|
28, 29, 30, 31, 32, 33, 34, 35, \
|
| 1471 |
|
|
44, 45, 46, 47, 48, 49, 50, 51, \
|
| 1472 |
|
|
52, 53, 54, 55, 56, 57, 58, 59, \
|
| 1473 |
|
|
/* FPUL */ 150, \
|
| 1474 |
|
|
/* SH5 branch target registers */ \
|
| 1475 |
|
|
128,129,130,131,132,133,134,135, \
|
| 1476 |
|
|
/* Fixed registers */ \
|
| 1477 |
|
|
15, 16, 24, 25, 26, 27, 63,144, \
|
| 1478 |
|
|
145,146,147,148,149,152,153 }
|
| 1479 |
|
|
|
| 1480 |
|
|
/* The class value for index registers, and the one for base regs. */
|
| 1481 |
|
|
#define INDEX_REG_CLASS \
|
| 1482 |
|
|
(!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
|
| 1483 |
|
|
#define BASE_REG_CLASS GENERAL_REGS
|
| 1484 |
|
|
|
| 1485 |
|
|
/* Get reg_class from a letter such as appears in the machine
|
| 1486 |
|
|
description. */
|
| 1487 |
|
|
extern enum reg_class reg_class_from_letter[];
|
| 1488 |
|
|
|
| 1489 |
|
|
/* We might use 'Rxx' constraints in the future for exotic reg classes.*/
|
| 1490 |
|
|
#define REG_CLASS_FROM_CONSTRAINT(C, STR) \
|
| 1491 |
|
|
(ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
|
| 1492 |
|
|
|
| 1493 |
|
|
/* Overview of uppercase letter constraints:
|
| 1494 |
|
|
A: Addresses (constraint len == 3)
|
| 1495 |
|
|
Ac4: sh4 cache operations
|
| 1496 |
|
|
Ac5: sh5 cache operations
|
| 1497 |
|
|
Bxx: miscellaneous constraints
|
| 1498 |
|
|
Bsc: SCRATCH - for the scratch register in movsi_ie in the
|
| 1499 |
|
|
fldi0 / fldi0 cases
|
| 1500 |
|
|
C: Constants other than only CONST_INT (constraint len == 3)
|
| 1501 |
|
|
C16: 16 bit constant, literal or symbolic
|
| 1502 |
|
|
Csy: label or symbol
|
| 1503 |
|
|
Cpg: non-explicit constants that can be directly loaded into a general
|
| 1504 |
|
|
purpose register in PIC code. like 's' except we don't allow
|
| 1505 |
|
|
PIC_DIRECT_ADDR_P
|
| 1506 |
|
|
IJKLMNOP: CONT_INT constants
|
| 1507 |
|
|
Ixx: signed xx bit
|
| 1508 |
|
|
J16: 0xffffffff00000000 | 0x00000000ffffffff
|
| 1509 |
|
|
Kxx: unsigned xx bit
|
| 1510 |
|
|
M: 1
|
| 1511 |
|
|
N: 0
|
| 1512 |
|
|
P27: 1 | 2 | 8 | 16
|
| 1513 |
|
|
Q: pc relative load operand
|
| 1514 |
|
|
Rxx: reserved for exotic register classes.
|
| 1515 |
|
|
S: extra memory (storage) constraints (constraint len == 3)
|
| 1516 |
|
|
Sua: unaligned memory operations
|
| 1517 |
|
|
W: vector
|
| 1518 |
|
|
Z: zero in any mode
|
| 1519 |
|
|
|
| 1520 |
|
|
unused CONST_INT constraint letters: LO
|
| 1521 |
|
|
unused EXTRA_CONSTRAINT letters: D T U Y */
|
| 1522 |
|
|
|
| 1523 |
|
|
#define CONSTRAINT_LEN(C,STR) \
|
| 1524 |
|
|
(((C) == 'A' || (C) == 'B' || (C) == 'C' \
|
| 1525 |
|
|
|| (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
|
| 1526 |
|
|
|| (C) == 'R' || (C) == 'S') \
|
| 1527 |
|
|
? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
|
| 1528 |
|
|
|
| 1529 |
|
|
/* The letters I, J, K, L and M in a register constraint string
|
| 1530 |
|
|
can be used to stand for particular ranges of immediate operands.
|
| 1531 |
|
|
This macro defines what the ranges are.
|
| 1532 |
|
|
C is the letter, and VALUE is a constant value.
|
| 1533 |
|
|
Return 1 if VALUE is in the range specified by C.
|
| 1534 |
|
|
I08: arithmetic operand -127..128, as used in add, sub, etc
|
| 1535 |
|
|
I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
|
| 1536 |
|
|
P27: shift operand 1,2,8 or 16
|
| 1537 |
|
|
K08: logical operand 0..255, as used in and, or, etc.
|
| 1538 |
|
|
M: constant 1
|
| 1539 |
|
|
N: constant 0
|
| 1540 |
|
|
I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
|
| 1541 |
|
|
I10: arithmetic operand -512..511, as used in SHmedia andi, ori
|
| 1542 |
|
|
*/
|
| 1543 |
|
|
|
| 1544 |
|
|
#define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
|
| 1545 |
|
|
&& ((HOST_WIDE_INT)(VALUE)) <= 31)
|
| 1546 |
|
|
#define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
|
| 1547 |
|
|
&& ((HOST_WIDE_INT)(VALUE)) <= 127)
|
| 1548 |
|
|
#define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
|
| 1549 |
|
|
&& ((HOST_WIDE_INT)(VALUE)) <= 511)
|
| 1550 |
|
|
#define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
|
| 1551 |
|
|
&& ((HOST_WIDE_INT)(VALUE)) <= 32767)
|
| 1552 |
|
|
#define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
|
| 1553 |
|
|
&& ((HOST_WIDE_INT)(VALUE)) <= 524287 \
|
| 1554 |
|
|
&& TARGET_SH2A)
|
| 1555 |
|
|
#define CONST_OK_FOR_I(VALUE, STR) \
|
| 1556 |
|
|
((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \
|
| 1557 |
|
|
: (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
|
| 1558 |
|
|
: (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
|
| 1559 |
|
|
: (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
|
| 1560 |
|
|
: (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
|
| 1561 |
|
|
: 0)
|
| 1562 |
|
|
|
| 1563 |
|
|
#define CONST_OK_FOR_J16(VALUE) \
|
| 1564 |
|
|
((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
|
| 1565 |
|
|
|| (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
|
| 1566 |
|
|
#define CONST_OK_FOR_J(VALUE, STR) \
|
| 1567 |
|
|
((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
|
| 1568 |
|
|
: 0)
|
| 1569 |
|
|
|
| 1570 |
|
|
#define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
|
| 1571 |
|
|
&& ((HOST_WIDE_INT)(VALUE)) <= 255)
|
| 1572 |
|
|
#define CONST_OK_FOR_K(VALUE, STR) \
|
| 1573 |
|
|
((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
|
| 1574 |
|
|
: 0)
|
| 1575 |
|
|
#define CONST_OK_FOR_P27(VALUE) \
|
| 1576 |
|
|
((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
|
| 1577 |
|
|
#define CONST_OK_FOR_P(VALUE, STR) \
|
| 1578 |
|
|
((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
|
| 1579 |
|
|
: 0)
|
| 1580 |
|
|
#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
|
| 1581 |
|
|
#define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
|
| 1582 |
|
|
#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
|
| 1583 |
|
|
((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
|
| 1584 |
|
|
: (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
|
| 1585 |
|
|
: (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
|
| 1586 |
|
|
: (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
|
| 1587 |
|
|
: (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
|
| 1588 |
|
|
: (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
|
| 1589 |
|
|
: 0)
|
| 1590 |
|
|
|
| 1591 |
|
|
/* Similar, but for floating constants, and defining letters G and H.
|
| 1592 |
|
|
Here VALUE is the CONST_DOUBLE rtx itself. */
|
| 1593 |
|
|
|
| 1594 |
|
|
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
|
| 1595 |
|
|
((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
|
| 1596 |
|
|
: (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
|
| 1597 |
|
|
: (C) == 'F')
|
| 1598 |
|
|
|
| 1599 |
|
|
/* Given an rtx X being reloaded into a reg required to be
|
| 1600 |
|
|
in class CLASS, return the class of reg to actually use.
|
| 1601 |
|
|
In general this is just CLASS; but on some machines
|
| 1602 |
|
|
in some cases it is preferable to use a more restrictive class. */
|
| 1603 |
|
|
|
| 1604 |
|
|
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
|
| 1605 |
|
|
((CLASS) == NO_REGS && TARGET_SHMEDIA \
|
| 1606 |
|
|
&& (GET_CODE (X) == CONST_DOUBLE \
|
| 1607 |
|
|
|| GET_CODE (X) == SYMBOL_REF \
|
| 1608 |
|
|
|| PIC_DIRECT_ADDR_P (X)) \
|
| 1609 |
|
|
? GENERAL_REGS \
|
| 1610 |
|
|
: (CLASS)) \
|
| 1611 |
|
|
|
| 1612 |
|
|
#define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
|
| 1613 |
|
|
((((REGCLASS_HAS_FP_REG (CLASS) \
|
| 1614 |
|
|
&& (GET_CODE (X) == REG \
|
| 1615 |
|
|
&& (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
|
| 1616 |
|
|
|| (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
|
| 1617 |
|
|
&& TARGET_FMOVD)))) \
|
| 1618 |
|
|
|| (REGCLASS_HAS_GENERAL_REG (CLASS) \
|
| 1619 |
|
|
&& GET_CODE (X) == REG \
|
| 1620 |
|
|
&& FP_REGISTER_P (REGNO (X)))) \
|
| 1621 |
|
|
&& ! TARGET_SHMEDIA \
|
| 1622 |
|
|
&& ((MODE) == SFmode || (MODE) == SImode)) \
|
| 1623 |
|
|
? FPUL_REGS \
|
| 1624 |
|
|
: (((CLASS) == FPUL_REGS \
|
| 1625 |
|
|
|| (REGCLASS_HAS_FP_REG (CLASS) \
|
| 1626 |
|
|
&& ! TARGET_SHMEDIA && MODE == SImode)) \
|
| 1627 |
|
|
&& (GET_CODE (X) == MEM \
|
| 1628 |
|
|
|| (GET_CODE (X) == REG \
|
| 1629 |
|
|
&& (REGNO (X) >= FIRST_PSEUDO_REGISTER \
|
| 1630 |
|
|
|| REGNO (X) == T_REG \
|
| 1631 |
|
|
|| system_reg_operand (X, VOIDmode))))) \
|
| 1632 |
|
|
? GENERAL_REGS \
|
| 1633 |
|
|
: (((CLASS) == TARGET_REGS \
|
| 1634 |
|
|
|| (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
|
| 1635 |
|
|
&& !EXTRA_CONSTRAINT_Csy (X) \
|
| 1636 |
|
|
&& (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
|
| 1637 |
|
|
? GENERAL_REGS \
|
| 1638 |
|
|
: (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
|
| 1639 |
|
|
&& GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
|
| 1640 |
|
|
&& (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
|
| 1641 |
|
|
? GENERAL_REGS \
|
| 1642 |
|
|
: ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
|
| 1643 |
|
|
&& TARGET_REGISTER_P (REGNO (X))) \
|
| 1644 |
|
|
? GENERAL_REGS : (ELSE))
|
| 1645 |
|
|
|
| 1646 |
|
|
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
|
| 1647 |
|
|
SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
|
| 1648 |
|
|
|
| 1649 |
|
|
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
|
| 1650 |
|
|
((REGCLASS_HAS_FP_REG (CLASS) \
|
| 1651 |
|
|
&& ! TARGET_SHMEDIA \
|
| 1652 |
|
|
&& immediate_operand ((X), (MODE)) \
|
| 1653 |
|
|
&& ! ((fp_zero_operand (X) || fp_one_operand (X)) \
|
| 1654 |
|
|
&& (MODE) == SFmode && fldi_ok ())) \
|
| 1655 |
|
|
? R0_REGS \
|
| 1656 |
|
|
: ((CLASS) == FPUL_REGS \
|
| 1657 |
|
|
&& ((GET_CODE (X) == REG \
|
| 1658 |
|
|
&& (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
|
| 1659 |
|
|
|| REGNO (X) == T_REG)) \
|
| 1660 |
|
|
|| GET_CODE (X) == PLUS)) \
|
| 1661 |
|
|
? GENERAL_REGS \
|
| 1662 |
|
|
: (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
|
| 1663 |
|
|
? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
|
| 1664 |
|
|
? GENERAL_REGS \
|
| 1665 |
|
|
: R0_REGS) \
|
| 1666 |
|
|
: ((CLASS) == FPSCR_REGS \
|
| 1667 |
|
|
&& ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|
| 1668 |
|
|
|| (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
|
| 1669 |
|
|
? GENERAL_REGS \
|
| 1670 |
|
|
: (REGCLASS_HAS_FP_REG (CLASS) \
|
| 1671 |
|
|
&& TARGET_SHMEDIA \
|
| 1672 |
|
|
&& immediate_operand ((X), (MODE)) \
|
| 1673 |
|
|
&& (X) != CONST0_RTX (GET_MODE (X)) \
|
| 1674 |
|
|
&& GET_MODE (X) != V4SFmode) \
|
| 1675 |
|
|
? GENERAL_REGS \
|
| 1676 |
|
|
: (((MODE) == QImode || (MODE) == HImode) \
|
| 1677 |
|
|
&& TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
|
| 1678 |
|
|
? GENERAL_REGS \
|
| 1679 |
|
|
: (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
|
| 1680 |
|
|
&& (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
|
| 1681 |
|
|
? TARGET_REGS \
|
| 1682 |
|
|
: SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
|
| 1683 |
|
|
|
| 1684 |
|
|
/* Return the maximum number of consecutive registers
|
| 1685 |
|
|
needed to represent mode MODE in a register of class CLASS.
|
| 1686 |
|
|
|
| 1687 |
|
|
If TARGET_SHMEDIA, we need two FP registers per word.
|
| 1688 |
|
|
Otherwise we will need at most one register per word. */
|
| 1689 |
|
|
#define CLASS_MAX_NREGS(CLASS, MODE) \
|
| 1690 |
|
|
(TARGET_SHMEDIA \
|
| 1691 |
|
|
&& TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
|
| 1692 |
|
|
? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
|
| 1693 |
|
|
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
| 1694 |
|
|
|
| 1695 |
|
|
/* If defined, gives a class of registers that cannot be used as the
|
| 1696 |
|
|
operand of a SUBREG that changes the mode of the object illegally. */
|
| 1697 |
|
|
/* ??? We need to renumber the internal numbers for the frnn registers
|
| 1698 |
|
|
when in little endian in order to allow mode size changes. */
|
| 1699 |
|
|
|
| 1700 |
|
|
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
|
| 1701 |
|
|
sh_cannot_change_mode_class (FROM, TO, CLASS)
|
| 1702 |
|
|
|
| 1703 |
|
|
/* Stack layout; function entry, exit and calling. */
|
| 1704 |
|
|
|
| 1705 |
|
|
/* Define the number of registers that can hold parameters.
|
| 1706 |
|
|
These macros are used only in other macro definitions below. */
|
| 1707 |
|
|
|
| 1708 |
|
|
#define NPARM_REGS(MODE) \
|
| 1709 |
|
|
(TARGET_FPU_ANY && (MODE) == SFmode \
|
| 1710 |
|
|
? (TARGET_SH5 ? 12 : 8) \
|
| 1711 |
|
|
: (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
| 1712 |
|
|
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
|
| 1713 |
|
|
? (TARGET_SH5 ? 12 : 8) \
|
| 1714 |
|
|
: (TARGET_SH5 ? 8 : 4))
|
| 1715 |
|
|
|
| 1716 |
|
|
#define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
|
| 1717 |
|
|
#define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
|
| 1718 |
|
|
|
| 1719 |
|
|
#define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
|
| 1720 |
|
|
#define FIRST_FP_RET_REG FIRST_FP_REG
|
| 1721 |
|
|
|
| 1722 |
|
|
/* Define this if pushing a word on the stack
|
| 1723 |
|
|
makes the stack pointer a smaller address. */
|
| 1724 |
|
|
#define STACK_GROWS_DOWNWARD
|
| 1725 |
|
|
|
| 1726 |
|
|
/* Define this macro to nonzero if the addresses of local variable slots
|
| 1727 |
|
|
are at negative offsets from the frame pointer. */
|
| 1728 |
|
|
#define FRAME_GROWS_DOWNWARD 1
|
| 1729 |
|
|
|
| 1730 |
|
|
/* Offset from the frame pointer to the first local variable slot to
|
| 1731 |
|
|
be allocated. */
|
| 1732 |
|
|
#define STARTING_FRAME_OFFSET 0
|
| 1733 |
|
|
|
| 1734 |
|
|
/* If we generate an insn to push BYTES bytes,
|
| 1735 |
|
|
this says how many the stack pointer really advances by. */
|
| 1736 |
|
|
/* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
|
| 1737 |
|
|
When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
|
| 1738 |
|
|
do correct alignment. */
|
| 1739 |
|
|
#if 0
|
| 1740 |
|
|
#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
|
| 1741 |
|
|
#endif
|
| 1742 |
|
|
|
| 1743 |
|
|
/* Offset of first parameter from the argument pointer register value. */
|
| 1744 |
|
|
#define FIRST_PARM_OFFSET(FNDECL) 0
|
| 1745 |
|
|
|
| 1746 |
|
|
/* Value is the number of byte of arguments automatically
|
| 1747 |
|
|
popped when returning from a subroutine call.
|
| 1748 |
|
|
FUNDECL is the declaration node of the function (as a tree),
|
| 1749 |
|
|
FUNTYPE is the data type of the function (as a tree),
|
| 1750 |
|
|
or for a library call it is an identifier node for the subroutine name.
|
| 1751 |
|
|
SIZE is the number of bytes of arguments passed on the stack.
|
| 1752 |
|
|
|
| 1753 |
|
|
On the SH, the caller does not pop any of its arguments that were passed
|
| 1754 |
|
|
on the stack. */
|
| 1755 |
|
|
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
|
| 1756 |
|
|
|
| 1757 |
|
|
/* Value is the number of bytes of arguments automatically popped when
|
| 1758 |
|
|
calling a subroutine.
|
| 1759 |
|
|
CUM is the accumulated argument list.
|
| 1760 |
|
|
|
| 1761 |
|
|
On SHcompact, the call trampoline pops arguments off the stack. */
|
| 1762 |
|
|
#define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
|
| 1763 |
|
|
|
| 1764 |
|
|
/* Some subroutine macros specific to this machine. */
|
| 1765 |
|
|
|
| 1766 |
|
|
#define BASE_RETURN_VALUE_REG(MODE) \
|
| 1767 |
|
|
((TARGET_FPU_ANY && ((MODE) == SFmode)) \
|
| 1768 |
|
|
? FIRST_FP_RET_REG \
|
| 1769 |
|
|
: TARGET_FPU_ANY && (MODE) == SCmode \
|
| 1770 |
|
|
? FIRST_FP_RET_REG \
|
| 1771 |
|
|
: (TARGET_FPU_DOUBLE \
|
| 1772 |
|
|
&& ((MODE) == DFmode || (MODE) == SFmode \
|
| 1773 |
|
|
|| (MODE) == DCmode || (MODE) == SCmode )) \
|
| 1774 |
|
|
? FIRST_FP_RET_REG \
|
| 1775 |
|
|
: FIRST_RET_REG)
|
| 1776 |
|
|
|
| 1777 |
|
|
#define BASE_ARG_REG(MODE) \
|
| 1778 |
|
|
((TARGET_SH2E && ((MODE) == SFmode)) \
|
| 1779 |
|
|
? FIRST_FP_PARM_REG \
|
| 1780 |
|
|
: (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
| 1781 |
|
|
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
|
| 1782 |
|
|
? FIRST_FP_PARM_REG \
|
| 1783 |
|
|
: FIRST_PARM_REG)
|
| 1784 |
|
|
|
| 1785 |
|
|
/* Define how to find the value returned by a function.
|
| 1786 |
|
|
VALTYPE is the data type of the value (as a tree).
|
| 1787 |
|
|
If the precise function being called is known, FUNC is its FUNCTION_DECL;
|
| 1788 |
|
|
otherwise, FUNC is 0.
|
| 1789 |
|
|
For the SH, this is like LIBCALL_VALUE, except that we must change the
|
| 1790 |
|
|
mode like PROMOTE_MODE does.
|
| 1791 |
|
|
??? PROMOTE_MODE is ignored for non-scalar types. The set of types
|
| 1792 |
|
|
tested here has to be kept in sync with the one in explow.c:promote_mode. */
|
| 1793 |
|
|
|
| 1794 |
|
|
#define FUNCTION_VALUE(VALTYPE, FUNC) \
|
| 1795 |
|
|
gen_rtx_REG ( \
|
| 1796 |
|
|
((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
|
| 1797 |
|
|
&& GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
|
| 1798 |
|
|
&& (TREE_CODE (VALTYPE) == INTEGER_TYPE \
|
| 1799 |
|
|
|| TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
|
| 1800 |
|
|
|| TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
|
| 1801 |
|
|
|| TREE_CODE (VALTYPE) == CHAR_TYPE \
|
| 1802 |
|
|
|| TREE_CODE (VALTYPE) == REAL_TYPE \
|
| 1803 |
|
|
|| TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
|
| 1804 |
|
|
&& sh_promote_prototypes (VALTYPE) \
|
| 1805 |
|
|
? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
|
| 1806 |
|
|
BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
|
| 1807 |
|
|
|
| 1808 |
|
|
/* Define how to find the value returned by a library function
|
| 1809 |
|
|
assuming the value has mode MODE. */
|
| 1810 |
|
|
#define LIBCALL_VALUE(MODE) \
|
| 1811 |
|
|
gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
|
| 1812 |
|
|
|
| 1813 |
|
|
/* 1 if N is a possible register number for a function value. */
|
| 1814 |
|
|
#define FUNCTION_VALUE_REGNO_P(REGNO) \
|
| 1815 |
|
|
((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
|
| 1816 |
|
|
|| (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
|
| 1817 |
|
|
|
| 1818 |
|
|
/* 1 if N is a possible register number for function argument passing. */
|
| 1819 |
|
|
/* ??? There are some callers that pass REGNO as int, and others that pass
|
| 1820 |
|
|
it as unsigned. We get warnings unless we do casts everywhere. */
|
| 1821 |
|
|
#define FUNCTION_ARG_REGNO_P(REGNO) \
|
| 1822 |
|
|
(((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
|
| 1823 |
|
|
&& (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
|
| 1824 |
|
|
|| (TARGET_FPU_ANY \
|
| 1825 |
|
|
&& (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
|
| 1826 |
|
|
&& (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
|
| 1827 |
|
|
+ NPARM_REGS (SFmode))))
|
| 1828 |
|
|
|
| 1829 |
|
|
/* Define a data type for recording info about an argument list
|
| 1830 |
|
|
during the scan of that argument list. This data type should
|
| 1831 |
|
|
hold all necessary information about the function itself
|
| 1832 |
|
|
and about the args processed so far, enough to enable macros
|
| 1833 |
|
|
such as FUNCTION_ARG to determine where the next arg should go.
|
| 1834 |
|
|
|
| 1835 |
|
|
On SH, this is a single integer, which is a number of words
|
| 1836 |
|
|
of arguments scanned so far (including the invisible argument,
|
| 1837 |
|
|
if any, which holds the structure-value-address).
|
| 1838 |
|
|
Thus NARGREGS or more means all following args should go on the stack. */
|
| 1839 |
|
|
|
| 1840 |
|
|
enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
|
| 1841 |
|
|
struct sh_args {
|
| 1842 |
|
|
int arg_count[2];
|
| 1843 |
|
|
int force_mem;
|
| 1844 |
|
|
/* Nonzero if a prototype is available for the function. */
|
| 1845 |
|
|
int prototype_p;
|
| 1846 |
|
|
/* The number of an odd floating-point register, that should be used
|
| 1847 |
|
|
for the next argument of type float. */
|
| 1848 |
|
|
int free_single_fp_reg;
|
| 1849 |
|
|
/* Whether we're processing an outgoing function call. */
|
| 1850 |
|
|
int outgoing;
|
| 1851 |
|
|
/* The number of general-purpose registers that should have been
|
| 1852 |
|
|
used to pass partial arguments, that are passed totally on the
|
| 1853 |
|
|
stack. On SHcompact, a call trampoline will pop them off the
|
| 1854 |
|
|
stack before calling the actual function, and, if the called
|
| 1855 |
|
|
function is implemented in SHcompact mode, the incoming arguments
|
| 1856 |
|
|
decoder will push such arguments back onto the stack. For
|
| 1857 |
|
|
incoming arguments, STACK_REGS also takes into account other
|
| 1858 |
|
|
arguments passed by reference, that the decoder will also push
|
| 1859 |
|
|
onto the stack. */
|
| 1860 |
|
|
int stack_regs;
|
| 1861 |
|
|
/* The number of general-purpose registers that should have been
|
| 1862 |
|
|
used to pass arguments, if the arguments didn't have to be passed
|
| 1863 |
|
|
by reference. */
|
| 1864 |
|
|
int byref_regs;
|
| 1865 |
|
|
/* Set as by shcompact_byref if the current argument is to be passed
|
| 1866 |
|
|
by reference. */
|
| 1867 |
|
|
int byref;
|
| 1868 |
|
|
|
| 1869 |
|
|
/* call_cookie is a bitmask used by call expanders, as well as
|
| 1870 |
|
|
function prologue and epilogues, to allow SHcompact to comply
|
| 1871 |
|
|
with the SH5 32-bit ABI, that requires 64-bit registers to be
|
| 1872 |
|
|
used even though only the lower 32-bit half is visible in
|
| 1873 |
|
|
SHcompact mode. The strategy is to call SHmedia trampolines.
|
| 1874 |
|
|
|
| 1875 |
|
|
The alternatives for each of the argument-passing registers are
|
| 1876 |
|
|
(a) leave it unchanged; (b) pop it off the stack; (c) load its
|
| 1877 |
|
|
contents from the address in it; (d) add 8 to it, storing the
|
| 1878 |
|
|
result in the next register, then (c); (e) copy it from some
|
| 1879 |
|
|
floating-point register,
|
| 1880 |
|
|
|
| 1881 |
|
|
Regarding copies from floating-point registers, r2 may only be
|
| 1882 |
|
|
copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
|
| 1883 |
|
|
copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
|
| 1884 |
|
|
dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
|
| 1885 |
|
|
r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
|
| 1886 |
|
|
dr10.
|
| 1887 |
|
|
|
| 1888 |
|
|
The bit mask is structured as follows:
|
| 1889 |
|
|
|
| 1890 |
|
|
- 1 bit to tell whether to set up a return trampoline.
|
| 1891 |
|
|
|
| 1892 |
|
|
- 3 bits to count the number consecutive registers to pop off the
|
| 1893 |
|
|
stack.
|
| 1894 |
|
|
|
| 1895 |
|
|
- 4 bits for each of r9, r8, r7 and r6.
|
| 1896 |
|
|
|
| 1897 |
|
|
- 3 bits for each of r5, r4, r3 and r2.
|
| 1898 |
|
|
|
| 1899 |
|
|
- 3 bits set to 0 (the most significant ones)
|
| 1900 |
|
|
|
| 1901 |
|
|
3 2 1 0
|
| 1902 |
|
|
1098 7654 3210 9876 5432 1098 7654 3210
|
| 1903 |
|
|
FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
|
| 1904 |
|
|
2223 3344 4555 6666 7777 8888 9999 SSS-
|
| 1905 |
|
|
|
| 1906 |
|
|
- If F is set, the register must be copied from an FP register,
|
| 1907 |
|
|
whose number is encoded in the remaining bits.
|
| 1908 |
|
|
|
| 1909 |
|
|
- Else, if L is set, the register must be loaded from the address
|
| 1910 |
|
|
contained in it. If the P bit is *not* set, the address of the
|
| 1911 |
|
|
following dword should be computed first, and stored in the
|
| 1912 |
|
|
following register.
|
| 1913 |
|
|
|
| 1914 |
|
|
- Else, if P is set, the register alone should be popped off the
|
| 1915 |
|
|
stack.
|
| 1916 |
|
|
|
| 1917 |
|
|
- After all this processing, the number of registers represented
|
| 1918 |
|
|
in SSS will be popped off the stack. This is an optimization
|
| 1919 |
|
|
for pushing/popping consecutive registers, typically used for
|
| 1920 |
|
|
varargs and large arguments partially passed in registers.
|
| 1921 |
|
|
|
| 1922 |
|
|
- If T is set, a return trampoline will be set up for 64-bit
|
| 1923 |
|
|
return values to be split into 2 32-bit registers. */
|
| 1924 |
|
|
#define CALL_COOKIE_RET_TRAMP_SHIFT 0
|
| 1925 |
|
|
#define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
|
| 1926 |
|
|
#define CALL_COOKIE_STACKSEQ_SHIFT 1
|
| 1927 |
|
|
#define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
|
| 1928 |
|
|
#define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
|
| 1929 |
|
|
(((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
|
| 1930 |
|
|
#define CALL_COOKIE_INT_REG_SHIFT(REG) \
|
| 1931 |
|
|
(4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
|
| 1932 |
|
|
#define CALL_COOKIE_INT_REG(REG, VAL) \
|
| 1933 |
|
|
((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
|
| 1934 |
|
|
#define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
|
| 1935 |
|
|
(((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
|
| 1936 |
|
|
long call_cookie;
|
| 1937 |
|
|
|
| 1938 |
|
|
/* This is set to nonzero when the call in question must use the Renesas ABI,
|
| 1939 |
|
|
even without the -mrenesas option. */
|
| 1940 |
|
|
int renesas_abi;
|
| 1941 |
|
|
};
|
| 1942 |
|
|
|
| 1943 |
|
|
#define CUMULATIVE_ARGS struct sh_args
|
| 1944 |
|
|
|
| 1945 |
|
|
#define GET_SH_ARG_CLASS(MODE) \
|
| 1946 |
|
|
((TARGET_FPU_ANY && (MODE) == SFmode) \
|
| 1947 |
|
|
? SH_ARG_FLOAT \
|
| 1948 |
|
|
/* There's no mention of complex float types in the SH5 ABI, so we
|
| 1949 |
|
|
should presumably handle them as aggregate types. */ \
|
| 1950 |
|
|
: TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
|
| 1951 |
|
|
? SH_ARG_INT \
|
| 1952 |
|
|
: TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
| 1953 |
|
|
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
|
| 1954 |
|
|
? SH_ARG_FLOAT : SH_ARG_INT)
|
| 1955 |
|
|
|
| 1956 |
|
|
#define ROUND_ADVANCE(SIZE) \
|
| 1957 |
|
|
(((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
| 1958 |
|
|
|
| 1959 |
|
|
/* Round a register number up to a proper boundary for an arg of mode
|
| 1960 |
|
|
MODE.
|
| 1961 |
|
|
|
| 1962 |
|
|
The SH doesn't care about double alignment, so we only
|
| 1963 |
|
|
round doubles to even regs when asked to explicitly. */
|
| 1964 |
|
|
|
| 1965 |
|
|
#define ROUND_REG(CUM, MODE) \
|
| 1966 |
|
|
(((TARGET_ALIGN_DOUBLE \
|
| 1967 |
|
|
|| ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
|
| 1968 |
|
|
&& (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
|
| 1969 |
|
|
&& GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
|
| 1970 |
|
|
? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
|
| 1971 |
|
|
+ ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
|
| 1972 |
|
|
: (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
|
| 1973 |
|
|
|
| 1974 |
|
|
/* Initialize a variable CUM of type CUMULATIVE_ARGS
|
| 1975 |
|
|
for a call to a function whose data type is FNTYPE.
|
| 1976 |
|
|
For a library call, FNTYPE is 0.
|
| 1977 |
|
|
|
| 1978 |
|
|
On SH, the offset always starts at 0: the first parm reg is always
|
| 1979 |
|
|
the same reg for a given argument class.
|
| 1980 |
|
|
|
| 1981 |
|
|
For TARGET_HITACHI, the structure value pointer is passed in memory. */
|
| 1982 |
|
|
|
| 1983 |
|
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
|
| 1984 |
|
|
sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
|
| 1985 |
|
|
|
| 1986 |
|
|
#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
|
| 1987 |
|
|
sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
|
| 1988 |
|
|
|
| 1989 |
|
|
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
| 1990 |
|
|
sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
|
| 1991 |
|
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
| 1992 |
|
|
sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
|
| 1993 |
|
|
|
| 1994 |
|
|
/* Return boolean indicating arg of mode MODE will be passed in a reg.
|
| 1995 |
|
|
This macro is only used in this file. */
|
| 1996 |
|
|
|
| 1997 |
|
|
#define PASS_IN_REG_P(CUM, MODE, TYPE) \
|
| 1998 |
|
|
(((TYPE) == 0 \
|
| 1999 |
|
|
|| (! TREE_ADDRESSABLE ((tree)(TYPE)) \
|
| 2000 |
|
|
&& (! (TARGET_HITACHI || (CUM).renesas_abi) \
|
| 2001 |
|
|
|| ! (AGGREGATE_TYPE_P (TYPE) \
|
| 2002 |
|
|
|| (!TARGET_FPU_ANY \
|
| 2003 |
|
|
&& (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
| 2004 |
|
|
&& GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
|
| 2005 |
|
|
&& ! (CUM).force_mem \
|
| 2006 |
|
|
&& (TARGET_SH2E \
|
| 2007 |
|
|
? ((MODE) == BLKmode \
|
| 2008 |
|
|
? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
|
| 2009 |
|
|
+ int_size_in_bytes (TYPE)) \
|
| 2010 |
|
|
<= NPARM_REGS (SImode) * UNITS_PER_WORD) \
|
| 2011 |
|
|
: ((ROUND_REG((CUM), (MODE)) \
|
| 2012 |
|
|
+ HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
|
| 2013 |
|
|
<= NPARM_REGS (MODE))) \
|
| 2014 |
|
|
: ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
|
| 2015 |
|
|
|
| 2016 |
|
|
/* By accident we got stuck with passing SCmode on SH4 little endian
|
| 2017 |
|
|
in two registers that are nominally successive - which is different from
|
| 2018 |
|
|
two single SFmode values, where we take endianness translation into
|
| 2019 |
|
|
account. That does not work at all if an odd number of registers is
|
| 2020 |
|
|
already in use, so that got fixed, but library functions are still more
|
| 2021 |
|
|
likely to use complex numbers without mixing them with SFmode arguments
|
| 2022 |
|
|
(which in C would have to be structures), so for the sake of ABI
|
| 2023 |
|
|
compatibility the way SCmode values are passed when an even number of
|
| 2024 |
|
|
FP registers is in use remains different from a pair of SFmode values for
|
| 2025 |
|
|
now.
|
| 2026 |
|
|
I.e.:
|
| 2027 |
|
|
foo (double); a: fr5,fr4
|
| 2028 |
|
|
foo (float a, float b); a: fr5 b: fr4
|
| 2029 |
|
|
foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
|
| 2030 |
|
|
this should be the other way round...
|
| 2031 |
|
|
foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
|
| 2032 |
|
|
#define FUNCTION_ARG_SCmode_WART 1
|
| 2033 |
|
|
|
| 2034 |
|
|
/* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
|
| 2035 |
|
|
register in SHcompact mode, it must be padded in the most
|
| 2036 |
|
|
significant end. This means that passing it by reference wouldn't
|
| 2037 |
|
|
pad properly on a big-endian machine. In this particular case, we
|
| 2038 |
|
|
pass this argument on the stack, in a way that the call trampoline
|
| 2039 |
|
|
will load its value into the appropriate register. */
|
| 2040 |
|
|
#define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
|
| 2041 |
|
|
((MODE) == BLKmode \
|
| 2042 |
|
|
&& TARGET_SHCOMPACT \
|
| 2043 |
|
|
&& ! TARGET_LITTLE_ENDIAN \
|
| 2044 |
|
|
&& int_size_in_bytes (TYPE) > 4 \
|
| 2045 |
|
|
&& int_size_in_bytes (TYPE) < 8)
|
| 2046 |
|
|
|
| 2047 |
|
|
/* Minimum alignment for an argument to be passed by callee-copy
|
| 2048 |
|
|
reference. We need such arguments to be aligned to 8 byte
|
| 2049 |
|
|
boundaries, because they'll be loaded using quad loads. */
|
| 2050 |
|
|
#define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
|
| 2051 |
|
|
|
| 2052 |
|
|
/* The SH5 ABI requires floating-point arguments to be passed to
|
| 2053 |
|
|
functions without a prototype in both an FP register and a regular
|
| 2054 |
|
|
register or the stack. When passing the argument in both FP and
|
| 2055 |
|
|
general-purpose registers, list the FP register first. */
|
| 2056 |
|
|
#define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
|
| 2057 |
|
|
(gen_rtx_PARALLEL \
|
| 2058 |
|
|
((MODE), \
|
| 2059 |
|
|
gen_rtvec (2, \
|
| 2060 |
|
|
gen_rtx_EXPR_LIST \
|
| 2061 |
|
|
(VOIDmode, \
|
| 2062 |
|
|
((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
|
| 2063 |
|
|
? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
|
| 2064 |
|
|
+ (CUM).arg_count[(int) SH_ARG_FLOAT]) \
|
| 2065 |
|
|
: NULL_RTX), \
|
| 2066 |
|
|
const0_rtx), \
|
| 2067 |
|
|
gen_rtx_EXPR_LIST \
|
| 2068 |
|
|
(VOIDmode, \
|
| 2069 |
|
|
((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
|
| 2070 |
|
|
? gen_rtx_REG ((MODE), FIRST_PARM_REG \
|
| 2071 |
|
|
+ (CUM).arg_count[(int) SH_ARG_INT]) \
|
| 2072 |
|
|
: gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
|
| 2073 |
|
|
+ (CUM).arg_count[(int) SH_ARG_FLOAT])), \
|
| 2074 |
|
|
const0_rtx))))
|
| 2075 |
|
|
|
| 2076 |
|
|
/* The SH5 ABI requires regular registers or stack slots to be
|
| 2077 |
|
|
reserved for floating-point arguments. Registers are taken care of
|
| 2078 |
|
|
in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
|
| 2079 |
|
|
Unfortunately, there's no way to just reserve a stack slot, so
|
| 2080 |
|
|
we'll end up needlessly storing a copy of the argument in the
|
| 2081 |
|
|
stack. For incoming arguments, however, the PARALLEL will be
|
| 2082 |
|
|
optimized to the register-only form, and the value in the stack
|
| 2083 |
|
|
slot won't be used at all. */
|
| 2084 |
|
|
#define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
|
| 2085 |
|
|
((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
|
| 2086 |
|
|
? gen_rtx_REG ((MODE), (REG)) \
|
| 2087 |
|
|
: gen_rtx_PARALLEL ((MODE), \
|
| 2088 |
|
|
gen_rtvec (2, \
|
| 2089 |
|
|
gen_rtx_EXPR_LIST \
|
| 2090 |
|
|
(VOIDmode, NULL_RTX, \
|
| 2091 |
|
|
const0_rtx), \
|
| 2092 |
|
|
gen_rtx_EXPR_LIST \
|
| 2093 |
|
|
(VOIDmode, gen_rtx_REG ((MODE), \
|
| 2094 |
|
|
(REG)), \
|
| 2095 |
|
|
const0_rtx))))
|
| 2096 |
|
|
|
| 2097 |
|
|
#define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
|
| 2098 |
|
|
(TARGET_SH5 \
|
| 2099 |
|
|
&& ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
|
| 2100 |
|
|
|| (MODE) == DCmode) \
|
| 2101 |
|
|
&& ((CUM).arg_count[(int) SH_ARG_INT] \
|
| 2102 |
|
|
+ (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
|
| 2103 |
|
|
|
| 2104 |
|
|
/* Perform any needed actions needed for a function that is receiving a
|
| 2105 |
|
|
variable number of arguments. */
|
| 2106 |
|
|
|
| 2107 |
|
|
/* Implement `va_start' for varargs and stdarg. */
|
| 2108 |
|
|
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
|
| 2109 |
|
|
sh_va_start (valist, nextarg)
|
| 2110 |
|
|
|
| 2111 |
|
|
/* Call the function profiler with a given profile label.
|
| 2112 |
|
|
We use two .aligns, so as to make sure that both the .long is aligned
|
| 2113 |
|
|
on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
|
| 2114 |
|
|
from the trapa instruction. */
|
| 2115 |
|
|
|
| 2116 |
|
|
#define FUNCTION_PROFILER(STREAM,LABELNO) \
|
| 2117 |
|
|
{ \
|
| 2118 |
|
|
if (TARGET_SHMEDIA) \
|
| 2119 |
|
|
{ \
|
| 2120 |
|
|
fprintf((STREAM), "\tmovi\t33,r0\n"); \
|
| 2121 |
|
|
fprintf((STREAM), "\ttrapa\tr0\n"); \
|
| 2122 |
|
|
asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
|
| 2123 |
|
|
} \
|
| 2124 |
|
|
else \
|
| 2125 |
|
|
{ \
|
| 2126 |
|
|
fprintf((STREAM), "\t.align\t2\n"); \
|
| 2127 |
|
|
fprintf((STREAM), "\ttrapa\t#33\n"); \
|
| 2128 |
|
|
fprintf((STREAM), "\t.align\t2\n"); \
|
| 2129 |
|
|
asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
|
| 2130 |
|
|
} \
|
| 2131 |
|
|
}
|
| 2132 |
|
|
|
| 2133 |
|
|
/* Define this macro if the code for function profiling should come
|
| 2134 |
|
|
before the function prologue. Normally, the profiling code comes
|
| 2135 |
|
|
after. */
|
| 2136 |
|
|
|
| 2137 |
|
|
#define PROFILE_BEFORE_PROLOGUE
|
| 2138 |
|
|
|
| 2139 |
|
|
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
|
| 2140 |
|
|
the stack pointer does not matter. The value is tested only in
|
| 2141 |
|
|
functions that have frame pointers.
|
| 2142 |
|
|
No definition is equivalent to always zero. */
|
| 2143 |
|
|
|
| 2144 |
|
|
#define EXIT_IGNORE_STACK 1
|
| 2145 |
|
|
|
| 2146 |
|
|
/*
|
| 2147 |
|
|
On the SH, the trampoline looks like
|
| 2148 |
|
|
2 0002 D202 mov.l l2,r2
|
| 2149 |
|
|
1 0000 D301 mov.l l1,r3
|
| 2150 |
|
|
3 0004 422B jmp @r2
|
| 2151 |
|
|
4 0006 0009 nop
|
| 2152 |
|
|
5 0008 00000000 l1: .long area
|
| 2153 |
|
|
6 000c 00000000 l2: .long function */
|
| 2154 |
|
|
|
| 2155 |
|
|
/* Length in units of the trampoline for entering a nested function. */
|
| 2156 |
|
|
#define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
|
| 2157 |
|
|
|
| 2158 |
|
|
/* Alignment required for a trampoline in bits . */
|
| 2159 |
|
|
#define TRAMPOLINE_ALIGNMENT \
|
| 2160 |
|
|
((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
|
| 2161 |
|
|
: TARGET_SHMEDIA ? 256 : 64)
|
| 2162 |
|
|
|
| 2163 |
|
|
/* Emit RTL insns to initialize the variable parts of a trampoline.
|
| 2164 |
|
|
FNADDR is an RTX for the address of the function's pure code.
|
| 2165 |
|
|
CXT is an RTX for the static chain value for the function. */
|
| 2166 |
|
|
|
| 2167 |
|
|
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
|
| 2168 |
|
|
sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
|
| 2169 |
|
|
|
| 2170 |
|
|
/* On SH5, trampolines are SHmedia code, so add 1 to the address. */
|
| 2171 |
|
|
|
| 2172 |
|
|
#define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
|
| 2173 |
|
|
{ \
|
| 2174 |
|
|
if (TARGET_SHMEDIA) \
|
| 2175 |
|
|
(TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
|
| 2176 |
|
|
gen_reg_rtx (Pmode), 0, \
|
| 2177 |
|
|
OPTAB_LIB_WIDEN); \
|
| 2178 |
|
|
} while (0)
|
| 2179 |
|
|
|
| 2180 |
|
|
/* A C expression whose value is RTL representing the value of the return
|
| 2181 |
|
|
address for the frame COUNT steps up from the current frame.
|
| 2182 |
|
|
FRAMEADDR is already the frame pointer of the COUNT frame, so we
|
| 2183 |
|
|
can ignore COUNT. */
|
| 2184 |
|
|
|
| 2185 |
|
|
#define RETURN_ADDR_RTX(COUNT, FRAME) \
|
| 2186 |
|
|
(((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
|
| 2187 |
|
|
|
| 2188 |
|
|
/* A C expression whose value is RTL representing the location of the
|
| 2189 |
|
|
incoming return address at the beginning of any function, before the
|
| 2190 |
|
|
prologue. This RTL is either a REG, indicating that the return
|
| 2191 |
|
|
value is saved in REG, or a MEM representing a location in
|
| 2192 |
|
|
the stack. */
|
| 2193 |
|
|
#define INCOMING_RETURN_ADDR_RTX \
|
| 2194 |
|
|
gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
|
| 2195 |
|
|
|
| 2196 |
|
|
/* Addressing modes, and classification of registers for them. */
|
| 2197 |
|
|
#define HAVE_POST_INCREMENT TARGET_SH1
|
| 2198 |
|
|
#define HAVE_PRE_DECREMENT TARGET_SH1
|
| 2199 |
|
|
|
| 2200 |
|
|
#define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
|
| 2201 |
|
|
? 0 : TARGET_SH1)
|
| 2202 |
|
|
#define USE_LOAD_PRE_DECREMENT(mode) 0
|
| 2203 |
|
|
#define USE_STORE_POST_INCREMENT(mode) 0
|
| 2204 |
|
|
#define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
|
| 2205 |
|
|
? 0 : TARGET_SH1)
|
| 2206 |
|
|
|
| 2207 |
|
|
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
|
| 2208 |
|
|
(move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
|
| 2209 |
|
|
< (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
|
| 2210 |
|
|
|
| 2211 |
|
|
#define STORE_BY_PIECES_P(SIZE, ALIGN) \
|
| 2212 |
|
|
(move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
|
| 2213 |
|
|
< (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
|
| 2214 |
|
|
|
| 2215 |
|
|
/* Macros to check register numbers against specific register classes. */
|
| 2216 |
|
|
|
| 2217 |
|
|
/* These assume that REGNO is a hard or pseudo reg number.
|
| 2218 |
|
|
They give nonzero only if REGNO is a hard reg of the suitable class
|
| 2219 |
|
|
or a pseudo reg currently allocated to a suitable hard reg.
|
| 2220 |
|
|
Since they use reg_renumber, they are safe only once reg_renumber
|
| 2221 |
|
|
has been allocated, which happens in local-alloc.c. */
|
| 2222 |
|
|
|
| 2223 |
|
|
#define REGNO_OK_FOR_BASE_P(REGNO) \
|
| 2224 |
|
|
(GENERAL_OR_AP_REGISTER_P (REGNO) \
|
| 2225 |
|
|
|| GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
|
| 2226 |
|
|
#define REGNO_OK_FOR_INDEX_P(REGNO) \
|
| 2227 |
|
|
(TARGET_SHMEDIA \
|
| 2228 |
|
|
? (GENERAL_REGISTER_P (REGNO) \
|
| 2229 |
|
|
|| GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
|
| 2230 |
|
|
: (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
|
| 2231 |
|
|
|
| 2232 |
|
|
/* Maximum number of registers that can appear in a valid memory
|
| 2233 |
|
|
address. */
|
| 2234 |
|
|
|
| 2235 |
|
|
#define MAX_REGS_PER_ADDRESS 2
|
| 2236 |
|
|
|
| 2237 |
|
|
/* Recognize any constant value that is a valid address. */
|
| 2238 |
|
|
|
| 2239 |
|
|
#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
|
| 2240 |
|
|
|
| 2241 |
|
|
/* Nonzero if the constant value X is a legitimate general operand. */
|
| 2242 |
|
|
|
| 2243 |
|
|
#define LEGITIMATE_CONSTANT_P(X) \
|
| 2244 |
|
|
(TARGET_SHMEDIA \
|
| 2245 |
|
|
? ((GET_MODE (X) != DFmode \
|
| 2246 |
|
|
&& GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
|
| 2247 |
|
|
|| (X) == CONST0_RTX (GET_MODE (X)) \
|
| 2248 |
|
|
|| ! TARGET_SHMEDIA_FPU \
|
| 2249 |
|
|
|| TARGET_SHMEDIA64) \
|
| 2250 |
|
|
: (GET_CODE (X) != CONST_DOUBLE \
|
| 2251 |
|
|
|| GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
|
| 2252 |
|
|
|| (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
|
| 2253 |
|
|
|
| 2254 |
|
|
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
| 2255 |
|
|
and check its validity for a certain class.
|
| 2256 |
|
|
We have two alternate definitions for each of them.
|
| 2257 |
|
|
The usual definition accepts all pseudo regs; the other rejects
|
| 2258 |
|
|
them unless they have been allocated suitable hard regs.
|
| 2259 |
|
|
The symbol REG_OK_STRICT causes the latter definition to be used. */
|
| 2260 |
|
|
|
| 2261 |
|
|
#ifndef REG_OK_STRICT
|
| 2262 |
|
|
|
| 2263 |
|
|
/* Nonzero if X is a hard reg that can be used as a base reg
|
| 2264 |
|
|
or if it is a pseudo reg. */
|
| 2265 |
|
|
#define REG_OK_FOR_BASE_P(X) \
|
| 2266 |
|
|
(GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
|
| 2267 |
|
|
|
| 2268 |
|
|
/* Nonzero if X is a hard reg that can be used as an index
|
| 2269 |
|
|
or if it is a pseudo reg. */
|
| 2270 |
|
|
#define REG_OK_FOR_INDEX_P(X) \
|
| 2271 |
|
|
((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
|
| 2272 |
|
|
: REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
|
| 2273 |
|
|
|
| 2274 |
|
|
/* Nonzero if X/OFFSET is a hard reg that can be used as an index
|
| 2275 |
|
|
or if X is a pseudo reg. */
|
| 2276 |
|
|
#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
|
| 2277 |
|
|
((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
|
| 2278 |
|
|
: REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
|
| 2279 |
|
|
|
| 2280 |
|
|
#else
|
| 2281 |
|
|
|
| 2282 |
|
|
/* Nonzero if X is a hard reg that can be used as a base reg. */
|
| 2283 |
|
|
#define REG_OK_FOR_BASE_P(X) \
|
| 2284 |
|
|
REGNO_OK_FOR_BASE_P (REGNO (X))
|
| 2285 |
|
|
|
| 2286 |
|
|
/* Nonzero if X is a hard reg that can be used as an index. */
|
| 2287 |
|
|
#define REG_OK_FOR_INDEX_P(X) \
|
| 2288 |
|
|
REGNO_OK_FOR_INDEX_P (REGNO (X))
|
| 2289 |
|
|
|
| 2290 |
|
|
/* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
|
| 2291 |
|
|
#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
|
| 2292 |
|
|
(REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
|
| 2293 |
|
|
|
| 2294 |
|
|
#endif
|
| 2295 |
|
|
|
| 2296 |
|
|
/* The 'Q' constraint is a pc relative load operand. */
|
| 2297 |
|
|
#define EXTRA_CONSTRAINT_Q(OP) \
|
| 2298 |
|
|
(GET_CODE (OP) == MEM \
|
| 2299 |
|
|
&& ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
|
| 2300 |
|
|
|| (GET_CODE (XEXP ((OP), 0)) == CONST \
|
| 2301 |
|
|
&& GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
|
| 2302 |
|
|
&& GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
|
| 2303 |
|
|
&& GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
|
| 2304 |
|
|
|
| 2305 |
|
|
/* Extra address constraints. */
|
| 2306 |
|
|
#define EXTRA_CONSTRAINT_A(OP, STR) 0
|
| 2307 |
|
|
|
| 2308 |
|
|
/* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
|
| 2309 |
|
|
operand is not SCRATCH (i.e. REG) then R0 is probably being
|
| 2310 |
|
|
used, hence mova is being used, hence do not select this pattern */
|
| 2311 |
|
|
#define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
|
| 2312 |
|
|
#define EXTRA_CONSTRAINT_B(OP, STR) \
|
| 2313 |
|
|
((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
|
| 2314 |
|
|
: 0)
|
| 2315 |
|
|
|
| 2316 |
|
|
/* The `C16' constraint is a 16-bit constant, literal or symbolic. */
|
| 2317 |
|
|
#define EXTRA_CONSTRAINT_C16(OP) \
|
| 2318 |
|
|
(GET_CODE (OP) == CONST \
|
| 2319 |
|
|
&& GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
|
| 2320 |
|
|
&& (GET_MODE (XEXP ((OP), 0)) == DImode \
|
| 2321 |
|
|
|| GET_MODE (XEXP ((OP), 0)) == SImode) \
|
| 2322 |
|
|
&& GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
|
| 2323 |
|
|
&& GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
|
| 2324 |
|
|
&& (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
|
| 2325 |
|
|
|| (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
|
| 2326 |
|
|
&& (MOVI_SHORI_BASE_OPERAND_P \
|
| 2327 |
|
|
(XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
|
| 2328 |
|
|
&& GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
|
| 2329 |
|
|
1)) == CONST_INT)))
|
| 2330 |
|
|
|
| 2331 |
|
|
/* Check whether OP is a datalabel unspec. */
|
| 2332 |
|
|
#define DATALABEL_REF_NO_CONST_P(OP) \
|
| 2333 |
|
|
(GET_CODE (OP) == UNSPEC \
|
| 2334 |
|
|
&& XINT ((OP), 1) == UNSPEC_DATALABEL \
|
| 2335 |
|
|
&& XVECLEN ((OP), 0) == 1 \
|
| 2336 |
|
|
&& GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
|
| 2337 |
|
|
|
| 2338 |
|
|
#define GOT_ENTRY_P(OP) \
|
| 2339 |
|
|
(GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
|
| 2340 |
|
|
&& XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
|
| 2341 |
|
|
|
| 2342 |
|
|
#define GOTPLT_ENTRY_P(OP) \
|
| 2343 |
|
|
(GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
|
| 2344 |
|
|
&& XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
|
| 2345 |
|
|
|
| 2346 |
|
|
#define UNSPEC_GOTOFF_P(OP) \
|
| 2347 |
|
|
(GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
|
| 2348 |
|
|
|
| 2349 |
|
|
#define GOTOFF_P(OP) \
|
| 2350 |
|
|
(GET_CODE (OP) == CONST \
|
| 2351 |
|
|
&& (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
|
| 2352 |
|
|
|| (GET_CODE (XEXP ((OP), 0)) == PLUS \
|
| 2353 |
|
|
&& UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
|
| 2354 |
|
|
&& GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
|
| 2355 |
|
|
|
| 2356 |
|
|
#define PIC_ADDR_P(OP) \
|
| 2357 |
|
|
(GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
|
| 2358 |
|
|
&& XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
|
| 2359 |
|
|
|
| 2360 |
|
|
#define PIC_OFFSET_P(OP) \
|
| 2361 |
|
|
(PIC_ADDR_P (OP) \
|
| 2362 |
|
|
&& GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
|
| 2363 |
|
|
&& reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
|
| 2364 |
|
|
|
| 2365 |
|
|
#define PIC_DIRECT_ADDR_P(OP) \
|
| 2366 |
|
|
(PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
|
| 2367 |
|
|
|
| 2368 |
|
|
#define NON_PIC_REFERENCE_P(OP) \
|
| 2369 |
|
|
(GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
|
| 2370 |
|
|
|| (GET_CODE (OP) == CONST \
|
| 2371 |
|
|
&& (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
|
| 2372 |
|
|
|| GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
|
| 2373 |
|
|
|| DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
|
| 2374 |
|
|
|| (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
|
| 2375 |
|
|
&& (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
|
| 2376 |
|
|
|| GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
|
| 2377 |
|
|
|| DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
|
| 2378 |
|
|
&& GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
|
| 2379 |
|
|
|
| 2380 |
|
|
#define PIC_REFERENCE_P(OP) \
|
| 2381 |
|
|
(GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
|
| 2382 |
|
|
|| GOTOFF_P (OP) || PIC_ADDR_P (OP))
|
| 2383 |
|
|
|
| 2384 |
|
|
#define MOVI_SHORI_BASE_OPERAND_P(OP) \
|
| 2385 |
|
|
(flag_pic \
|
| 2386 |
|
|
? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
|
| 2387 |
|
|
|| PIC_OFFSET_P (OP)) \
|
| 2388 |
|
|
: NON_PIC_REFERENCE_P (OP))
|
| 2389 |
|
|
|
| 2390 |
|
|
/* The `Csy' constraint is a label or a symbol. */
|
| 2391 |
|
|
#define EXTRA_CONSTRAINT_Csy(OP) \
|
| 2392 |
|
|
(NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
|
| 2393 |
|
|
|
| 2394 |
|
|
/* A zero in any shape or form. */
|
| 2395 |
|
|
#define EXTRA_CONSTRAINT_Z(OP) \
|
| 2396 |
|
|
((OP) == CONST0_RTX (GET_MODE (OP)))
|
| 2397 |
|
|
|
| 2398 |
|
|
/* Any vector constant we can handle. */
|
| 2399 |
|
|
#define EXTRA_CONSTRAINT_W(OP) \
|
| 2400 |
|
|
(GET_CODE (OP) == CONST_VECTOR \
|
| 2401 |
|
|
&& (sh_rep_vec ((OP), VOIDmode) \
|
| 2402 |
|
|
|| (HOST_BITS_PER_WIDE_INT >= 64 \
|
| 2403 |
|
|
? sh_const_vec ((OP), VOIDmode) \
|
| 2404 |
|
|
: sh_1el_vec ((OP), VOIDmode))))
|
| 2405 |
|
|
|
| 2406 |
|
|
/* A non-explicit constant that can be loaded directly into a general purpose
|
| 2407 |
|
|
register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
|
| 2408 |
|
|
#define EXTRA_CONSTRAINT_Cpg(OP) \
|
| 2409 |
|
|
(CONSTANT_P (OP) \
|
| 2410 |
|
|
&& GET_CODE (OP) != CONST_INT \
|
| 2411 |
|
|
&& GET_CODE (OP) != CONST_DOUBLE \
|
| 2412 |
|
|
&& (!flag_pic \
|
| 2413 |
|
|
|| (LEGITIMATE_PIC_OPERAND_P (OP) \
|
| 2414 |
|
|
&& (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
|
| 2415 |
|
|
&& GET_CODE (OP) != LABEL_REF)))
|
| 2416 |
|
|
#define EXTRA_CONSTRAINT_C(OP, STR) \
|
| 2417 |
|
|
((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
|
| 2418 |
|
|
: (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
|
| 2419 |
|
|
: (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
|
| 2420 |
|
|
: 0)
|
| 2421 |
|
|
|
| 2422 |
|
|
#define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
|
| 2423 |
|
|
#define EXTRA_CONSTRAINT_Sr0(OP) \
|
| 2424 |
|
|
(memory_operand((OP), GET_MODE (OP)) \
|
| 2425 |
|
|
&& ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
|
| 2426 |
|
|
#define EXTRA_CONSTRAINT_Sua(OP) \
|
| 2427 |
|
|
(memory_operand((OP), GET_MODE (OP)) \
|
| 2428 |
|
|
&& GET_CODE (XEXP (OP, 0)) != PLUS)
|
| 2429 |
|
|
#define EXTRA_CONSTRAINT_S(OP, STR) \
|
| 2430 |
|
|
((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
|
| 2431 |
|
|
: (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
|
| 2432 |
|
|
: 0)
|
| 2433 |
|
|
|
| 2434 |
|
|
#define EXTRA_CONSTRAINT_STR(OP, C, STR) \
|
| 2435 |
|
|
((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
|
| 2436 |
|
|
: (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
|
| 2437 |
|
|
: (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
|
| 2438 |
|
|
: (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
|
| 2439 |
|
|
: (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
|
| 2440 |
|
|
: (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
|
| 2441 |
|
|
: (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
|
| 2442 |
|
|
: 0)
|
| 2443 |
|
|
|
| 2444 |
|
|
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
|
| 2445 |
|
|
that is a valid memory address for an instruction.
|
| 2446 |
|
|
The MODE argument is the machine mode for the MEM expression
|
| 2447 |
|
|
that wants to use this address. */
|
| 2448 |
|
|
|
| 2449 |
|
|
#define MODE_DISP_OK_4(X,MODE) \
|
| 2450 |
|
|
(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
|
| 2451 |
|
|
&& ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
|
| 2452 |
|
|
|
| 2453 |
|
|
#define MODE_DISP_OK_8(X,MODE) \
|
| 2454 |
|
|
((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
|
| 2455 |
|
|
&& ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
|
| 2456 |
|
|
|
| 2457 |
|
|
#undef MODE_DISP_OK_4
|
| 2458 |
|
|
#define MODE_DISP_OK_4(X,MODE) \
|
| 2459 |
|
|
((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
|
| 2460 |
|
|
&& ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
|
| 2461 |
|
|
|| ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
|
| 2462 |
|
|
&& ! (INTVAL(X) & 3) && TARGET_SH2A))
|
| 2463 |
|
|
|
| 2464 |
|
|
#undef MODE_DISP_OK_8
|
| 2465 |
|
|
#define MODE_DISP_OK_8(X,MODE) \
|
| 2466 |
|
|
(((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
|
| 2467 |
|
|
&& ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
|
| 2468 |
|
|
|| ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
|
| 2469 |
|
|
&& ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
|
| 2470 |
|
|
|
| 2471 |
|
|
#define BASE_REGISTER_RTX_P(X) \
|
| 2472 |
|
|
((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
|
| 2473 |
|
|
|| (GET_CODE (X) == SUBREG \
|
| 2474 |
|
|
&& TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
|
| 2475 |
|
|
GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
|
| 2476 |
|
|
&& GET_CODE (SUBREG_REG (X)) == REG \
|
| 2477 |
|
|
&& REG_OK_FOR_BASE_P (SUBREG_REG (X))))
|
| 2478 |
|
|
|
| 2479 |
|
|
/* Since this must be r0, which is a single register class, we must check
|
| 2480 |
|
|
SUBREGs more carefully, to be sure that we don't accept one that extends
|
| 2481 |
|
|
outside the class. */
|
| 2482 |
|
|
#define INDEX_REGISTER_RTX_P(X) \
|
| 2483 |
|
|
((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
|
| 2484 |
|
|
|| (GET_CODE (X) == SUBREG \
|
| 2485 |
|
|
&& TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
|
| 2486 |
|
|
GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
|
| 2487 |
|
|
&& GET_CODE (SUBREG_REG (X)) == REG \
|
| 2488 |
|
|
&& SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
|
| 2489 |
|
|
|
| 2490 |
|
|
/* Jump to LABEL if X is a valid address RTX. This must also take
|
| 2491 |
|
|
REG_OK_STRICT into account when deciding about valid registers, but it uses
|
| 2492 |
|
|
the above macros so we are in luck.
|
| 2493 |
|
|
|
| 2494 |
|
|
Allow REG
|
| 2495 |
|
|
REG+disp
|
| 2496 |
|
|
REG+r0
|
| 2497 |
|
|
REG++
|
| 2498 |
|
|
--REG */
|
| 2499 |
|
|
|
| 2500 |
|
|
/* ??? The SH2e does not have the REG+disp addressing mode when loading values
|
| 2501 |
|
|
into the FRx registers. We implement this by setting the maximum offset
|
| 2502 |
|
|
to zero when the value is SFmode. This also restricts loading of SFmode
|
| 2503 |
|
|
values into the integer registers, but that can't be helped. */
|
| 2504 |
|
|
|
| 2505 |
|
|
/* The SH allows a displacement in a QI or HI amode, but only when the
|
| 2506 |
|
|
other operand is R0. GCC doesn't handle this very well, so we forgo
|
| 2507 |
|
|
all of that.
|
| 2508 |
|
|
|
| 2509 |
|
|
A legitimate index for a QI or HI is 0, SI can be any number 0..63,
|
| 2510 |
|
|
DI can be any number 0..60. */
|
| 2511 |
|
|
|
| 2512 |
|
|
#define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
|
| 2513 |
|
|
do { \
|
| 2514 |
|
|
if (GET_CODE (OP) == CONST_INT) \
|
| 2515 |
|
|
{ \
|
| 2516 |
|
|
if (TARGET_SHMEDIA) \
|
| 2517 |
|
|
{ \
|
| 2518 |
|
|
int MODE_SIZE; \
|
| 2519 |
|
|
/* Check if this the address of an unaligned load / store. */\
|
| 2520 |
|
|
if ((MODE) == VOIDmode) \
|
| 2521 |
|
|
{ \
|
| 2522 |
|
|
if (CONST_OK_FOR_I06 (INTVAL (OP))) \
|
| 2523 |
|
|
goto LABEL; \
|
| 2524 |
|
|
break; \
|
| 2525 |
|
|
} \
|
| 2526 |
|
|
MODE_SIZE = GET_MODE_SIZE (MODE); \
|
| 2527 |
|
|
if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
|
| 2528 |
|
|
&& INTVAL (OP) >= -512 * MODE_SIZE \
|
| 2529 |
|
|
&& INTVAL (OP) < 512 * MODE_SIZE) \
|
| 2530 |
|
|
goto LABEL; \
|
| 2531 |
|
|
else \
|
| 2532 |
|
|
break; \
|
| 2533 |
|
|
} \
|
| 2534 |
|
|
if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
|
| 2535 |
|
|
if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
|
| 2536 |
|
|
} \
|
| 2537 |
|
|
} while(0)
|
| 2538 |
|
|
|
| 2539 |
|
|
#define ALLOW_INDEXED_ADDRESS \
|
| 2540 |
|
|
((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
|
| 2541 |
|
|
|
| 2542 |
|
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
|
| 2543 |
|
|
{ \
|
| 2544 |
|
|
if (BASE_REGISTER_RTX_P (X)) \
|
| 2545 |
|
|
goto LABEL; \
|
| 2546 |
|
|
else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
|
| 2547 |
|
|
&& ! TARGET_SHMEDIA \
|
| 2548 |
|
|
&& BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
|
| 2549 |
|
|
goto LABEL; \
|
| 2550 |
|
|
else if (GET_CODE (X) == PLUS \
|
| 2551 |
|
|
&& ((MODE) != PSImode || reload_completed)) \
|
| 2552 |
|
|
{ \
|
| 2553 |
|
|
rtx xop0 = XEXP ((X), 0); \
|
| 2554 |
|
|
rtx xop1 = XEXP ((X), 1); \
|
| 2555 |
|
|
if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
|
| 2556 |
|
|
GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
|
| 2557 |
|
|
if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
|
| 2558 |
|
|
|| ((xop0 == stack_pointer_rtx \
|
| 2559 |
|
|
|| xop0 == hard_frame_pointer_rtx) \
|
| 2560 |
|
|
&& REG_P (xop1) && REGNO (xop1) == R0_REG) \
|
| 2561 |
|
|
|| ((xop1 == stack_pointer_rtx \
|
| 2562 |
|
|
|| xop1 == hard_frame_pointer_rtx) \
|
| 2563 |
|
|
&& REG_P (xop0) && REGNO (xop0) == R0_REG)) \
|
| 2564 |
|
|
&& ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
|
| 2565 |
|
|
|| (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
|
| 2566 |
|
|
|| ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
|
| 2567 |
|
|
&& TARGET_FMOVD && MODE == DFmode))) \
|
| 2568 |
|
|
{ \
|
| 2569 |
|
|
if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
|
| 2570 |
|
|
goto LABEL; \
|
| 2571 |
|
|
if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
|
| 2572 |
|
|
goto LABEL; \
|
| 2573 |
|
|
} \
|
| 2574 |
|
|
} \
|
| 2575 |
|
|
}
|
| 2576 |
|
|
|
| 2577 |
|
|
/* Try machine-dependent ways of modifying an illegitimate address
|
| 2578 |
|
|
to be legitimate. If we find one, return the new, valid address.
|
| 2579 |
|
|
This macro is used in only one place: `memory_address' in explow.c.
|
| 2580 |
|
|
|
| 2581 |
|
|
OLDX is the address as it was before break_out_memory_refs was called.
|
| 2582 |
|
|
In some cases it is useful to look at this to decide what needs to be done.
|
| 2583 |
|
|
|
| 2584 |
|
|
MODE and WIN are passed so that this macro can use
|
| 2585 |
|
|
GO_IF_LEGITIMATE_ADDRESS.
|
| 2586 |
|
|
|
| 2587 |
|
|
It is always safe for this macro to do nothing. It exists to recognize
|
| 2588 |
|
|
opportunities to optimize the output.
|
| 2589 |
|
|
|
| 2590 |
|
|
For the SH, if X is almost suitable for indexing, but the offset is
|
| 2591 |
|
|
out of range, convert it into a normal form so that cse has a chance
|
| 2592 |
|
|
of reducing the number of address registers used. */
|
| 2593 |
|
|
|
| 2594 |
|
|
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
|
| 2595 |
|
|
{ \
|
| 2596 |
|
|
if (flag_pic) \
|
| 2597 |
|
|
(X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
|
| 2598 |
|
|
if (GET_CODE (X) == PLUS \
|
| 2599 |
|
|
&& (GET_MODE_SIZE (MODE) == 4 \
|
| 2600 |
|
|
|| GET_MODE_SIZE (MODE) == 8) \
|
| 2601 |
|
|
&& GET_CODE (XEXP ((X), 1)) == CONST_INT \
|
| 2602 |
|
|
&& BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
|
| 2603 |
|
|
&& ! TARGET_SHMEDIA \
|
| 2604 |
|
|
&& ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
|
| 2605 |
|
|
&& ! (TARGET_SH2E && (MODE) == SFmode)) \
|
| 2606 |
|
|
{ \
|
| 2607 |
|
|
rtx index_rtx = XEXP ((X), 1); \
|
| 2608 |
|
|
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
|
| 2609 |
|
|
rtx sum; \
|
| 2610 |
|
|
\
|
| 2611 |
|
|
GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
|
| 2612 |
|
|
/* On rare occasions, we might get an unaligned pointer \
|
| 2613 |
|
|
that is indexed in a way to give an aligned address. \
|
| 2614 |
|
|
Therefore, keep the lower two bits in offset_base. */ \
|
| 2615 |
|
|
/* Instead of offset_base 128..131 use 124..127, so that \
|
| 2616 |
|
|
simple add suffices. */ \
|
| 2617 |
|
|
if (offset > 127) \
|
| 2618 |
|
|
{ \
|
| 2619 |
|
|
offset_base = ((offset + 4) & ~60) - 4; \
|
| 2620 |
|
|
} \
|
| 2621 |
|
|
else \
|
| 2622 |
|
|
offset_base = offset & ~60; \
|
| 2623 |
|
|
/* Sometimes the normal form does not suit DImode. We \
|
| 2624 |
|
|
could avoid that by using smaller ranges, but that \
|
| 2625 |
|
|
would give less optimized code when SImode is \
|
| 2626 |
|
|
prevalent. */ \
|
| 2627 |
|
|
if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
|
| 2628 |
|
|
{ \
|
| 2629 |
|
|
sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
|
| 2630 |
|
|
GEN_INT (offset_base), NULL_RTX, 0, \
|
| 2631 |
|
|
OPTAB_LIB_WIDEN); \
|
| 2632 |
|
|
\
|
| 2633 |
|
|
(X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
|
| 2634 |
|
|
goto WIN; \
|
| 2635 |
|
|
} \
|
| 2636 |
|
|
} \
|
| 2637 |
|
|
}
|
| 2638 |
|
|
|
| 2639 |
|
|
/* A C compound statement that attempts to replace X, which is an address
|
| 2640 |
|
|
that needs reloading, with a valid memory address for an operand of
|
| 2641 |
|
|
mode MODE. WIN is a C statement label elsewhere in the code.
|
| 2642 |
|
|
|
| 2643 |
|
|
Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
|
| 2644 |
|
|
of the address. That will allow inheritance of the address reloads. */
|
| 2645 |
|
|
|
| 2646 |
|
|
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
|
| 2647 |
|
|
{ \
|
| 2648 |
|
|
if (GET_CODE (X) == PLUS \
|
| 2649 |
|
|
&& (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
|
| 2650 |
|
|
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
|
| 2651 |
|
|
&& BASE_REGISTER_RTX_P (XEXP (X, 0)) \
|
| 2652 |
|
|
&& ! TARGET_SHMEDIA \
|
| 2653 |
|
|
&& ! (TARGET_SH4 && (MODE) == DFmode) \
|
| 2654 |
|
|
&& ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
|
| 2655 |
|
|
&& (ALLOW_INDEXED_ADDRESS \
|
| 2656 |
|
|
|| XEXP ((X), 0) == stack_pointer_rtx \
|
| 2657 |
|
|
|| XEXP ((X), 0) == hard_frame_pointer_rtx)) \
|
| 2658 |
|
|
{ \
|
| 2659 |
|
|
rtx index_rtx = XEXP (X, 1); \
|
| 2660 |
|
|
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
|
| 2661 |
|
|
rtx sum; \
|
| 2662 |
|
|
\
|
| 2663 |
|
|
if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
|
| 2664 |
|
|
{ \
|
| 2665 |
|
|
push_reload (X, NULL_RTX, &X, NULL, \
|
| 2666 |
|
|
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
|
| 2667 |
|
|
(TYPE)); \
|
| 2668 |
|
|
goto WIN; \
|
| 2669 |
|
|
} \
|
| 2670 |
|
|
if (TARGET_SH2E && MODE == SFmode) \
|
| 2671 |
|
|
{ \
|
| 2672 |
|
|
X = copy_rtx (X); \
|
| 2673 |
|
|
push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
|
| 2674 |
|
|
R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
|
| 2675 |
|
|
(TYPE)); \
|
| 2676 |
|
|
goto WIN; \
|
| 2677 |
|
|
} \
|
| 2678 |
|
|
/* Instead of offset_base 128..131 use 124..127, so that \
|
| 2679 |
|
|
simple add suffices. */ \
|
| 2680 |
|
|
if (offset > 127) \
|
| 2681 |
|
|
{ \
|
| 2682 |
|
|
offset_base = ((offset + 4) & ~60) - 4; \
|
| 2683 |
|
|
} \
|
| 2684 |
|
|
else \
|
| 2685 |
|
|
offset_base = offset & ~60; \
|
| 2686 |
|
|
/* Sometimes the normal form does not suit DImode. We \
|
| 2687 |
|
|
could avoid that by using smaller ranges, but that \
|
| 2688 |
|
|
would give less optimized code when SImode is \
|
| 2689 |
|
|
prevalent. */ \
|
| 2690 |
|
|
if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
|
| 2691 |
|
|
{ \
|
| 2692 |
|
|
sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
|
| 2693 |
|
|
GEN_INT (offset_base)); \
|
| 2694 |
|
|
X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
|
| 2695 |
|
|
push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
|
| 2696 |
|
|
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
|
| 2697 |
|
|
(TYPE)); \
|
| 2698 |
|
|
goto WIN; \
|
| 2699 |
|
|
} \
|
| 2700 |
|
|
} \
|
| 2701 |
|
|
/* We must re-recognize what we created before. */ \
|
| 2702 |
|
|
else if (GET_CODE (X) == PLUS \
|
| 2703 |
|
|
&& (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
|
| 2704 |
|
|
&& GET_CODE (XEXP (X, 0)) == PLUS \
|
| 2705 |
|
|
&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
|
| 2706 |
|
|
&& BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
|
| 2707 |
|
|
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
|
| 2708 |
|
|
&& ! TARGET_SHMEDIA \
|
| 2709 |
|
|
&& ! (TARGET_SH2E && MODE == SFmode)) \
|
| 2710 |
|
|
{ \
|
| 2711 |
|
|
/* Because this address is so complex, we know it must have \
|
| 2712 |
|
|
been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
|
| 2713 |
|
|
it is already unshared, and needs no further unsharing. */ \
|
| 2714 |
|
|
push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
|
| 2715 |
|
|
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
|
| 2716 |
|
|
goto WIN; \
|
| 2717 |
|
|
} \
|
| 2718 |
|
|
}
|
| 2719 |
|
|
|
| 2720 |
|
|
/* Go to LABEL if ADDR (a legitimate address expression)
|
| 2721 |
|
|
has an effect that depends on the machine mode it is used for.
|
| 2722 |
|
|
|
| 2723 |
|
|
??? Strictly speaking, we should also include all indexed addressing,
|
| 2724 |
|
|
because the index scale factor is the length of the operand.
|
| 2725 |
|
|
However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
|
| 2726 |
|
|
high if we did that. So we rely on reload to fix things up. */
|
| 2727 |
|
|
|
| 2728 |
|
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
|
| 2729 |
|
|
{ \
|
| 2730 |
|
|
if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
|
| 2731 |
|
|
goto LABEL; \
|
| 2732 |
|
|
}
|
| 2733 |
|
|
|
| 2734 |
|
|
/* Specify the machine mode that this machine uses
|
| 2735 |
|
|
for the index in the tablejump instruction. */
|
| 2736 |
|
|
#define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
|
| 2737 |
|
|
|
| 2738 |
|
|
#define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
|
| 2739 |
|
|
((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
|
| 2740 |
|
|
? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
|
| 2741 |
|
|
: (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
|
| 2742 |
|
|
? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
|
| 2743 |
|
|
: (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
|
| 2744 |
|
|
: SImode)
|
| 2745 |
|
|
|
| 2746 |
|
|
/* Define as C expression which evaluates to nonzero if the tablejump
|
| 2747 |
|
|
instruction expects the table to contain offsets from the address of the
|
| 2748 |
|
|
table.
|
| 2749 |
|
|
Do not define this if the table should contain absolute addresses. */
|
| 2750 |
|
|
#define CASE_VECTOR_PC_RELATIVE 1
|
| 2751 |
|
|
|
| 2752 |
|
|
/* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
|
| 2753 |
|
|
#define FLOAT_TYPE_SIZE 32
|
| 2754 |
|
|
|
| 2755 |
|
|
/* Since the SH2e has only `float' support, it is desirable to make all
|
| 2756 |
|
|
floating point types equivalent to `float'. */
|
| 2757 |
|
|
#define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
|
| 2758 |
|
|
|
| 2759 |
|
|
/* 'char' is signed by default. */
|
| 2760 |
|
|
#define DEFAULT_SIGNED_CHAR 1
|
| 2761 |
|
|
|
| 2762 |
|
|
/* The type of size_t unsigned int. */
|
| 2763 |
|
|
#define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
|
| 2764 |
|
|
|
| 2765 |
|
|
#undef PTRDIFF_TYPE
|
| 2766 |
|
|
#define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
|
| 2767 |
|
|
|
| 2768 |
|
|
#define WCHAR_TYPE "short unsigned int"
|
| 2769 |
|
|
#define WCHAR_TYPE_SIZE 16
|
| 2770 |
|
|
|
| 2771 |
|
|
#define SH_ELF_WCHAR_TYPE "long int"
|
| 2772 |
|
|
|
| 2773 |
|
|
/* Max number of bytes we can move from memory to memory
|
| 2774 |
|
|
in one reasonably fast instruction. */
|
| 2775 |
|
|
#define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
|
| 2776 |
|
|
|
| 2777 |
|
|
/* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
|
| 2778 |
|
|
MOVE_MAX is not a compile-time constant. */
|
| 2779 |
|
|
#define MAX_MOVE_MAX 8
|
| 2780 |
|
|
|
| 2781 |
|
|
/* Max number of bytes we want move_by_pieces to be able to copy
|
| 2782 |
|
|
efficiently. */
|
| 2783 |
|
|
#define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
|
| 2784 |
|
|
|
| 2785 |
|
|
/* Define if operations between registers always perform the operation
|
| 2786 |
|
|
on the full register even if a narrower mode is specified. */
|
| 2787 |
|
|
#define WORD_REGISTER_OPERATIONS
|
| 2788 |
|
|
|
| 2789 |
|
|
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
|
| 2790 |
|
|
will either zero-extend or sign-extend. The value of this macro should
|
| 2791 |
|
|
be the code that says which one of the two operations is implicitly
|
| 2792 |
|
|
done, UNKNOWN if none. */
|
| 2793 |
|
|
/* For SHmedia, we can truncate to QImode easier using zero extension. */
|
| 2794 |
|
|
/* FP registers can load SImode values, but don't implicitly sign-extend
|
| 2795 |
|
|
them to DImode. */
|
| 2796 |
|
|
#define LOAD_EXTEND_OP(MODE) \
|
| 2797 |
|
|
(((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
|
| 2798 |
|
|
: (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
|
| 2799 |
|
|
|
| 2800 |
|
|
/* Define if loading short immediate values into registers sign extends. */
|
| 2801 |
|
|
#define SHORT_IMMEDIATES_SIGN_EXTEND
|
| 2802 |
|
|
|
| 2803 |
|
|
/* Nonzero if access to memory by bytes is no faster than for words. */
|
| 2804 |
|
|
#define SLOW_BYTE_ACCESS 1
|
| 2805 |
|
|
|
| 2806 |
|
|
/* Immediate shift counts are truncated by the output routines (or was it
|
| 2807 |
|
|
the assembler?). Shift counts in a register are truncated by SH. Note
|
| 2808 |
|
|
that the native compiler puts too large (> 32) immediate shift counts
|
| 2809 |
|
|
into a register and shifts by the register, letting the SH decide what
|
| 2810 |
|
|
to do instead of doing that itself. */
|
| 2811 |
|
|
/* ??? The library routines in lib1funcs.asm truncate the shift count.
|
| 2812 |
|
|
However, the SH3 has hardware shifts that do not truncate exactly as gcc
|
| 2813 |
|
|
expects - the sign bit is significant - so it appears that we need to
|
| 2814 |
|
|
leave this zero for correct SH3 code. */
|
| 2815 |
|
|
#define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
|
| 2816 |
|
|
|
| 2817 |
|
|
/* All integers have the same format so truncation is easy. */
|
| 2818 |
|
|
/* But SHmedia must sign-extend DImode when truncating to SImode. */
|
| 2819 |
|
|
#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
|
| 2820 |
|
|
(!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
|
| 2821 |
|
|
|
| 2822 |
|
|
/* Define this if addresses of constant functions
|
| 2823 |
|
|
shouldn't be put through pseudo regs where they can be cse'd.
|
| 2824 |
|
|
Desirable on machines where ordinary constants are expensive
|
| 2825 |
|
|
but a CALL with constant address is cheap. */
|
| 2826 |
|
|
/*#define NO_FUNCTION_CSE 1*/
|
| 2827 |
|
|
|
| 2828 |
|
|
/* The machine modes of pointers and functions. */
|
| 2829 |
|
|
#define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
|
| 2830 |
|
|
#define FUNCTION_MODE Pmode
|
| 2831 |
|
|
|
| 2832 |
|
|
/* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
|
| 2833 |
|
|
are actually function calls with some special constraints on arguments
|
| 2834 |
|
|
and register usage.
|
| 2835 |
|
|
|
| 2836 |
|
|
These macros tell reorg that the references to arguments and
|
| 2837 |
|
|
register clobbers for insns of type sfunc do not appear to happen
|
| 2838 |
|
|
until after the millicode call. This allows reorg to put insns
|
| 2839 |
|
|
which set the argument registers into the delay slot of the millicode
|
| 2840 |
|
|
call -- thus they act more like traditional CALL_INSNs.
|
| 2841 |
|
|
|
| 2842 |
|
|
get_attr_is_sfunc will try to recognize the given insn, so make sure to
|
| 2843 |
|
|
filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
|
| 2844 |
|
|
in particular. */
|
| 2845 |
|
|
|
| 2846 |
|
|
#define INSN_SETS_ARE_DELAYED(X) \
|
| 2847 |
|
|
((GET_CODE (X) == INSN \
|
| 2848 |
|
|
&& GET_CODE (PATTERN (X)) != SEQUENCE \
|
| 2849 |
|
|
&& GET_CODE (PATTERN (X)) != USE \
|
| 2850 |
|
|
&& GET_CODE (PATTERN (X)) != CLOBBER \
|
| 2851 |
|
|
&& get_attr_is_sfunc (X)))
|
| 2852 |
|
|
|
| 2853 |
|
|
#define INSN_REFERENCES_ARE_DELAYED(X) \
|
| 2854 |
|
|
((GET_CODE (X) == INSN \
|
| 2855 |
|
|
&& GET_CODE (PATTERN (X)) != SEQUENCE \
|
| 2856 |
|
|
&& GET_CODE (PATTERN (X)) != USE \
|
| 2857 |
|
|
&& GET_CODE (PATTERN (X)) != CLOBBER \
|
| 2858 |
|
|
&& get_attr_is_sfunc (X)))
|
| 2859 |
|
|
|
| 2860 |
|
|
|
| 2861 |
|
|
/* Position Independent Code. */
|
| 2862 |
|
|
|
| 2863 |
|
|
/* We can't directly access anything that contains a symbol,
|
| 2864 |
|
|
nor can we indirect via the constant pool. */
|
| 2865 |
|
|
#define LEGITIMATE_PIC_OPERAND_P(X) \
|
| 2866 |
|
|
((! nonpic_symbol_mentioned_p (X) \
|
| 2867 |
|
|
&& (GET_CODE (X) != SYMBOL_REF \
|
| 2868 |
|
|
|| ! CONSTANT_POOL_ADDRESS_P (X) \
|
| 2869 |
|
|
|| ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
|
| 2870 |
|
|
|| (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
|
| 2871 |
|
|
|
| 2872 |
|
|
#define SYMBOLIC_CONST_P(X) \
|
| 2873 |
|
|
((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
|
| 2874 |
|
|
&& nonpic_symbol_mentioned_p (X))
|
| 2875 |
|
|
|
| 2876 |
|
|
/* Compute extra cost of moving data between one register class
|
| 2877 |
|
|
and another. */
|
| 2878 |
|
|
|
| 2879 |
|
|
/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
|
| 2880 |
|
|
uses this information. Hence, the general register <-> floating point
|
| 2881 |
|
|
register information here is not used for SFmode. */
|
| 2882 |
|
|
|
| 2883 |
|
|
#define REGCLASS_HAS_GENERAL_REG(CLASS) \
|
| 2884 |
|
|
((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
|
| 2885 |
|
|
|| (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
|
| 2886 |
|
|
|
| 2887 |
|
|
#define REGCLASS_HAS_FP_REG(CLASS) \
|
| 2888 |
|
|
((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
|
| 2889 |
|
|
|| (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
|
| 2890 |
|
|
|
| 2891 |
|
|
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
|
| 2892 |
|
|
sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
|
| 2893 |
|
|
|
| 2894 |
|
|
/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
|
| 2895 |
|
|
would be so that people with slow memory systems could generate
|
| 2896 |
|
|
different code that does fewer memory accesses. */
|
| 2897 |
|
|
|
| 2898 |
|
|
/* A C expression for the cost of a branch instruction. A value of 1
|
| 2899 |
|
|
is the default; other values are interpreted relative to that.
|
| 2900 |
|
|
The SH1 does not have delay slots, hence we get a pipeline stall
|
| 2901 |
|
|
at every branch. The SH4 is superscalar, so the single delay slot
|
| 2902 |
|
|
is not sufficient to keep both pipelines filled. */
|
| 2903 |
|
|
#define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
|
| 2904 |
|
|
|
| 2905 |
|
|
/* Assembler output control. */
|
| 2906 |
|
|
|
| 2907 |
|
|
/* A C string constant describing how to begin a comment in the target
|
| 2908 |
|
|
assembler language. The compiler assumes that the comment will end at
|
| 2909 |
|
|
the end of the line. */
|
| 2910 |
|
|
#define ASM_COMMENT_START "!"
|
| 2911 |
|
|
|
| 2912 |
|
|
#define ASM_APP_ON ""
|
| 2913 |
|
|
#define ASM_APP_OFF ""
|
| 2914 |
|
|
#define FILE_ASM_OP "\t.file\n"
|
| 2915 |
|
|
#define SET_ASM_OP "\t.set\t"
|
| 2916 |
|
|
|
| 2917 |
|
|
/* How to change between sections. */
|
| 2918 |
|
|
|
| 2919 |
|
|
#define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
|
| 2920 |
|
|
#define DATA_SECTION_ASM_OP "\t.data"
|
| 2921 |
|
|
|
| 2922 |
|
|
#if defined CRT_BEGIN || defined CRT_END
|
| 2923 |
|
|
/* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
|
| 2924 |
|
|
# undef TEXT_SECTION_ASM_OP
|
| 2925 |
|
|
# if __SHMEDIA__ == 1 && __SH5__ == 32
|
| 2926 |
|
|
# define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
|
| 2927 |
|
|
# else
|
| 2928 |
|
|
# define TEXT_SECTION_ASM_OP "\t.text"
|
| 2929 |
|
|
# endif
|
| 2930 |
|
|
#endif
|
| 2931 |
|
|
|
| 2932 |
|
|
|
| 2933 |
|
|
/* If defined, a C expression whose value is a string containing the
|
| 2934 |
|
|
assembler operation to identify the following data as
|
| 2935 |
|
|
uninitialized global data. If not defined, and neither
|
| 2936 |
|
|
`ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
|
| 2937 |
|
|
uninitialized global data will be output in the data section if
|
| 2938 |
|
|
`-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
|
| 2939 |
|
|
used. */
|
| 2940 |
|
|
#ifndef BSS_SECTION_ASM_OP
|
| 2941 |
|
|
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
|
| 2942 |
|
|
#endif
|
| 2943 |
|
|
|
| 2944 |
|
|
/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
|
| 2945 |
|
|
separate, explicit argument. If you define this macro, it is used
|
| 2946 |
|
|
in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
|
| 2947 |
|
|
handling the required alignment of the variable. The alignment is
|
| 2948 |
|
|
specified as the number of bits.
|
| 2949 |
|
|
|
| 2950 |
|
|
Try to use function `asm_output_aligned_bss' defined in file
|
| 2951 |
|
|
`varasm.c' when defining this macro. */
|
| 2952 |
|
|
#ifndef ASM_OUTPUT_ALIGNED_BSS
|
| 2953 |
|
|
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
|
| 2954 |
|
|
asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
|
| 2955 |
|
|
#endif
|
| 2956 |
|
|
|
| 2957 |
|
|
/* Define this so that jump tables go in same section as the current function,
|
| 2958 |
|
|
which could be text or it could be a user defined section. */
|
| 2959 |
|
|
#define JUMP_TABLES_IN_TEXT_SECTION 1
|
| 2960 |
|
|
|
| 2961 |
|
|
#undef DO_GLOBAL_CTORS_BODY
|
| 2962 |
|
|
#define DO_GLOBAL_CTORS_BODY \
|
| 2963 |
|
|
{ \
|
| 2964 |
|
|
typedef (*pfunc)(); \
|
| 2965 |
|
|
extern pfunc __ctors[]; \
|
| 2966 |
|
|
extern pfunc __ctors_end[]; \
|
| 2967 |
|
|
pfunc *p; \
|
| 2968 |
|
|
for (p = __ctors_end; p > __ctors; ) \
|
| 2969 |
|
|
{ \
|
| 2970 |
|
|
(*--p)(); \
|
| 2971 |
|
|
} \
|
| 2972 |
|
|
}
|
| 2973 |
|
|
|
| 2974 |
|
|
#undef DO_GLOBAL_DTORS_BODY
|
| 2975 |
|
|
#define DO_GLOBAL_DTORS_BODY \
|
| 2976 |
|
|
{ \
|
| 2977 |
|
|
typedef (*pfunc)(); \
|
| 2978 |
|
|
extern pfunc __dtors[]; \
|
| 2979 |
|
|
extern pfunc __dtors_end[]; \
|
| 2980 |
|
|
pfunc *p; \
|
| 2981 |
|
|
for (p = __dtors; p < __dtors_end; p++) \
|
| 2982 |
|
|
{ \
|
| 2983 |
|
|
(*p)(); \
|
| 2984 |
|
|
} \
|
| 2985 |
|
|
}
|
| 2986 |
|
|
|
| 2987 |
|
|
#define ASM_OUTPUT_REG_PUSH(file, v) \
|
| 2988 |
|
|
{ \
|
| 2989 |
|
|
if (TARGET_SHMEDIA) \
|
| 2990 |
|
|
{ \
|
| 2991 |
|
|
fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
|
| 2992 |
|
|
fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
|
| 2993 |
|
|
} \
|
| 2994 |
|
|
else \
|
| 2995 |
|
|
fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
|
| 2996 |
|
|
}
|
| 2997 |
|
|
|
| 2998 |
|
|
#define ASM_OUTPUT_REG_POP(file, v) \
|
| 2999 |
|
|
{ \
|
| 3000 |
|
|
if (TARGET_SHMEDIA) \
|
| 3001 |
|
|
{ \
|
| 3002 |
|
|
fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
|
| 3003 |
|
|
fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
|
| 3004 |
|
|
} \
|
| 3005 |
|
|
else \
|
| 3006 |
|
|
fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
|
| 3007 |
|
|
}
|
| 3008 |
|
|
|
| 3009 |
|
|
/* DBX register number for a given compiler register number. */
|
| 3010 |
|
|
/* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
|
| 3011 |
|
|
to match gdb. */
|
| 3012 |
|
|
/* svr4.h undefines this macro, yet we really want to use the same numbers
|
| 3013 |
|
|
for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
|
| 3014 |
|
|
/* expand_builtin_init_dwarf_reg_sizes uses this to test if a
|
| 3015 |
|
|
register exists, so we should return -1 for invalid register numbers. */
|
| 3016 |
|
|
#define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
|
| 3017 |
|
|
|
| 3018 |
|
|
/* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
|
| 3019 |
|
|
used to use the encodings 245..260, but that doesn't make sense:
|
| 3020 |
|
|
PR_REG and PR_MEDIA_REG are actually the same register, and likewise
|
| 3021 |
|
|
the FP registers stay the same when switching between compact and media
|
| 3022 |
|
|
mode. Hence, we also need to use the same dwarf frame columns.
|
| 3023 |
|
|
Likewise, we need to support unwind information for SHmedia registers
|
| 3024 |
|
|
even in compact code. */
|
| 3025 |
|
|
#define SH_DBX_REGISTER_NUMBER(REGNO) \
|
| 3026 |
|
|
(IN_RANGE ((REGNO), \
|
| 3027 |
|
|
(unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
|
| 3028 |
|
|
FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
|
| 3029 |
|
|
? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
|
| 3030 |
|
|
: ((int) (REGNO) >= FIRST_FP_REG \
|
| 3031 |
|
|
&& ((int) (REGNO) \
|
| 3032 |
|
|
<= (FIRST_FP_REG + \
|
| 3033 |
|
|
((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
|
| 3034 |
|
|
? ((unsigned) (REGNO) - FIRST_FP_REG \
|
| 3035 |
|
|
+ (TARGET_SH5 ? 77 : 25)) \
|
| 3036 |
|
|
: XD_REGISTER_P (REGNO) \
|
| 3037 |
|
|
? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
|
| 3038 |
|
|
: TARGET_REGISTER_P (REGNO) \
|
| 3039 |
|
|
? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
|
| 3040 |
|
|
: (REGNO) == PR_REG \
|
| 3041 |
|
|
? (TARGET_SH5 ? 18 : 17) \
|
| 3042 |
|
|
: (REGNO) == PR_MEDIA_REG \
|
| 3043 |
|
|
? (TARGET_SH5 ? 18 : (unsigned) -1) \
|
| 3044 |
|
|
: (REGNO) == T_REG \
|
| 3045 |
|
|
? (TARGET_SH5 ? 242 : 18) \
|
| 3046 |
|
|
: (REGNO) == GBR_REG \
|
| 3047 |
|
|
? (TARGET_SH5 ? 238 : 19) \
|
| 3048 |
|
|
: (REGNO) == MACH_REG \
|
| 3049 |
|
|
? (TARGET_SH5 ? 239 : 20) \
|
| 3050 |
|
|
: (REGNO) == MACL_REG \
|
| 3051 |
|
|
? (TARGET_SH5 ? 240 : 21) \
|
| 3052 |
|
|
: (REGNO) == FPUL_REG \
|
| 3053 |
|
|
? (TARGET_SH5 ? 244 : 23) \
|
| 3054 |
|
|
: (unsigned) -1)
|
| 3055 |
|
|
|
| 3056 |
|
|
/* This is how to output a reference to a symbol_ref. On SH5,
|
| 3057 |
|
|
references to non-code symbols must be preceded by `datalabel'. */
|
| 3058 |
|
|
#define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
|
| 3059 |
|
|
do \
|
| 3060 |
|
|
{ \
|
| 3061 |
|
|
if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
|
| 3062 |
|
|
fputs ("datalabel ", (FILE)); \
|
| 3063 |
|
|
assemble_name ((FILE), XSTR ((SYM), 0)); \
|
| 3064 |
|
|
} \
|
| 3065 |
|
|
while (0)
|
| 3066 |
|
|
|
| 3067 |
|
|
/* This is how to output an assembler line
|
| 3068 |
|
|
that says to advance the location counter
|
| 3069 |
|
|
to a multiple of 2**LOG bytes. */
|
| 3070 |
|
|
|
| 3071 |
|
|
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
|
| 3072 |
|
|
if ((LOG) != 0) \
|
| 3073 |
|
|
fprintf ((FILE), "\t.align %d\n", (LOG))
|
| 3074 |
|
|
|
| 3075 |
|
|
/* Globalizing directive for a label. */
|
| 3076 |
|
|
#define GLOBAL_ASM_OP "\t.global\t"
|
| 3077 |
|
|
|
| 3078 |
|
|
/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
|
| 3079 |
|
|
|
| 3080 |
|
|
/* Output a relative address table. */
|
| 3081 |
|
|
|
| 3082 |
|
|
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
|
| 3083 |
|
|
switch (GET_MODE (BODY)) \
|
| 3084 |
|
|
{ \
|
| 3085 |
|
|
case SImode: \
|
| 3086 |
|
|
if (TARGET_SH5) \
|
| 3087 |
|
|
{ \
|
| 3088 |
|
|
asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
|
| 3089 |
|
|
(VALUE), (REL)); \
|
| 3090 |
|
|
break; \
|
| 3091 |
|
|
} \
|
| 3092 |
|
|
asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
|
| 3093 |
|
|
break; \
|
| 3094 |
|
|
case HImode: \
|
| 3095 |
|
|
if (TARGET_SH5) \
|
| 3096 |
|
|
{ \
|
| 3097 |
|
|
asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
|
| 3098 |
|
|
(VALUE), (REL)); \
|
| 3099 |
|
|
break; \
|
| 3100 |
|
|
} \
|
| 3101 |
|
|
asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
|
| 3102 |
|
|
break; \
|
| 3103 |
|
|
case QImode: \
|
| 3104 |
|
|
if (TARGET_SH5) \
|
| 3105 |
|
|
{ \
|
| 3106 |
|
|
asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
|
| 3107 |
|
|
(VALUE), (REL)); \
|
| 3108 |
|
|
break; \
|
| 3109 |
|
|
} \
|
| 3110 |
|
|
asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
|
| 3111 |
|
|
break; \
|
| 3112 |
|
|
default: \
|
| 3113 |
|
|
break; \
|
| 3114 |
|
|
}
|
| 3115 |
|
|
|
| 3116 |
|
|
/* Output an absolute table element. */
|
| 3117 |
|
|
|
| 3118 |
|
|
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
|
| 3119 |
|
|
if (! optimize || TARGET_BIGTABLE) \
|
| 3120 |
|
|
asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
|
| 3121 |
|
|
else \
|
| 3122 |
|
|
asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
|
| 3123 |
|
|
|
| 3124 |
|
|
|
| 3125 |
|
|
/* A C statement to be executed just prior to the output of
|
| 3126 |
|
|
assembler code for INSN, to modify the extracted operands so
|
| 3127 |
|
|
they will be output differently.
|
| 3128 |
|
|
|
| 3129 |
|
|
Here the argument OPVEC is the vector containing the operands
|
| 3130 |
|
|
extracted from INSN, and NOPERANDS is the number of elements of
|
| 3131 |
|
|
the vector which contain meaningful data for this insn.
|
| 3132 |
|
|
The contents of this vector are what will be used to convert the insn
|
| 3133 |
|
|
template into assembler code, so you can change the assembler output
|
| 3134 |
|
|
by changing the contents of the vector. */
|
| 3135 |
|
|
|
| 3136 |
|
|
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
|
| 3137 |
|
|
final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
|
| 3138 |
|
|
|
| 3139 |
|
|
/* Print operand X (an rtx) in assembler syntax to file FILE.
|
| 3140 |
|
|
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
|
| 3141 |
|
|
For `%' followed by punctuation, CODE is the punctuation and X is null. */
|
| 3142 |
|
|
|
| 3143 |
|
|
#define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
|
| 3144 |
|
|
|
| 3145 |
|
|
/* Print a memory address as an operand to reference that memory location. */
|
| 3146 |
|
|
|
| 3147 |
|
|
#define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
|
| 3148 |
|
|
|
| 3149 |
|
|
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
|
| 3150 |
|
|
((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
|
| 3151 |
|
|
|| (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
|
| 3152 |
|
|
|
| 3153 |
|
|
/* Recognize machine-specific patterns that may appear within
|
| 3154 |
|
|
constants. Used for PIC-specific UNSPECs. */
|
| 3155 |
|
|
#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
|
| 3156 |
|
|
do \
|
| 3157 |
|
|
if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
|
| 3158 |
|
|
{ \
|
| 3159 |
|
|
switch (XINT ((X), 1)) \
|
| 3160 |
|
|
{ \
|
| 3161 |
|
|
case UNSPEC_DATALABEL: \
|
| 3162 |
|
|
fputs ("datalabel ", (STREAM)); \
|
| 3163 |
|
|
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
|
| 3164 |
|
|
break; \
|
| 3165 |
|
|
case UNSPEC_PIC: \
|
| 3166 |
|
|
/* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
|
| 3167 |
|
|
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
|
| 3168 |
|
|
break; \
|
| 3169 |
|
|
case UNSPEC_GOT: \
|
| 3170 |
|
|
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
|
| 3171 |
|
|
fputs ("@GOT", (STREAM)); \
|
| 3172 |
|
|
break; \
|
| 3173 |
|
|
case UNSPEC_GOTOFF: \
|
| 3174 |
|
|
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
|
| 3175 |
|
|
fputs ("@GOTOFF", (STREAM)); \
|
| 3176 |
|
|
break; \
|
| 3177 |
|
|
case UNSPEC_PLT: \
|
| 3178 |
|
|
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
|
| 3179 |
|
|
fputs ("@PLT", (STREAM)); \
|
| 3180 |
|
|
break; \
|
| 3181 |
|
|
case UNSPEC_GOTPLT: \
|
| 3182 |
|
|
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
|
| 3183 |
|
|
fputs ("@GOTPLT", (STREAM)); \
|
| 3184 |
|
|
break; \
|
| 3185 |
|
|
case UNSPEC_DTPOFF: \
|
| 3186 |
|
|
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
|
| 3187 |
|
|
fputs ("@DTPOFF", (STREAM)); \
|
| 3188 |
|
|
break; \
|
| 3189 |
|
|
case UNSPEC_GOTTPOFF: \
|
| 3190 |
|
|
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
|
| 3191 |
|
|
fputs ("@GOTTPOFF", (STREAM)); \
|
| 3192 |
|
|
break; \
|
| 3193 |
|
|
case UNSPEC_TPOFF: \
|
| 3194 |
|
|
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
|
| 3195 |
|
|
fputs ("@TPOFF", (STREAM)); \
|
| 3196 |
|
|
break; \
|
| 3197 |
|
|
case UNSPEC_CALLER: \
|
| 3198 |
|
|
{ \
|
| 3199 |
|
|
char name[32]; \
|
| 3200 |
|
|
/* LPCS stands for Label for PIC Call Site. */ \
|
| 3201 |
|
|
ASM_GENERATE_INTERNAL_LABEL \
|
| 3202 |
|
|
(name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
|
| 3203 |
|
|
assemble_name ((STREAM), name); \
|
| 3204 |
|
|
} \
|
| 3205 |
|
|
break; \
|
| 3206 |
|
|
default: \
|
| 3207 |
|
|
goto FAIL; \
|
| 3208 |
|
|
} \
|
| 3209 |
|
|
break; \
|
| 3210 |
|
|
} \
|
| 3211 |
|
|
else \
|
| 3212 |
|
|
goto FAIL; \
|
| 3213 |
|
|
while (0)
|
| 3214 |
|
|
|
| 3215 |
|
|
|
| 3216 |
|
|
extern struct rtx_def *sh_compare_op0;
|
| 3217 |
|
|
extern struct rtx_def *sh_compare_op1;
|
| 3218 |
|
|
|
| 3219 |
|
|
/* Which processor to schedule for. The elements of the enumeration must
|
| 3220 |
|
|
match exactly the cpu attribute in the sh.md file. */
|
| 3221 |
|
|
|
| 3222 |
|
|
enum processor_type {
|
| 3223 |
|
|
PROCESSOR_SH1,
|
| 3224 |
|
|
PROCESSOR_SH2,
|
| 3225 |
|
|
PROCESSOR_SH2E,
|
| 3226 |
|
|
PROCESSOR_SH2A,
|
| 3227 |
|
|
PROCESSOR_SH3,
|
| 3228 |
|
|
PROCESSOR_SH3E,
|
| 3229 |
|
|
PROCESSOR_SH4,
|
| 3230 |
|
|
PROCESSOR_SH4A,
|
| 3231 |
|
|
PROCESSOR_SH5
|
| 3232 |
|
|
};
|
| 3233 |
|
|
|
| 3234 |
|
|
#define sh_cpu_attr ((enum attr_cpu)sh_cpu)
|
| 3235 |
|
|
extern enum processor_type sh_cpu;
|
| 3236 |
|
|
|
| 3237 |
|
|
extern int optimize; /* needed for gen_casesi. */
|
| 3238 |
|
|
|
| 3239 |
|
|
enum mdep_reorg_phase_e
|
| 3240 |
|
|
{
|
| 3241 |
|
|
SH_BEFORE_MDEP_REORG,
|
| 3242 |
|
|
SH_INSERT_USES_LABELS,
|
| 3243 |
|
|
SH_SHORTEN_BRANCHES0,
|
| 3244 |
|
|
SH_FIXUP_PCLOAD,
|
| 3245 |
|
|
SH_SHORTEN_BRANCHES1,
|
| 3246 |
|
|
SH_AFTER_MDEP_REORG
|
| 3247 |
|
|
};
|
| 3248 |
|
|
|
| 3249 |
|
|
extern enum mdep_reorg_phase_e mdep_reorg_phase;
|
| 3250 |
|
|
|
| 3251 |
|
|
/* Handle Renesas compiler's pragmas. */
|
| 3252 |
|
|
#define REGISTER_TARGET_PRAGMAS() do { \
|
| 3253 |
|
|
c_register_pragma (0, "interrupt", sh_pr_interrupt); \
|
| 3254 |
|
|
c_register_pragma (0, "trapa", sh_pr_trapa); \
|
| 3255 |
|
|
c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
|
| 3256 |
|
|
} while (0)
|
| 3257 |
|
|
|
| 3258 |
|
|
extern tree sh_deferred_function_attributes;
|
| 3259 |
|
|
extern tree *sh_deferred_function_attributes_tail;
|
| 3260 |
|
|
|
| 3261 |
|
|
/* Set when processing a function with interrupt attribute. */
|
| 3262 |
|
|
|
| 3263 |
|
|
extern int current_function_interrupt;
|
| 3264 |
|
|
|
| 3265 |
|
|
|
| 3266 |
|
|
/* Instructions with unfilled delay slots take up an
|
| 3267 |
|
|
extra two bytes for the nop in the delay slot.
|
| 3268 |
|
|
sh-dsp parallel processing insns are four bytes long. */
|
| 3269 |
|
|
|
| 3270 |
|
|
#define ADJUST_INSN_LENGTH(X, LENGTH) \
|
| 3271 |
|
|
(LENGTH) += sh_insn_length_adjustment (X);
|
| 3272 |
|
|
|
| 3273 |
|
|
/* Define this macro if it is advisable to hold scalars in registers
|
| 3274 |
|
|
in a wider mode than that declared by the program. In such cases,
|
| 3275 |
|
|
the value is constrained to be within the bounds of the declared
|
| 3276 |
|
|
type, but kept valid in the wider mode. The signedness of the
|
| 3277 |
|
|
extension may differ from that of the type.
|
| 3278 |
|
|
|
| 3279 |
|
|
Leaving the unsignedp unchanged gives better code than always setting it
|
| 3280 |
|
|
to 0. This is despite the fact that we have only signed char and short
|
| 3281 |
|
|
load instructions. */
|
| 3282 |
|
|
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
|
| 3283 |
|
|
if (GET_MODE_CLASS (MODE) == MODE_INT \
|
| 3284 |
|
|
&& GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
|
| 3285 |
|
|
(UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
|
| 3286 |
|
|
(MODE) = (TARGET_SH1 ? SImode \
|
| 3287 |
|
|
: TARGET_SHMEDIA32 ? SImode : DImode);
|
| 3288 |
|
|
|
| 3289 |
|
|
#define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
|
| 3290 |
|
|
|
| 3291 |
|
|
#define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
|
| 3292 |
|
|
|
| 3293 |
|
|
/* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
|
| 3294 |
|
|
and popping arguments. However, we do have push/pop instructions, and
|
| 3295 |
|
|
rather limited offsets (4 bits) in load/store instructions, so it isn't
|
| 3296 |
|
|
clear if this would give better code. If implemented, should check for
|
| 3297 |
|
|
compatibility problems. */
|
| 3298 |
|
|
|
| 3299 |
|
|
#define SH_DYNAMIC_SHIFT_COST \
|
| 3300 |
|
|
(TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
|
| 3301 |
|
|
|
| 3302 |
|
|
|
| 3303 |
|
|
#define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
|
| 3304 |
|
|
|
| 3305 |
|
|
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
|
| 3306 |
|
|
|
| 3307 |
|
|
#define ACTUAL_NORMAL_MODE(ENTITY) \
|
| 3308 |
|
|
(TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
|
| 3309 |
|
|
|
| 3310 |
|
|
#define NORMAL_MODE(ENTITY) \
|
| 3311 |
|
|
(sh_cfun_interrupt_handler_p () \
|
| 3312 |
|
|
? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
|
| 3313 |
|
|
: ACTUAL_NORMAL_MODE (ENTITY))
|
| 3314 |
|
|
|
| 3315 |
|
|
#define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
|
| 3316 |
|
|
|
| 3317 |
|
|
#define MODE_EXIT(ENTITY) \
|
| 3318 |
|
|
(sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
|
| 3319 |
|
|
|
| 3320 |
|
|
#define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
|
| 3321 |
|
|
&& (REGNO) == FPSCR_REG)
|
| 3322 |
|
|
|
| 3323 |
|
|
#define MODE_NEEDED(ENTITY, INSN) \
|
| 3324 |
|
|
(recog_memoized (INSN) >= 0 \
|
| 3325 |
|
|
? get_attr_fp_mode (INSN) \
|
| 3326 |
|
|
: FP_MODE_NONE)
|
| 3327 |
|
|
|
| 3328 |
|
|
#define MODE_AFTER(MODE, INSN) \
|
| 3329 |
|
|
(TARGET_HITACHI \
|
| 3330 |
|
|
&& recog_memoized (INSN) >= 0 \
|
| 3331 |
|
|
&& get_attr_fp_set (INSN) != FP_SET_NONE \
|
| 3332 |
|
|
? (int) get_attr_fp_set (INSN) \
|
| 3333 |
|
|
: (MODE))
|
| 3334 |
|
|
|
| 3335 |
|
|
#define MODE_PRIORITY_TO_MODE(ENTITY, N) \
|
| 3336 |
|
|
((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
|
| 3337 |
|
|
|
| 3338 |
|
|
#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
|
| 3339 |
|
|
fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
|
| 3340 |
|
|
|
| 3341 |
|
|
#define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
|
| 3342 |
|
|
sh_can_redirect_branch ((INSN), (SEQ))
|
| 3343 |
|
|
|
| 3344 |
|
|
#define DWARF_FRAME_RETURN_COLUMN \
|
| 3345 |
|
|
(TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
|
| 3346 |
|
|
|
| 3347 |
|
|
#define EH_RETURN_DATA_REGNO(N) \
|
| 3348 |
|
|
((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
|
| 3349 |
|
|
|
| 3350 |
|
|
#define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
|
| 3351 |
|
|
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
|
| 3352 |
|
|
|
| 3353 |
|
|
/* We have to distinguish between code and data, so that we apply
|
| 3354 |
|
|
datalabel where and only where appropriate. Use sdataN for data. */
|
| 3355 |
|
|
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
|
| 3356 |
|
|
((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
|
| 3357 |
|
|
| (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
|
| 3358 |
|
|
| ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
|
| 3359 |
|
|
|
| 3360 |
|
|
/* Handle special EH pointer encodings. Absolute, pc-relative, and
|
| 3361 |
|
|
indirect are handled automatically. */
|
| 3362 |
|
|
#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
|
| 3363 |
|
|
do { \
|
| 3364 |
|
|
if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
|
| 3365 |
|
|
&& ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
|
| 3366 |
|
|
{ \
|
| 3367 |
|
|
gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
|
| 3368 |
|
|
SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
|
| 3369 |
|
|
if (0) goto DONE; \
|
| 3370 |
|
|
} \
|
| 3371 |
|
|
} while (0)
|
| 3372 |
|
|
|
| 3373 |
|
|
#if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
|
| 3374 |
|
|
/* SH constant pool breaks the devices in crtstuff.c to control section
|
| 3375 |
|
|
in where code resides. We have to write it as asm code. */
|
| 3376 |
|
|
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
|
| 3377 |
|
|
asm (SECTION_OP "\n\
|
| 3378 |
|
|
mov.l 1f,r1\n\
|
| 3379 |
|
|
mova 2f,r0\n\
|
| 3380 |
|
|
braf r1\n\
|
| 3381 |
|
|
lds r0,pr\n\
|
| 3382 |
|
|
0: .p2align 2\n\
|
| 3383 |
|
|
1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
|
| 3384 |
|
|
2:\n" TEXT_SECTION_ASM_OP);
|
| 3385 |
|
|
#endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
|
| 3386 |
|
|
|
| 3387 |
|
|
#define SIMULTANEOUS_PREFETCHES 2
|
| 3388 |
|
|
|
| 3389 |
|
|
/* FIXME: middle-end support for highpart optimizations is missing. */
|
| 3390 |
|
|
#define high_life_started reload_in_progress
|
| 3391 |
|
|
|
| 3392 |
|
|
#endif /* ! GCC_SH_H */
|
