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1 12 jlechner 
;; Machine description for GNU compiler, VAX Version
2 
;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
3 
;; 2002, 2004, 2005 Free Software Foundation, Inc.
4 
 
5 
;; This file is part of GCC.
6 
 
7 
;; GCC is free software; you can redistribute it and/or modify
8 
;; it under the terms of the GNU General Public License as published by
9 
;; the Free Software Foundation; either version 2, or (at your option)
10 
;; any later version.
11 
 
12 
;; GCC is distributed in the hope that it will be useful,
13 
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
;; GNU General Public License for more details.
16 
 
17 
;; You should have received a copy of the GNU General Public License
18 
;; along with GCC; see the file COPYING.  If not, write to
19 
;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 
;; Boston, MA 02110-1301, USA.
21 
 
22 
 
23 
;;- Instruction patterns.  When multiple patterns apply,
24 
;;- the first one in the file is chosen.
25 
;;-
26 
;;- See file "rtl.def" for documentation on define_insn, match_*, et al.
27 
;;-
28 
;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29 
;;- updates for most instructions.
30 
 
31 
;; UNSPEC_VOLATILE usage:
32 
 
33 
(define_constants
34 
  [(VUNSPEC_BLOCKAGE 0)     ; `blockage' insn to prevent scheduling across an
35 
                            ; insn in the code.
36 
   (VUNSPEC_SYNC_ISTREAM 1) ; sequence of insns to sync the I-stream
37 
   (VAX_AP_REGNUM 12)       ; Register 12 contains the argument pointer
38 
   (VAX_FP_REGNUM 13)       ; Register 13 contains the frame pointer
39 
   (VAX_SP_REGNUM 14)       ; Register 14 contains the stack pointer
40 
   (VAX_PC_REGNUM 15)       ; Register 15 contains the program counter
41 
  ]
42 
)
43 
 
44 
;; Integer modes supported on VAX, with a mapping from machine mode
45 
;; to mnemonic suffix.  DImode is always a special case.
46 
(define_mode_macro VAXint [QI HI SI])
47 
(define_mode_attr  isfx [(QI "b") (HI "w") (SI "l")])
48 
 
49 
;; Similar for float modes supported on VAX.
50 
(define_mode_macro VAXfp [SF DF])
51 
(define_mode_attr  fsfx [(SF "f") (DF "%#")])
52 
 
53 
;; Some output patterns want integer immediates with a prefix...
54 
(define_mode_attr  iprefx [(QI "B") (HI "H") (SI "N")])
55 
 
56 
;; We don't want to allow a constant operand for test insns because
57 
;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
58 
;; be folded while optimizing anyway.
59 
 
60 
(define_insn "tst"
61 
  [(set (cc0)
62 
        (match_operand:VAXint 0 "nonimmediate_operand" "g"))]
63 
  ""
64 
  "tst %0")
65 
 
66 
(define_insn "tst"
67 
  [(set (cc0)
68 
        (match_operand:VAXfp 0 "general_operand" "gF"))]
69 
  ""
70 
  "tst %0")
71 
 
72 
(define_insn "cmp"
73 
  [(set (cc0)
74 
        (compare (match_operand:VAXint 0 "nonimmediate_operand" "g")
75 
                 (match_operand:VAXint 1 "general_operand" "g")))]
76 
  ""
77 
  "cmp %0,%1")
78 
 
79 
(define_insn "cmp"
80 
  [(set (cc0)
81 
        (compare (match_operand:VAXfp 0 "general_operand" "gF,gF")
82 
                 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
83 
  ""
84 
  "@
85 
   tst %0
86 
   cmp %0,%1")
87 
 
88 
(define_insn "*bit"
89 
  [(set (cc0)
90 
        (and:VAXint (match_operand:VAXint 0 "general_operand" "g")
91 
                   (match_operand:VAXint 1 "general_operand" "g")))]
92 
  ""
93 
  "bit %0,%1")
94 
 
95 
;; The VAX has no sCOND insns.  It does have add/subtract with carry
96 
;; which could be used to implement the sltu and sgeu patterns.  However,
97 
;; to do this properly requires a complete rewrite of the compare insns
98 
;; to keep them together with the sltu/sgeu insns until after the
99 
;; reload pass is complete.  The previous implementation didn't do this
100 
;; and has been deleted.
101 
 
102 
 
103 
(define_insn "mov"
104 
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
105 
        (match_operand:VAXfp 1 "general_operand" "G,gF"))]
106 
  ""
107 
  "@
108 
   clr %0
109 
   mov %1,%0")
110 
 
111 
;; Some VAXen don't support this instruction.
112 
;;(define_insn "movti"
113 
;;  [(set (match_operand:TI 0 "general_operand" "=g")
114 
;;      (match_operand:TI 1 "general_operand" "g"))]
115 
;;  ""
116 
;;  "movh %1,%0")
117 
 
118 
(define_insn "movdi"
119 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g,g")
120 
        (match_operand:DI 1 "general_operand" "I,g"))]
121 
  ""
122 
  "@
123 
   clrq %0
124 
   movq %D1,%0")
125 
 
126 
;; The VAX move instructions have space-time tradeoffs.  On a MicroVAX
127 
;; register-register mov instructions take 3 bytes and 2 CPU cycles.  clrl
128 
;; takes 2 bytes and 3 cycles.  mov from constant to register takes 2 cycles
129 
;; if the constant is smaller than 4 bytes, 3 cycles for a longword
130 
;; constant.  movz, mneg, and mcom are as fast as mov, so movzwl is faster
131 
;; than movl for positive constants that fit in 16 bits but not 6 bits.  cvt
132 
;; instructions take 4 cycles.  inc takes 3 cycles.  The machine description
133 
;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
134 
;; instead of movl).
135 
 
136 
;; Cycle counts for other models may vary (on a VAX 750 they are similar,
137 
;; but on a VAX 9000 most move and add instructions with one constant
138 
;; operand take 1 cycle).
139 
 
140 
;;  Loads of constants between 64 and 128 used to be done with
141 
;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
142 
 
143 
(define_insn "mov"
144 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
145 
        (match_operand:VAXint 1 "general_operand" "g"))]
146 
  ""
147 
  "* return vax_output_int_move (insn, operands, mode);")
148 
 
149 
(define_insn "movstricthi"
150 
  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
151 
        (match_operand:HI 1 "general_operand" "g"))]
152 
  ""
153 
  "*
154 
{
155 
  if (GET_CODE (operands[1]) == CONST_INT)
156 
    {
157 
      int i = INTVAL (operands[1]);
158 
      if (i == 0)
159 
        return \"clrw %0\";
160 
      else if ((unsigned int)i < 64)
161 
        return \"movw %1,%0\";
162 
      else if ((unsigned int)~i < 64)
163 
        return \"mcomw %H1,%0\";
164 
      else if ((unsigned int)i < 256)
165 
        return \"movzbw %1,%0\";
166 
    }
167 
  return \"movw %1,%0\";
168 
}")
169 
 
170 
(define_insn "movstrictqi"
171 
  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
172 
        (match_operand:QI 1 "general_operand" "g"))]
173 
  ""
174 
  "*
175 
{
176 
  if (GET_CODE (operands[1]) == CONST_INT)
177 
    {
178 
      int i = INTVAL (operands[1]);
179 
      if (i == 0)
180 
        return \"clrb %0\";
181 
      else if ((unsigned int)~i < 64)
182 
        return \"mcomb %B1,%0\";
183 
    }
184 
  return \"movb %1,%0\";
185 
}")
186 
 
187 
;; This is here to accept 4 arguments and pass the first 3 along
188 
;; to the movmemhi1 pattern that really does the work.
189 
(define_expand "movmemhi"
190 
  [(set (match_operand:BLK 0 "general_operand" "=g")
191 
        (match_operand:BLK 1 "general_operand" "g"))
192 
   (use (match_operand:HI 2 "general_operand" "g"))
193 
   (match_operand 3 "" "")]
194 
  ""
195 
  "
196 
  emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
197 
  DONE;
198 
")
199 
 
200 
;; The definition of this insn does not really explain what it does,
201 
;; but it should suffice
202 
;; that anything generated as this insn will be recognized as one
203 
;; and that it won't successfully combine with anything.
204 
(define_insn "movmemhi1"
205 
  [(set (match_operand:BLK 0 "memory_operand" "=m")
206 
        (match_operand:BLK 1 "memory_operand" "m"))
207 
   (use (match_operand:HI 2 "general_operand" "g"))
208 
   (clobber (reg:SI 0))
209 
   (clobber (reg:SI 1))
210 
   (clobber (reg:SI 2))
211 
   (clobber (reg:SI 3))
212 
   (clobber (reg:SI 4))
213 
   (clobber (reg:SI 5))]
214 
  ""
215 
  "movc3 %2,%1,%0")
216 
 
217 
;; Extension and truncation insns.
218 
 
219 
(define_insn "truncsiqi2"
220 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
221 
        (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
222 
  ""
223 
  "cvtlb %1,%0")
224 
 
225 
(define_insn "truncsihi2"
226 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
227 
        (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
228 
  ""
229 
  "cvtlw %1,%0")
230 
 
231 
(define_insn "trunchiqi2"
232 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
233 
        (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
234 
  ""
235 
  "cvtwb %1,%0")
236 
 
237 
(define_insn "extendhisi2"
238 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
239 
        (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
240 
  ""
241 
  "cvtwl %1,%0")
242 
 
243 
(define_insn "extendqihi2"
244 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
245 
        (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
246 
  ""
247 
  "cvtbw %1,%0")
248 
 
249 
(define_insn "extendqisi2"
250 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
251 
        (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
252 
  ""
253 
  "cvtbl %1,%0")
254 
 
255 
(define_insn "extendsfdf2"
256 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
257 
        (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
258 
  ""
259 
  "cvtf%# %1,%0")
260 
 
261 
(define_insn "truncdfsf2"
262 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
263 
        (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
264 
  ""
265 
  "cvt%#f %1,%0")
266 
 
267 
(define_insn "zero_extendhisi2"
268 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
269 
        (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
270 
  ""
271 
  "movzwl %1,%0")
272 
 
273 
(define_insn "zero_extendqihi2"
274 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
275 
        (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
276 
  ""
277 
  "movzbw %1,%0")
278 
 
279 
(define_insn "zero_extendqisi2"
280 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
281 
        (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
282 
  ""
283 
  "movzbl %1,%0")
284 
 
285 
;; Fix-to-float conversion insns.
286 
 
287 
(define_insn "float2"
288 
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
289 
        (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
290 
  ""
291 
  "cvt %1,%0")
292 
 
293 
;; Float-to-fix conversion insns.
294 
 
295 
(define_insn "fix_trunc2"
296 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
297 
        (fix:VAXint (fix:VAXfp (match_operand:VAXfp 1 "general_operand" "gF"))))]
298 
  ""
299 
  "cvt %1,%0")
300 
 
301 
;;- All kinds of add instructions.
302 
 
303 
(define_insn "add3"
304 
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
305 
        (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
306 
                    (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
307 
  ""
308 
  "@
309 
   add2 %2,%0
310 
   add2 %1,%0
311 
   add3 %1,%2,%0")
312 
 
313 
(define_insn "add3"
314 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
315 
        (plus:VAXint (match_operand:VAXint 1 "general_operand" "g")
316 
                    (match_operand:VAXint 2 "general_operand" "g")))]
317 
  ""
318 
  "* return vax_output_int_add (insn, operands, mode);")
319 
 
320 
;; The add-with-carry (adwc) instruction only accepts two operands.
321 
(define_insn "adddi3"
322 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
323 
        (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
324 
                 (match_operand:DI 2 "general_operand" "Fro,F")))]
325 
  ""
326 
  "*
327 
{
328 
  rtx low[3];
329 
  const char *pattern;
330 
  int carry = 1;
331 
 
332 
  split_quadword_operands (operands, low, 3);
333 
  /* Add low parts.  */
334 
  if (rtx_equal_p (operands[0], operands[1]))
335 
    {
336 
      if (low[2] == const0_rtx)
337 
        /* Should examine operand, punt if not POST_INC.  */
338 
        pattern = \"tstl %0\", carry = 0;
339 
      else if (low[2] == const1_rtx)
340 
        pattern = \"incl %0\";
341 
      else
342 
        pattern = \"addl2 %2,%0\";
343 
    }
344 
  else
345 
    {
346 
      if (low[2] == const0_rtx)
347 
        pattern = \"movl %1,%0\", carry = 0;
348 
      else
349 
        pattern = \"addl3 %2,%1,%0\";
350 
    }
351 
  if (pattern)
352 
    output_asm_insn (pattern, low);
353 
  if (!carry)
354 
    /* If CARRY is 0, we don't have any carry value to worry about.  */
355 
    return get_insn_template (CODE_FOR_addsi3, insn);
356 
  /* %0 = C + %1 + %2 */
357 
  if (!rtx_equal_p (operands[0], operands[1]))
358 
    output_asm_insn ((operands[1] == const0_rtx
359 
                      ? \"clrl %0\"
360 
                      : \"movl %1,%0\"), operands);
361 
  return \"adwc %2,%0\";
362 
}")
363 
 
364 
;;- All kinds of subtract instructions.
365 
 
366 
(define_insn "sub3"
367 
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
368 
        (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
369 
                     (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
370 
  ""
371 
  "@
372 
   sub2 %2,%0
373 
   sub3 %2,%1,%0")
374 
 
375 
(define_insn "sub3"
376 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
377 
        (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,g")
378 
                     (match_operand:VAXint 2 "general_operand" "g,g")))]
379 
  ""
380 
  "@
381 
   sub2 %2,%0
382 
   sub3 %2,%1,%0")
383 
 
384 
;; The subtract-with-carry (sbwc) instruction only takes two operands.
385 
(define_insn "subdi3"
386 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
387 
        (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
388 
                  (match_operand:DI 2 "general_operand" "For,F")))]
389 
  ""
390 
  "*
391 
{
392 
  rtx low[3];
393 
  const char *pattern;
394 
  int carry = 1;
395 
 
396 
  split_quadword_operands (operands, low, 3);
397 
  /* Subtract low parts.  */
398 
  if (rtx_equal_p (operands[0], operands[1]))
399 
    {
400 
      if (low[2] == const0_rtx)
401 
        pattern = 0, carry = 0;
402 
      else if (low[2] == constm1_rtx)
403 
        pattern = \"decl %0\";
404 
      else
405 
        pattern = \"subl2 %2,%0\";
406 
    }
407 
  else
408 
    {
409 
      if (low[2] == constm1_rtx)
410 
        pattern = \"decl %0\";
411 
      else if (low[2] == const0_rtx)
412 
        pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0;
413 
      else
414 
        pattern = \"subl3 %2,%1,%0\";
415 
    }
416 
  if (pattern)
417 
    output_asm_insn (pattern, low);
418 
  if (carry)
419 
    {
420 
      if (!rtx_equal_p (operands[0], operands[1]))
421 
        return \"movl %1,%0\;sbwc %2,%0\";
422 
      return \"sbwc %2,%0\";
423 
      /* %0 = %2 - %1 - C */
424 
    }
425 
  return get_insn_template (CODE_FOR_subsi3, insn);
426 
}")
427 
 
428 
;;- Multiply instructions.
429 
 
430 
(define_insn "mul3"
431 
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
432 
        (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
433 
                    (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
434 
  ""
435 
  "@
436 
   mul2 %2,%0
437 
   mul2 %1,%0
438 
   mul3 %1,%2,%0")
439 
 
440 
(define_insn "mul3"
441 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
442 
        (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g")
443 
                    (match_operand:VAXint 2 "general_operand" "g,0,g")))]
444 
  ""
445 
  "@
446 
   mul2 %2,%0
447 
   mul2 %1,%0
448 
   mul3 %1,%2,%0")
449 
 
450 
(define_insn "mulsidi3"
451 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
452 
        (mult:DI (sign_extend:DI
453 
                  (match_operand:SI 1 "nonimmediate_operand" "g"))
454 
                 (sign_extend:DI
455 
                  (match_operand:SI 2 "nonimmediate_operand" "g"))))]
456 
  ""
457 
  "emul %1,%2,$0,%0")
458 
 
459 
(define_insn ""
460 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
461 
        (plus:DI
462 
         (mult:DI (sign_extend:DI
463 
                   (match_operand:SI 1 "nonimmediate_operand" "g"))
464 
                  (sign_extend:DI
465 
                   (match_operand:SI 2 "nonimmediate_operand" "g")))
466 
         (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
467 
  ""
468 
  "emul %1,%2,%3,%0")
469 
 
470 
;; 'F' constraint means type CONST_DOUBLE
471 
(define_insn ""
472 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
473 
        (plus:DI
474 
         (mult:DI (sign_extend:DI
475 
                   (match_operand:SI 1 "nonimmediate_operand" "g"))
476 
                  (sign_extend:DI
477 
                   (match_operand:SI 2 "nonimmediate_operand" "g")))
478 
         (match_operand:DI 3 "immediate_operand" "F")))]
479 
  "GET_CODE (operands[3]) == CONST_DOUBLE
480 
    && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
481 
  "*
482 
{
483 
  if (CONST_DOUBLE_HIGH (operands[3]))
484 
    operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
485 
  return \"emul %1,%2,%3,%0\";
486 
}")
487 
 
488 
;;- Divide instructions.
489 
 
490 
(define_insn "div3"
491 
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
492 
        (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
493 
                   (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
494 
  ""
495 
  "@
496 
   div2 %2,%0
497 
   div3 %2,%1,%0")
498 
 
499 
(define_insn "div3"
500 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
501 
        (div:VAXint (match_operand:VAXint 1 "general_operand" "0,g")
502 
                   (match_operand:VAXint 2 "general_operand" "g,g")))]
503 
  ""
504 
  "@
505 
   div2 %2,%0
506 
   div3 %2,%1,%0")
507 
 
508 
;This is left out because it is very slow;
509 
;we are better off programming around the "lack" of this insn.
510 
;(define_insn "divmoddisi4"
511 
;  [(set (match_operand:SI 0 "general_operand" "=g")
512 
;       (div:SI (match_operand:DI 1 "general_operand" "g")
513 
;               (match_operand:SI 2 "general_operand" "g")))
514 
;   (set (match_operand:SI 3 "general_operand" "=g")
515 
;       (mod:SI (match_operand:DI 1 "general_operand" "g")
516 
;               (match_operand:SI 2 "general_operand" "g")))]
517 
;  ""
518 
;  "ediv %2,%1,%0,%3")
519 
 
520 
;; Bit-and on the VAX is done with a clear-bits insn.
521 
(define_expand "and3"
522 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
523 
        (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
524 
                   (match_operand:VAXint 2 "general_operand" "")))]
525 
  ""
526 
  "
527 
{
528 
  rtx op1 = operands[1];
529 
 
530 
  /* If there is a constant argument, complement that one.  */
531 
  if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
532 
    {
533 
      operands[1] = operands[2];
534 
      operands[2] = op1;
535 
      op1 = operands[1];
536 
    }
537 
 
538 
  if (GET_CODE (op1) == CONST_INT)
539 
    operands[1] = GEN_INT (~INTVAL (op1));
540 
  else
541 
    operands[1] = expand_unop (mode, one_cmpl_optab, op1, 0, 1);
542 
}")
543 
 
544 
(define_insn "*and"
545 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
546 
        (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "g,g"))
547 
                    (match_operand:VAXint 2 "general_operand" "0,g")))]
548 
  ""
549 
  "@
550 
   bic2 %1,%0
551 
   bic3 %1,%2,%0")
552 
 
553 
;; The following used to be needed because constant propagation can
554 
;; create them starting from the bic insn patterns above.  This is no
555 
;; longer a problem.  However, having these patterns allows optimization
556 
;; opportunities in combine.c.
557 
 
558 
(define_insn "*and_const_int"
559 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
560 
        (and:VAXint (match_operand:VAXint 1 "general_operand" "0,g")
561 
                   (match_operand:VAXint 2 "const_int_operand" "n,n")))]
562 
  ""
563 
  "@
564 
   bic2 %2,%0
565 
   bic3 %2,%1,%0")
566 
 
567 
 
568 
;;- Bit set instructions.
569 
 
570 
(define_insn "ior3"
571 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
572 
        (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g")
573 
                   (match_operand:VAXint 2 "general_operand" "g,0,g")))]
574 
  ""
575 
  "@
576 
   bis2 %2,%0
577 
   bis2 %1,%0
578 
   bis3 %2,%1,%0")
579 
 
580 
;;- xor instructions.
581 
 
582 
(define_insn "xor3"
583 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
584 
        (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g")
585 
                   (match_operand:VAXint 2 "general_operand" "g,0,g")))]
586 
  ""
587 
  "@
588 
   xor2 %2,%0
589 
   xor2 %1,%0
590 
   xor3 %2,%1,%0")
591 
 
592 
 
593 
(define_insn "neg2"
594 
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
595 
        (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
596 
  ""
597 
  "mneg %1,%0")
598 
 
599 
(define_insn "neg2"
600 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
601 
        (neg:VAXint (match_operand:VAXint 1 "general_operand" "g")))]
602 
  ""
603 
  "mneg %1,%0")
604 
 
605 
(define_insn "one_cmpl2"
606 
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
607 
        (not:VAXint (match_operand:VAXint 1 "general_operand" "g")))]
608 
  ""
609 
  "mcom %1,%0")
610 
 
611 
 
612 
;; Arithmetic right shift on the VAX works by negating the shift count,
613 
;; then emitting a right shift with the shift count negated.  This means
614 
;; that all actual shift counts in the RTL will be positive.  This
615 
;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
616 
;; which isn't valid.
617 
(define_expand "ashrsi3"
618 
  [(set (match_operand:SI 0 "general_operand" "=g")
619 
        (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
620 
                   (match_operand:QI 2 "general_operand" "g")))]
621 
  ""
622 
  "
623 
{
624 
  if (GET_CODE (operands[2]) != CONST_INT)
625 
    operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
626 
}")
627 
 
628 
(define_insn ""
629 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
630 
        (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
631 
                     (match_operand:QI 2 "const_int_operand" "n")))]
632 
  ""
633 
  "ashl $%n2,%1,%0")
634 
 
635 
(define_insn ""
636 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
637 
        (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
638 
                     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
639 
  ""
640 
  "ashl %2,%1,%0")
641 
 
642 
(define_insn "ashlsi3"
643 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
644 
        (ashift:SI (match_operand:SI 1 "general_operand" "g")
645 
                   (match_operand:QI 2 "general_operand" "g")))]
646 
  ""
647 
  "*
648 
{
649 
  if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
650 
    return \"addl2 %0,%0\";
651 
  if (GET_CODE (operands[1]) == REG
652 
      && GET_CODE (operands[2]) == CONST_INT)
653 
    {
654 
      int i = INTVAL (operands[2]);
655 
      if (i == 1)
656 
        return \"addl3 %1,%1,%0\";
657 
      if (i == 2)
658 
        return \"moval 0[%1],%0\";
659 
      if (i == 3)
660 
        return \"movad 0[%1],%0\";
661 
    }
662 
  return \"ashl %2,%1,%0\";
663 
}")
664 
 
665 
;; Arithmetic right shift on the VAX works by negating the shift count.
666 
(define_expand "ashrdi3"
667 
  [(set (match_operand:DI 0 "general_operand" "=g")
668 
        (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
669 
                     (match_operand:QI 2 "general_operand" "g")))]
670 
  ""
671 
  "
672 
{
673 
  operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
674 
}")
675 
 
676 
(define_insn "ashldi3"
677 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
678 
        (ashift:DI (match_operand:DI 1 "general_operand" "g")
679 
                   (match_operand:QI 2 "general_operand" "g")))]
680 
  ""
681 
  "ashq %2,%1,%0")
682 
 
683 
(define_insn ""
684 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
685 
        (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
686 
                     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
687 
  ""
688 
  "ashq %2,%1,%0")
689 
 
690 
;; We used to have expand_shift handle logical right shifts by using extzv,
691 
;; but this make it very difficult to do lshrdi3.  Since the VAX is the
692 
;; only machine with this kludge, it's better to just do this with a
693 
;; define_expand and remove that case from expand_shift.
694 
 
695 
(define_expand "lshrsi3"
696 
  [(set (match_dup 3)
697 
        (minus:QI (const_int 32)
698 
                  (match_dup 4)))
699 
   (set (match_operand:SI 0 "general_operand" "=g")
700 
        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
701 
                         (match_dup 3)
702 
                         (match_operand:SI 2 "register_operand" "g")))]
703 
  ""
704 
  "
705 
{
706 
  operands[3] = gen_reg_rtx (QImode);
707 
  operands[4] = gen_lowpart (QImode, operands[2]);
708 
}")
709 
 
710 
;; Rotate right on the VAX works by negating the shift count.
711 
(define_expand "rotrsi3"
712 
  [(set (match_operand:SI 0 "general_operand" "=g")
713 
        (rotatert:SI (match_operand:SI 1 "general_operand" "g")
714 
                     (match_operand:QI 2 "general_operand" "g")))]
715 
  ""
716 
  "
717 
{
718 
  if (GET_CODE (operands[2]) != CONST_INT)
719 
    operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
720 
}")
721 
 
722 
(define_insn "rotlsi3"
723 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
724 
        (rotate:SI (match_operand:SI 1 "general_operand" "g")
725 
                   (match_operand:QI 2 "general_operand" "g")))]
726 
  ""
727 
  "rotl %2,%1,%0")
728 
 
729 
(define_insn ""
730 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
731 
        (rotatert:SI (match_operand:SI 1 "general_operand" "g")
732 
                     (match_operand:QI 2 "const_int_operand" "n")))]
733 
  ""
734 
  "rotl %R2,%1,%0")
735 
 
736 
(define_insn ""
737 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
738 
        (rotatert:SI (match_operand:SI 1 "general_operand" "g")
739 
                     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
740 
  ""
741 
  "rotl %2,%1,%0")
742 
 
743 
;This insn is probably slower than a multiply and an add.
744 
;(define_insn ""
745 
;  [(set (match_operand:SI 0 "general_operand" "=g")
746 
;       (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
747 
;                         (match_operand:SI 2 "general_operand" "g"))
748 
;                (match_operand:SI 3 "general_operand" "g")))]
749 
;  ""
750 
;  "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
751 
 
752 
;; Special cases of bit-field insns which we should
753 
;; recognize in preference to the general case.
754 
;; These handle aligned 8-bit and 16-bit fields,
755 
;; which can usually be done with move instructions.
756 
 
757 
(define_insn ""
758 
  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
759 
                         (match_operand:QI 1 "const_int_operand" "n")
760 
                         (match_operand:SI 2 "const_int_operand" "n"))
761 
        (match_operand:SI 3 "general_operand" "g"))]
762 
   "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
763 
   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
764 
   && (GET_CODE (operands[0]) == REG
765 
       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
766 
  "*
767 
{
768 
  if (REG_P (operands[0]))
769 
    {
770 
      if (INTVAL (operands[2]) != 0)
771 
        return \"insv %3,%2,%1,%0\";
772 
    }
773 
  else
774 
    operands[0]
775 
      = adjust_address (operands[0],
776 
                        INTVAL (operands[1]) == 8 ? QImode : HImode,
777 
                        INTVAL (operands[2]) / 8);
778 
 
779 
  CC_STATUS_INIT;
780 
  if (INTVAL (operands[1]) == 8)
781 
    return \"movb %3,%0\";
782 
  return \"movw %3,%0\";
783 
}")
784 
 
785 
(define_insn ""
786 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
787 
        (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
788 
                         (match_operand:QI 2 "const_int_operand" "n")
789 
                         (match_operand:SI 3 "const_int_operand" "n")))]
790 
  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
791 
   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
792 
   && (GET_CODE (operands[1]) == REG
793 
       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
794 
  "*
795 
{
796 
  if (REG_P (operands[1]))
797 
    {
798 
      if (INTVAL (operands[3]) != 0)
799 
        return \"extzv %3,%2,%1,%0\";
800 
    }
801 
  else
802 
    operands[1]
803 
      = adjust_address (operands[1],
804 
                        INTVAL (operands[2]) == 8 ? QImode : HImode,
805 
                        INTVAL (operands[3]) / 8);
806 
 
807 
  if (INTVAL (operands[2]) == 8)
808 
    return \"movzbl %1,%0\";
809 
  return \"movzwl %1,%0\";
810 
}")
811 
 
812 
(define_insn ""
813 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
814 
        (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
815 
                         (match_operand:QI 2 "const_int_operand" "n")
816 
                         (match_operand:SI 3 "const_int_operand" "n")))]
817 
  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
818 
   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
819 
   && (GET_CODE (operands[1]) == REG
820 
       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
821 
  "*
822 
{
823 
  if (REG_P (operands[1]))
824 
    {
825 
      if (INTVAL (operands[3]) != 0)
826 
        return \"extv %3,%2,%1,%0\";
827 
    }
828 
  else
829 
    operands[1]
830 
      = adjust_address (operands[1],
831 
                        INTVAL (operands[2]) == 8 ? QImode : HImode,
832 
                        INTVAL (operands[3]) / 8);
833 
 
834 
  if (INTVAL (operands[2]) == 8)
835 
    return \"cvtbl %1,%0\";
836 
  return \"cvtwl %1,%0\";
837 
}")
838 
 
839 
;; Register-only SImode cases of bit-field insns.
840 
 
841 
(define_insn ""
842 
  [(set (cc0)
843 
        (compare
844 
         (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
845 
                          (match_operand:QI 1 "general_operand" "g")
846 
                          (match_operand:SI 2 "general_operand" "g"))
847 
         (match_operand:SI 3 "general_operand" "g")))]
848 
  ""
849 
  "cmpv %2,%1,%0,%3")
850 
 
851 
(define_insn ""
852 
  [(set (cc0)
853 
        (compare
854 
         (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
855 
                          (match_operand:QI 1 "general_operand" "g")
856 
                          (match_operand:SI 2 "general_operand" "g"))
857 
         (match_operand:SI 3 "general_operand" "g")))]
858 
  ""
859 
  "cmpzv %2,%1,%0,%3")
860 
 
861 
;; When the field position and size are constant and the destination
862 
;; is a register, extv and extzv are much slower than a rotate followed
863 
;; by a bicl or sign extension.  Because we might end up choosing ext[z]v
864 
;; anyway, we can't allow immediate values for the primary source operand.
865 
 
866 
(define_insn ""
867 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
868 
        (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
869 
                         (match_operand:QI 2 "general_operand" "g")
870 
                         (match_operand:SI 3 "general_operand" "g")))]
871 
  ""
872 
  "*
873 
{
874 
  if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
875 
      || GET_CODE (operands[0]) != REG
876 
      || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
877 
    return \"extv %3,%2,%1,%0\";
878 
  if (INTVAL (operands[2]) == 8)
879 
    return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
880 
  return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
881 
}")
882 
 
883 
(define_insn ""
884 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
885 
        (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
886 
                         (match_operand:QI 2 "general_operand" "g")
887 
                         (match_operand:SI 3 "general_operand" "g")))]
888 
  ""
889 
  "*
890 
{
891 
  if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
892 
      || GET_CODE (operands[0]) != REG)
893 
    return \"extzv %3,%2,%1,%0\";
894 
  if (INTVAL (operands[2]) == 8)
895 
    return \"rotl %R3,%1,%0\;movzbl %0,%0\";
896 
  if (INTVAL (operands[2]) == 16)
897 
    return \"rotl %R3,%1,%0\;movzwl %0,%0\";
898 
  if (INTVAL (operands[3]) & 31)
899 
    return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
900 
  if (rtx_equal_p (operands[0], operands[1]))
901 
    return \"bicl2 %M2,%0\";
902 
  return \"bicl3 %M2,%1,%0\";
903 
}")
904 
 
905 
;; Non-register cases.
906 
;; nonimmediate_operand is used to make sure that mode-ambiguous cases
907 
;; don't match these (and therefore match the cases above instead).
908 
 
909 
(define_insn ""
910 
  [(set (cc0)
911 
        (compare
912 
         (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
913 
                          (match_operand:QI 1 "general_operand" "g")
914 
                          (match_operand:SI 2 "general_operand" "g"))
915 
         (match_operand:SI 3 "general_operand" "g")))]
916 
  ""
917 
  "cmpv %2,%1,%0,%3")
918 
 
919 
(define_insn ""
920 
  [(set (cc0)
921 
        (compare
922 
         (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
923 
                          (match_operand:QI 1 "general_operand" "g")
924 
                          (match_operand:SI 2 "general_operand" "g"))
925 
         (match_operand:SI 3 "general_operand" "g")))]
926 
  ""
927 
  "cmpzv %2,%1,%0,%3")
928 
 
929 
(define_insn "extv"
930 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
931 
        (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
932 
                         (match_operand:QI 2 "general_operand" "g")
933 
                         (match_operand:SI 3 "general_operand" "g")))]
934 
  ""
935 
  "*
936 
{
937 
  if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
938 
      || GET_CODE (operands[3]) != CONST_INT
939 
      || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
940 
      || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
941 
      || side_effects_p (operands[1])
942 
      || (GET_CODE (operands[1]) == MEM
943 
          && mode_dependent_address_p (XEXP (operands[1], 0))))
944 
    return \"extv %3,%2,%1,%0\";
945 
  if (INTVAL (operands[2]) == 8)
946 
    return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
947 
  return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
948 
}")
949 
 
950 
(define_expand "extzv"
951 
  [(set (match_operand:SI 0 "general_operand" "")
952 
        (zero_extract:SI (match_operand:SI 1 "general_operand" "")
953 
                         (match_operand:QI 2 "general_operand" "")
954 
                         (match_operand:SI 3 "general_operand" "")))]
955 
  ""
956 
  "")
957 
 
958 
(define_insn ""
959 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
960 
        (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
961 
                         (match_operand:QI 2 "general_operand" "g")
962 
                         (match_operand:SI 3 "general_operand" "g")))]
963 
  ""
964 
  "*
965 
{
966 
  if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
967 
      || GET_CODE (operands[3]) != CONST_INT
968 
      || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
969 
      || side_effects_p (operands[1])
970 
      || (GET_CODE (operands[1]) == MEM
971 
          && mode_dependent_address_p (XEXP (operands[1], 0))))
972 
    return \"extzv %3,%2,%1,%0\";
973 
  if (INTVAL (operands[2]) == 8)
974 
    return \"rotl %R3,%1,%0\;movzbl %0,%0\";
975 
  if (INTVAL (operands[2]) == 16)
976 
    return \"rotl %R3,%1,%0\;movzwl %0,%0\";
977 
  return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
978 
}")
979 
 
980 
(define_expand "insv"
981 
  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
982 
                         (match_operand:QI 1 "general_operand" "")
983 
                         (match_operand:SI 2 "general_operand" ""))
984 
        (match_operand:SI 3 "general_operand" ""))]
985 
  ""
986 
  "")
987 
 
988 
(define_insn ""
989 
  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
990 
                         (match_operand:QI 1 "general_operand" "g")
991 
                         (match_operand:SI 2 "general_operand" "g"))
992 
        (match_operand:SI 3 "general_operand" "g"))]
993 
  ""
994 
  "insv %3,%2,%1,%0")
995 
 
996 
(define_insn ""
997 
  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
998 
                         (match_operand:QI 1 "general_operand" "g")
999 
                         (match_operand:SI 2 "general_operand" "g"))
1000 
        (match_operand:SI 3 "general_operand" "g"))]
1001 
  ""
1002 
  "insv %3,%2,%1,%0")
1003 
 
1004 
;; Unconditional jump
1005 
(define_insn "jump"
1006 
  [(set (pc)
1007 
        (label_ref (match_operand 0 "" "")))]
1008 
  ""
1009 
  "jbr %l0")
1010 
 
1011 
;; Conditional jumps
1012 
(define_code_macro any_cond [eq ne gt lt gtu ltu ge le geu leu])
1013 
 
1014 
(define_insn "b"
1015 
  [(set (pc)
1016 
        (if_then_else (any_cond (cc0)
1017 
                                (const_int 0))
1018 
                      (label_ref (match_operand 0 "" ""))
1019 
                      (pc)))]
1020 
  ""
1021 
  "* return vax_output_conditional_branch ();")
1022 
 
1023 
;; Recognize reversed jumps.
1024 
(define_insn ""
1025 
  [(set (pc)
1026 
        (if_then_else (match_operator 0 "comparison_operator"
1027 
                                      [(cc0)
1028 
                                       (const_int 0)])
1029 
                      (pc)
1030 
                      (label_ref (match_operand 1 "" ""))))]
1031 
  ""
1032 
  "j%C0 %l1") ; %C0 negates condition
1033 
 
1034 
;; Recognize jbs, jlbs, jbc and jlbc instructions.  Note that the operand
1035 
;; of jlbs and jlbc insns are SImode in the hardware.  However, if it is
1036 
;; memory, we use QImode in the insn.  So we can't use those instructions
1037 
;; for mode-dependent addresses.
1038 
 
1039 
(define_insn ""
1040 
  [(set (pc)
1041 
        (if_then_else
1042 
         (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1043 
                              (const_int 1)
1044 
                              (match_operand:SI 1 "general_operand" "I,g"))
1045 
             (const_int 0))
1046 
         (label_ref (match_operand 2 "" ""))
1047 
         (pc)))]
1048 
  ""
1049 
  "@
1050 
   jlbs %0,%l2
1051 
   jbs %1,%0,%l2")
1052 
 
1053 
(define_insn ""
1054 
  [(set (pc)
1055 
        (if_then_else
1056 
         (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1057 
                              (const_int 1)
1058 
                              (match_operand:SI 1 "general_operand" "I,g"))
1059 
             (const_int 0))
1060 
         (label_ref (match_operand 2 "" ""))
1061 
         (pc)))]
1062 
  ""
1063 
  "@
1064 
   jlbc %0,%l2
1065 
   jbc %1,%0,%l2")
1066 
 
1067 
(define_insn ""
1068 
  [(set (pc)
1069 
        (if_then_else
1070 
         (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1071 
                              (const_int 1)
1072 
                              (match_operand:SI 1 "general_operand" "I,g"))
1073 
             (const_int 0))
1074 
         (label_ref (match_operand 2 "" ""))
1075 
         (pc)))]
1076 
  ""
1077 
  "@
1078 
   jlbs %0,%l2
1079 
   jbs %1,%0,%l2")
1080 
 
1081 
(define_insn ""
1082 
  [(set (pc)
1083 
        (if_then_else
1084 
         (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1085 
                              (const_int 1)
1086 
                              (match_operand:SI 1 "general_operand" "I,g"))
1087 
             (const_int 0))
1088 
         (label_ref (match_operand 2 "" ""))
1089 
         (pc)))]
1090 
  ""
1091 
  "@
1092 
   jlbc %0,%l2
1093 
   jbc %1,%0,%l2")
1094 
 
1095 
;; Subtract-and-jump and Add-and-jump insns.
1096 
;; These are not used when output is for the Unix assembler
1097 
;; because it does not know how to modify them to reach far.
1098 
 
1099 
;; Normal sob insns.
1100 
 
1101 
(define_insn ""
1102 
  [(set (pc)
1103 
        (if_then_else
1104 
         (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1105 
                      (const_int -1))
1106 
             (const_int 0))
1107 
         (label_ref (match_operand 1 "" ""))
1108 
         (pc)))
1109 
   (set (match_dup 0)
1110 
        (plus:SI (match_dup 0)
1111 
                 (const_int -1)))]
1112 
  "!TARGET_UNIX_ASM"
1113 
  "jsobgtr %0,%l1")
1114 
 
1115 
(define_insn ""
1116 
  [(set (pc)
1117 
        (if_then_else
1118 
         (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1119 
                      (const_int -1))
1120 
             (const_int 0))
1121 
         (label_ref (match_operand 1 "" ""))
1122 
         (pc)))
1123 
   (set (match_dup 0)
1124 
        (plus:SI (match_dup 0)
1125 
                 (const_int -1)))]
1126 
  "!TARGET_UNIX_ASM"
1127 
  "jsobgeq %0,%l1")
1128 
 
1129 
;; Normal aob insns.  Define a version for when operands[1] is a constant.
1130 
(define_insn ""
1131 
  [(set (pc)
1132 
        (if_then_else
1133 
         (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1134 
                      (const_int 1))
1135 
             (match_operand:SI 1 "general_operand" "g"))
1136 
         (label_ref (match_operand 2 "" ""))
1137 
         (pc)))
1138 
   (set (match_dup 0)
1139 
        (plus:SI (match_dup 0)
1140 
                 (const_int 1)))]
1141 
  "!TARGET_UNIX_ASM"
1142 
  "jaoblss %1,%0,%l2")
1143 
 
1144 
(define_insn ""
1145 
  [(set (pc)
1146 
        (if_then_else
1147 
         (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1148 
             (match_operand:SI 1 "general_operand" "g"))
1149 
         (label_ref (match_operand 2 "" ""))
1150 
         (pc)))
1151 
   (set (match_dup 0)
1152 
        (plus:SI (match_dup 0)
1153 
                 (const_int 1)))]
1154 
  "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1155 
  "jaoblss %P1,%0,%l2")
1156 
 
1157 
(define_insn ""
1158 
  [(set (pc)
1159 
        (if_then_else
1160 
         (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1161 
                      (const_int 1))
1162 
             (match_operand:SI 1 "general_operand" "g"))
1163 
         (label_ref (match_operand 2 "" ""))
1164 
         (pc)))
1165 
   (set (match_dup 0)
1166 
        (plus:SI (match_dup 0)
1167 
                 (const_int 1)))]
1168 
  "!TARGET_UNIX_ASM"
1169 
  "jaobleq %1,%0,%l2")
1170 
 
1171 
(define_insn ""
1172 
  [(set (pc)
1173 
        (if_then_else
1174 
         (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1175 
             (match_operand:SI 1 "general_operand" "g"))
1176 
         (label_ref (match_operand 2 "" ""))
1177 
         (pc)))
1178 
   (set (match_dup 0)
1179 
        (plus:SI (match_dup 0)
1180 
                 (const_int 1)))]
1181 
  "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1182 
  "jaobleq %P1,%0,%l2")
1183 
 
1184 
;; Something like a sob insn, but compares against -1.
1185 
;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1186 
 
1187 
(define_insn ""
1188 
  [(set (pc)
1189 
        (if_then_else
1190 
         (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1191 
             (const_int 0))
1192 
         (label_ref (match_operand 1 "" ""))
1193 
         (pc)))
1194 
   (set (match_dup 0)
1195 
        (plus:SI (match_dup 0)
1196 
                 (const_int -1)))]
1197 
  ""
1198 
  "decl %0\;jgequ %l1")
1199 
 
1200 
(define_expand "call_pop"
1201 
  [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1202 
                    (match_operand:SI 1 "const_int_operand" ""))
1203 
              (set (reg:SI VAX_SP_REGNUM)
1204 
                   (plus:SI (reg:SI VAX_SP_REGNUM)
1205 
                            (match_operand:SI 3 "immediate_operand" "")))])]
1206 
  ""
1207 
{
1208 
  gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0);
1209 
 
1210 
  /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1211 
     during EH unwinding.  We must include the argument count pushed by
1212 
     the calls instruction.  */
1213 
  operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
1214 
})
1215 
 
1216 
(define_insn "*call_pop"
1217 
  [(call (match_operand:QI 0 "memory_operand" "m")
1218 
         (match_operand:SI 1 "const_int_operand" "n"))
1219 
   (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
1220 
                                        (match_operand:SI 2 "immediate_operand" "i")))]
1221 
  ""
1222 
{
1223 
  operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
1224 
  return "calls %1,%0";
1225 
})
1226 
 
1227 
(define_expand "call_value_pop"
1228 
  [(parallel [(set (match_operand 0 "" "")
1229 
                   (call (match_operand:QI 1 "memory_operand" "")
1230 
                         (match_operand:SI 2 "const_int_operand" "")))
1231 
              (set (reg:SI VAX_SP_REGNUM)
1232 
                   (plus:SI (reg:SI VAX_SP_REGNUM)
1233 
                            (match_operand:SI 4 "immediate_operand" "")))])]
1234 
  ""
1235 
{
1236 
  gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0);
1237 
 
1238 
  /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1239 
     during EH unwinding.  We must include the argument count pushed by
1240 
     the calls instruction.  */
1241 
  operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
1242 
})
1243 
 
1244 
(define_insn "*call_value_pop"
1245 
  [(set (match_operand 0 "" "")
1246 
        (call (match_operand:QI 1 "memory_operand" "m")
1247 
              (match_operand:SI 2 "const_int_operand" "n")))
1248 
   (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
1249 
                                        (match_operand:SI 3 "immediate_operand" "i")))]
1250 
  ""
1251 
  "*
1252 
{
1253 
  operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
1254 
  return \"calls %2,%1\";
1255 
}")
1256 
 
1257 
(define_expand "call"
1258 
  [(call (match_operand:QI 0 "memory_operand" "")
1259 
      (match_operand:SI 1 "const_int_operand" ""))]
1260 
  ""
1261 
  "
1262 
{
1263 
  /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1264 
     during EH unwinding.  We must include the argument count pushed by
1265 
     the calls instruction.  */
1266 
  operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
1267 
}")
1268 
 
1269 
(define_insn "*call"
1270 
   [(call (match_operand:QI 0 "memory_operand" "m")
1271 
       (match_operand:SI 1 "const_int_operand" ""))]
1272 
  ""
1273 
  "calls $0,%0")
1274 
 
1275 
(define_expand "call_value"
1276 
  [(set (match_operand 0 "" "")
1277 
      (call (match_operand:QI 1 "memory_operand" "")
1278 
            (match_operand:SI 2 "const_int_operand" "")))]
1279 
  ""
1280 
  "
1281 
{
1282 
  /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1283 
     during EH unwinding.  We must include the argument count pushed by
1284 
     the calls instruction.  */
1285 
  operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
1286 
}")
1287 
 
1288 
(define_insn "*call_value"
1289 
  [(set (match_operand 0 "" "")
1290 
        (call (match_operand:QI 1 "memory_operand" "m")
1291 
              (match_operand:SI 2 "const_int_operand" "")))]
1292 
  ""
1293 
  "calls $0,%1")
1294 
 
1295 
;; Call subroutine returning any type.
1296 
 
1297 
(define_expand "untyped_call"
1298 
  [(parallel [(call (match_operand 0 "" "")
1299 
                  (const_int 0))
1300 
            (match_operand 1 "" "")
1301 
            (match_operand 2 "" "")])]
1302 
  ""
1303 
  "
1304 
{
1305 
  int i;
1306 
 
1307 
  emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1308 
 
1309 
  for (i = 0; i < XVECLEN (operands[2], 0); i++)
1310 
    {
1311 
      rtx set = XVECEXP (operands[2], 0, i);
1312 
      emit_move_insn (SET_DEST (set), SET_SRC (set));
1313 
    }
1314 
 
1315 
  /* The optimizer does not know that the call sets the function value
1316 
     registers we stored in the result block.  We avoid problems by
1317 
     claiming that all hard registers are used and clobbered at this
1318 
     point.  */
1319 
  emit_insn (gen_blockage ());
1320 
 
1321 
  DONE;
1322 
}")
1323 
 
1324 
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1325 
;; all of memory.  This blocks insns from being moved across this point.
1326 
 
1327 
(define_insn "blockage"
1328 
  [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
1329 
  ""
1330 
  "")
1331 
 
1332 
(define_insn "return"
1333 
  [(return)]
1334 
  ""
1335 
  "ret")
1336 
 
1337 
(define_expand "epilogue"
1338 
  [(return)]
1339 
  ""
1340 
  "
1341 
{
1342 
  emit_jump_insn (gen_return ());
1343 
  DONE;
1344 
}")
1345 
 
1346 
(define_insn "nop"
1347 
  [(const_int 0)]
1348 
  ""
1349 
  "nop")
1350 
 
1351 
;; This had a wider constraint once, and it had trouble.
1352 
;; If you are tempted to try `g', please don't--it's not worth
1353 
;; the risk we will reopen the same bug.
1354 
(define_insn "indirect_jump"
1355 
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1356 
  ""
1357 
  "jmp (%0)")
1358 
 
1359 
;; This is here to accept 5 arguments (as passed by expand_end_case)
1360 
;; and pass the first 4 along to the casesi1 pattern that really does
1361 
;; the actual casesi work.  We emit a jump here to the default label
1362 
;; _before_ the casesi so that we can be sure that the casesi never
1363 
;; drops through.
1364 
;; This is suboptimal perhaps, but so is much of the rest of this
1365 
;; machine description.  For what it's worth, HPPA uses the same trick.
1366 
;;
1367 
;; operand 0 is index
1368 
;; operand 1 is the minimum bound (a const_int)
1369 
;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
1370 
;; operand 3 is CODE_LABEL for the table;
1371 
;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
1372 
;;
1373 
;; We emit:
1374 
;;      i = index - minimum_bound
1375 
;;      if (i > (maximum_bound - minimum_bound + 1) goto default;
1376 
;;      casesi (i, 0, table);
1377 
;;
1378 
(define_expand "casesi"
1379 
  [(match_operand:SI 0 "general_operand" "")
1380 
   (match_operand:SI 1 "general_operand" "")
1381 
   (match_operand:SI 2 "general_operand" "")
1382 
   (match_operand 3 "" "")
1383 
   (match_operand 4 "" "")]
1384 
  ""
1385 
{
1386 
  /* i = index - minimum_bound;
1387 
     But only if the lower bound is not already zero.  */
1388 
  if (operands[1] != const0_rtx)
1389 
    {
1390 
      rtx index = gen_reg_rtx (SImode);
1391 
      emit_insn (gen_addsi3 (index,
1392 
                             operands[0],
1393 
                             GEN_INT (-INTVAL (operands[1]))));
1394 
      operands[0] = index;
1395 
    }
1396 
 
1397 
  /* if (i > (maximum_bound - minimum_bound + 1) goto default;  */
1398 
  emit_insn (gen_cmpsi (operands[0], operands[2]));
1399 
  emit_jump_insn (gen_bgtu (operands[4]));
1400 
 
1401 
  /* casesi (i, 0, table);  */
1402 
  emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
1403 
  DONE;
1404 
})
1405 
 
1406 
;; This insn is a bit of a lier.  It actually falls through if no case
1407 
;; matches.  But, we prevent that from ever happening by emitting a jump
1408 
;; before this, see the define_expand above.
1409 
(define_insn "casesi1"
1410 
  [(match_operand:SI 1 "const_int_operand" "n")
1411 
   (set (pc)
1412 
        (plus:SI (sign_extend:SI
1413 
                  (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "g")
1414 
                                            (const_int 2))
1415 
                          (pc))))
1416 
                 (label_ref:SI (match_operand 2 "" ""))))]
1417 
  ""
1418 
  "casel %0,$0,%1")
1419 
 
1420 
;;- load or push effective address
1421 
;; These come after the move and add/sub patterns
1422 
;; because we don't want pushl $1 turned into pushad 1.
1423 
;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1424 
 
1425 
;; It does not work to use constraints to distinguish pushes from moves,
1426 
;; because < matches any autodecrement, not just a push.
1427 
 
1428 
(define_insn ""
1429 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1430 
        (match_operand:QI 1 "address_operand" "p"))]
1431 
  ""
1432 
  "*
1433 
{
1434 
  if (push_operand (operands[0], SImode))
1435 
    return \"pushab %a1\";
1436 
  else
1437 
    return \"movab %a1,%0\";
1438 
}")
1439 
 
1440 
(define_insn ""
1441 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1442 
        (match_operand:HI 1 "address_operand" "p"))]
1443 
  ""
1444 
  "*
1445 
{
1446 
  if (push_operand (operands[0], SImode))
1447 
    return \"pushaw %a1\";
1448 
  else
1449 
    return \"movaw %a1,%0\";
1450 
}")
1451 
 
1452 
(define_insn ""
1453 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1454 
        (match_operand:SI 1 "address_operand" "p"))]
1455 
  ""
1456 
  "*
1457 
{
1458 
  if (push_operand (operands[0], SImode))
1459 
    return \"pushal %a1\";
1460 
  else
1461 
    return \"moval %a1,%0\";
1462 
}")
1463 
 
1464 
(define_insn ""
1465 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1466 
        (match_operand:DI 1 "address_operand" "p"))]
1467 
  ""
1468 
  "*
1469 
{
1470 
  if (push_operand (operands[0], SImode))
1471 
    return \"pushaq %a1\";
1472 
  else
1473 
    return \"movaq %a1,%0\";
1474 
}")
1475 
 
1476 
(define_insn ""
1477 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1478 
        (match_operand:SF 1 "address_operand" "p"))]
1479 
  ""
1480 
  "*
1481 
{
1482 
  if (push_operand (operands[0], SImode))
1483 
    return \"pushaf %a1\";
1484 
  else
1485 
    return \"movaf %a1,%0\";
1486 
}")
1487 
 
1488 
(define_insn ""
1489 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1490 
        (match_operand:DF 1 "address_operand" "p"))]
1491 
  ""
1492 
  "*
1493 
{
1494 
  if (push_operand (operands[0], SImode))
1495 
    return \"pushad %a1\";
1496 
  else
1497 
    return \"movad %a1,%0\";
1498 
}")
1499 
 
1500 
;; These used to be peepholes, but it is more straightforward to do them
1501 
;; as single insns.  However, we must force the output to be a register
1502 
;; if it is not an offsettable address so that we know that we can assign
1503 
;; to it twice.
1504 
 
1505 
;; If we had a good way of evaluating the relative costs, these could be
1506 
;; machine-independent.
1507 
 
1508 
;; Optimize   extzv ...,z;    andl2 ...,z
1509 
;; or         ashl ...,z;     andl2 ...,z
1510 
;; with other operands constant.  This is what the combiner converts the
1511 
;; above sequences to before attempting to recognize the new insn.
1512 
 
1513 
(define_insn ""
1514 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1515 
        (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1516 
                             (match_operand:QI 2 "const_int_operand" "n"))
1517 
                (match_operand:SI 3 "const_int_operand" "n")))]
1518 
  "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
1519 
  "*
1520 
{
1521 
  unsigned long mask1 = INTVAL (operands[3]);
1522 
  unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
1523 
 
1524 
  if ((mask1 & mask2) != mask1)
1525 
    operands[3] = GEN_INT (mask1 & mask2);
1526 
 
1527 
  return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
1528 
}")
1529 
 
1530 
;; left-shift and mask
1531 
;; The only case where `ashl' is better is if the mask only turns off
1532 
;; bits that the ashl would anyways, in which case it should have been
1533 
;; optimized away.
1534 
 
1535 
(define_insn ""
1536 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1537 
        (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
1538 
                           (match_operand:QI 2 "const_int_operand" "n"))
1539 
                (match_operand:SI 3 "const_int_operand" "n")))]
1540 
  ""
1541 
  "*
1542 
{
1543 
  operands[3]
1544 
    = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
1545 
  return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
1546 
}")
1547 
 
1548 
;; Instruction sequence to sync the VAX instruction stream.
1549 
(define_insn "sync_istream"
1550 
  [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
1551 
  ""
1552 
  "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")

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