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@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
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@c 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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@c This is part of the GCC manual.
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@c For copying conditions, see the file gcc.texi.
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@ifset INTERNALS
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@node Machine Desc
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@chapter Machine Descriptions
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@cindex machine descriptions
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A machine description has two parts: a file of instruction patterns
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(@file{.md} file) and a C header file of macro definitions.
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The @file{.md} file for a target machine contains a pattern for each
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instruction that the target machine supports (or at least each instruction
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that is worth telling the compiler about). It may also contain comments.
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A semicolon causes the rest of the line to be a comment, unless the semicolon
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is inside a quoted string.
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See the next chapter for information on the C header file.
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@menu
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* Overview:: How the machine description is used.
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* Patterns:: How to write instruction patterns.
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* Example:: An explained example of a @code{define_insn} pattern.
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* RTL Template:: The RTL template defines what insns match a pattern.
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* Output Template:: The output template says how to make assembler code
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from such an insn.
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* Output Statement:: For more generality, write C code to output
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the assembler code.
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* Predicates:: Controlling what kinds of operands can be used
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for an insn.
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* Constraints:: Fine-tuning operand selection.
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* Standard Names:: Names mark patterns to use for code generation.
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* Pattern Ordering:: When the order of patterns makes a difference.
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* Dependent Patterns:: Having one pattern may make you need another.
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* Jump Patterns:: Special considerations for patterns for jump insns.
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* Looping Patterns:: How to define patterns for special looping insns.
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* Insn Canonicalizations::Canonicalization of Instructions
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* Expander Definitions::Generating a sequence of several RTL insns
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for a standard operation.
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* Insn Splitting:: Splitting Instructions into Multiple Instructions.
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* Including Patterns:: Including Patterns in Machine Descriptions.
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* Peephole Definitions::Defining machine-specific peephole optimizations.
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* Insn Attributes:: Specifying the value of attributes for generated insns.
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* Conditional Execution::Generating @code{define_insn} patterns for
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predication.
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* Constant Definitions::Defining symbolic constants that can be used in the
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md file.
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* Macros:: Using macros to generate patterns from a template.
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@end menu
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@node Overview
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@section Overview of How the Machine Description is Used
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There are three main conversions that happen in the compiler:
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@enumerate
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@item
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The front end reads the source code and builds a parse tree.
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@item
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The parse tree is used to generate an RTL insn list based on named
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instruction patterns.
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@item
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The insn list is matched against the RTL templates to produce assembler
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code.
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@end enumerate
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For the generate pass, only the names of the insns matter, from either a
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named @code{define_insn} or a @code{define_expand}. The compiler will
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choose the pattern with the right name and apply the operands according
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to the documentation later in this chapter, without regard for the RTL
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template or operand constraints. Note that the names the compiler looks
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for are hard-coded in the compiler---it will ignore unnamed patterns and
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patterns with names it doesn't know about, but if you don't provide a
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named pattern it needs, it will abort.
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If a @code{define_insn} is used, the template given is inserted into the
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insn list. If a @code{define_expand} is used, one of three things
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happens, based on the condition logic. The condition logic may manually
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create new insns for the insn list, say via @code{emit_insn()}, and
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invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
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compiler to use an alternate way of performing that task. If it invokes
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neither @code{DONE} nor @code{FAIL}, the template given in the pattern
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is inserted, as if the @code{define_expand} were a @code{define_insn}.
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Once the insn list is generated, various optimization passes convert,
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replace, and rearrange the insns in the insn list. This is where the
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@code{define_split} and @code{define_peephole} patterns get used, for
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example.
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Finally, the insn list's RTL is matched up with the RTL templates in the
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@code{define_insn} patterns, and those patterns are used to emit the
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final assembly code. For this purpose, each named @code{define_insn}
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acts like it's unnamed, since the names are ignored.
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@node Patterns
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@section Everything about Instruction Patterns
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@cindex patterns
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@cindex instruction patterns
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@findex define_insn
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Each instruction pattern contains an incomplete RTL expression, with pieces
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to be filled in later, operand constraints that restrict how the pieces can
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be filled in, and an output pattern or C code to generate the assembler
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output, all wrapped up in a @code{define_insn} expression.
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A @code{define_insn} is an RTL expression containing four or five operands:
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@enumerate
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@item
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An optional name. The presence of a name indicate that this instruction
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pattern can perform a certain standard job for the RTL-generation
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pass of the compiler. This pass knows certain names and will use
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the instruction patterns with those names, if the names are defined
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in the machine description.
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The absence of a name is indicated by writing an empty string
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where the name should go. Nameless instruction patterns are never
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used for generating RTL code, but they may permit several simpler insns
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to be combined later on.
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Names that are not thus known and used in RTL-generation have no
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effect; they are equivalent to no name at all.
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For the purpose of debugging the compiler, you may also specify a
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name beginning with the @samp{*} character. Such a name is used only
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for identifying the instruction in RTL dumps; it is entirely equivalent
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to having a nameless pattern for all other purposes.
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@item
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The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
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RTL expressions which show what the instruction should look like. It is
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incomplete because it may contain @code{match_operand},
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@code{match_operator}, and @code{match_dup} expressions that stand for
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operands of the instruction.
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If the vector has only one element, that element is the template for the
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instruction pattern. If the vector has multiple elements, then the
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instruction pattern is a @code{parallel} expression containing the
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elements described.
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@item
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@cindex pattern conditions
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@cindex conditions, in patterns
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A condition. This is a string which contains a C expression that is
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the final test to decide whether an insn body matches this pattern.
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@cindex named patterns and conditions
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For a named pattern, the condition (if present) may not depend on
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the data in the insn being matched, but only the target-machine-type
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flags. The compiler needs to test these conditions during
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initialization in order to learn exactly which named instructions are
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available in a particular run.
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@findex operands
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For nameless patterns, the condition is applied only when matching an
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individual insn, and only after the insn has matched the pattern's
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recognition template. The insn's operands may be found in the vector
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@code{operands}. For an insn where the condition has once matched, it
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can't be used to control register allocation, for example by excluding
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certain hard registers or hard register combinations.
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@item
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The @dfn{output template}: a string that says how to output matching
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insns as assembler code. @samp{%} in this string specifies where
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to substitute the value of an operand. @xref{Output Template}.
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When simple substitution isn't general enough, you can specify a piece
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of C code to compute the output. @xref{Output Statement}.
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@item
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Optionally, a vector containing the values of attributes for insns matching
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this pattern. @xref{Insn Attributes}.
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@end enumerate
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@node Example
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@section Example of @code{define_insn}
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@cindex @code{define_insn} example
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Here is an actual example of an instruction pattern, for the 68000/68020.
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@smallexample
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(define_insn "tstsi"
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[(set (cc0)
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(match_operand:SI 0 "general_operand" "rm"))]
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""
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"*
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@{
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if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
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return \"tstl %0\";
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return \"cmpl #0,%0\";
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@}")
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@end smallexample
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@noindent
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This can also be written using braced strings:
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@smallexample
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(define_insn "tstsi"
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[(set (cc0)
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(match_operand:SI 0 "general_operand" "rm"))]
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""
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@{
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if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
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return "tstl %0";
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return "cmpl #0,%0";
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@})
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@end smallexample
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This is an instruction that sets the condition codes based on the value of
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a general operand. It has no condition, so any insn whose RTL description
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has the form shown may be handled according to this pattern. The name
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@samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
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pass that, when it is necessary to test such a value, an insn to do so
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can be constructed using this pattern.
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The output control string is a piece of C code which chooses which
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output template to return based on the kind of operand and the specific
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type of CPU for which code is being generated.
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@samp{"rm"} is an operand constraint. Its meaning is explained below.
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@node RTL Template
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@section RTL Template
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@cindex RTL insn template
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@cindex generating insns
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@cindex insns, generating
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@cindex recognizing insns
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@cindex insns, recognizing
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The RTL template is used to define which insns match the particular pattern
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and how to find their operands. For named patterns, the RTL template also
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says how to construct an insn from specified operands.
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Construction involves substituting specified operands into a copy of the
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template. Matching involves determining the values that serve as the
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operands in the insn being matched. Both of these activities are
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controlled by special expression types that direct matching and
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substitution of the operands.
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@table @code
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@findex match_operand
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@item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
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This expression is a placeholder for operand number @var{n} of
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the insn. When constructing an insn, operand number @var{n}
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will be substituted at this point. When matching an insn, whatever
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appears at this position in the insn will be taken as operand
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number @var{n}; but it must satisfy @var{predicate} or this instruction
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pattern will not match at all.
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Operand numbers must be chosen consecutively counting from zero in
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each instruction pattern. There may be only one @code{match_operand}
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expression in the pattern for each operand number. Usually operands
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are numbered in the order of appearance in @code{match_operand}
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expressions. In the case of a @code{define_expand}, any operand numbers
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used only in @code{match_dup} expressions have higher values than all
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other operand numbers.
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@var{predicate} is a string that is the name of a function that
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accepts two arguments, an expression and a machine mode.
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@xref{Predicates}. During matching, the function will be called with
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the putative operand as the expression and @var{m} as the mode
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argument (if @var{m} is not specified, @code{VOIDmode} will be used,
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which normally causes @var{predicate} to accept any mode). If it
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returns zero, this instruction pattern fails to match.
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@var{predicate} may be an empty string; then it means no test is to be
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done on the operand, so anything which occurs in this position is
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valid.
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Most of the time, @var{predicate} will reject modes other than @var{m}---but
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not always. For example, the predicate @code{address_operand} uses
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@var{m} as the mode of memory ref that the address should be valid for.
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Many predicates accept @code{const_int} nodes even though their mode is
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@code{VOIDmode}.
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@var{constraint} controls reloading and the choice of the best register
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class to use for a value, as explained later (@pxref{Constraints}).
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If the constraint would be an empty string, it can be omitted.
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People are often unclear on the difference between the constraint and the
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predicate. The predicate helps decide whether a given insn matches the
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pattern. The constraint plays no role in this decision; instead, it
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controls various decisions in the case of an insn which does match.
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@findex match_scratch
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@item (match_scratch:@var{m} @var{n} @var{constraint})
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This expression is also a placeholder for operand number @var{n}
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and indicates that operand must be a @code{scratch} or @code{reg}
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expression.
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When matching patterns, this is equivalent to
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@smallexample
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(match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
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@end smallexample
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but, when generating RTL, it produces a (@code{scratch}:@var{m})
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expression.
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If the last few expressions in a @code{parallel} are @code{clobber}
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expressions whose operands are either a hard register or
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@code{match_scratch}, the combiner can add or delete them when
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necessary. @xref{Side Effects}.
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@findex match_dup
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@item (match_dup @var{n})
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This expression is also a placeholder for operand number @var{n}.
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It is used when the operand needs to appear more than once in the
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insn.
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In construction, @code{match_dup} acts just like @code{match_operand}:
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the operand is substituted into the insn being constructed. But in
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matching, @code{match_dup} behaves differently. It assumes that operand
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number @var{n} has already been determined by a @code{match_operand}
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appearing earlier in the recognition template, and it matches only an
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identical-looking expression.
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Note that @code{match_dup} should not be used to tell the compiler that
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a particular register is being used for two operands (example:
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@code{add} that adds one register to another; the second register is
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both an input operand and the output operand). Use a matching
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constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
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operand is used in two places in the template, such as an instruction
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that computes both a quotient and a remainder, where the opcode takes
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two input operands but the RTL template has to refer to each of those
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twice; once for the quotient pattern and once for the remainder pattern.
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|
|
333 |
|
|
@findex match_operator
|
334 |
|
|
@item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
|
335 |
|
|
This pattern is a kind of placeholder for a variable RTL expression
|
336 |
|
|
code.
|
337 |
|
|
|
338 |
|
|
When constructing an insn, it stands for an RTL expression whose
|
339 |
|
|
expression code is taken from that of operand @var{n}, and whose
|
340 |
|
|
operands are constructed from the patterns @var{operands}.
|
341 |
|
|
|
342 |
|
|
When matching an expression, it matches an expression if the function
|
343 |
|
|
@var{predicate} returns nonzero on that expression @emph{and} the
|
344 |
|
|
patterns @var{operands} match the operands of the expression.
|
345 |
|
|
|
346 |
|
|
Suppose that the function @code{commutative_operator} is defined as
|
347 |
|
|
follows, to match any expression whose operator is one of the
|
348 |
|
|
commutative arithmetic operators of RTL and whose mode is @var{mode}:
|
349 |
|
|
|
350 |
|
|
@smallexample
|
351 |
|
|
int
|
352 |
|
|
commutative_integer_operator (x, mode)
|
353 |
|
|
rtx x;
|
354 |
|
|
enum machine_mode mode;
|
355 |
|
|
@{
|
356 |
|
|
enum rtx_code code = GET_CODE (x);
|
357 |
|
|
if (GET_MODE (x) != mode)
|
358 |
|
|
return 0;
|
359 |
|
|
return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
|
360 |
|
|
|| code == EQ || code == NE);
|
361 |
|
|
@}
|
362 |
|
|
@end smallexample
|
363 |
|
|
|
364 |
|
|
Then the following pattern will match any RTL expression consisting
|
365 |
|
|
of a commutative operator applied to two general operands:
|
366 |
|
|
|
367 |
|
|
@smallexample
|
368 |
|
|
(match_operator:SI 3 "commutative_operator"
|
369 |
|
|
[(match_operand:SI 1 "general_operand" "g")
|
370 |
|
|
(match_operand:SI 2 "general_operand" "g")])
|
371 |
|
|
@end smallexample
|
372 |
|
|
|
373 |
|
|
Here the vector @code{[@var{operands}@dots{}]} contains two patterns
|
374 |
|
|
because the expressions to be matched all contain two operands.
|
375 |
|
|
|
376 |
|
|
When this pattern does match, the two operands of the commutative
|
377 |
|
|
operator are recorded as operands 1 and 2 of the insn. (This is done
|
378 |
|
|
by the two instances of @code{match_operand}.) Operand 3 of the insn
|
379 |
|
|
will be the entire commutative expression: use @code{GET_CODE
|
380 |
|
|
(operands[3])} to see which commutative operator was used.
|
381 |
|
|
|
382 |
|
|
The machine mode @var{m} of @code{match_operator} works like that of
|
383 |
|
|
@code{match_operand}: it is passed as the second argument to the
|
384 |
|
|
predicate function, and that function is solely responsible for
|
385 |
|
|
deciding whether the expression to be matched ``has'' that mode.
|
386 |
|
|
|
387 |
|
|
When constructing an insn, argument 3 of the gen-function will specify
|
388 |
|
|
the operation (i.e.@: the expression code) for the expression to be
|
389 |
|
|
made. It should be an RTL expression, whose expression code is copied
|
390 |
|
|
into a new expression whose operands are arguments 1 and 2 of the
|
391 |
|
|
gen-function. The subexpressions of argument 3 are not used;
|
392 |
|
|
only its expression code matters.
|
393 |
|
|
|
394 |
|
|
When @code{match_operator} is used in a pattern for matching an insn,
|
395 |
|
|
it usually best if the operand number of the @code{match_operator}
|
396 |
|
|
is higher than that of the actual operands of the insn. This improves
|
397 |
|
|
register allocation because the register allocator often looks at
|
398 |
|
|
operands 1 and 2 of insns to see if it can do register tying.
|
399 |
|
|
|
400 |
|
|
There is no way to specify constraints in @code{match_operator}. The
|
401 |
|
|
operand of the insn which corresponds to the @code{match_operator}
|
402 |
|
|
never has any constraints because it is never reloaded as a whole.
|
403 |
|
|
However, if parts of its @var{operands} are matched by
|
404 |
|
|
@code{match_operand} patterns, those parts may have constraints of
|
405 |
|
|
their own.
|
406 |
|
|
|
407 |
|
|
@findex match_op_dup
|
408 |
|
|
@item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
|
409 |
|
|
Like @code{match_dup}, except that it applies to operators instead of
|
410 |
|
|
operands. When constructing an insn, operand number @var{n} will be
|
411 |
|
|
substituted at this point. But in matching, @code{match_op_dup} behaves
|
412 |
|
|
differently. It assumes that operand number @var{n} has already been
|
413 |
|
|
determined by a @code{match_operator} appearing earlier in the
|
414 |
|
|
recognition template, and it matches only an identical-looking
|
415 |
|
|
expression.
|
416 |
|
|
|
417 |
|
|
@findex match_parallel
|
418 |
|
|
@item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
|
419 |
|
|
This pattern is a placeholder for an insn that consists of a
|
420 |
|
|
@code{parallel} expression with a variable number of elements. This
|
421 |
|
|
expression should only appear at the top level of an insn pattern.
|
422 |
|
|
|
423 |
|
|
When constructing an insn, operand number @var{n} will be substituted at
|
424 |
|
|
this point. When matching an insn, it matches if the body of the insn
|
425 |
|
|
is a @code{parallel} expression with at least as many elements as the
|
426 |
|
|
vector of @var{subpat} expressions in the @code{match_parallel}, if each
|
427 |
|
|
@var{subpat} matches the corresponding element of the @code{parallel},
|
428 |
|
|
@emph{and} the function @var{predicate} returns nonzero on the
|
429 |
|
|
@code{parallel} that is the body of the insn. It is the responsibility
|
430 |
|
|
of the predicate to validate elements of the @code{parallel} beyond
|
431 |
|
|
those listed in the @code{match_parallel}.
|
432 |
|
|
|
433 |
|
|
A typical use of @code{match_parallel} is to match load and store
|
434 |
|
|
multiple expressions, which can contain a variable number of elements
|
435 |
|
|
in a @code{parallel}. For example,
|
436 |
|
|
|
437 |
|
|
@smallexample
|
438 |
|
|
(define_insn ""
|
439 |
|
|
[(match_parallel 0 "load_multiple_operation"
|
440 |
|
|
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
|
441 |
|
|
(match_operand:SI 2 "memory_operand" "m"))
|
442 |
|
|
(use (reg:SI 179))
|
443 |
|
|
(clobber (reg:SI 179))])]
|
444 |
|
|
""
|
445 |
|
|
"loadm 0,0,%1,%2")
|
446 |
|
|
@end smallexample
|
447 |
|
|
|
448 |
|
|
This example comes from @file{a29k.md}. The function
|
449 |
|
|
@code{load_multiple_operation} is defined in @file{a29k.c} and checks
|
450 |
|
|
that subsequent elements in the @code{parallel} are the same as the
|
451 |
|
|
@code{set} in the pattern, except that they are referencing subsequent
|
452 |
|
|
registers and memory locations.
|
453 |
|
|
|
454 |
|
|
An insn that matches this pattern might look like:
|
455 |
|
|
|
456 |
|
|
@smallexample
|
457 |
|
|
(parallel
|
458 |
|
|
[(set (reg:SI 20) (mem:SI (reg:SI 100)))
|
459 |
|
|
(use (reg:SI 179))
|
460 |
|
|
(clobber (reg:SI 179))
|
461 |
|
|
(set (reg:SI 21)
|
462 |
|
|
(mem:SI (plus:SI (reg:SI 100)
|
463 |
|
|
(const_int 4))))
|
464 |
|
|
(set (reg:SI 22)
|
465 |
|
|
(mem:SI (plus:SI (reg:SI 100)
|
466 |
|
|
(const_int 8))))])
|
467 |
|
|
@end smallexample
|
468 |
|
|
|
469 |
|
|
@findex match_par_dup
|
470 |
|
|
@item (match_par_dup @var{n} [@var{subpat}@dots{}])
|
471 |
|
|
Like @code{match_op_dup}, but for @code{match_parallel} instead of
|
472 |
|
|
@code{match_operator}.
|
473 |
|
|
|
474 |
|
|
@end table
|
475 |
|
|
|
476 |
|
|
@node Output Template
|
477 |
|
|
@section Output Templates and Operand Substitution
|
478 |
|
|
@cindex output templates
|
479 |
|
|
@cindex operand substitution
|
480 |
|
|
|
481 |
|
|
@cindex @samp{%} in template
|
482 |
|
|
@cindex percent sign
|
483 |
|
|
The @dfn{output template} is a string which specifies how to output the
|
484 |
|
|
assembler code for an instruction pattern. Most of the template is a
|
485 |
|
|
fixed string which is output literally. The character @samp{%} is used
|
486 |
|
|
to specify where to substitute an operand; it can also be used to
|
487 |
|
|
identify places where different variants of the assembler require
|
488 |
|
|
different syntax.
|
489 |
|
|
|
490 |
|
|
In the simplest case, a @samp{%} followed by a digit @var{n} says to output
|
491 |
|
|
operand @var{n} at that point in the string.
|
492 |
|
|
|
493 |
|
|
@samp{%} followed by a letter and a digit says to output an operand in an
|
494 |
|
|
alternate fashion. Four letters have standard, built-in meanings described
|
495 |
|
|
below. The machine description macro @code{PRINT_OPERAND} can define
|
496 |
|
|
additional letters with nonstandard meanings.
|
497 |
|
|
|
498 |
|
|
@samp{%c@var{digit}} can be used to substitute an operand that is a
|
499 |
|
|
constant value without the syntax that normally indicates an immediate
|
500 |
|
|
operand.
|
501 |
|
|
|
502 |
|
|
@samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
|
503 |
|
|
the constant is negated before printing.
|
504 |
|
|
|
505 |
|
|
@samp{%a@var{digit}} can be used to substitute an operand as if it were a
|
506 |
|
|
memory reference, with the actual operand treated as the address. This may
|
507 |
|
|
be useful when outputting a ``load address'' instruction, because often the
|
508 |
|
|
assembler syntax for such an instruction requires you to write the operand
|
509 |
|
|
as if it were a memory reference.
|
510 |
|
|
|
511 |
|
|
@samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
|
512 |
|
|
instruction.
|
513 |
|
|
|
514 |
|
|
@samp{%=} outputs a number which is unique to each instruction in the
|
515 |
|
|
entire compilation. This is useful for making local labels to be
|
516 |
|
|
referred to more than once in a single template that generates multiple
|
517 |
|
|
assembler instructions.
|
518 |
|
|
|
519 |
|
|
@samp{%} followed by a punctuation character specifies a substitution that
|
520 |
|
|
does not use an operand. Only one case is standard: @samp{%%} outputs a
|
521 |
|
|
@samp{%} into the assembler code. Other nonstandard cases can be
|
522 |
|
|
defined in the @code{PRINT_OPERAND} macro. You must also define
|
523 |
|
|
which punctuation characters are valid with the
|
524 |
|
|
@code{PRINT_OPERAND_PUNCT_VALID_P} macro.
|
525 |
|
|
|
526 |
|
|
@cindex \
|
527 |
|
|
@cindex backslash
|
528 |
|
|
The template may generate multiple assembler instructions. Write the text
|
529 |
|
|
for the instructions, with @samp{\;} between them.
|
530 |
|
|
|
531 |
|
|
@cindex matching operands
|
532 |
|
|
When the RTL contains two operands which are required by constraint to match
|
533 |
|
|
each other, the output template must refer only to the lower-numbered operand.
|
534 |
|
|
Matching operands are not always identical, and the rest of the compiler
|
535 |
|
|
arranges to put the proper RTL expression for printing into the lower-numbered
|
536 |
|
|
operand.
|
537 |
|
|
|
538 |
|
|
One use of nonstandard letters or punctuation following @samp{%} is to
|
539 |
|
|
distinguish between different assembler languages for the same machine; for
|
540 |
|
|
example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
|
541 |
|
|
requires periods in most opcode names, while MIT syntax does not. For
|
542 |
|
|
example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
|
543 |
|
|
syntax. The same file of patterns is used for both kinds of output syntax,
|
544 |
|
|
but the character sequence @samp{%.} is used in each place where Motorola
|
545 |
|
|
syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
|
546 |
|
|
defines the sequence to output a period; the macro for MIT syntax defines
|
547 |
|
|
it to do nothing.
|
548 |
|
|
|
549 |
|
|
@cindex @code{#} in template
|
550 |
|
|
As a special case, a template consisting of the single character @code{#}
|
551 |
|
|
instructs the compiler to first split the insn, and then output the
|
552 |
|
|
resulting instructions separately. This helps eliminate redundancy in the
|
553 |
|
|
output templates. If you have a @code{define_insn} that needs to emit
|
554 |
|
|
multiple assembler instructions, and there is an matching @code{define_split}
|
555 |
|
|
already defined, then you can simply use @code{#} as the output template
|
556 |
|
|
instead of writing an output template that emits the multiple assembler
|
557 |
|
|
instructions.
|
558 |
|
|
|
559 |
|
|
If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
|
560 |
|
|
of the form @samp{@{option0|option1|option2@}} in the templates. These
|
561 |
|
|
describe multiple variants of assembler language syntax.
|
562 |
|
|
@xref{Instruction Output}.
|
563 |
|
|
|
564 |
|
|
@node Output Statement
|
565 |
|
|
@section C Statements for Assembler Output
|
566 |
|
|
@cindex output statements
|
567 |
|
|
@cindex C statements for assembler output
|
568 |
|
|
@cindex generating assembler output
|
569 |
|
|
|
570 |
|
|
Often a single fixed template string cannot produce correct and efficient
|
571 |
|
|
assembler code for all the cases that are recognized by a single
|
572 |
|
|
instruction pattern. For example, the opcodes may depend on the kinds of
|
573 |
|
|
operands; or some unfortunate combinations of operands may require extra
|
574 |
|
|
machine instructions.
|
575 |
|
|
|
576 |
|
|
If the output control string starts with a @samp{@@}, then it is actually
|
577 |
|
|
a series of templates, each on a separate line. (Blank lines and
|
578 |
|
|
leading spaces and tabs are ignored.) The templates correspond to the
|
579 |
|
|
pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
|
580 |
|
|
if a target machine has a two-address add instruction @samp{addr} to add
|
581 |
|
|
into a register and another @samp{addm} to add a register to memory, you
|
582 |
|
|
might write this pattern:
|
583 |
|
|
|
584 |
|
|
@smallexample
|
585 |
|
|
(define_insn "addsi3"
|
586 |
|
|
[(set (match_operand:SI 0 "general_operand" "=r,m")
|
587 |
|
|
(plus:SI (match_operand:SI 1 "general_operand" "0,0")
|
588 |
|
|
(match_operand:SI 2 "general_operand" "g,r")))]
|
589 |
|
|
""
|
590 |
|
|
"@@
|
591 |
|
|
addr %2,%0
|
592 |
|
|
addm %2,%0")
|
593 |
|
|
@end smallexample
|
594 |
|
|
|
595 |
|
|
@cindex @code{*} in template
|
596 |
|
|
@cindex asterisk in template
|
597 |
|
|
If the output control string starts with a @samp{*}, then it is not an
|
598 |
|
|
output template but rather a piece of C program that should compute a
|
599 |
|
|
template. It should execute a @code{return} statement to return the
|
600 |
|
|
template-string you want. Most such templates use C string literals, which
|
601 |
|
|
require doublequote characters to delimit them. To include these
|
602 |
|
|
doublequote characters in the string, prefix each one with @samp{\}.
|
603 |
|
|
|
604 |
|
|
If the output control string is written as a brace block instead of a
|
605 |
|
|
double-quoted string, it is automatically assumed to be C code. In that
|
606 |
|
|
case, it is not necessary to put in a leading asterisk, or to escape the
|
607 |
|
|
doublequotes surrounding C string literals.
|
608 |
|
|
|
609 |
|
|
The operands may be found in the array @code{operands}, whose C data type
|
610 |
|
|
is @code{rtx []}.
|
611 |
|
|
|
612 |
|
|
It is very common to select different ways of generating assembler code
|
613 |
|
|
based on whether an immediate operand is within a certain range. Be
|
614 |
|
|
careful when doing this, because the result of @code{INTVAL} is an
|
615 |
|
|
integer on the host machine. If the host machine has more bits in an
|
616 |
|
|
@code{int} than the target machine has in the mode in which the constant
|
617 |
|
|
will be used, then some of the bits you get from @code{INTVAL} will be
|
618 |
|
|
superfluous. For proper results, you must carefully disregard the
|
619 |
|
|
values of those bits.
|
620 |
|
|
|
621 |
|
|
@findex output_asm_insn
|
622 |
|
|
It is possible to output an assembler instruction and then go on to output
|
623 |
|
|
or compute more of them, using the subroutine @code{output_asm_insn}. This
|
624 |
|
|
receives two arguments: a template-string and a vector of operands. The
|
625 |
|
|
vector may be @code{operands}, or it may be another array of @code{rtx}
|
626 |
|
|
that you declare locally and initialize yourself.
|
627 |
|
|
|
628 |
|
|
@findex which_alternative
|
629 |
|
|
When an insn pattern has multiple alternatives in its constraints, often
|
630 |
|
|
the appearance of the assembler code is determined mostly by which alternative
|
631 |
|
|
was matched. When this is so, the C code can test the variable
|
632 |
|
|
@code{which_alternative}, which is the ordinal number of the alternative
|
633 |
|
|
that was actually satisfied (0 for the first, 1 for the second alternative,
|
634 |
|
|
etc.).
|
635 |
|
|
|
636 |
|
|
For example, suppose there are two opcodes for storing zero, @samp{clrreg}
|
637 |
|
|
for registers and @samp{clrmem} for memory locations. Here is how
|
638 |
|
|
a pattern could use @code{which_alternative} to choose between them:
|
639 |
|
|
|
640 |
|
|
@smallexample
|
641 |
|
|
(define_insn ""
|
642 |
|
|
[(set (match_operand:SI 0 "general_operand" "=r,m")
|
643 |
|
|
(const_int 0))]
|
644 |
|
|
""
|
645 |
|
|
@{
|
646 |
|
|
return (which_alternative == 0
|
647 |
|
|
? "clrreg %0" : "clrmem %0");
|
648 |
|
|
@})
|
649 |
|
|
@end smallexample
|
650 |
|
|
|
651 |
|
|
The example above, where the assembler code to generate was
|
652 |
|
|
@emph{solely} determined by the alternative, could also have been specified
|
653 |
|
|
as follows, having the output control string start with a @samp{@@}:
|
654 |
|
|
|
655 |
|
|
@smallexample
|
656 |
|
|
@group
|
657 |
|
|
(define_insn ""
|
658 |
|
|
[(set (match_operand:SI 0 "general_operand" "=r,m")
|
659 |
|
|
(const_int 0))]
|
660 |
|
|
""
|
661 |
|
|
"@@
|
662 |
|
|
clrreg %0
|
663 |
|
|
clrmem %0")
|
664 |
|
|
@end group
|
665 |
|
|
@end smallexample
|
666 |
|
|
|
667 |
|
|
@node Predicates
|
668 |
|
|
@section Predicates
|
669 |
|
|
@cindex predicates
|
670 |
|
|
@cindex operand predicates
|
671 |
|
|
@cindex operator predicates
|
672 |
|
|
|
673 |
|
|
A predicate determines whether a @code{match_operand} or
|
674 |
|
|
@code{match_operator} expression matches, and therefore whether the
|
675 |
|
|
surrounding instruction pattern will be used for that combination of
|
676 |
|
|
operands. GCC has a number of machine-independent predicates, and you
|
677 |
|
|
can define machine-specific predicates as needed. By convention,
|
678 |
|
|
predicates used with @code{match_operand} have names that end in
|
679 |
|
|
@samp{_operand}, and those used with @code{match_operator} have names
|
680 |
|
|
that end in @samp{_operator}.
|
681 |
|
|
|
682 |
|
|
All predicates are Boolean functions (in the mathematical sense) of
|
683 |
|
|
two arguments: the RTL expression that is being considered at that
|
684 |
|
|
position in the instruction pattern, and the machine mode that the
|
685 |
|
|
@code{match_operand} or @code{match_operator} specifies. In this
|
686 |
|
|
section, the first argument is called @var{op} and the second argument
|
687 |
|
|
@var{mode}. Predicates can be called from C as ordinary two-argument
|
688 |
|
|
functions; this can be useful in output templates or other
|
689 |
|
|
machine-specific code.
|
690 |
|
|
|
691 |
|
|
Operand predicates can allow operands that are not actually acceptable
|
692 |
|
|
to the hardware, as long as the constraints give reload the ability to
|
693 |
|
|
fix them up (@pxref{Constraints}). However, GCC will usually generate
|
694 |
|
|
better code if the predicates specify the requirements of the machine
|
695 |
|
|
instructions as closely as possible. Reload cannot fix up operands
|
696 |
|
|
that must be constants (``immediate operands''); you must use a
|
697 |
|
|
predicate that allows only constants, or else enforce the requirement
|
698 |
|
|
in the extra condition.
|
699 |
|
|
|
700 |
|
|
@cindex predicates and machine modes
|
701 |
|
|
@cindex normal predicates
|
702 |
|
|
@cindex special predicates
|
703 |
|
|
Most predicates handle their @var{mode} argument in a uniform manner.
|
704 |
|
|
If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
|
705 |
|
|
any mode. If @var{mode} is anything else, then @var{op} must have the
|
706 |
|
|
same mode, unless @var{op} is a @code{CONST_INT} or integer
|
707 |
|
|
@code{CONST_DOUBLE}. These RTL expressions always have
|
708 |
|
|
@code{VOIDmode}, so it would be counterproductive to check that their
|
709 |
|
|
mode matches. Instead, predicates that accept @code{CONST_INT} and/or
|
710 |
|
|
integer @code{CONST_DOUBLE} check that the value stored in the
|
711 |
|
|
constant will fit in the requested mode.
|
712 |
|
|
|
713 |
|
|
Predicates with this behavior are called @dfn{normal}.
|
714 |
|
|
@command{genrecog} can optimize the instruction recognizer based on
|
715 |
|
|
knowledge of how normal predicates treat modes. It can also diagnose
|
716 |
|
|
certain kinds of common errors in the use of normal predicates; for
|
717 |
|
|
instance, it is almost always an error to use a normal predicate
|
718 |
|
|
without specifying a mode.
|
719 |
|
|
|
720 |
|
|
Predicates that do something different with their @var{mode} argument
|
721 |
|
|
are called @dfn{special}. The generic predicates
|
722 |
|
|
@code{address_operand} and @code{pmode_register_operand} are special
|
723 |
|
|
predicates. @command{genrecog} does not do any optimizations or
|
724 |
|
|
diagnosis when special predicates are used.
|
725 |
|
|
|
726 |
|
|
@menu
|
727 |
|
|
* Machine-Independent Predicates:: Predicates available to all back ends.
|
728 |
|
|
* Defining Predicates:: How to write machine-specific predicate
|
729 |
|
|
functions.
|
730 |
|
|
@end menu
|
731 |
|
|
|
732 |
|
|
@node Machine-Independent Predicates
|
733 |
|
|
@subsection Machine-Independent Predicates
|
734 |
|
|
@cindex machine-independent predicates
|
735 |
|
|
@cindex generic predicates
|
736 |
|
|
|
737 |
|
|
These are the generic predicates available to all back ends. They are
|
738 |
|
|
defined in @file{recog.c}. The first category of predicates allow
|
739 |
|
|
only constant, or @dfn{immediate}, operands.
|
740 |
|
|
|
741 |
|
|
@defun immediate_operand
|
742 |
|
|
This predicate allows any sort of constant that fits in @var{mode}.
|
743 |
|
|
It is an appropriate choice for instructions that take operands that
|
744 |
|
|
must be constant.
|
745 |
|
|
@end defun
|
746 |
|
|
|
747 |
|
|
@defun const_int_operand
|
748 |
|
|
This predicate allows any @code{CONST_INT} expression that fits in
|
749 |
|
|
@var{mode}. It is an appropriate choice for an immediate operand that
|
750 |
|
|
does not allow a symbol or label.
|
751 |
|
|
@end defun
|
752 |
|
|
|
753 |
|
|
@defun const_double_operand
|
754 |
|
|
This predicate accepts any @code{CONST_DOUBLE} expression that has
|
755 |
|
|
exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
|
756 |
|
|
accept @code{CONST_INT}. It is intended for immediate floating point
|
757 |
|
|
constants.
|
758 |
|
|
@end defun
|
759 |
|
|
|
760 |
|
|
@noindent
|
761 |
|
|
The second category of predicates allow only some kind of machine
|
762 |
|
|
register.
|
763 |
|
|
|
764 |
|
|
@defun register_operand
|
765 |
|
|
This predicate allows any @code{REG} or @code{SUBREG} expression that
|
766 |
|
|
is valid for @var{mode}. It is often suitable for arithmetic
|
767 |
|
|
instruction operands on a RISC machine.
|
768 |
|
|
@end defun
|
769 |
|
|
|
770 |
|
|
@defun pmode_register_operand
|
771 |
|
|
This is a slight variant on @code{register_operand} which works around
|
772 |
|
|
a limitation in the machine-description reader.
|
773 |
|
|
|
774 |
|
|
@smallexample
|
775 |
|
|
(match_operand @var{n} "pmode_register_operand" @var{constraint})
|
776 |
|
|
@end smallexample
|
777 |
|
|
|
778 |
|
|
@noindent
|
779 |
|
|
means exactly what
|
780 |
|
|
|
781 |
|
|
@smallexample
|
782 |
|
|
(match_operand:P @var{n} "register_operand" @var{constraint})
|
783 |
|
|
@end smallexample
|
784 |
|
|
|
785 |
|
|
@noindent
|
786 |
|
|
would mean, if the machine-description reader accepted @samp{:P}
|
787 |
|
|
mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
|
788 |
|
|
alias for some other mode, and might vary with machine-specific
|
789 |
|
|
options. @xref{Misc}.
|
790 |
|
|
@end defun
|
791 |
|
|
|
792 |
|
|
@defun scratch_operand
|
793 |
|
|
This predicate allows hard registers and @code{SCRATCH} expressions,
|
794 |
|
|
but not pseudo-registers. It is used internally by @code{match_scratch};
|
795 |
|
|
it should not be used directly.
|
796 |
|
|
@end defun
|
797 |
|
|
|
798 |
|
|
@noindent
|
799 |
|
|
The third category of predicates allow only some kind of memory reference.
|
800 |
|
|
|
801 |
|
|
@defun memory_operand
|
802 |
|
|
This predicate allows any valid reference to a quantity of mode
|
803 |
|
|
@var{mode} in memory, as determined by the weak form of
|
804 |
|
|
@code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
|
805 |
|
|
@end defun
|
806 |
|
|
|
807 |
|
|
@defun address_operand
|
808 |
|
|
This predicate is a little unusual; it allows any operand that is a
|
809 |
|
|
valid expression for the @emph{address} of a quantity of mode
|
810 |
|
|
@var{mode}, again determined by the weak form of
|
811 |
|
|
@code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
|
812 |
|
|
@samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
|
813 |
|
|
@code{memory_operand}, then @var{exp} is acceptable to
|
814 |
|
|
@code{address_operand}. Note that @var{exp} does not necessarily have
|
815 |
|
|
the mode @var{mode}.
|
816 |
|
|
@end defun
|
817 |
|
|
|
818 |
|
|
@defun indirect_operand
|
819 |
|
|
This is a stricter form of @code{memory_operand} which allows only
|
820 |
|
|
memory references with a @code{general_operand} as the address
|
821 |
|
|
expression. New uses of this predicate are discouraged, because
|
822 |
|
|
@code{general_operand} is very permissive, so it's hard to tell what
|
823 |
|
|
an @code{indirect_operand} does or does not allow. If a target has
|
824 |
|
|
different requirements for memory operands for different instructions,
|
825 |
|
|
it is better to define target-specific predicates which enforce the
|
826 |
|
|
hardware's requirements explicitly.
|
827 |
|
|
@end defun
|
828 |
|
|
|
829 |
|
|
@defun push_operand
|
830 |
|
|
This predicate allows a memory reference suitable for pushing a value
|
831 |
|
|
onto the stack. This will be a @code{MEM} which refers to
|
832 |
|
|
@code{stack_pointer_rtx}, with a side-effect in its address expression
|
833 |
|
|
(@pxref{Incdec}); which one is determined by the
|
834 |
|
|
@code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
|
835 |
|
|
@end defun
|
836 |
|
|
|
837 |
|
|
@defun pop_operand
|
838 |
|
|
This predicate allows a memory reference suitable for popping a value
|
839 |
|
|
off the stack. Again, this will be a @code{MEM} referring to
|
840 |
|
|
@code{stack_pointer_rtx}, with a side-effect in its address
|
841 |
|
|
expression. However, this time @code{STACK_POP_CODE} is expected.
|
842 |
|
|
@end defun
|
843 |
|
|
|
844 |
|
|
@noindent
|
845 |
|
|
The fourth category of predicates allow some combination of the above
|
846 |
|
|
operands.
|
847 |
|
|
|
848 |
|
|
@defun nonmemory_operand
|
849 |
|
|
This predicate allows any immediate or register operand valid for @var{mode}.
|
850 |
|
|
@end defun
|
851 |
|
|
|
852 |
|
|
@defun nonimmediate_operand
|
853 |
|
|
This predicate allows any register or memory operand valid for @var{mode}.
|
854 |
|
|
@end defun
|
855 |
|
|
|
856 |
|
|
@defun general_operand
|
857 |
|
|
This predicate allows any immediate, register, or memory operand
|
858 |
|
|
valid for @var{mode}.
|
859 |
|
|
@end defun
|
860 |
|
|
|
861 |
|
|
@noindent
|
862 |
|
|
Finally, there is one generic operator predicate.
|
863 |
|
|
|
864 |
|
|
@defun comparison_operator
|
865 |
|
|
This predicate matches any expression which performs an arithmetic
|
866 |
|
|
comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
|
867 |
|
|
expression code.
|
868 |
|
|
@end defun
|
869 |
|
|
|
870 |
|
|
@node Defining Predicates
|
871 |
|
|
@subsection Defining Machine-Specific Predicates
|
872 |
|
|
@cindex defining predicates
|
873 |
|
|
@findex define_predicate
|
874 |
|
|
@findex define_special_predicate
|
875 |
|
|
|
876 |
|
|
Many machines have requirements for their operands that cannot be
|
877 |
|
|
expressed precisely using the generic predicates. You can define
|
878 |
|
|
additional predicates using @code{define_predicate} and
|
879 |
|
|
@code{define_special_predicate} expressions. These expressions have
|
880 |
|
|
three operands:
|
881 |
|
|
|
882 |
|
|
@itemize @bullet
|
883 |
|
|
@item
|
884 |
|
|
The name of the predicate, as it will be referred to in
|
885 |
|
|
@code{match_operand} or @code{match_operator} expressions.
|
886 |
|
|
|
887 |
|
|
@item
|
888 |
|
|
An RTL expression which evaluates to true if the predicate allows the
|
889 |
|
|
operand @var{op}, false if it does not. This expression can only use
|
890 |
|
|
the following RTL codes:
|
891 |
|
|
|
892 |
|
|
@table @code
|
893 |
|
|
@item MATCH_OPERAND
|
894 |
|
|
When written inside a predicate expression, a @code{MATCH_OPERAND}
|
895 |
|
|
expression evaluates to true if the predicate it names would allow
|
896 |
|
|
@var{op}. The operand number and constraint are ignored. Due to
|
897 |
|
|
limitations in @command{genrecog}, you can only refer to generic
|
898 |
|
|
predicates and predicates that have already been defined.
|
899 |
|
|
|
900 |
|
|
@item MATCH_CODE
|
901 |
|
|
This expression has one operand, a string constant containing a
|
902 |
|
|
comma-separated list of RTX code names (in lower case). It evaluates
|
903 |
|
|
to true if @var{op} has any of the listed codes.
|
904 |
|
|
|
905 |
|
|
@item MATCH_TEST
|
906 |
|
|
This expression has one operand, a string constant containing a C
|
907 |
|
|
expression. The predicate's arguments, @var{op} and @var{mode}, are
|
908 |
|
|
available with those names in the C expression. The @code{MATCH_TEST}
|
909 |
|
|
evaluates to true if the C expression evaluates to a nonzero value.
|
910 |
|
|
@code{MATCH_TEST} expressions must not have side effects.
|
911 |
|
|
|
912 |
|
|
@item AND
|
913 |
|
|
@itemx IOR
|
914 |
|
|
@itemx NOT
|
915 |
|
|
@itemx IF_THEN_ELSE
|
916 |
|
|
The basic @samp{MATCH_} expressions can be combined using these
|
917 |
|
|
logical operators, which have the semantics of the C operators
|
918 |
|
|
@samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively.
|
919 |
|
|
@end table
|
920 |
|
|
|
921 |
|
|
@item
|
922 |
|
|
An optional block of C code, which should execute
|
923 |
|
|
@samp{@w{return true}} if the predicate is found to match and
|
924 |
|
|
@samp{@w{return false}} if it does not. It must not have any side
|
925 |
|
|
effects. The predicate arguments, @var{op} and @var{mode}, are
|
926 |
|
|
available with those names.
|
927 |
|
|
|
928 |
|
|
If a code block is present in a predicate definition, then the RTL
|
929 |
|
|
expression must evaluate to true @emph{and} the code block must
|
930 |
|
|
execute @samp{@w{return true}} for the predicate to allow the operand.
|
931 |
|
|
The RTL expression is evaluated first; do not re-check anything in the
|
932 |
|
|
code block that was checked in the RTL expression.
|
933 |
|
|
@end itemize
|
934 |
|
|
|
935 |
|
|
The program @command{genrecog} scans @code{define_predicate} and
|
936 |
|
|
@code{define_special_predicate} expressions to determine which RTX
|
937 |
|
|
codes are possibly allowed. You should always make this explicit in
|
938 |
|
|
the RTL predicate expression, using @code{MATCH_OPERAND} and
|
939 |
|
|
@code{MATCH_CODE}.
|
940 |
|
|
|
941 |
|
|
Here is an example of a simple predicate definition, from the IA64
|
942 |
|
|
machine description:
|
943 |
|
|
|
944 |
|
|
@smallexample
|
945 |
|
|
@group
|
946 |
|
|
;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
|
947 |
|
|
(define_predicate "small_addr_symbolic_operand"
|
948 |
|
|
(and (match_code "symbol_ref")
|
949 |
|
|
(match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
|
950 |
|
|
@end group
|
951 |
|
|
@end smallexample
|
952 |
|
|
|
953 |
|
|
@noindent
|
954 |
|
|
And here is another, showing the use of the C block.
|
955 |
|
|
|
956 |
|
|
@smallexample
|
957 |
|
|
@group
|
958 |
|
|
;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
|
959 |
|
|
(define_predicate "gr_register_operand"
|
960 |
|
|
(match_operand 0 "register_operand")
|
961 |
|
|
@{
|
962 |
|
|
unsigned int regno;
|
963 |
|
|
if (GET_CODE (op) == SUBREG)
|
964 |
|
|
op = SUBREG_REG (op);
|
965 |
|
|
|
966 |
|
|
regno = REGNO (op);
|
967 |
|
|
return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
|
968 |
|
|
@})
|
969 |
|
|
@end group
|
970 |
|
|
@end smallexample
|
971 |
|
|
|
972 |
|
|
Predicates written with @code{define_predicate} automatically include
|
973 |
|
|
a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
|
974 |
|
|
mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
|
975 |
|
|
@code{CONST_DOUBLE}. They do @emph{not} check specifically for
|
976 |
|
|
integer @code{CONST_DOUBLE}, nor do they test that the value of either
|
977 |
|
|
kind of constant fits in the requested mode. This is because
|
978 |
|
|
target-specific predicates that take constants usually have to do more
|
979 |
|
|
stringent value checks anyway. If you need the exact same treatment
|
980 |
|
|
of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
|
981 |
|
|
provide, use a @code{MATCH_OPERAND} subexpression to call
|
982 |
|
|
@code{const_int_operand}, @code{const_double_operand}, or
|
983 |
|
|
@code{immediate_operand}.
|
984 |
|
|
|
985 |
|
|
Predicates written with @code{define_special_predicate} do not get any
|
986 |
|
|
automatic mode checks, and are treated as having special mode handling
|
987 |
|
|
by @command{genrecog}.
|
988 |
|
|
|
989 |
|
|
The program @command{genpreds} is responsible for generating code to
|
990 |
|
|
test predicates. It also writes a header file containing function
|
991 |
|
|
declarations for all machine-specific predicates. It is not necessary
|
992 |
|
|
to declare these predicates in @file{@var{cpu}-protos.h}.
|
993 |
|
|
@end ifset
|
994 |
|
|
|
995 |
|
|
@c Most of this node appears by itself (in a different place) even
|
996 |
|
|
@c when the INTERNALS flag is clear. Passages that require the internals
|
997 |
|
|
@c manual's context are conditionalized to appear only in the internals manual.
|
998 |
|
|
@ifset INTERNALS
|
999 |
|
|
@node Constraints
|
1000 |
|
|
@section Operand Constraints
|
1001 |
|
|
@cindex operand constraints
|
1002 |
|
|
@cindex constraints
|
1003 |
|
|
|
1004 |
|
|
Each @code{match_operand} in an instruction pattern can specify
|
1005 |
|
|
constraints for the operands allowed. The constraints allow you to
|
1006 |
|
|
fine-tune matching within the set of operands allowed by the
|
1007 |
|
|
predicate.
|
1008 |
|
|
|
1009 |
|
|
@end ifset
|
1010 |
|
|
@ifclear INTERNALS
|
1011 |
|
|
@node Constraints
|
1012 |
|
|
@section Constraints for @code{asm} Operands
|
1013 |
|
|
@cindex operand constraints, @code{asm}
|
1014 |
|
|
@cindex constraints, @code{asm}
|
1015 |
|
|
@cindex @code{asm} constraints
|
1016 |
|
|
|
1017 |
|
|
Here are specific details on what constraint letters you can use with
|
1018 |
|
|
@code{asm} operands.
|
1019 |
|
|
@end ifclear
|
1020 |
|
|
Constraints can say whether
|
1021 |
|
|
an operand may be in a register, and which kinds of register; whether the
|
1022 |
|
|
operand can be a memory reference, and which kinds of address; whether the
|
1023 |
|
|
operand may be an immediate constant, and which possible values it may
|
1024 |
|
|
have. Constraints can also require two operands to match.
|
1025 |
|
|
|
1026 |
|
|
@ifset INTERNALS
|
1027 |
|
|
@menu
|
1028 |
|
|
* Simple Constraints:: Basic use of constraints.
|
1029 |
|
|
* Multi-Alternative:: When an insn has two alternative constraint-patterns.
|
1030 |
|
|
* Class Preferences:: Constraints guide which hard register to put things in.
|
1031 |
|
|
* Modifiers:: More precise control over effects of constraints.
|
1032 |
|
|
* Machine Constraints:: Existing constraints for some particular machines.
|
1033 |
|
|
@end menu
|
1034 |
|
|
@end ifset
|
1035 |
|
|
|
1036 |
|
|
@ifclear INTERNALS
|
1037 |
|
|
@menu
|
1038 |
|
|
* Simple Constraints:: Basic use of constraints.
|
1039 |
|
|
* Multi-Alternative:: When an insn has two alternative constraint-patterns.
|
1040 |
|
|
* Modifiers:: More precise control over effects of constraints.
|
1041 |
|
|
* Machine Constraints:: Special constraints for some particular machines.
|
1042 |
|
|
@end menu
|
1043 |
|
|
@end ifclear
|
1044 |
|
|
|
1045 |
|
|
@node Simple Constraints
|
1046 |
|
|
@subsection Simple Constraints
|
1047 |
|
|
@cindex simple constraints
|
1048 |
|
|
|
1049 |
|
|
The simplest kind of constraint is a string full of letters, each of
|
1050 |
|
|
which describes one kind of operand that is permitted. Here are
|
1051 |
|
|
the letters that are allowed:
|
1052 |
|
|
|
1053 |
|
|
@table @asis
|
1054 |
|
|
@item whitespace
|
1055 |
|
|
Whitespace characters are ignored and can be inserted at any position
|
1056 |
|
|
except the first. This enables each alternative for different operands to
|
1057 |
|
|
be visually aligned in the machine description even if they have different
|
1058 |
|
|
number of constraints and modifiers.
|
1059 |
|
|
|
1060 |
|
|
@cindex @samp{m} in constraint
|
1061 |
|
|
@cindex memory references in constraints
|
1062 |
|
|
@item @samp{m}
|
1063 |
|
|
A memory operand is allowed, with any kind of address that the machine
|
1064 |
|
|
supports in general.
|
1065 |
|
|
|
1066 |
|
|
@cindex offsettable address
|
1067 |
|
|
@cindex @samp{o} in constraint
|
1068 |
|
|
@item @samp{o}
|
1069 |
|
|
A memory operand is allowed, but only if the address is
|
1070 |
|
|
@dfn{offsettable}. This means that adding a small integer (actually,
|
1071 |
|
|
the width in bytes of the operand, as determined by its machine mode)
|
1072 |
|
|
may be added to the address and the result is also a valid memory
|
1073 |
|
|
address.
|
1074 |
|
|
|
1075 |
|
|
@cindex autoincrement/decrement addressing
|
1076 |
|
|
For example, an address which is constant is offsettable; so is an
|
1077 |
|
|
address that is the sum of a register and a constant (as long as a
|
1078 |
|
|
slightly larger constant is also within the range of address-offsets
|
1079 |
|
|
supported by the machine); but an autoincrement or autodecrement
|
1080 |
|
|
address is not offsettable. More complicated indirect/indexed
|
1081 |
|
|
addresses may or may not be offsettable depending on the other
|
1082 |
|
|
addressing modes that the machine supports.
|
1083 |
|
|
|
1084 |
|
|
Note that in an output operand which can be matched by another
|
1085 |
|
|
operand, the constraint letter @samp{o} is valid only when accompanied
|
1086 |
|
|
by both @samp{<} (if the target machine has predecrement addressing)
|
1087 |
|
|
and @samp{>} (if the target machine has preincrement addressing).
|
1088 |
|
|
|
1089 |
|
|
@cindex @samp{V} in constraint
|
1090 |
|
|
@item @samp{V}
|
1091 |
|
|
A memory operand that is not offsettable. In other words, anything that
|
1092 |
|
|
would fit the @samp{m} constraint but not the @samp{o} constraint.
|
1093 |
|
|
|
1094 |
|
|
@cindex @samp{<} in constraint
|
1095 |
|
|
@item @samp{<}
|
1096 |
|
|
A memory operand with autodecrement addressing (either predecrement or
|
1097 |
|
|
postdecrement) is allowed.
|
1098 |
|
|
|
1099 |
|
|
@cindex @samp{>} in constraint
|
1100 |
|
|
@item @samp{>}
|
1101 |
|
|
A memory operand with autoincrement addressing (either preincrement or
|
1102 |
|
|
postincrement) is allowed.
|
1103 |
|
|
|
1104 |
|
|
@cindex @samp{r} in constraint
|
1105 |
|
|
@cindex registers in constraints
|
1106 |
|
|
@item @samp{r}
|
1107 |
|
|
A register operand is allowed provided that it is in a general
|
1108 |
|
|
register.
|
1109 |
|
|
|
1110 |
|
|
@cindex constants in constraints
|
1111 |
|
|
@cindex @samp{i} in constraint
|
1112 |
|
|
@item @samp{i}
|
1113 |
|
|
An immediate integer operand (one with constant value) is allowed.
|
1114 |
|
|
This includes symbolic constants whose values will be known only at
|
1115 |
|
|
assembly time or later.
|
1116 |
|
|
|
1117 |
|
|
@cindex @samp{n} in constraint
|
1118 |
|
|
@item @samp{n}
|
1119 |
|
|
An immediate integer operand with a known numeric value is allowed.
|
1120 |
|
|
Many systems cannot support assembly-time constants for operands less
|
1121 |
|
|
than a word wide. Constraints for these operands should use @samp{n}
|
1122 |
|
|
rather than @samp{i}.
|
1123 |
|
|
|
1124 |
|
|
@cindex @samp{I} in constraint
|
1125 |
|
|
@item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
|
1126 |
|
|
Other letters in the range @samp{I} through @samp{P} may be defined in
|
1127 |
|
|
a machine-dependent fashion to permit immediate integer operands with
|
1128 |
|
|
explicit integer values in specified ranges. For example, on the
|
1129 |
|
|
68000, @samp{I} is defined to stand for the range of values 1 to 8.
|
1130 |
|
|
This is the range permitted as a shift count in the shift
|
1131 |
|
|
instructions.
|
1132 |
|
|
|
1133 |
|
|
@cindex @samp{E} in constraint
|
1134 |
|
|
@item @samp{E}
|
1135 |
|
|
An immediate floating operand (expression code @code{const_double}) is
|
1136 |
|
|
allowed, but only if the target floating point format is the same as
|
1137 |
|
|
that of the host machine (on which the compiler is running).
|
1138 |
|
|
|
1139 |
|
|
@cindex @samp{F} in constraint
|
1140 |
|
|
@item @samp{F}
|
1141 |
|
|
An immediate floating operand (expression code @code{const_double} or
|
1142 |
|
|
@code{const_vector}) is allowed.
|
1143 |
|
|
|
1144 |
|
|
@cindex @samp{G} in constraint
|
1145 |
|
|
@cindex @samp{H} in constraint
|
1146 |
|
|
@item @samp{G}, @samp{H}
|
1147 |
|
|
@samp{G} and @samp{H} may be defined in a machine-dependent fashion to
|
1148 |
|
|
permit immediate floating operands in particular ranges of values.
|
1149 |
|
|
|
1150 |
|
|
@cindex @samp{s} in constraint
|
1151 |
|
|
@item @samp{s}
|
1152 |
|
|
An immediate integer operand whose value is not an explicit integer is
|
1153 |
|
|
allowed.
|
1154 |
|
|
|
1155 |
|
|
This might appear strange; if an insn allows a constant operand with a
|
1156 |
|
|
value not known at compile time, it certainly must allow any known
|
1157 |
|
|
value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
|
1158 |
|
|
better code to be generated.
|
1159 |
|
|
|
1160 |
|
|
For example, on the 68000 in a fullword instruction it is possible to
|
1161 |
|
|
use an immediate operand; but if the immediate value is between @minus{}128
|
1162 |
|
|
and 127, better code results from loading the value into a register and
|
1163 |
|
|
using the register. This is because the load into the register can be
|
1164 |
|
|
done with a @samp{moveq} instruction. We arrange for this to happen
|
1165 |
|
|
by defining the letter @samp{K} to mean ``any integer outside the
|
1166 |
|
|
range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
|
1167 |
|
|
constraints.
|
1168 |
|
|
|
1169 |
|
|
@cindex @samp{g} in constraint
|
1170 |
|
|
@item @samp{g}
|
1171 |
|
|
Any register, memory or immediate integer operand is allowed, except for
|
1172 |
|
|
registers that are not general registers.
|
1173 |
|
|
|
1174 |
|
|
@cindex @samp{X} in constraint
|
1175 |
|
|
@item @samp{X}
|
1176 |
|
|
@ifset INTERNALS
|
1177 |
|
|
Any operand whatsoever is allowed, even if it does not satisfy
|
1178 |
|
|
@code{general_operand}. This is normally used in the constraint of
|
1179 |
|
|
a @code{match_scratch} when certain alternatives will not actually
|
1180 |
|
|
require a scratch register.
|
1181 |
|
|
@end ifset
|
1182 |
|
|
@ifclear INTERNALS
|
1183 |
|
|
Any operand whatsoever is allowed.
|
1184 |
|
|
@end ifclear
|
1185 |
|
|
|
1186 |
|
|
@cindex @samp{0} in constraint
|
1187 |
|
|
@cindex digits in constraint
|
1188 |
|
|
@item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
|
1189 |
|
|
An operand that matches the specified operand number is allowed. If a
|
1190 |
|
|
digit is used together with letters within the same alternative, the
|
1191 |
|
|
digit should come last.
|
1192 |
|
|
|
1193 |
|
|
This number is allowed to be more than a single digit. If multiple
|
1194 |
|
|
digits are encountered consecutively, they are interpreted as a single
|
1195 |
|
|
decimal integer. There is scant chance for ambiguity, since to-date
|
1196 |
|
|
it has never been desirable that @samp{10} be interpreted as matching
|
1197 |
|
|
either operand 1 @emph{or} operand 0. Should this be desired, one
|
1198 |
|
|
can use multiple alternatives instead.
|
1199 |
|
|
|
1200 |
|
|
@cindex matching constraint
|
1201 |
|
|
@cindex constraint, matching
|
1202 |
|
|
This is called a @dfn{matching constraint} and what it really means is
|
1203 |
|
|
that the assembler has only a single operand that fills two roles
|
1204 |
|
|
@ifset INTERNALS
|
1205 |
|
|
considered separate in the RTL insn. For example, an add insn has two
|
1206 |
|
|
input operands and one output operand in the RTL, but on most CISC
|
1207 |
|
|
@end ifset
|
1208 |
|
|
@ifclear INTERNALS
|
1209 |
|
|
which @code{asm} distinguishes. For example, an add instruction uses
|
1210 |
|
|
two input operands and an output operand, but on most CISC
|
1211 |
|
|
@end ifclear
|
1212 |
|
|
machines an add instruction really has only two operands, one of them an
|
1213 |
|
|
input-output operand:
|
1214 |
|
|
|
1215 |
|
|
@smallexample
|
1216 |
|
|
addl #35,r12
|
1217 |
|
|
@end smallexample
|
1218 |
|
|
|
1219 |
|
|
Matching constraints are used in these circumstances.
|
1220 |
|
|
More precisely, the two operands that match must include one input-only
|
1221 |
|
|
operand and one output-only operand. Moreover, the digit must be a
|
1222 |
|
|
smaller number than the number of the operand that uses it in the
|
1223 |
|
|
constraint.
|
1224 |
|
|
|
1225 |
|
|
@ifset INTERNALS
|
1226 |
|
|
For operands to match in a particular case usually means that they
|
1227 |
|
|
are identical-looking RTL expressions. But in a few special cases
|
1228 |
|
|
specific kinds of dissimilarity are allowed. For example, @code{*x}
|
1229 |
|
|
as an input operand will match @code{*x++} as an output operand.
|
1230 |
|
|
For proper results in such cases, the output template should always
|
1231 |
|
|
use the output-operand's number when printing the operand.
|
1232 |
|
|
@end ifset
|
1233 |
|
|
|
1234 |
|
|
@cindex load address instruction
|
1235 |
|
|
@cindex push address instruction
|
1236 |
|
|
@cindex address constraints
|
1237 |
|
|
@cindex @samp{p} in constraint
|
1238 |
|
|
@item @samp{p}
|
1239 |
|
|
An operand that is a valid memory address is allowed. This is
|
1240 |
|
|
for ``load address'' and ``push address'' instructions.
|
1241 |
|
|
|
1242 |
|
|
@findex address_operand
|
1243 |
|
|
@samp{p} in the constraint must be accompanied by @code{address_operand}
|
1244 |
|
|
as the predicate in the @code{match_operand}. This predicate interprets
|
1245 |
|
|
the mode specified in the @code{match_operand} as the mode of the memory
|
1246 |
|
|
reference for which the address would be valid.
|
1247 |
|
|
|
1248 |
|
|
@cindex other register constraints
|
1249 |
|
|
@cindex extensible constraints
|
1250 |
|
|
@item @var{other-letters}
|
1251 |
|
|
Other letters can be defined in machine-dependent fashion to stand for
|
1252 |
|
|
particular classes of registers or other arbitrary operand types.
|
1253 |
|
|
@samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
|
1254 |
|
|
for data, address and floating point registers.
|
1255 |
|
|
|
1256 |
|
|
@ifset INTERNALS
|
1257 |
|
|
The machine description macro @code{REG_CLASS_FROM_LETTER} has first
|
1258 |
|
|
cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
|
1259 |
|
|
then @code{EXTRA_CONSTRAINT} is evaluated.
|
1260 |
|
|
|
1261 |
|
|
A typical use for @code{EXTRA_CONSTRAINT} would be to distinguish certain
|
1262 |
|
|
types of memory references that affect other insn operands.
|
1263 |
|
|
@end ifset
|
1264 |
|
|
@end table
|
1265 |
|
|
|
1266 |
|
|
@ifset INTERNALS
|
1267 |
|
|
In order to have valid assembler code, each operand must satisfy
|
1268 |
|
|
its constraint. But a failure to do so does not prevent the pattern
|
1269 |
|
|
from applying to an insn. Instead, it directs the compiler to modify
|
1270 |
|
|
the code so that the constraint will be satisfied. Usually this is
|
1271 |
|
|
done by copying an operand into a register.
|
1272 |
|
|
|
1273 |
|
|
Contrast, therefore, the two instruction patterns that follow:
|
1274 |
|
|
|
1275 |
|
|
@smallexample
|
1276 |
|
|
(define_insn ""
|
1277 |
|
|
[(set (match_operand:SI 0 "general_operand" "=r")
|
1278 |
|
|
(plus:SI (match_dup 0)
|
1279 |
|
|
(match_operand:SI 1 "general_operand" "r")))]
|
1280 |
|
|
""
|
1281 |
|
|
"@dots{}")
|
1282 |
|
|
@end smallexample
|
1283 |
|
|
|
1284 |
|
|
@noindent
|
1285 |
|
|
which has two operands, one of which must appear in two places, and
|
1286 |
|
|
|
1287 |
|
|
@smallexample
|
1288 |
|
|
(define_insn ""
|
1289 |
|
|
[(set (match_operand:SI 0 "general_operand" "=r")
|
1290 |
|
|
(plus:SI (match_operand:SI 1 "general_operand" "0")
|
1291 |
|
|
(match_operand:SI 2 "general_operand" "r")))]
|
1292 |
|
|
""
|
1293 |
|
|
"@dots{}")
|
1294 |
|
|
@end smallexample
|
1295 |
|
|
|
1296 |
|
|
@noindent
|
1297 |
|
|
which has three operands, two of which are required by a constraint to be
|
1298 |
|
|
identical. If we are considering an insn of the form
|
1299 |
|
|
|
1300 |
|
|
@smallexample
|
1301 |
|
|
(insn @var{n} @var{prev} @var{next}
|
1302 |
|
|
(set (reg:SI 3)
|
1303 |
|
|
(plus:SI (reg:SI 6) (reg:SI 109)))
|
1304 |
|
|
@dots{})
|
1305 |
|
|
@end smallexample
|
1306 |
|
|
|
1307 |
|
|
@noindent
|
1308 |
|
|
the first pattern would not apply at all, because this insn does not
|
1309 |
|
|
contain two identical subexpressions in the right place. The pattern would
|
1310 |
|
|
say, ``That does not look like an add instruction; try other patterns''.
|
1311 |
|
|
The second pattern would say, ``Yes, that's an add instruction, but there
|
1312 |
|
|
is something wrong with it''. It would direct the reload pass of the
|
1313 |
|
|
compiler to generate additional insns to make the constraint true. The
|
1314 |
|
|
results might look like this:
|
1315 |
|
|
|
1316 |
|
|
@smallexample
|
1317 |
|
|
(insn @var{n2} @var{prev} @var{n}
|
1318 |
|
|
(set (reg:SI 3) (reg:SI 6))
|
1319 |
|
|
@dots{})
|
1320 |
|
|
|
1321 |
|
|
(insn @var{n} @var{n2} @var{next}
|
1322 |
|
|
(set (reg:SI 3)
|
1323 |
|
|
(plus:SI (reg:SI 3) (reg:SI 109)))
|
1324 |
|
|
@dots{})
|
1325 |
|
|
@end smallexample
|
1326 |
|
|
|
1327 |
|
|
It is up to you to make sure that each operand, in each pattern, has
|
1328 |
|
|
constraints that can handle any RTL expression that could be present for
|
1329 |
|
|
that operand. (When multiple alternatives are in use, each pattern must,
|
1330 |
|
|
for each possible combination of operand expressions, have at least one
|
1331 |
|
|
alternative which can handle that combination of operands.) The
|
1332 |
|
|
constraints don't need to @emph{allow} any possible operand---when this is
|
1333 |
|
|
the case, they do not constrain---but they must at least point the way to
|
1334 |
|
|
reloading any possible operand so that it will fit.
|
1335 |
|
|
|
1336 |
|
|
@itemize @bullet
|
1337 |
|
|
@item
|
1338 |
|
|
If the constraint accepts whatever operands the predicate permits,
|
1339 |
|
|
there is no problem: reloading is never necessary for this operand.
|
1340 |
|
|
|
1341 |
|
|
For example, an operand whose constraints permit everything except
|
1342 |
|
|
registers is safe provided its predicate rejects registers.
|
1343 |
|
|
|
1344 |
|
|
An operand whose predicate accepts only constant values is safe
|
1345 |
|
|
provided its constraints include the letter @samp{i}. If any possible
|
1346 |
|
|
constant value is accepted, then nothing less than @samp{i} will do;
|
1347 |
|
|
if the predicate is more selective, then the constraints may also be
|
1348 |
|
|
more selective.
|
1349 |
|
|
|
1350 |
|
|
@item
|
1351 |
|
|
Any operand expression can be reloaded by copying it into a register.
|
1352 |
|
|
So if an operand's constraints allow some kind of register, it is
|
1353 |
|
|
certain to be safe. It need not permit all classes of registers; the
|
1354 |
|
|
compiler knows how to copy a register into another register of the
|
1355 |
|
|
proper class in order to make an instruction valid.
|
1356 |
|
|
|
1357 |
|
|
@cindex nonoffsettable memory reference
|
1358 |
|
|
@cindex memory reference, nonoffsettable
|
1359 |
|
|
@item
|
1360 |
|
|
A nonoffsettable memory reference can be reloaded by copying the
|
1361 |
|
|
address into a register. So if the constraint uses the letter
|
1362 |
|
|
@samp{o}, all memory references are taken care of.
|
1363 |
|
|
|
1364 |
|
|
@item
|
1365 |
|
|
A constant operand can be reloaded by allocating space in memory to
|
1366 |
|
|
hold it as preinitialized data. Then the memory reference can be used
|
1367 |
|
|
in place of the constant. So if the constraint uses the letters
|
1368 |
|
|
@samp{o} or @samp{m}, constant operands are not a problem.
|
1369 |
|
|
|
1370 |
|
|
@item
|
1371 |
|
|
If the constraint permits a constant and a pseudo register used in an insn
|
1372 |
|
|
was not allocated to a hard register and is equivalent to a constant,
|
1373 |
|
|
the register will be replaced with the constant. If the predicate does
|
1374 |
|
|
not permit a constant and the insn is re-recognized for some reason, the
|
1375 |
|
|
compiler will crash. Thus the predicate must always recognize any
|
1376 |
|
|
objects allowed by the constraint.
|
1377 |
|
|
@end itemize
|
1378 |
|
|
|
1379 |
|
|
If the operand's predicate can recognize registers, but the constraint does
|
1380 |
|
|
not permit them, it can make the compiler crash. When this operand happens
|
1381 |
|
|
to be a register, the reload pass will be stymied, because it does not know
|
1382 |
|
|
how to copy a register temporarily into memory.
|
1383 |
|
|
|
1384 |
|
|
If the predicate accepts a unary operator, the constraint applies to the
|
1385 |
|
|
operand. For example, the MIPS processor at ISA level 3 supports an
|
1386 |
|
|
instruction which adds two registers in @code{SImode} to produce a
|
1387 |
|
|
@code{DImode} result, but only if the registers are correctly sign
|
1388 |
|
|
extended. This predicate for the input operands accepts a
|
1389 |
|
|
@code{sign_extend} of an @code{SImode} register. Write the constraint
|
1390 |
|
|
to indicate the type of register that is required for the operand of the
|
1391 |
|
|
@code{sign_extend}.
|
1392 |
|
|
@end ifset
|
1393 |
|
|
|
1394 |
|
|
@node Multi-Alternative
|
1395 |
|
|
@subsection Multiple Alternative Constraints
|
1396 |
|
|
@cindex multiple alternative constraints
|
1397 |
|
|
|
1398 |
|
|
Sometimes a single instruction has multiple alternative sets of possible
|
1399 |
|
|
operands. For example, on the 68000, a logical-or instruction can combine
|
1400 |
|
|
register or an immediate value into memory, or it can combine any kind of
|
1401 |
|
|
operand into a register; but it cannot combine one memory location into
|
1402 |
|
|
another.
|
1403 |
|
|
|
1404 |
|
|
These constraints are represented as multiple alternatives. An alternative
|
1405 |
|
|
can be described by a series of letters for each operand. The overall
|
1406 |
|
|
constraint for an operand is made from the letters for this operand
|
1407 |
|
|
from the first alternative, a comma, the letters for this operand from
|
1408 |
|
|
the second alternative, a comma, and so on until the last alternative.
|
1409 |
|
|
@ifset INTERNALS
|
1410 |
|
|
Here is how it is done for fullword logical-or on the 68000:
|
1411 |
|
|
|
1412 |
|
|
@smallexample
|
1413 |
|
|
(define_insn "iorsi3"
|
1414 |
|
|
[(set (match_operand:SI 0 "general_operand" "=m,d")
|
1415 |
|
|
(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
|
1416 |
|
|
(match_operand:SI 2 "general_operand" "dKs,dmKs")))]
|
1417 |
|
|
@dots{})
|
1418 |
|
|
@end smallexample
|
1419 |
|
|
|
1420 |
|
|
The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
|
1421 |
|
|
operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
|
1422 |
|
|
2. The second alternative has @samp{d} (data register) for operand 0,
|
1423 |
|
|
@samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
|
1424 |
|
|
@samp{%} in the constraints apply to all the alternatives; their
|
1425 |
|
|
meaning is explained in the next section (@pxref{Class Preferences}).
|
1426 |
|
|
@end ifset
|
1427 |
|
|
|
1428 |
|
|
@c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
|
1429 |
|
|
If all the operands fit any one alternative, the instruction is valid.
|
1430 |
|
|
Otherwise, for each alternative, the compiler counts how many instructions
|
1431 |
|
|
must be added to copy the operands so that that alternative applies.
|
1432 |
|
|
The alternative requiring the least copying is chosen. If two alternatives
|
1433 |
|
|
need the same amount of copying, the one that comes first is chosen.
|
1434 |
|
|
These choices can be altered with the @samp{?} and @samp{!} characters:
|
1435 |
|
|
|
1436 |
|
|
@table @code
|
1437 |
|
|
@cindex @samp{?} in constraint
|
1438 |
|
|
@cindex question mark
|
1439 |
|
|
@item ?
|
1440 |
|
|
Disparage slightly the alternative that the @samp{?} appears in,
|
1441 |
|
|
as a choice when no alternative applies exactly. The compiler regards
|
1442 |
|
|
this alternative as one unit more costly for each @samp{?} that appears
|
1443 |
|
|
in it.
|
1444 |
|
|
|
1445 |
|
|
@cindex @samp{!} in constraint
|
1446 |
|
|
@cindex exclamation point
|
1447 |
|
|
@item !
|
1448 |
|
|
Disparage severely the alternative that the @samp{!} appears in.
|
1449 |
|
|
This alternative can still be used if it fits without reloading,
|
1450 |
|
|
but if reloading is needed, some other alternative will be used.
|
1451 |
|
|
@end table
|
1452 |
|
|
|
1453 |
|
|
@ifset INTERNALS
|
1454 |
|
|
When an insn pattern has multiple alternatives in its constraints, often
|
1455 |
|
|
the appearance of the assembler code is determined mostly by which
|
1456 |
|
|
alternative was matched. When this is so, the C code for writing the
|
1457 |
|
|
assembler code can use the variable @code{which_alternative}, which is
|
1458 |
|
|
the ordinal number of the alternative that was actually satisfied (0 for
|
1459 |
|
|
the first, 1 for the second alternative, etc.). @xref{Output Statement}.
|
1460 |
|
|
@end ifset
|
1461 |
|
|
|
1462 |
|
|
@ifset INTERNALS
|
1463 |
|
|
@node Class Preferences
|
1464 |
|
|
@subsection Register Class Preferences
|
1465 |
|
|
@cindex class preference constraints
|
1466 |
|
|
@cindex register class preference constraints
|
1467 |
|
|
|
1468 |
|
|
@cindex voting between constraint alternatives
|
1469 |
|
|
The operand constraints have another function: they enable the compiler
|
1470 |
|
|
to decide which kind of hardware register a pseudo register is best
|
1471 |
|
|
allocated to. The compiler examines the constraints that apply to the
|
1472 |
|
|
insns that use the pseudo register, looking for the machine-dependent
|
1473 |
|
|
letters such as @samp{d} and @samp{a} that specify classes of registers.
|
1474 |
|
|
The pseudo register is put in whichever class gets the most ``votes''.
|
1475 |
|
|
The constraint letters @samp{g} and @samp{r} also vote: they vote in
|
1476 |
|
|
favor of a general register. The machine description says which registers
|
1477 |
|
|
are considered general.
|
1478 |
|
|
|
1479 |
|
|
Of course, on some machines all registers are equivalent, and no register
|
1480 |
|
|
classes are defined. Then none of this complexity is relevant.
|
1481 |
|
|
@end ifset
|
1482 |
|
|
|
1483 |
|
|
@node Modifiers
|
1484 |
|
|
@subsection Constraint Modifier Characters
|
1485 |
|
|
@cindex modifiers in constraints
|
1486 |
|
|
@cindex constraint modifier characters
|
1487 |
|
|
|
1488 |
|
|
@c prevent bad page break with this line
|
1489 |
|
|
Here are constraint modifier characters.
|
1490 |
|
|
|
1491 |
|
|
@table @samp
|
1492 |
|
|
@cindex @samp{=} in constraint
|
1493 |
|
|
@item =
|
1494 |
|
|
Means that this operand is write-only for this instruction: the previous
|
1495 |
|
|
value is discarded and replaced by output data.
|
1496 |
|
|
|
1497 |
|
|
@cindex @samp{+} in constraint
|
1498 |
|
|
@item +
|
1499 |
|
|
Means that this operand is both read and written by the instruction.
|
1500 |
|
|
|
1501 |
|
|
When the compiler fixes up the operands to satisfy the constraints,
|
1502 |
|
|
it needs to know which operands are inputs to the instruction and
|
1503 |
|
|
which are outputs from it. @samp{=} identifies an output; @samp{+}
|
1504 |
|
|
identifies an operand that is both input and output; all other operands
|
1505 |
|
|
are assumed to be input only.
|
1506 |
|
|
|
1507 |
|
|
If you specify @samp{=} or @samp{+} in a constraint, you put it in the
|
1508 |
|
|
first character of the constraint string.
|
1509 |
|
|
|
1510 |
|
|
@cindex @samp{&} in constraint
|
1511 |
|
|
@cindex earlyclobber operand
|
1512 |
|
|
@item &
|
1513 |
|
|
Means (in a particular alternative) that this operand is an
|
1514 |
|
|
@dfn{earlyclobber} operand, which is modified before the instruction is
|
1515 |
|
|
finished using the input operands. Therefore, this operand may not lie
|
1516 |
|
|
in a register that is used as an input operand or as part of any memory
|
1517 |
|
|
address.
|
1518 |
|
|
|
1519 |
|
|
@samp{&} applies only to the alternative in which it is written. In
|
1520 |
|
|
constraints with multiple alternatives, sometimes one alternative
|
1521 |
|
|
requires @samp{&} while others do not. See, for example, the
|
1522 |
|
|
@samp{movdf} insn of the 68000.
|
1523 |
|
|
|
1524 |
|
|
An input operand can be tied to an earlyclobber operand if its only
|
1525 |
|
|
use as an input occurs before the early result is written. Adding
|
1526 |
|
|
alternatives of this form often allows GCC to produce better code
|
1527 |
|
|
when only some of the inputs can be affected by the earlyclobber.
|
1528 |
|
|
See, for example, the @samp{mulsi3} insn of the ARM@.
|
1529 |
|
|
|
1530 |
|
|
@samp{&} does not obviate the need to write @samp{=}.
|
1531 |
|
|
|
1532 |
|
|
@cindex @samp{%} in constraint
|
1533 |
|
|
@item %
|
1534 |
|
|
Declares the instruction to be commutative for this operand and the
|
1535 |
|
|
following operand. This means that the compiler may interchange the
|
1536 |
|
|
two operands if that is the cheapest way to make all operands fit the
|
1537 |
|
|
constraints.
|
1538 |
|
|
@ifset INTERNALS
|
1539 |
|
|
This is often used in patterns for addition instructions
|
1540 |
|
|
that really have only two operands: the result must go in one of the
|
1541 |
|
|
arguments. Here for example, is how the 68000 halfword-add
|
1542 |
|
|
instruction is defined:
|
1543 |
|
|
|
1544 |
|
|
@smallexample
|
1545 |
|
|
(define_insn "addhi3"
|
1546 |
|
|
[(set (match_operand:HI 0 "general_operand" "=m,r")
|
1547 |
|
|
(plus:HI (match_operand:HI 1 "general_operand" "%0,0")
|
1548 |
|
|
(match_operand:HI 2 "general_operand" "di,g")))]
|
1549 |
|
|
@dots{})
|
1550 |
|
|
@end smallexample
|
1551 |
|
|
@end ifset
|
1552 |
|
|
GCC can only handle one commutative pair in an asm; if you use more,
|
1553 |
|
|
the compiler may fail. Note that you need not use the modifier if
|
1554 |
|
|
the two alternatives are strictly identical; this would only waste
|
1555 |
|
|
time in the reload pass. The modifier is not operational after
|
1556 |
|
|
register allocation, so the result of @code{define_peephole2}
|
1557 |
|
|
and @code{define_split}s performed after reload cannot rely on
|
1558 |
|
|
@samp{%} to make the intended insn match.
|
1559 |
|
|
|
1560 |
|
|
@cindex @samp{#} in constraint
|
1561 |
|
|
@item #
|
1562 |
|
|
Says that all following characters, up to the next comma, are to be
|
1563 |
|
|
ignored as a constraint. They are significant only for choosing
|
1564 |
|
|
register preferences.
|
1565 |
|
|
|
1566 |
|
|
@cindex @samp{*} in constraint
|
1567 |
|
|
@item *
|
1568 |
|
|
Says that the following character should be ignored when choosing
|
1569 |
|
|
register preferences. @samp{*} has no effect on the meaning of the
|
1570 |
|
|
constraint as a constraint, and no effect on reloading.
|
1571 |
|
|
|
1572 |
|
|
@ifset INTERNALS
|
1573 |
|
|
Here is an example: the 68000 has an instruction to sign-extend a
|
1574 |
|
|
halfword in a data register, and can also sign-extend a value by
|
1575 |
|
|
copying it into an address register. While either kind of register is
|
1576 |
|
|
acceptable, the constraints on an address-register destination are
|
1577 |
|
|
less strict, so it is best if register allocation makes an address
|
1578 |
|
|
register its goal. Therefore, @samp{*} is used so that the @samp{d}
|
1579 |
|
|
constraint letter (for data register) is ignored when computing
|
1580 |
|
|
register preferences.
|
1581 |
|
|
|
1582 |
|
|
@smallexample
|
1583 |
|
|
(define_insn "extendhisi2"
|
1584 |
|
|
[(set (match_operand:SI 0 "general_operand" "=*d,a")
|
1585 |
|
|
(sign_extend:SI
|
1586 |
|
|
(match_operand:HI 1 "general_operand" "0,g")))]
|
1587 |
|
|
@dots{})
|
1588 |
|
|
@end smallexample
|
1589 |
|
|
@end ifset
|
1590 |
|
|
@end table
|
1591 |
|
|
|
1592 |
|
|
@node Machine Constraints
|
1593 |
|
|
@subsection Constraints for Particular Machines
|
1594 |
|
|
@cindex machine specific constraints
|
1595 |
|
|
@cindex constraints, machine specific
|
1596 |
|
|
|
1597 |
|
|
Whenever possible, you should use the general-purpose constraint letters
|
1598 |
|
|
in @code{asm} arguments, since they will convey meaning more readily to
|
1599 |
|
|
people reading your code. Failing that, use the constraint letters
|
1600 |
|
|
that usually have very similar meanings across architectures. The most
|
1601 |
|
|
commonly used constraints are @samp{m} and @samp{r} (for memory and
|
1602 |
|
|
general-purpose registers respectively; @pxref{Simple Constraints}), and
|
1603 |
|
|
@samp{I}, usually the letter indicating the most common
|
1604 |
|
|
immediate-constant format.
|
1605 |
|
|
|
1606 |
|
|
For each machine architecture, the
|
1607 |
|
|
@file{config/@var{machine}/@var{machine}.h} file defines additional
|
1608 |
|
|
constraints. These constraints are used by the compiler itself for
|
1609 |
|
|
instruction generation, as well as for @code{asm} statements; therefore,
|
1610 |
|
|
some of the constraints are not particularly interesting for @code{asm}.
|
1611 |
|
|
The constraints are defined through these macros:
|
1612 |
|
|
|
1613 |
|
|
@table @code
|
1614 |
|
|
@item REG_CLASS_FROM_LETTER
|
1615 |
|
|
Register class constraints (usually lowercase).
|
1616 |
|
|
|
1617 |
|
|
@item CONST_OK_FOR_LETTER_P
|
1618 |
|
|
Immediate constant constraints, for non-floating point constants of
|
1619 |
|
|
word size or smaller precision (usually uppercase).
|
1620 |
|
|
|
1621 |
|
|
@item CONST_DOUBLE_OK_FOR_LETTER_P
|
1622 |
|
|
Immediate constant constraints, for all floating point constants and for
|
1623 |
|
|
constants of greater than word size precision (usually uppercase).
|
1624 |
|
|
|
1625 |
|
|
@item EXTRA_CONSTRAINT
|
1626 |
|
|
Special cases of registers or memory. This macro is not required, and
|
1627 |
|
|
is only defined for some machines.
|
1628 |
|
|
@end table
|
1629 |
|
|
|
1630 |
|
|
Inspecting these macro definitions in the compiler source for your
|
1631 |
|
|
machine is the best way to be certain you have the right constraints.
|
1632 |
|
|
However, here is a summary of the machine-dependent constraints
|
1633 |
|
|
available on some particular machines.
|
1634 |
|
|
|
1635 |
|
|
@table @emph
|
1636 |
|
|
@item ARM family---@file{arm.h}
|
1637 |
|
|
@table @code
|
1638 |
|
|
@item f
|
1639 |
|
|
Floating-point register
|
1640 |
|
|
|
1641 |
|
|
@item w
|
1642 |
|
|
VFP floating-point register
|
1643 |
|
|
|
1644 |
|
|
@item F
|
1645 |
|
|
One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
|
1646 |
|
|
or 10.0
|
1647 |
|
|
|
1648 |
|
|
@item G
|
1649 |
|
|
Floating-point constant that would satisfy the constraint @samp{F} if it
|
1650 |
|
|
were negated
|
1651 |
|
|
|
1652 |
|
|
@item I
|
1653 |
|
|
Integer that is valid as an immediate operand in a data processing
|
1654 |
|
|
instruction. That is, an integer in the range 0 to 255 rotated by a
|
1655 |
|
|
multiple of 2
|
1656 |
|
|
|
1657 |
|
|
@item J
|
1658 |
|
|
Integer in the range @minus{}4095 to 4095
|
1659 |
|
|
|
1660 |
|
|
@item K
|
1661 |
|
|
Integer that satisfies constraint @samp{I} when inverted (ones complement)
|
1662 |
|
|
|
1663 |
|
|
@item L
|
1664 |
|
|
Integer that satisfies constraint @samp{I} when negated (twos complement)
|
1665 |
|
|
|
1666 |
|
|
@item M
|
1667 |
|
|
Integer in the range 0 to 32
|
1668 |
|
|
|
1669 |
|
|
@item Q
|
1670 |
|
|
A memory reference where the exact address is in a single register
|
1671 |
|
|
(`@samp{m}' is preferable for @code{asm} statements)
|
1672 |
|
|
|
1673 |
|
|
@item R
|
1674 |
|
|
An item in the constant pool
|
1675 |
|
|
|
1676 |
|
|
@item S
|
1677 |
|
|
A symbol in the text segment of the current file
|
1678 |
|
|
|
1679 |
|
|
@item Uv
|
1680 |
|
|
A memory reference suitable for VFP load/store insns (reg+constant offset)
|
1681 |
|
|
|
1682 |
|
|
@item Uy
|
1683 |
|
|
A memory reference suitable for iWMMXt load/store instructions.
|
1684 |
|
|
|
1685 |
|
|
@item Uq
|
1686 |
|
|
A memory reference suitable for the ARMv4 ldrsb instruction.
|
1687 |
|
|
@end table
|
1688 |
|
|
|
1689 |
|
|
@item AVR family---@file{avr.h}
|
1690 |
|
|
@table @code
|
1691 |
|
|
@item l
|
1692 |
|
|
Registers from r0 to r15
|
1693 |
|
|
|
1694 |
|
|
@item a
|
1695 |
|
|
Registers from r16 to r23
|
1696 |
|
|
|
1697 |
|
|
@item d
|
1698 |
|
|
Registers from r16 to r31
|
1699 |
|
|
|
1700 |
|
|
@item w
|
1701 |
|
|
Registers from r24 to r31. These registers can be used in @samp{adiw} command
|
1702 |
|
|
|
1703 |
|
|
@item e
|
1704 |
|
|
Pointer register (r26--r31)
|
1705 |
|
|
|
1706 |
|
|
@item b
|
1707 |
|
|
Base pointer register (r28--r31)
|
1708 |
|
|
|
1709 |
|
|
@item q
|
1710 |
|
|
Stack pointer register (SPH:SPL)
|
1711 |
|
|
|
1712 |
|
|
@item t
|
1713 |
|
|
Temporary register r0
|
1714 |
|
|
|
1715 |
|
|
@item x
|
1716 |
|
|
Register pair X (r27:r26)
|
1717 |
|
|
|
1718 |
|
|
@item y
|
1719 |
|
|
Register pair Y (r29:r28)
|
1720 |
|
|
|
1721 |
|
|
@item z
|
1722 |
|
|
Register pair Z (r31:r30)
|
1723 |
|
|
|
1724 |
|
|
@item I
|
1725 |
|
|
Constant greater than @minus{}1, less than 64
|
1726 |
|
|
|
1727 |
|
|
@item J
|
1728 |
|
|
Constant greater than @minus{}64, less than 1
|
1729 |
|
|
|
1730 |
|
|
@item K
|
1731 |
|
|
Constant integer 2
|
1732 |
|
|
|
1733 |
|
|
@item L
|
1734 |
|
|
Constant integer 0
|
1735 |
|
|
|
1736 |
|
|
@item M
|
1737 |
|
|
Constant that fits in 8 bits
|
1738 |
|
|
|
1739 |
|
|
@item N
|
1740 |
|
|
Constant integer @minus{}1
|
1741 |
|
|
|
1742 |
|
|
@item O
|
1743 |
|
|
Constant integer 8, 16, or 24
|
1744 |
|
|
|
1745 |
|
|
@item P
|
1746 |
|
|
Constant integer 1
|
1747 |
|
|
|
1748 |
|
|
@item G
|
1749 |
|
|
A floating point constant 0.0
|
1750 |
|
|
@end table
|
1751 |
|
|
|
1752 |
|
|
@item CRX Architecture---@file{crx.h}
|
1753 |
|
|
@table @code
|
1754 |
|
|
|
1755 |
|
|
@item b
|
1756 |
|
|
Registers from r0 to r14 (registers without stack pointer)
|
1757 |
|
|
|
1758 |
|
|
@item l
|
1759 |
|
|
Register r16 (64-bit accumulator lo register)
|
1760 |
|
|
|
1761 |
|
|
@item h
|
1762 |
|
|
Register r17 (64-bit accumulator hi register)
|
1763 |
|
|
|
1764 |
|
|
@item k
|
1765 |
|
|
Register pair r16-r17. (64-bit accumulator lo-hi pair)
|
1766 |
|
|
|
1767 |
|
|
@item I
|
1768 |
|
|
Constant that fits in 3 bits
|
1769 |
|
|
|
1770 |
|
|
@item J
|
1771 |
|
|
Constant that fits in 4 bits
|
1772 |
|
|
|
1773 |
|
|
@item K
|
1774 |
|
|
Constant that fits in 5 bits
|
1775 |
|
|
|
1776 |
|
|
@item L
|
1777 |
|
|
Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
|
1778 |
|
|
|
1779 |
|
|
@item G
|
1780 |
|
|
Floating point constant that is legal for store immediate
|
1781 |
|
|
@end table
|
1782 |
|
|
|
1783 |
|
|
@item PowerPC and IBM RS6000---@file{rs6000.h}
|
1784 |
|
|
@table @code
|
1785 |
|
|
@item b
|
1786 |
|
|
Address base register
|
1787 |
|
|
|
1788 |
|
|
@item f
|
1789 |
|
|
Floating point register
|
1790 |
|
|
|
1791 |
|
|
@item v
|
1792 |
|
|
Vector register
|
1793 |
|
|
|
1794 |
|
|
@item h
|
1795 |
|
|
@samp{MQ}, @samp{CTR}, or @samp{LINK} register
|
1796 |
|
|
|
1797 |
|
|
@item q
|
1798 |
|
|
@samp{MQ} register
|
1799 |
|
|
|
1800 |
|
|
@item c
|
1801 |
|
|
@samp{CTR} register
|
1802 |
|
|
|
1803 |
|
|
@item l
|
1804 |
|
|
@samp{LINK} register
|
1805 |
|
|
|
1806 |
|
|
@item x
|
1807 |
|
|
@samp{CR} register (condition register) number 0
|
1808 |
|
|
|
1809 |
|
|
@item y
|
1810 |
|
|
@samp{CR} register (condition register)
|
1811 |
|
|
|
1812 |
|
|
@item z
|
1813 |
|
|
@samp{FPMEM} stack memory for FPR-GPR transfers
|
1814 |
|
|
|
1815 |
|
|
@item I
|
1816 |
|
|
Signed 16-bit constant
|
1817 |
|
|
|
1818 |
|
|
@item J
|
1819 |
|
|
Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
|
1820 |
|
|
@code{SImode} constants)
|
1821 |
|
|
|
1822 |
|
|
@item K
|
1823 |
|
|
Unsigned 16-bit constant
|
1824 |
|
|
|
1825 |
|
|
@item L
|
1826 |
|
|
Signed 16-bit constant shifted left 16 bits
|
1827 |
|
|
|
1828 |
|
|
@item M
|
1829 |
|
|
Constant larger than 31
|
1830 |
|
|
|
1831 |
|
|
@item N
|
1832 |
|
|
Exact power of 2
|
1833 |
|
|
|
1834 |
|
|
@item O
|
1835 |
|
|
Zero
|
1836 |
|
|
|
1837 |
|
|
@item P
|
1838 |
|
|
Constant whose negation is a signed 16-bit constant
|
1839 |
|
|
|
1840 |
|
|
@item G
|
1841 |
|
|
Floating point constant that can be loaded into a register with one
|
1842 |
|
|
instruction per word
|
1843 |
|
|
|
1844 |
|
|
@item Q
|
1845 |
|
|
Memory operand that is an offset from a register (@samp{m} is preferable
|
1846 |
|
|
for @code{asm} statements)
|
1847 |
|
|
|
1848 |
|
|
@item R
|
1849 |
|
|
AIX TOC entry
|
1850 |
|
|
|
1851 |
|
|
@item S
|
1852 |
|
|
Constant suitable as a 64-bit mask operand
|
1853 |
|
|
|
1854 |
|
|
@item T
|
1855 |
|
|
Constant suitable as a 32-bit mask operand
|
1856 |
|
|
|
1857 |
|
|
@item U
|
1858 |
|
|
System V Release 4 small data area reference
|
1859 |
|
|
@end table
|
1860 |
|
|
|
1861 |
|
|
@item MorphoTech family---@file{mt.h}
|
1862 |
|
|
@table @code
|
1863 |
|
|
@item I
|
1864 |
|
|
Constant for an arithmetic insn (16-bit signed integer).
|
1865 |
|
|
|
1866 |
|
|
@item J
|
1867 |
|
|
The constant 0.
|
1868 |
|
|
|
1869 |
|
|
@item K
|
1870 |
|
|
Constant for a logical insn (16-bit zero-extended integer).
|
1871 |
|
|
|
1872 |
|
|
@item L
|
1873 |
|
|
A constant that can be loaded with @code{lui} (i.e.@: the bottom 16
|
1874 |
|
|
bits are zero).
|
1875 |
|
|
|
1876 |
|
|
@item M
|
1877 |
|
|
A constant that takes two words to load (i.e.@: not matched by
|
1878 |
|
|
@code{I}, @code{K}, or @code{L}).
|
1879 |
|
|
|
1880 |
|
|
@item N
|
1881 |
|
|
Negative 16-bit constants other than -65536.
|
1882 |
|
|
|
1883 |
|
|
@item O
|
1884 |
|
|
A 15-bit signed integer constant.
|
1885 |
|
|
|
1886 |
|
|
@item P
|
1887 |
|
|
A positive 16-bit constant.
|
1888 |
|
|
@end table
|
1889 |
|
|
|
1890 |
|
|
@item Intel 386---@file{i386.h}
|
1891 |
|
|
@table @code
|
1892 |
|
|
@item q
|
1893 |
|
|
@samp{a}, @code{b}, @code{c}, or @code{d} register for the i386.
|
1894 |
|
|
For x86-64 it is equivalent to @samp{r} class (for 8-bit instructions that
|
1895 |
|
|
do not use upper halves).
|
1896 |
|
|
|
1897 |
|
|
@item Q
|
1898 |
|
|
@samp{a}, @code{b}, @code{c}, or @code{d} register (for 8-bit instructions,
|
1899 |
|
|
that do use upper halves).
|
1900 |
|
|
|
1901 |
|
|
@item R
|
1902 |
|
|
Legacy register---equivalent to @code{r} class in i386 mode.
|
1903 |
|
|
(for non-8-bit registers used together with 8-bit upper halves in a single
|
1904 |
|
|
instruction)
|
1905 |
|
|
|
1906 |
|
|
@item A
|
1907 |
|
|
Specifies the @samp{a} or @samp{d} registers. This is primarily useful
|
1908 |
|
|
for 64-bit integer values (when in 32-bit mode) intended to be returned
|
1909 |
|
|
with the @samp{d} register holding the most significant bits and the
|
1910 |
|
|
@samp{a} register holding the least significant bits.
|
1911 |
|
|
|
1912 |
|
|
@item f
|
1913 |
|
|
Floating point register
|
1914 |
|
|
|
1915 |
|
|
@item t
|
1916 |
|
|
First (top of stack) floating point register
|
1917 |
|
|
|
1918 |
|
|
@item u
|
1919 |
|
|
Second floating point register
|
1920 |
|
|
|
1921 |
|
|
@item a
|
1922 |
|
|
@samp{a} register
|
1923 |
|
|
|
1924 |
|
|
@item b
|
1925 |
|
|
@samp{b} register
|
1926 |
|
|
|
1927 |
|
|
@item c
|
1928 |
|
|
@samp{c} register
|
1929 |
|
|
|
1930 |
|
|
@item C
|
1931 |
|
|
Specifies constant that can be easily constructed in SSE register without
|
1932 |
|
|
loading it from memory.
|
1933 |
|
|
|
1934 |
|
|
@item d
|
1935 |
|
|
@samp{d} register
|
1936 |
|
|
|
1937 |
|
|
@item D
|
1938 |
|
|
@samp{di} register
|
1939 |
|
|
|
1940 |
|
|
@item S
|
1941 |
|
|
@samp{si} register
|
1942 |
|
|
|
1943 |
|
|
@item x
|
1944 |
|
|
@samp{xmm} SSE register
|
1945 |
|
|
|
1946 |
|
|
@item y
|
1947 |
|
|
MMX register
|
1948 |
|
|
|
1949 |
|
|
@item I
|
1950 |
|
|
Constant in range 0 to 31 (for 32-bit shifts)
|
1951 |
|
|
|
1952 |
|
|
@item J
|
1953 |
|
|
Constant in range 0 to 63 (for 64-bit shifts)
|
1954 |
|
|
|
1955 |
|
|
@item K
|
1956 |
|
|
@samp{0xff}
|
1957 |
|
|
|
1958 |
|
|
@item L
|
1959 |
|
|
@samp{0xffff}
|
1960 |
|
|
|
1961 |
|
|
@item M
|
1962 |
|
|
0, 1, 2, or 3 (shifts for @code{lea} instruction)
|
1963 |
|
|
|
1964 |
|
|
@item N
|
1965 |
|
|
Constant in range 0 to 255 (for @code{out} instruction)
|
1966 |
|
|
|
1967 |
|
|
@item Z
|
1968 |
|
|
Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range.
|
1969 |
|
|
(for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
|
1970 |
|
|
|
1971 |
|
|
@item e
|
1972 |
|
|
Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range.
|
1973 |
|
|
(for using immediates in 64-bit x86-64 instructions)
|
1974 |
|
|
|
1975 |
|
|
@item G
|
1976 |
|
|
Standard 80387 floating point constant
|
1977 |
|
|
@end table
|
1978 |
|
|
|
1979 |
|
|
@item Intel IA-64---@file{ia64.h}
|
1980 |
|
|
@table @code
|
1981 |
|
|
@item a
|
1982 |
|
|
General register @code{r0} to @code{r3} for @code{addl} instruction
|
1983 |
|
|
|
1984 |
|
|
@item b
|
1985 |
|
|
Branch register
|
1986 |
|
|
|
1987 |
|
|
@item c
|
1988 |
|
|
Predicate register (@samp{c} as in ``conditional'')
|
1989 |
|
|
|
1990 |
|
|
@item d
|
1991 |
|
|
Application register residing in M-unit
|
1992 |
|
|
|
1993 |
|
|
@item e
|
1994 |
|
|
Application register residing in I-unit
|
1995 |
|
|
|
1996 |
|
|
@item f
|
1997 |
|
|
Floating-point register
|
1998 |
|
|
|
1999 |
|
|
@item m
|
2000 |
|
|
Memory operand.
|
2001 |
|
|
Remember that @samp{m} allows postincrement and postdecrement which
|
2002 |
|
|
require printing with @samp{%Pn} on IA-64.
|
2003 |
|
|
Use @samp{S} to disallow postincrement and postdecrement.
|
2004 |
|
|
|
2005 |
|
|
@item G
|
2006 |
|
|
Floating-point constant 0.0 or 1.0
|
2007 |
|
|
|
2008 |
|
|
@item I
|
2009 |
|
|
14-bit signed integer constant
|
2010 |
|
|
|
2011 |
|
|
@item J
|
2012 |
|
|
22-bit signed integer constant
|
2013 |
|
|
|
2014 |
|
|
@item K
|
2015 |
|
|
8-bit signed integer constant for logical instructions
|
2016 |
|
|
|
2017 |
|
|
@item L
|
2018 |
|
|
8-bit adjusted signed integer constant for compare pseudo-ops
|
2019 |
|
|
|
2020 |
|
|
@item M
|
2021 |
|
|
6-bit unsigned integer constant for shift counts
|
2022 |
|
|
|
2023 |
|
|
@item N
|
2024 |
|
|
9-bit signed integer constant for load and store postincrements
|
2025 |
|
|
|
2026 |
|
|
@item O
|
2027 |
|
|
The constant zero
|
2028 |
|
|
|
2029 |
|
|
@item P
|
2030 |
|
|
|
2031 |
|
|
|
2032 |
|
|
@item Q
|
2033 |
|
|
Non-volatile memory for floating-point loads and stores
|
2034 |
|
|
|
2035 |
|
|
@item R
|
2036 |
|
|
Integer constant in the range 1 to 4 for @code{shladd} instruction
|
2037 |
|
|
|
2038 |
|
|
@item S
|
2039 |
|
|
Memory operand except postincrement and postdecrement
|
2040 |
|
|
@end table
|
2041 |
|
|
|
2042 |
|
|
@item FRV---@file{frv.h}
|
2043 |
|
|
@table @code
|
2044 |
|
|
@item a
|
2045 |
|
|
Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
|
2046 |
|
|
|
2047 |
|
|
@item b
|
2048 |
|
|
Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
|
2049 |
|
|
|
2050 |
|
|
@item c
|
2051 |
|
|
Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
|
2052 |
|
|
@code{icc0} to @code{icc3}).
|
2053 |
|
|
|
2054 |
|
|
@item d
|
2055 |
|
|
Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
|
2056 |
|
|
|
2057 |
|
|
@item e
|
2058 |
|
|
Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
|
2059 |
|
|
Odd registers are excluded not in the class but through the use of a machine
|
2060 |
|
|
mode larger than 4 bytes.
|
2061 |
|
|
|
2062 |
|
|
@item f
|
2063 |
|
|
Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
|
2064 |
|
|
|
2065 |
|
|
@item h
|
2066 |
|
|
Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
|
2067 |
|
|
Odd registers are excluded not in the class but through the use of a machine
|
2068 |
|
|
mode larger than 4 bytes.
|
2069 |
|
|
|
2070 |
|
|
@item l
|
2071 |
|
|
Register in the class @code{LR_REG} (the @code{lr} register).
|
2072 |
|
|
|
2073 |
|
|
@item q
|
2074 |
|
|
Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
|
2075 |
|
|
Register numbers not divisible by 4 are excluded not in the class but through
|
2076 |
|
|
the use of a machine mode larger than 8 bytes.
|
2077 |
|
|
|
2078 |
|
|
@item t
|
2079 |
|
|
Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
|
2080 |
|
|
|
2081 |
|
|
@item u
|
2082 |
|
|
Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
|
2083 |
|
|
|
2084 |
|
|
@item v
|
2085 |
|
|
Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
|
2086 |
|
|
|
2087 |
|
|
@item w
|
2088 |
|
|
Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
|
2089 |
|
|
|
2090 |
|
|
@item x
|
2091 |
|
|
Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
|
2092 |
|
|
Register numbers not divisible by 4 are excluded not in the class but through
|
2093 |
|
|
the use of a machine mode larger than 8 bytes.
|
2094 |
|
|
|
2095 |
|
|
@item z
|
2096 |
|
|
Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
|
2097 |
|
|
|
2098 |
|
|
@item A
|
2099 |
|
|
Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
|
2100 |
|
|
|
2101 |
|
|
@item B
|
2102 |
|
|
Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
|
2103 |
|
|
|
2104 |
|
|
@item C
|
2105 |
|
|
Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
|
2106 |
|
|
|
2107 |
|
|
@item G
|
2108 |
|
|
Floating point constant zero
|
2109 |
|
|
|
2110 |
|
|
@item I
|
2111 |
|
|
6-bit signed integer constant
|
2112 |
|
|
|
2113 |
|
|
@item J
|
2114 |
|
|
10-bit signed integer constant
|
2115 |
|
|
|
2116 |
|
|
@item L
|
2117 |
|
|
16-bit signed integer constant
|
2118 |
|
|
|
2119 |
|
|
@item M
|
2120 |
|
|
16-bit unsigned integer constant
|
2121 |
|
|
|
2122 |
|
|
@item N
|
2123 |
|
|
12-bit signed integer constant that is negative---i.e.@: in the
|
2124 |
|
|
range of @minus{}2048 to @minus{}1
|
2125 |
|
|
|
2126 |
|
|
@item O
|
2127 |
|
|
Constant zero
|
2128 |
|
|
|
2129 |
|
|
@item P
|
2130 |
|
|
12-bit signed integer constant that is greater than zero---i.e.@: in the
|
2131 |
|
|
range of 1 to 2047.
|
2132 |
|
|
|
2133 |
|
|
@end table
|
2134 |
|
|
|
2135 |
|
|
@item Blackfin family---@file{bfin.h}
|
2136 |
|
|
@table @code
|
2137 |
|
|
@item a
|
2138 |
|
|
P register
|
2139 |
|
|
|
2140 |
|
|
@item d
|
2141 |
|
|
D register
|
2142 |
|
|
|
2143 |
|
|
@item z
|
2144 |
|
|
A call clobbered P register.
|
2145 |
|
|
|
2146 |
|
|
@item D
|
2147 |
|
|
Even-numbered D register
|
2148 |
|
|
|
2149 |
|
|
@item W
|
2150 |
|
|
Odd-numbered D register
|
2151 |
|
|
|
2152 |
|
|
@item e
|
2153 |
|
|
Accumulator register.
|
2154 |
|
|
|
2155 |
|
|
@item A
|
2156 |
|
|
Even-numbered accumulator register.
|
2157 |
|
|
|
2158 |
|
|
@item B
|
2159 |
|
|
Odd-numbered accumulator register.
|
2160 |
|
|
|
2161 |
|
|
@item b
|
2162 |
|
|
I register
|
2163 |
|
|
|
2164 |
|
|
@item B
|
2165 |
|
|
B register
|
2166 |
|
|
|
2167 |
|
|
@item f
|
2168 |
|
|
M register
|
2169 |
|
|
|
2170 |
|
|
@item c
|
2171 |
|
|
Registers used for circular buffering, i.e. I, B, or L registers.
|
2172 |
|
|
|
2173 |
|
|
@item C
|
2174 |
|
|
The CC register.
|
2175 |
|
|
|
2176 |
|
|
@item x
|
2177 |
|
|
Any D, P, B, M, I or L register.
|
2178 |
|
|
|
2179 |
|
|
@item y
|
2180 |
|
|
Additional registers typically used only in prologues and epilogues: RETS,
|
2181 |
|
|
RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
|
2182 |
|
|
|
2183 |
|
|
@item w
|
2184 |
|
|
Any register except accumulators or CC.
|
2185 |
|
|
|
2186 |
|
|
@item Ksh
|
2187 |
|
|
Signed 16 bit integer (in the range -32768 to 32767)
|
2188 |
|
|
|
2189 |
|
|
@item Kuh
|
2190 |
|
|
Unsigned 16 bit integer (in the range 0 to 65535)
|
2191 |
|
|
|
2192 |
|
|
@item Ks7
|
2193 |
|
|
Signed 7 bit integer (in the range -64 to 63)
|
2194 |
|
|
|
2195 |
|
|
@item Ku7
|
2196 |
|
|
Unsigned 7 bit integer (in the range 0 to 127)
|
2197 |
|
|
|
2198 |
|
|
@item Ku5
|
2199 |
|
|
Unsigned 5 bit integer (in the range 0 to 31)
|
2200 |
|
|
|
2201 |
|
|
@item Ks4
|
2202 |
|
|
Signed 4 bit integer (in the range -8 to 7)
|
2203 |
|
|
|
2204 |
|
|
@item Ks3
|
2205 |
|
|
Signed 3 bit integer (in the range -3 to 4)
|
2206 |
|
|
|
2207 |
|
|
@item Ku3
|
2208 |
|
|
Unsigned 3 bit integer (in the range 0 to 7)
|
2209 |
|
|
|
2210 |
|
|
@item P@var{n}
|
2211 |
|
|
Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
|
2212 |
|
|
|
2213 |
|
|
@item M1
|
2214 |
|
|
Constant 255.
|
2215 |
|
|
|
2216 |
|
|
@item M2
|
2217 |
|
|
Constant 65535.
|
2218 |
|
|
|
2219 |
|
|
@item J
|
2220 |
|
|
An integer constant with exactly a single bit set.
|
2221 |
|
|
|
2222 |
|
|
@item L
|
2223 |
|
|
An integer constant with all bits set except exactly one.
|
2224 |
|
|
|
2225 |
|
|
@item H
|
2226 |
|
|
|
2227 |
|
|
@item Q
|
2228 |
|
|
Any SYMBOL_REF.
|
2229 |
|
|
@end table
|
2230 |
|
|
|
2231 |
|
|
@item M32C---@file{m32c.c}
|
2232 |
|
|
|
2233 |
|
|
@item Rsp
|
2234 |
|
|
@itemx Rfb
|
2235 |
|
|
@itemx Rsb
|
2236 |
|
|
@samp{$sp}, @samp{$fb}, @samp{$sb}.
|
2237 |
|
|
|
2238 |
|
|
@item Rcr
|
2239 |
|
|
Any control register, when they're 16 bits wide (nothing if control
|
2240 |
|
|
registers are 24 bits wide)
|
2241 |
|
|
|
2242 |
|
|
@item Rcl
|
2243 |
|
|
Any control register, when they're 24 bits wide.
|
2244 |
|
|
|
2245 |
|
|
@item R0w
|
2246 |
|
|
@itemx R1w
|
2247 |
|
|
@itemx R2w
|
2248 |
|
|
@itemx R3w
|
2249 |
|
|
$r0, $r1, $r2, $r3.
|
2250 |
|
|
|
2251 |
|
|
@item R02
|
2252 |
|
|
$r0 or $r2, or $r2r0 for 32 bit values.
|
2253 |
|
|
|
2254 |
|
|
@item R13
|
2255 |
|
|
$r1 or $r3, or $r3r1 for 32 bit values.
|
2256 |
|
|
|
2257 |
|
|
@item Rdi
|
2258 |
|
|
A register that can hold a 64 bit value.
|
2259 |
|
|
|
2260 |
|
|
@item Rhl
|
2261 |
|
|
$r0 or $r1 (registers with addressable high/low bytes)
|
2262 |
|
|
|
2263 |
|
|
@item R23
|
2264 |
|
|
$r2 or $r3
|
2265 |
|
|
|
2266 |
|
|
@item Raa
|
2267 |
|
|
Address registers
|
2268 |
|
|
|
2269 |
|
|
@item Raw
|
2270 |
|
|
Address registers when they're 16 bits wide.
|
2271 |
|
|
|
2272 |
|
|
@item Ral
|
2273 |
|
|
Address registers when they're 24 bits wide.
|
2274 |
|
|
|
2275 |
|
|
@item Rqi
|
2276 |
|
|
Registers that can hold QI values.
|
2277 |
|
|
|
2278 |
|
|
@item Rad
|
2279 |
|
|
Registers that can be used with displacements ($a0, $a1, $sb).
|
2280 |
|
|
|
2281 |
|
|
@item Rsi
|
2282 |
|
|
Registers that can hold 32 bit values.
|
2283 |
|
|
|
2284 |
|
|
@item Rhi
|
2285 |
|
|
Registers that can hold 16 bit values.
|
2286 |
|
|
|
2287 |
|
|
@item Rhc
|
2288 |
|
|
Registers chat can hold 16 bit values, including all control
|
2289 |
|
|
registers.
|
2290 |
|
|
|
2291 |
|
|
@item Rra
|
2292 |
|
|
$r0 through R1, plus $a0 and $a1.
|
2293 |
|
|
|
2294 |
|
|
@item Rfl
|
2295 |
|
|
The flags register.
|
2296 |
|
|
|
2297 |
|
|
@item Rmm
|
2298 |
|
|
The memory-based pseudo-registers $mem0 through $mem15.
|
2299 |
|
|
|
2300 |
|
|
@item Rpi
|
2301 |
|
|
Registers that can hold pointers (16 bit registers for r8c, m16c; 24
|
2302 |
|
|
bit registers for m32cm, m32c).
|
2303 |
|
|
|
2304 |
|
|
@item Rpa
|
2305 |
|
|
Matches multiple registers in a PARALLEL to form a larger register.
|
2306 |
|
|
Used to match function return values.
|
2307 |
|
|
|
2308 |
|
|
@item Is3
|
2309 |
|
|
-8 @dots{} 7
|
2310 |
|
|
|
2311 |
|
|
@item IS1
|
2312 |
|
|
-128 @dots{} 127
|
2313 |
|
|
|
2314 |
|
|
@item IS2
|
2315 |
|
|
-32768 @dots{} 32767
|
2316 |
|
|
|
2317 |
|
|
@item IU2
|
2318 |
|
|
|
2319 |
|
|
|
2320 |
|
|
@item In4
|
2321 |
|
|
-8 @dots{} -1 or 1 @dots{} 8
|
2322 |
|
|
|
2323 |
|
|
@item In5
|
2324 |
|
|
-16 @dots{} -1 or 1 @dots{} 16
|
2325 |
|
|
|
2326 |
|
|
@item In4
|
2327 |
|
|
-8 @dots{} -1 or 1 @dots{} 8
|
2328 |
|
|
|
2329 |
|
|
@item IM2
|
2330 |
|
|
-65536 @dots{} -1
|
2331 |
|
|
|
2332 |
|
|
@item Ilb
|
2333 |
|
|
An 8 bit value with exactly one bit set.
|
2334 |
|
|
|
2335 |
|
|
@item Ilw
|
2336 |
|
|
A 16 bit value with exactly one bit set.
|
2337 |
|
|
|
2338 |
|
|
@item Sd
|
2339 |
|
|
The common src/dest memory addressing modes.
|
2340 |
|
|
|
2341 |
|
|
@item Sa
|
2342 |
|
|
Memory addressed using $a0 or $a1.
|
2343 |
|
|
|
2344 |
|
|
@item Si
|
2345 |
|
|
Memory addressed with immediate addresses.
|
2346 |
|
|
|
2347 |
|
|
@item Ss
|
2348 |
|
|
Memory addressed using the stack pointer ($sp).
|
2349 |
|
|
|
2350 |
|
|
@item Sf
|
2351 |
|
|
Memory addressed using the frame base register ($fb).
|
2352 |
|
|
|
2353 |
|
|
@item Ss
|
2354 |
|
|
Memory addressed using the small base register ($sb).
|
2355 |
|
|
|
2356 |
|
|
@item S1
|
2357 |
|
|
$r1h
|
2358 |
|
|
|
2359 |
|
|
|
2360 |
|
|
@item MIPS---@file{mips.h}
|
2361 |
|
|
@table @code
|
2362 |
|
|
@item d
|
2363 |
|
|
General-purpose integer register
|
2364 |
|
|
|
2365 |
|
|
@item f
|
2366 |
|
|
Floating-point register (if available)
|
2367 |
|
|
|
2368 |
|
|
@item h
|
2369 |
|
|
@samp{Hi} register
|
2370 |
|
|
|
2371 |
|
|
@item l
|
2372 |
|
|
@samp{Lo} register
|
2373 |
|
|
|
2374 |
|
|
@item x
|
2375 |
|
|
@samp{Hi} or @samp{Lo} register
|
2376 |
|
|
|
2377 |
|
|
@item y
|
2378 |
|
|
General-purpose integer register
|
2379 |
|
|
|
2380 |
|
|
@item z
|
2381 |
|
|
Floating-point status register
|
2382 |
|
|
|
2383 |
|
|
@item I
|
2384 |
|
|
Signed 16-bit constant (for arithmetic instructions)
|
2385 |
|
|
|
2386 |
|
|
@item J
|
2387 |
|
|
Zero
|
2388 |
|
|
|
2389 |
|
|
@item K
|
2390 |
|
|
Zero-extended 16-bit constant (for logic instructions)
|
2391 |
|
|
|
2392 |
|
|
@item L
|
2393 |
|
|
Constant with low 16 bits zero (can be loaded with @code{lui})
|
2394 |
|
|
|
2395 |
|
|
@item M
|
2396 |
|
|
32-bit constant which requires two instructions to load (a constant
|
2397 |
|
|
which is not @samp{I}, @samp{K}, or @samp{L})
|
2398 |
|
|
|
2399 |
|
|
@item N
|
2400 |
|
|
Negative 16-bit constant
|
2401 |
|
|
|
2402 |
|
|
@item O
|
2403 |
|
|
Exact power of two
|
2404 |
|
|
|
2405 |
|
|
@item P
|
2406 |
|
|
Positive 16-bit constant
|
2407 |
|
|
|
2408 |
|
|
@item G
|
2409 |
|
|
Floating point zero
|
2410 |
|
|
|
2411 |
|
|
@item Q
|
2412 |
|
|
Memory reference that can be loaded with more than one instruction
|
2413 |
|
|
(@samp{m} is preferable for @code{asm} statements)
|
2414 |
|
|
|
2415 |
|
|
@item R
|
2416 |
|
|
Memory reference that can be loaded with one instruction
|
2417 |
|
|
(@samp{m} is preferable for @code{asm} statements)
|
2418 |
|
|
|
2419 |
|
|
@item S
|
2420 |
|
|
Memory reference in external OSF/rose PIC format
|
2421 |
|
|
(@samp{m} is preferable for @code{asm} statements)
|
2422 |
|
|
@end table
|
2423 |
|
|
|
2424 |
|
|
@item Motorola 680x0---@file{m68k.h}
|
2425 |
|
|
@table @code
|
2426 |
|
|
@item a
|
2427 |
|
|
Address register
|
2428 |
|
|
|
2429 |
|
|
@item d
|
2430 |
|
|
Data register
|
2431 |
|
|
|
2432 |
|
|
@item f
|
2433 |
|
|
68881 floating-point register, if available
|
2434 |
|
|
|
2435 |
|
|
@item I
|
2436 |
|
|
Integer in the range 1 to 8
|
2437 |
|
|
|
2438 |
|
|
@item J
|
2439 |
|
|
16-bit signed number
|
2440 |
|
|
|
2441 |
|
|
@item K
|
2442 |
|
|
Signed number whose magnitude is greater than 0x80
|
2443 |
|
|
|
2444 |
|
|
@item L
|
2445 |
|
|
Integer in the range @minus{}8 to @minus{}1
|
2446 |
|
|
|
2447 |
|
|
@item M
|
2448 |
|
|
Signed number whose magnitude is greater than 0x100
|
2449 |
|
|
|
2450 |
|
|
@item G
|
2451 |
|
|
Floating point constant that is not a 68881 constant
|
2452 |
|
|
@end table
|
2453 |
|
|
|
2454 |
|
|
@item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
|
2455 |
|
|
@table @code
|
2456 |
|
|
@item a
|
2457 |
|
|
Register `a'
|
2458 |
|
|
|
2459 |
|
|
@item b
|
2460 |
|
|
Register `b'
|
2461 |
|
|
|
2462 |
|
|
@item d
|
2463 |
|
|
Register `d'
|
2464 |
|
|
|
2465 |
|
|
@item q
|
2466 |
|
|
An 8-bit register
|
2467 |
|
|
|
2468 |
|
|
@item t
|
2469 |
|
|
Temporary soft register _.tmp
|
2470 |
|
|
|
2471 |
|
|
@item u
|
2472 |
|
|
A soft register _.d1 to _.d31
|
2473 |
|
|
|
2474 |
|
|
@item w
|
2475 |
|
|
Stack pointer register
|
2476 |
|
|
|
2477 |
|
|
@item x
|
2478 |
|
|
Register `x'
|
2479 |
|
|
|
2480 |
|
|
@item y
|
2481 |
|
|
Register `y'
|
2482 |
|
|
|
2483 |
|
|
@item z
|
2484 |
|
|
Pseudo register `z' (replaced by `x' or `y' at the end)
|
2485 |
|
|
|
2486 |
|
|
@item A
|
2487 |
|
|
An address register: x, y or z
|
2488 |
|
|
|
2489 |
|
|
@item B
|
2490 |
|
|
An address register: x or y
|
2491 |
|
|
|
2492 |
|
|
@item D
|
2493 |
|
|
Register pair (x:d) to form a 32-bit value
|
2494 |
|
|
|
2495 |
|
|
@item L
|
2496 |
|
|
Constants in the range @minus{}65536 to 65535
|
2497 |
|
|
|
2498 |
|
|
@item M
|
2499 |
|
|
Constants whose 16-bit low part is zero
|
2500 |
|
|
|
2501 |
|
|
@item N
|
2502 |
|
|
Constant integer 1 or @minus{}1
|
2503 |
|
|
|
2504 |
|
|
@item O
|
2505 |
|
|
Constant integer 16
|
2506 |
|
|
|
2507 |
|
|
@item P
|
2508 |
|
|
Constants in the range @minus{}8 to 2
|
2509 |
|
|
|
2510 |
|
|
@end table
|
2511 |
|
|
|
2512 |
|
|
@need 1000
|
2513 |
|
|
@item SPARC---@file{sparc.h}
|
2514 |
|
|
@table @code
|
2515 |
|
|
@item f
|
2516 |
|
|
Floating-point register on the SPARC-V8 architecture and
|
2517 |
|
|
lower floating-point register on the SPARC-V9 architecture.
|
2518 |
|
|
|
2519 |
|
|
@item e
|
2520 |
|
|
Floating-point register. It is equivalent to @samp{f} on the
|
2521 |
|
|
SPARC-V8 architecture and contains both lower and upper
|
2522 |
|
|
floating-point registers on the SPARC-V9 architecture.
|
2523 |
|
|
|
2524 |
|
|
@item c
|
2525 |
|
|
Floating-point condition code register.
|
2526 |
|
|
|
2527 |
|
|
@item d
|
2528 |
|
|
Lower floating-point register. It is only valid on the SPARC-V9
|
2529 |
|
|
architecture when the Visual Instruction Set is available.
|
2530 |
|
|
|
2531 |
|
|
@item b
|
2532 |
|
|
Floating-point register. It is only valid on the SPARC-V9 architecture
|
2533 |
|
|
when the Visual Instruction Set is available.
|
2534 |
|
|
|
2535 |
|
|
@item h
|
2536 |
|
|
64-bit global or out register for the SPARC-V8+ architecture.
|
2537 |
|
|
|
2538 |
|
|
@item I
|
2539 |
|
|
Signed 13-bit constant
|
2540 |
|
|
|
2541 |
|
|
@item J
|
2542 |
|
|
Zero
|
2543 |
|
|
|
2544 |
|
|
@item K
|
2545 |
|
|
32-bit constant with the low 12 bits clear (a constant that can be
|
2546 |
|
|
loaded with the @code{sethi} instruction)
|
2547 |
|
|
|
2548 |
|
|
@item L
|
2549 |
|
|
A constant in the range supported by @code{movcc} instructions
|
2550 |
|
|
|
2551 |
|
|
@item M
|
2552 |
|
|
A constant in the range supported by @code{movrcc} instructions
|
2553 |
|
|
|
2554 |
|
|
@item N
|
2555 |
|
|
Same as @samp{K}, except that it verifies that bits that are not in the
|
2556 |
|
|
lower 32-bit range are all zero. Must be used instead of @samp{K} for
|
2557 |
|
|
modes wider than @code{SImode}
|
2558 |
|
|
|
2559 |
|
|
@item O
|
2560 |
|
|
The constant 4096
|
2561 |
|
|
|
2562 |
|
|
@item G
|
2563 |
|
|
Floating-point zero
|
2564 |
|
|
|
2565 |
|
|
@item H
|
2566 |
|
|
Signed 13-bit constant, sign-extended to 32 or 64 bits
|
2567 |
|
|
|
2568 |
|
|
@item Q
|
2569 |
|
|
Floating-point constant whose integral representation can
|
2570 |
|
|
be moved into an integer register using a single sethi
|
2571 |
|
|
instruction
|
2572 |
|
|
|
2573 |
|
|
@item R
|
2574 |
|
|
Floating-point constant whose integral representation can
|
2575 |
|
|
be moved into an integer register using a single mov
|
2576 |
|
|
instruction
|
2577 |
|
|
|
2578 |
|
|
@item S
|
2579 |
|
|
Floating-point constant whose integral representation can
|
2580 |
|
|
be moved into an integer register using a high/lo_sum
|
2581 |
|
|
instruction sequence
|
2582 |
|
|
|
2583 |
|
|
@item T
|
2584 |
|
|
Memory address aligned to an 8-byte boundary
|
2585 |
|
|
|
2586 |
|
|
@item U
|
2587 |
|
|
Even register
|
2588 |
|
|
|
2589 |
|
|
@item W
|
2590 |
|
|
Memory address for @samp{e} constraint registers
|
2591 |
|
|
|
2592 |
|
|
@item Y
|
2593 |
|
|
Vector zero
|
2594 |
|
|
|
2595 |
|
|
@end table
|
2596 |
|
|
|
2597 |
|
|
@item TMS320C3x/C4x---@file{c4x.h}
|
2598 |
|
|
@table @code
|
2599 |
|
|
@item a
|
2600 |
|
|
Auxiliary (address) register (ar0-ar7)
|
2601 |
|
|
|
2602 |
|
|
@item b
|
2603 |
|
|
Stack pointer register (sp)
|
2604 |
|
|
|
2605 |
|
|
@item c
|
2606 |
|
|
Standard (32-bit) precision integer register
|
2607 |
|
|
|
2608 |
|
|
@item f
|
2609 |
|
|
Extended (40-bit) precision register (r0-r11)
|
2610 |
|
|
|
2611 |
|
|
@item k
|
2612 |
|
|
Block count register (bk)
|
2613 |
|
|
|
2614 |
|
|
@item q
|
2615 |
|
|
Extended (40-bit) precision low register (r0-r7)
|
2616 |
|
|
|
2617 |
|
|
@item t
|
2618 |
|
|
Extended (40-bit) precision register (r0-r1)
|
2619 |
|
|
|
2620 |
|
|
@item u
|
2621 |
|
|
Extended (40-bit) precision register (r2-r3)
|
2622 |
|
|
|
2623 |
|
|
@item v
|
2624 |
|
|
Repeat count register (rc)
|
2625 |
|
|
|
2626 |
|
|
@item x
|
2627 |
|
|
Index register (ir0-ir1)
|
2628 |
|
|
|
2629 |
|
|
@item y
|
2630 |
|
|
Status (condition code) register (st)
|
2631 |
|
|
|
2632 |
|
|
@item z
|
2633 |
|
|
Data page register (dp)
|
2634 |
|
|
|
2635 |
|
|
@item G
|
2636 |
|
|
Floating-point zero
|
2637 |
|
|
|
2638 |
|
|
@item H
|
2639 |
|
|
Immediate 16-bit floating-point constant
|
2640 |
|
|
|
2641 |
|
|
@item I
|
2642 |
|
|
Signed 16-bit constant
|
2643 |
|
|
|
2644 |
|
|
@item J
|
2645 |
|
|
Signed 8-bit constant
|
2646 |
|
|
|
2647 |
|
|
@item K
|
2648 |
|
|
Signed 5-bit constant
|
2649 |
|
|
|
2650 |
|
|
@item L
|
2651 |
|
|
Unsigned 16-bit constant
|
2652 |
|
|
|
2653 |
|
|
@item M
|
2654 |
|
|
Unsigned 8-bit constant
|
2655 |
|
|
|
2656 |
|
|
@item N
|
2657 |
|
|
Ones complement of unsigned 16-bit constant
|
2658 |
|
|
|
2659 |
|
|
@item O
|
2660 |
|
|
High 16-bit constant (32-bit constant with 16 LSBs zero)
|
2661 |
|
|
|
2662 |
|
|
@item Q
|
2663 |
|
|
Indirect memory reference with signed 8-bit or index register displacement
|
2664 |
|
|
|
2665 |
|
|
@item R
|
2666 |
|
|
Indirect memory reference with unsigned 5-bit displacement
|
2667 |
|
|
|
2668 |
|
|
@item S
|
2669 |
|
|
Indirect memory reference with 1 bit or index register displacement
|
2670 |
|
|
|
2671 |
|
|
@item T
|
2672 |
|
|
Direct memory reference
|
2673 |
|
|
|
2674 |
|
|
@item U
|
2675 |
|
|
Symbolic address
|
2676 |
|
|
|
2677 |
|
|
@end table
|
2678 |
|
|
|
2679 |
|
|
@item S/390 and zSeries---@file{s390.h}
|
2680 |
|
|
@table @code
|
2681 |
|
|
@item a
|
2682 |
|
|
Address register (general purpose register except r0)
|
2683 |
|
|
|
2684 |
|
|
@item c
|
2685 |
|
|
Condition code register
|
2686 |
|
|
|
2687 |
|
|
@item d
|
2688 |
|
|
Data register (arbitrary general purpose register)
|
2689 |
|
|
|
2690 |
|
|
@item f
|
2691 |
|
|
Floating-point register
|
2692 |
|
|
|
2693 |
|
|
@item I
|
2694 |
|
|
Unsigned 8-bit constant (0--255)
|
2695 |
|
|
|
2696 |
|
|
@item J
|
2697 |
|
|
Unsigned 12-bit constant (0--4095)
|
2698 |
|
|
|
2699 |
|
|
@item K
|
2700 |
|
|
Signed 16-bit constant (@minus{}32768--32767)
|
2701 |
|
|
|
2702 |
|
|
@item L
|
2703 |
|
|
Value appropriate as displacement.
|
2704 |
|
|
@table @code
|
2705 |
|
|
@item (0..4095)
|
2706 |
|
|
for short displacement
|
2707 |
|
|
@item (-524288..524287)
|
2708 |
|
|
for long displacement
|
2709 |
|
|
@end table
|
2710 |
|
|
|
2711 |
|
|
@item M
|
2712 |
|
|
Constant integer with a value of 0x7fffffff.
|
2713 |
|
|
|
2714 |
|
|
@item N
|
2715 |
|
|
Multiple letter constraint followed by 4 parameter letters.
|
2716 |
|
|
@table @code
|
2717 |
|
|
@item 0..9:
|
2718 |
|
|
number of the part counting from most to least significant
|
2719 |
|
|
@item H,Q:
|
2720 |
|
|
mode of the part
|
2721 |
|
|
@item D,S,H:
|
2722 |
|
|
mode of the containing operand
|
2723 |
|
|
@item 0,F:
|
2724 |
|
|
value of the other parts (F---all bits set)
|
2725 |
|
|
@end table
|
2726 |
|
|
The constraint matches if the specified part of a constant
|
2727 |
|
|
has a value different from it's other parts.
|
2728 |
|
|
|
2729 |
|
|
@item Q
|
2730 |
|
|
Memory reference without index register and with short displacement.
|
2731 |
|
|
|
2732 |
|
|
@item R
|
2733 |
|
|
Memory reference with index register and short displacement.
|
2734 |
|
|
|
2735 |
|
|
@item S
|
2736 |
|
|
Memory reference without index register but with long displacement.
|
2737 |
|
|
|
2738 |
|
|
@item T
|
2739 |
|
|
Memory reference with index register and long displacement.
|
2740 |
|
|
|
2741 |
|
|
@item U
|
2742 |
|
|
Pointer with short displacement.
|
2743 |
|
|
|
2744 |
|
|
@item W
|
2745 |
|
|
Pointer with long displacement.
|
2746 |
|
|
|
2747 |
|
|
@item Y
|
2748 |
|
|
Shift count operand.
|
2749 |
|
|
|
2750 |
|
|
@end table
|
2751 |
|
|
|
2752 |
|
|
@item Xstormy16---@file{stormy16.h}
|
2753 |
|
|
@table @code
|
2754 |
|
|
@item a
|
2755 |
|
|
Register r0.
|
2756 |
|
|
|
2757 |
|
|
@item b
|
2758 |
|
|
Register r1.
|
2759 |
|
|
|
2760 |
|
|
@item c
|
2761 |
|
|
Register r2.
|
2762 |
|
|
|
2763 |
|
|
@item d
|
2764 |
|
|
Register r8.
|
2765 |
|
|
|
2766 |
|
|
@item e
|
2767 |
|
|
Registers r0 through r7.
|
2768 |
|
|
|
2769 |
|
|
@item t
|
2770 |
|
|
Registers r0 and r1.
|
2771 |
|
|
|
2772 |
|
|
@item y
|
2773 |
|
|
The carry register.
|
2774 |
|
|
|
2775 |
|
|
@item z
|
2776 |
|
|
Registers r8 and r9.
|
2777 |
|
|
|
2778 |
|
|
@item I
|
2779 |
|
|
A constant between 0 and 3 inclusive.
|
2780 |
|
|
|
2781 |
|
|
@item J
|
2782 |
|
|
A constant that has exactly one bit set.
|
2783 |
|
|
|
2784 |
|
|
@item K
|
2785 |
|
|
A constant that has exactly one bit clear.
|
2786 |
|
|
|
2787 |
|
|
@item L
|
2788 |
|
|
A constant between 0 and 255 inclusive.
|
2789 |
|
|
|
2790 |
|
|
@item M
|
2791 |
|
|
A constant between @minus{}255 and 0 inclusive.
|
2792 |
|
|
|
2793 |
|
|
@item N
|
2794 |
|
|
A constant between @minus{}3 and 0 inclusive.
|
2795 |
|
|
|
2796 |
|
|
@item O
|
2797 |
|
|
A constant between 1 and 4 inclusive.
|
2798 |
|
|
|
2799 |
|
|
@item P
|
2800 |
|
|
A constant between @minus{}4 and @minus{}1 inclusive.
|
2801 |
|
|
|
2802 |
|
|
@item Q
|
2803 |
|
|
A memory reference that is a stack push.
|
2804 |
|
|
|
2805 |
|
|
@item R
|
2806 |
|
|
A memory reference that is a stack pop.
|
2807 |
|
|
|
2808 |
|
|
@item S
|
2809 |
|
|
A memory reference that refers to a constant address of known value.
|
2810 |
|
|
|
2811 |
|
|
@item T
|
2812 |
|
|
The register indicated by Rx (not implemented yet).
|
2813 |
|
|
|
2814 |
|
|
@item U
|
2815 |
|
|
A constant that is not between 2 and 15 inclusive.
|
2816 |
|
|
|
2817 |
|
|
@item Z
|
2818 |
|
|
The constant 0.
|
2819 |
|
|
|
2820 |
|
|
@end table
|
2821 |
|
|
|
2822 |
|
|
@item Xtensa---@file{xtensa.h}
|
2823 |
|
|
@table @code
|
2824 |
|
|
@item a
|
2825 |
|
|
General-purpose 32-bit register
|
2826 |
|
|
|
2827 |
|
|
@item b
|
2828 |
|
|
One-bit boolean register
|
2829 |
|
|
|
2830 |
|
|
@item A
|
2831 |
|
|
MAC16 40-bit accumulator register
|
2832 |
|
|
|
2833 |
|
|
@item I
|
2834 |
|
|
Signed 12-bit integer constant, for use in MOVI instructions
|
2835 |
|
|
|
2836 |
|
|
@item J
|
2837 |
|
|
Signed 8-bit integer constant, for use in ADDI instructions
|
2838 |
|
|
|
2839 |
|
|
@item K
|
2840 |
|
|
Integer constant valid for BccI instructions
|
2841 |
|
|
|
2842 |
|
|
@item L
|
2843 |
|
|
Unsigned constant valid for BccUI instructions
|
2844 |
|
|
|
2845 |
|
|
@end table
|
2846 |
|
|
|
2847 |
|
|
@end table
|
2848 |
|
|
|
2849 |
|
|
@ifset INTERNALS
|
2850 |
|
|
@node Standard Names
|
2851 |
|
|
@section Standard Pattern Names For Generation
|
2852 |
|
|
@cindex standard pattern names
|
2853 |
|
|
@cindex pattern names
|
2854 |
|
|
@cindex names, pattern
|
2855 |
|
|
|
2856 |
|
|
Here is a table of the instruction names that are meaningful in the RTL
|
2857 |
|
|
generation pass of the compiler. Giving one of these names to an
|
2858 |
|
|
instruction pattern tells the RTL generation pass that it can use the
|
2859 |
|
|
pattern to accomplish a certain task.
|
2860 |
|
|
|
2861 |
|
|
@table @asis
|
2862 |
|
|
@cindex @code{mov@var{m}} instruction pattern
|
2863 |
|
|
@item @samp{mov@var{m}}
|
2864 |
|
|
Here @var{m} stands for a two-letter machine mode name, in lowercase.
|
2865 |
|
|
This instruction pattern moves data with that machine mode from operand
|
2866 |
|
|
1 to operand 0. For example, @samp{movsi} moves full-word data.
|
2867 |
|
|
|
2868 |
|
|
If operand 0 is a @code{subreg} with mode @var{m} of a register whose
|
2869 |
|
|
own mode is wider than @var{m}, the effect of this instruction is
|
2870 |
|
|
to store the specified value in the part of the register that corresponds
|
2871 |
|
|
to mode @var{m}. Bits outside of @var{m}, but which are within the
|
2872 |
|
|
same target word as the @code{subreg} are undefined. Bits which are
|
2873 |
|
|
outside the target word are left unchanged.
|
2874 |
|
|
|
2875 |
|
|
This class of patterns is special in several ways. First of all, each
|
2876 |
|
|
of these names up to and including full word size @emph{must} be defined,
|
2877 |
|
|
because there is no other way to copy a datum from one place to another.
|
2878 |
|
|
If there are patterns accepting operands in larger modes,
|
2879 |
|
|
@samp{mov@var{m}} must be defined for integer modes of those sizes.
|
2880 |
|
|
|
2881 |
|
|
Second, these patterns are not used solely in the RTL generation pass.
|
2882 |
|
|
Even the reload pass can generate move insns to copy values from stack
|
2883 |
|
|
slots into temporary registers. When it does so, one of the operands is
|
2884 |
|
|
a hard register and the other is an operand that can need to be reloaded
|
2885 |
|
|
into a register.
|
2886 |
|
|
|
2887 |
|
|
@findex force_reg
|
2888 |
|
|
Therefore, when given such a pair of operands, the pattern must generate
|
2889 |
|
|
RTL which needs no reloading and needs no temporary registers---no
|
2890 |
|
|
registers other than the operands. For example, if you support the
|
2891 |
|
|
pattern with a @code{define_expand}, then in such a case the
|
2892 |
|
|
@code{define_expand} mustn't call @code{force_reg} or any other such
|
2893 |
|
|
function which might generate new pseudo registers.
|
2894 |
|
|
|
2895 |
|
|
This requirement exists even for subword modes on a RISC machine where
|
2896 |
|
|
fetching those modes from memory normally requires several insns and
|
2897 |
|
|
some temporary registers.
|
2898 |
|
|
|
2899 |
|
|
@findex change_address
|
2900 |
|
|
During reload a memory reference with an invalid address may be passed
|
2901 |
|
|
as an operand. Such an address will be replaced with a valid address
|
2902 |
|
|
later in the reload pass. In this case, nothing may be done with the
|
2903 |
|
|
address except to use it as it stands. If it is copied, it will not be
|
2904 |
|
|
replaced with a valid address. No attempt should be made to make such
|
2905 |
|
|
an address into a valid address and no routine (such as
|
2906 |
|
|
@code{change_address}) that will do so may be called. Note that
|
2907 |
|
|
@code{general_operand} will fail when applied to such an address.
|
2908 |
|
|
|
2909 |
|
|
@findex reload_in_progress
|
2910 |
|
|
The global variable @code{reload_in_progress} (which must be explicitly
|
2911 |
|
|
declared if required) can be used to determine whether such special
|
2912 |
|
|
handling is required.
|
2913 |
|
|
|
2914 |
|
|
The variety of operands that have reloads depends on the rest of the
|
2915 |
|
|
machine description, but typically on a RISC machine these can only be
|
2916 |
|
|
pseudo registers that did not get hard registers, while on other
|
2917 |
|
|
machines explicit memory references will get optional reloads.
|
2918 |
|
|
|
2919 |
|
|
If a scratch register is required to move an object to or from memory,
|
2920 |
|
|
it can be allocated using @code{gen_reg_rtx} prior to life analysis.
|
2921 |
|
|
|
2922 |
|
|
If there are cases which need scratch registers during or after reload,
|
2923 |
|
|
you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
|
2924 |
|
|
@code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
|
2925 |
|
|
patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
|
2926 |
|
|
them. @xref{Register Classes}.
|
2927 |
|
|
|
2928 |
|
|
@findex no_new_pseudos
|
2929 |
|
|
The global variable @code{no_new_pseudos} can be used to determine if it
|
2930 |
|
|
is unsafe to create new pseudo registers. If this variable is nonzero, then
|
2931 |
|
|
it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
|
2932 |
|
|
|
2933 |
|
|
The constraints on a @samp{mov@var{m}} must permit moving any hard
|
2934 |
|
|
register to any other hard register provided that
|
2935 |
|
|
@code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
|
2936 |
|
|
@code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
|
2937 |
|
|
|
2938 |
|
|
It is obligatory to support floating point @samp{mov@var{m}}
|
2939 |
|
|
instructions into and out of any registers that can hold fixed point
|
2940 |
|
|
values, because unions and structures (which have modes @code{SImode} or
|
2941 |
|
|
@code{DImode}) can be in those registers and they may have floating
|
2942 |
|
|
point members.
|
2943 |
|
|
|
2944 |
|
|
There may also be a need to support fixed point @samp{mov@var{m}}
|
2945 |
|
|
instructions in and out of floating point registers. Unfortunately, I
|
2946 |
|
|
have forgotten why this was so, and I don't know whether it is still
|
2947 |
|
|
true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
|
2948 |
|
|
floating point registers, then the constraints of the fixed point
|
2949 |
|
|
@samp{mov@var{m}} instructions must be designed to avoid ever trying to
|
2950 |
|
|
reload into a floating point register.
|
2951 |
|
|
|
2952 |
|
|
@cindex @code{reload_in} instruction pattern
|
2953 |
|
|
@cindex @code{reload_out} instruction pattern
|
2954 |
|
|
@item @samp{reload_in@var{m}}
|
2955 |
|
|
@itemx @samp{reload_out@var{m}}
|
2956 |
|
|
Like @samp{mov@var{m}}, but used when a scratch register is required to
|
2957 |
|
|
move between operand 0 and operand 1. Operand 2 describes the scratch
|
2958 |
|
|
register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
|
2959 |
|
|
macro in @pxref{Register Classes}.
|
2960 |
|
|
|
2961 |
|
|
There are special restrictions on the form of the @code{match_operand}s
|
2962 |
|
|
used in these patterns. First, only the predicate for the reload
|
2963 |
|
|
operand is examined, i.e., @code{reload_in} examines operand 1, but not
|
2964 |
|
|
the predicates for operand 0 or 2. Second, there may be only one
|
2965 |
|
|
alternative in the constraints. Third, only a single register class
|
2966 |
|
|
letter may be used for the constraint; subsequent constraint letters
|
2967 |
|
|
are ignored. As a special exception, an empty constraint string
|
2968 |
|
|
matches the @code{ALL_REGS} register class. This may relieve ports
|
2969 |
|
|
of the burden of defining an @code{ALL_REGS} constraint letter just
|
2970 |
|
|
for these patterns.
|
2971 |
|
|
|
2972 |
|
|
@cindex @code{movstrict@var{m}} instruction pattern
|
2973 |
|
|
@item @samp{movstrict@var{m}}
|
2974 |
|
|
Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
|
2975 |
|
|
with mode @var{m} of a register whose natural mode is wider,
|
2976 |
|
|
the @samp{movstrict@var{m}} instruction is guaranteed not to alter
|
2977 |
|
|
any of the register except the part which belongs to mode @var{m}.
|
2978 |
|
|
|
2979 |
|
|
@cindex @code{movmisalign@var{m}} instruction pattern
|
2980 |
|
|
@item @samp{movmisalign@var{m}}
|
2981 |
|
|
This variant of a move pattern is designed to load or store a value
|
2982 |
|
|
from a memory address that is not naturally aligned for its mode.
|
2983 |
|
|
For a store, the memory will be in operand 0; for a load, the memory
|
2984 |
|
|
will be in operand 1. The other operand is guaranteed not to be a
|
2985 |
|
|
memory, so that it's easy to tell whether this is a load or store.
|
2986 |
|
|
|
2987 |
|
|
This pattern is used by the autovectorizer, and when expanding a
|
2988 |
|
|
@code{MISALIGNED_INDIRECT_REF} expression.
|
2989 |
|
|
|
2990 |
|
|
@cindex @code{load_multiple} instruction pattern
|
2991 |
|
|
@item @samp{load_multiple}
|
2992 |
|
|
Load several consecutive memory locations into consecutive registers.
|
2993 |
|
|
Operand 0 is the first of the consecutive registers, operand 1
|
2994 |
|
|
is the first memory location, and operand 2 is a constant: the
|
2995 |
|
|
number of consecutive registers.
|
2996 |
|
|
|
2997 |
|
|
Define this only if the target machine really has such an instruction;
|
2998 |
|
|
do not define this if the most efficient way of loading consecutive
|
2999 |
|
|
registers from memory is to do them one at a time.
|
3000 |
|
|
|
3001 |
|
|
On some machines, there are restrictions as to which consecutive
|
3002 |
|
|
registers can be stored into memory, such as particular starting or
|
3003 |
|
|
ending register numbers or only a range of valid counts. For those
|
3004 |
|
|
machines, use a @code{define_expand} (@pxref{Expander Definitions})
|
3005 |
|
|
and make the pattern fail if the restrictions are not met.
|
3006 |
|
|
|
3007 |
|
|
Write the generated insn as a @code{parallel} with elements being a
|
3008 |
|
|
@code{set} of one register from the appropriate memory location (you may
|
3009 |
|
|
also need @code{use} or @code{clobber} elements). Use a
|
3010 |
|
|
@code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
|
3011 |
|
|
@file{rs6000.md} for examples of the use of this insn pattern.
|
3012 |
|
|
|
3013 |
|
|
@cindex @samp{store_multiple} instruction pattern
|
3014 |
|
|
@item @samp{store_multiple}
|
3015 |
|
|
Similar to @samp{load_multiple}, but store several consecutive registers
|
3016 |
|
|
into consecutive memory locations. Operand 0 is the first of the
|
3017 |
|
|
consecutive memory locations, operand 1 is the first register, and
|
3018 |
|
|
operand 2 is a constant: the number of consecutive registers.
|
3019 |
|
|
|
3020 |
|
|
@cindex @code{vec_set@var{m}} instruction pattern
|
3021 |
|
|
@item @samp{vec_set@var{m}}
|
3022 |
|
|
Set given field in the vector value. Operand 0 is the vector to modify,
|
3023 |
|
|
operand 1 is new value of field and operand 2 specify the field index.
|
3024 |
|
|
|
3025 |
|
|
@cindex @code{vec_extract@var{m}} instruction pattern
|
3026 |
|
|
@item @samp{vec_extract@var{m}}
|
3027 |
|
|
Extract given field from the vector value. Operand 1 is the vector, operand 2
|
3028 |
|
|
specify field index and operand 0 place to store value into.
|
3029 |
|
|
|
3030 |
|
|
@cindex @code{vec_init@var{m}} instruction pattern
|
3031 |
|
|
@item @samp{vec_init@var{m}}
|
3032 |
|
|
Initialize the vector to given values. Operand 0 is the vector to initialize
|
3033 |
|
|
and operand 1 is parallel containing values for individual fields.
|
3034 |
|
|
|
3035 |
|
|
@cindex @code{push@var{m}1} instruction pattern
|
3036 |
|
|
@item @samp{push@var{m}1}
|
3037 |
|
|
Output a push instruction. Operand 0 is value to push. Used only when
|
3038 |
|
|
@code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
|
3039 |
|
|
missing and in such case an @code{mov} expander is used instead, with a
|
3040 |
|
|
@code{MEM} expression forming the push operation. The @code{mov} expander
|
3041 |
|
|
method is deprecated.
|
3042 |
|
|
|
3043 |
|
|
@cindex @code{add@var{m}3} instruction pattern
|
3044 |
|
|
@item @samp{add@var{m}3}
|
3045 |
|
|
Add operand 2 and operand 1, storing the result in operand 0. All operands
|
3046 |
|
|
must have mode @var{m}. This can be used even on two-address machines, by
|
3047 |
|
|
means of constraints requiring operands 1 and 0 to be the same location.
|
3048 |
|
|
|
3049 |
|
|
@cindex @code{sub@var{m}3} instruction pattern
|
3050 |
|
|
@cindex @code{mul@var{m}3} instruction pattern
|
3051 |
|
|
@cindex @code{div@var{m}3} instruction pattern
|
3052 |
|
|
@cindex @code{udiv@var{m}3} instruction pattern
|
3053 |
|
|
@cindex @code{mod@var{m}3} instruction pattern
|
3054 |
|
|
@cindex @code{umod@var{m}3} instruction pattern
|
3055 |
|
|
@cindex @code{umin@var{m}3} instruction pattern
|
3056 |
|
|
@cindex @code{umax@var{m}3} instruction pattern
|
3057 |
|
|
@cindex @code{and@var{m}3} instruction pattern
|
3058 |
|
|
@cindex @code{ior@var{m}3} instruction pattern
|
3059 |
|
|
@cindex @code{xor@var{m}3} instruction pattern
|
3060 |
|
|
@item @samp{sub@var{m}3}, @samp{mul@var{m}3}
|
3061 |
|
|
@itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}
|
3062 |
|
|
@itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
|
3063 |
|
|
@itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
|
3064 |
|
|
@itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
|
3065 |
|
|
Similar, for other arithmetic operations.
|
3066 |
|
|
|
3067 |
|
|
@cindex @code{min@var{m}3} instruction pattern
|
3068 |
|
|
@cindex @code{max@var{m}3} instruction pattern
|
3069 |
|
|
@item @samp{smin@var{m}3}, @samp{smax@var{m}3}
|
3070 |
|
|
Signed minimum and maximum operations. When used with floating point,
|
3071 |
|
|
if both operands are zeros, or if either operand is @code{NaN}, then
|
3072 |
|
|
it is unspecified which of the two operands is returned as the result.
|
3073 |
|
|
|
3074 |
|
|
@cindex @code{reduc_smin_@var{m}} instruction pattern
|
3075 |
|
|
@cindex @code{reduc_smax_@var{m}} instruction pattern
|
3076 |
|
|
@item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
|
3077 |
|
|
Find the signed minimum/maximum of the elements of a vector. The vector is
|
3078 |
|
|
operand 1, and the scalar result is stored in the least significant bits of
|
3079 |
|
|
operand 0 (also a vector). The output and input vector should have the same
|
3080 |
|
|
modes.
|
3081 |
|
|
|
3082 |
|
|
@cindex @code{reduc_umin_@var{m}} instruction pattern
|
3083 |
|
|
@cindex @code{reduc_umax_@var{m}} instruction pattern
|
3084 |
|
|
@item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
|
3085 |
|
|
Find the unsigned minimum/maximum of the elements of a vector. The vector is
|
3086 |
|
|
operand 1, and the scalar result is stored in the least significant bits of
|
3087 |
|
|
operand 0 (also a vector). The output and input vector should have the same
|
3088 |
|
|
modes.
|
3089 |
|
|
|
3090 |
|
|
@cindex @code{reduc_splus_@var{m}} instruction pattern
|
3091 |
|
|
@item @samp{reduc_splus_@var{m}}
|
3092 |
|
|
Compute the sum of the signed elements of a vector. The vector is operand 1,
|
3093 |
|
|
and the scalar result is stored in the least significant bits of operand 0
|
3094 |
|
|
(also a vector). The output and input vector should have the same modes.
|
3095 |
|
|
|
3096 |
|
|
@cindex @code{reduc_uplus_@var{m}} instruction pattern
|
3097 |
|
|
@item @samp{reduc_uplus_@var{m}}
|
3098 |
|
|
Compute the sum of the unsigned elements of a vector. The vector is operand 1,
|
3099 |
|
|
and the scalar result is stored in the least significant bits of operand 0
|
3100 |
|
|
(also a vector). The output and input vector should have the same modes.
|
3101 |
|
|
|
3102 |
|
|
@cindex @code{vec_shl_@var{m}} instruction pattern
|
3103 |
|
|
@cindex @code{vec_shr_@var{m}} instruction pattern
|
3104 |
|
|
@item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
|
3105 |
|
|
Whole vector left/right shift in bits.
|
3106 |
|
|
Operand 1 is a vector to be shifted.
|
3107 |
|
|
Operand 2 is an integer shift amount in bits.
|
3108 |
|
|
Operand 0 is where the resulting shifted vector is stored.
|
3109 |
|
|
The output and input vectors should have the same modes.
|
3110 |
|
|
|
3111 |
|
|
@cindex @code{mulhisi3} instruction pattern
|
3112 |
|
|
@item @samp{mulhisi3}
|
3113 |
|
|
Multiply operands 1 and 2, which have mode @code{HImode}, and store
|
3114 |
|
|
a @code{SImode} product in operand 0.
|
3115 |
|
|
|
3116 |
|
|
@cindex @code{mulqihi3} instruction pattern
|
3117 |
|
|
@cindex @code{mulsidi3} instruction pattern
|
3118 |
|
|
@item @samp{mulqihi3}, @samp{mulsidi3}
|
3119 |
|
|
Similar widening-multiplication instructions of other widths.
|
3120 |
|
|
|
3121 |
|
|
@cindex @code{umulqihi3} instruction pattern
|
3122 |
|
|
@cindex @code{umulhisi3} instruction pattern
|
3123 |
|
|
@cindex @code{umulsidi3} instruction pattern
|
3124 |
|
|
@item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
|
3125 |
|
|
Similar widening-multiplication instructions that do unsigned
|
3126 |
|
|
multiplication.
|
3127 |
|
|
|
3128 |
|
|
@cindex @code{smul@var{m}3_highpart} instruction pattern
|
3129 |
|
|
@item @samp{smul@var{m}3_highpart}
|
3130 |
|
|
Perform a signed multiplication of operands 1 and 2, which have mode
|
3131 |
|
|
@var{m}, and store the most significant half of the product in operand 0.
|
3132 |
|
|
The least significant half of the product is discarded.
|
3133 |
|
|
|
3134 |
|
|
@cindex @code{umul@var{m}3_highpart} instruction pattern
|
3135 |
|
|
@item @samp{umul@var{m}3_highpart}
|
3136 |
|
|
Similar, but the multiplication is unsigned.
|
3137 |
|
|
|
3138 |
|
|
@cindex @code{divmod@var{m}4} instruction pattern
|
3139 |
|
|
@item @samp{divmod@var{m}4}
|
3140 |
|
|
Signed division that produces both a quotient and a remainder.
|
3141 |
|
|
Operand 1 is divided by operand 2 to produce a quotient stored
|
3142 |
|
|
in operand 0 and a remainder stored in operand 3.
|
3143 |
|
|
|
3144 |
|
|
For machines with an instruction that produces both a quotient and a
|
3145 |
|
|
remainder, provide a pattern for @samp{divmod@var{m}4} but do not
|
3146 |
|
|
provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
|
3147 |
|
|
allows optimization in the relatively common case when both the quotient
|
3148 |
|
|
and remainder are computed.
|
3149 |
|
|
|
3150 |
|
|
If an instruction that just produces a quotient or just a remainder
|
3151 |
|
|
exists and is more efficient than the instruction that produces both,
|
3152 |
|
|
write the output routine of @samp{divmod@var{m}4} to call
|
3153 |
|
|
@code{find_reg_note} and look for a @code{REG_UNUSED} note on the
|
3154 |
|
|
quotient or remainder and generate the appropriate instruction.
|
3155 |
|
|
|
3156 |
|
|
@cindex @code{udivmod@var{m}4} instruction pattern
|
3157 |
|
|
@item @samp{udivmod@var{m}4}
|
3158 |
|
|
Similar, but does unsigned division.
|
3159 |
|
|
|
3160 |
|
|
@anchor{shift patterns}
|
3161 |
|
|
@cindex @code{ashl@var{m}3} instruction pattern
|
3162 |
|
|
@item @samp{ashl@var{m}3}
|
3163 |
|
|
Arithmetic-shift operand 1 left by a number of bits specified by operand
|
3164 |
|
|
2, and store the result in operand 0. Here @var{m} is the mode of
|
3165 |
|
|
operand 0 and operand 1; operand 2's mode is specified by the
|
3166 |
|
|
instruction pattern, and the compiler will convert the operand to that
|
3167 |
|
|
mode before generating the instruction. The meaning of out-of-range shift
|
3168 |
|
|
counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
|
3169 |
|
|
@xref{TARGET_SHIFT_TRUNCATION_MASK}.
|
3170 |
|
|
|
3171 |
|
|
@cindex @code{ashr@var{m}3} instruction pattern
|
3172 |
|
|
@cindex @code{lshr@var{m}3} instruction pattern
|
3173 |
|
|
@cindex @code{rotl@var{m}3} instruction pattern
|
3174 |
|
|
@cindex @code{rotr@var{m}3} instruction pattern
|
3175 |
|
|
@item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
|
3176 |
|
|
Other shift and rotate instructions, analogous to the
|
3177 |
|
|
@code{ashl@var{m}3} instructions.
|
3178 |
|
|
|
3179 |
|
|
@cindex @code{neg@var{m}2} instruction pattern
|
3180 |
|
|
@item @samp{neg@var{m}2}
|
3181 |
|
|
Negate operand 1 and store the result in operand 0.
|
3182 |
|
|
|
3183 |
|
|
@cindex @code{abs@var{m}2} instruction pattern
|
3184 |
|
|
@item @samp{abs@var{m}2}
|
3185 |
|
|
Store the absolute value of operand 1 into operand 0.
|
3186 |
|
|
|
3187 |
|
|
@cindex @code{sqrt@var{m}2} instruction pattern
|
3188 |
|
|
@item @samp{sqrt@var{m}2}
|
3189 |
|
|
Store the square root of operand 1 into operand 0.
|
3190 |
|
|
|
3191 |
|
|
The @code{sqrt} built-in function of C always uses the mode which
|
3192 |
|
|
corresponds to the C data type @code{double} and the @code{sqrtf}
|
3193 |
|
|
built-in function uses the mode which corresponds to the C data
|
3194 |
|
|
type @code{float}.
|
3195 |
|
|
|
3196 |
|
|
@cindex @code{cos@var{m}2} instruction pattern
|
3197 |
|
|
@item @samp{cos@var{m}2}
|
3198 |
|
|
Store the cosine of operand 1 into operand 0.
|
3199 |
|
|
|
3200 |
|
|
The @code{cos} built-in function of C always uses the mode which
|
3201 |
|
|
corresponds to the C data type @code{double} and the @code{cosf}
|
3202 |
|
|
built-in function uses the mode which corresponds to the C data
|
3203 |
|
|
type @code{float}.
|
3204 |
|
|
|
3205 |
|
|
@cindex @code{sin@var{m}2} instruction pattern
|
3206 |
|
|
@item @samp{sin@var{m}2}
|
3207 |
|
|
Store the sine of operand 1 into operand 0.
|
3208 |
|
|
|
3209 |
|
|
The @code{sin} built-in function of C always uses the mode which
|
3210 |
|
|
corresponds to the C data type @code{double} and the @code{sinf}
|
3211 |
|
|
built-in function uses the mode which corresponds to the C data
|
3212 |
|
|
type @code{float}.
|
3213 |
|
|
|
3214 |
|
|
@cindex @code{exp@var{m}2} instruction pattern
|
3215 |
|
|
@item @samp{exp@var{m}2}
|
3216 |
|
|
Store the exponential of operand 1 into operand 0.
|
3217 |
|
|
|
3218 |
|
|
The @code{exp} built-in function of C always uses the mode which
|
3219 |
|
|
corresponds to the C data type @code{double} and the @code{expf}
|
3220 |
|
|
built-in function uses the mode which corresponds to the C data
|
3221 |
|
|
type @code{float}.
|
3222 |
|
|
|
3223 |
|
|
@cindex @code{log@var{m}2} instruction pattern
|
3224 |
|
|
@item @samp{log@var{m}2}
|
3225 |
|
|
Store the natural logarithm of operand 1 into operand 0.
|
3226 |
|
|
|
3227 |
|
|
The @code{log} built-in function of C always uses the mode which
|
3228 |
|
|
corresponds to the C data type @code{double} and the @code{logf}
|
3229 |
|
|
built-in function uses the mode which corresponds to the C data
|
3230 |
|
|
type @code{float}.
|
3231 |
|
|
|
3232 |
|
|
@cindex @code{pow@var{m}3} instruction pattern
|
3233 |
|
|
@item @samp{pow@var{m}3}
|
3234 |
|
|
Store the value of operand 1 raised to the exponent operand 2
|
3235 |
|
|
into operand 0.
|
3236 |
|
|
|
3237 |
|
|
The @code{pow} built-in function of C always uses the mode which
|
3238 |
|
|
corresponds to the C data type @code{double} and the @code{powf}
|
3239 |
|
|
built-in function uses the mode which corresponds to the C data
|
3240 |
|
|
type @code{float}.
|
3241 |
|
|
|
3242 |
|
|
@cindex @code{atan2@var{m}3} instruction pattern
|
3243 |
|
|
@item @samp{atan2@var{m}3}
|
3244 |
|
|
Store the arc tangent (inverse tangent) of operand 1 divided by
|
3245 |
|
|
operand 2 into operand 0, using the signs of both arguments to
|
3246 |
|
|
determine the quadrant of the result.
|
3247 |
|
|
|
3248 |
|
|
The @code{atan2} built-in function of C always uses the mode which
|
3249 |
|
|
corresponds to the C data type @code{double} and the @code{atan2f}
|
3250 |
|
|
built-in function uses the mode which corresponds to the C data
|
3251 |
|
|
type @code{float}.
|
3252 |
|
|
|
3253 |
|
|
@cindex @code{floor@var{m}2} instruction pattern
|
3254 |
|
|
@item @samp{floor@var{m}2}
|
3255 |
|
|
Store the largest integral value not greater than argument.
|
3256 |
|
|
|
3257 |
|
|
The @code{floor} built-in function of C always uses the mode which
|
3258 |
|
|
corresponds to the C data type @code{double} and the @code{floorf}
|
3259 |
|
|
built-in function uses the mode which corresponds to the C data
|
3260 |
|
|
type @code{float}.
|
3261 |
|
|
|
3262 |
|
|
@cindex @code{btrunc@var{m}2} instruction pattern
|
3263 |
|
|
@item @samp{btrunc@var{m}2}
|
3264 |
|
|
Store the argument rounded to integer towards zero.
|
3265 |
|
|
|
3266 |
|
|
The @code{trunc} built-in function of C always uses the mode which
|
3267 |
|
|
corresponds to the C data type @code{double} and the @code{truncf}
|
3268 |
|
|
built-in function uses the mode which corresponds to the C data
|
3269 |
|
|
type @code{float}.
|
3270 |
|
|
|
3271 |
|
|
@cindex @code{round@var{m}2} instruction pattern
|
3272 |
|
|
@item @samp{round@var{m}2}
|
3273 |
|
|
Store the argument rounded to integer away from zero.
|
3274 |
|
|
|
3275 |
|
|
The @code{round} built-in function of C always uses the mode which
|
3276 |
|
|
corresponds to the C data type @code{double} and the @code{roundf}
|
3277 |
|
|
built-in function uses the mode which corresponds to the C data
|
3278 |
|
|
type @code{float}.
|
3279 |
|
|
|
3280 |
|
|
@cindex @code{ceil@var{m}2} instruction pattern
|
3281 |
|
|
@item @samp{ceil@var{m}2}
|
3282 |
|
|
Store the argument rounded to integer away from zero.
|
3283 |
|
|
|
3284 |
|
|
The @code{ceil} built-in function of C always uses the mode which
|
3285 |
|
|
corresponds to the C data type @code{double} and the @code{ceilf}
|
3286 |
|
|
built-in function uses the mode which corresponds to the C data
|
3287 |
|
|
type @code{float}.
|
3288 |
|
|
|
3289 |
|
|
@cindex @code{nearbyint@var{m}2} instruction pattern
|
3290 |
|
|
@item @samp{nearbyint@var{m}2}
|
3291 |
|
|
Store the argument rounded according to the default rounding mode
|
3292 |
|
|
|
3293 |
|
|
The @code{nearbyint} built-in function of C always uses the mode which
|
3294 |
|
|
corresponds to the C data type @code{double} and the @code{nearbyintf}
|
3295 |
|
|
built-in function uses the mode which corresponds to the C data
|
3296 |
|
|
type @code{float}.
|
3297 |
|
|
|
3298 |
|
|
@cindex @code{rint@var{m}2} instruction pattern
|
3299 |
|
|
@item @samp{rint@var{m}2}
|
3300 |
|
|
Store the argument rounded according to the default rounding mode and
|
3301 |
|
|
raise the inexact exception when the result differs in value from
|
3302 |
|
|
the argument
|
3303 |
|
|
|
3304 |
|
|
The @code{rint} built-in function of C always uses the mode which
|
3305 |
|
|
corresponds to the C data type @code{double} and the @code{rintf}
|
3306 |
|
|
built-in function uses the mode which corresponds to the C data
|
3307 |
|
|
type @code{float}.
|
3308 |
|
|
|
3309 |
|
|
@cindex @code{copysign@var{m}3} instruction pattern
|
3310 |
|
|
@item @samp{copysign@var{m}3}
|
3311 |
|
|
Store a value with the magnitude of operand 1 and the sign of operand
|
3312 |
|
|
2 into operand 0.
|
3313 |
|
|
|
3314 |
|
|
The @code{copysign} built-in function of C always uses the mode which
|
3315 |
|
|
corresponds to the C data type @code{double} and the @code{copysignf}
|
3316 |
|
|
built-in function uses the mode which corresponds to the C data
|
3317 |
|
|
type @code{float}.
|
3318 |
|
|
|
3319 |
|
|
@cindex @code{ffs@var{m}2} instruction pattern
|
3320 |
|
|
@item @samp{ffs@var{m}2}
|
3321 |
|
|
Store into operand 0 one plus the index of the least significant 1-bit
|
3322 |
|
|
of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
|
3323 |
|
|
of operand 0; operand 1's mode is specified by the instruction
|
3324 |
|
|
pattern, and the compiler will convert the operand to that mode before
|
3325 |
|
|
generating the instruction.
|
3326 |
|
|
|
3327 |
|
|
The @code{ffs} built-in function of C always uses the mode which
|
3328 |
|
|
corresponds to the C data type @code{int}.
|
3329 |
|
|
|
3330 |
|
|
@cindex @code{clz@var{m}2} instruction pattern
|
3331 |
|
|
@item @samp{clz@var{m}2}
|
3332 |
|
|
Store into operand 0 the number of leading 0-bits in @var{x}, starting
|
3333 |
|
|
at the most significant bit position. If @var{x} is 0, the result is
|
3334 |
|
|
undefined. @var{m} is the mode of operand 0; operand 1's mode is
|
3335 |
|
|
specified by the instruction pattern, and the compiler will convert the
|
3336 |
|
|
operand to that mode before generating the instruction.
|
3337 |
|
|
|
3338 |
|
|
@cindex @code{ctz@var{m}2} instruction pattern
|
3339 |
|
|
@item @samp{ctz@var{m}2}
|
3340 |
|
|
Store into operand 0 the number of trailing 0-bits in @var{x}, starting
|
3341 |
|
|
at the least significant bit position. If @var{x} is 0, the result is
|
3342 |
|
|
undefined. @var{m} is the mode of operand 0; operand 1's mode is
|
3343 |
|
|
specified by the instruction pattern, and the compiler will convert the
|
3344 |
|
|
operand to that mode before generating the instruction.
|
3345 |
|
|
|
3346 |
|
|
@cindex @code{popcount@var{m}2} instruction pattern
|
3347 |
|
|
@item @samp{popcount@var{m}2}
|
3348 |
|
|
Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
|
3349 |
|
|
mode of operand 0; operand 1's mode is specified by the instruction
|
3350 |
|
|
pattern, and the compiler will convert the operand to that mode before
|
3351 |
|
|
generating the instruction.
|
3352 |
|
|
|
3353 |
|
|
@cindex @code{parity@var{m}2} instruction pattern
|
3354 |
|
|
@item @samp{parity@var{m}2}
|
3355 |
|
|
Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
|
3356 |
|
|
in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
|
3357 |
|
|
is specified by the instruction pattern, and the compiler will convert
|
3358 |
|
|
the operand to that mode before generating the instruction.
|
3359 |
|
|
|
3360 |
|
|
@cindex @code{one_cmpl@var{m}2} instruction pattern
|
3361 |
|
|
@item @samp{one_cmpl@var{m}2}
|
3362 |
|
|
Store the bitwise-complement of operand 1 into operand 0.
|
3363 |
|
|
|
3364 |
|
|
@cindex @code{cmp@var{m}} instruction pattern
|
3365 |
|
|
@item @samp{cmp@var{m}}
|
3366 |
|
|
Compare operand 0 and operand 1, and set the condition codes.
|
3367 |
|
|
The RTL pattern should look like this:
|
3368 |
|
|
|
3369 |
|
|
@smallexample
|
3370 |
|
|
(set (cc0) (compare (match_operand:@var{m} 0 @dots{})
|
3371 |
|
|
(match_operand:@var{m} 1 @dots{})))
|
3372 |
|
|
@end smallexample
|
3373 |
|
|
|
3374 |
|
|
@cindex @code{tst@var{m}} instruction pattern
|
3375 |
|
|
@item @samp{tst@var{m}}
|
3376 |
|
|
Compare operand 0 against zero, and set the condition codes.
|
3377 |
|
|
The RTL pattern should look like this:
|
3378 |
|
|
|
3379 |
|
|
@smallexample
|
3380 |
|
|
(set (cc0) (match_operand:@var{m} 0 @dots{}))
|
3381 |
|
|
@end smallexample
|
3382 |
|
|
|
3383 |
|
|
@samp{tst@var{m}} patterns should not be defined for machines that do
|
3384 |
|
|
not use @code{(cc0)}. Doing so would confuse the optimizer since it
|
3385 |
|
|
would no longer be clear which @code{set} operations were comparisons.
|
3386 |
|
|
The @samp{cmp@var{m}} patterns should be used instead.
|
3387 |
|
|
|
3388 |
|
|
@cindex @code{movmem@var{m}} instruction pattern
|
3389 |
|
|
@item @samp{movmem@var{m}}
|
3390 |
|
|
Block move instruction. The destination and source blocks of memory
|
3391 |
|
|
are the first two operands, and both are @code{mem:BLK}s with an
|
3392 |
|
|
address in mode @code{Pmode}.
|
3393 |
|
|
|
3394 |
|
|
The number of bytes to move is the third operand, in mode @var{m}.
|
3395 |
|
|
Usually, you specify @code{word_mode} for @var{m}. However, if you can
|
3396 |
|
|
generate better code knowing the range of valid lengths is smaller than
|
3397 |
|
|
those representable in a full word, you should provide a pattern with a
|
3398 |
|
|
mode corresponding to the range of values you can handle efficiently
|
3399 |
|
|
(e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
|
3400 |
|
|
that appear negative) and also a pattern with @code{word_mode}.
|
3401 |
|
|
|
3402 |
|
|
The fourth operand is the known shared alignment of the source and
|
3403 |
|
|
destination, in the form of a @code{const_int} rtx. Thus, if the
|
3404 |
|
|
compiler knows that both source and destination are word-aligned,
|
3405 |
|
|
it may provide the value 4 for this operand.
|
3406 |
|
|
|
3407 |
|
|
Descriptions of multiple @code{movmem@var{m}} patterns can only be
|
3408 |
|
|
beneficial if the patterns for smaller modes have fewer restrictions
|
3409 |
|
|
on their first, second and fourth operands. Note that the mode @var{m}
|
3410 |
|
|
in @code{movmem@var{m}} does not impose any restriction on the mode of
|
3411 |
|
|
individually moved data units in the block.
|
3412 |
|
|
|
3413 |
|
|
These patterns need not give special consideration to the possibility
|
3414 |
|
|
that the source and destination strings might overlap.
|
3415 |
|
|
|
3416 |
|
|
@cindex @code{movstr} instruction pattern
|
3417 |
|
|
@item @samp{movstr}
|
3418 |
|
|
String copy instruction, with @code{stpcpy} semantics. Operand 0 is
|
3419 |
|
|
an output operand in mode @code{Pmode}. The addresses of the
|
3420 |
|
|
destination and source strings are operands 1 and 2, and both are
|
3421 |
|
|
@code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
|
3422 |
|
|
the expansion of this pattern should store in operand 0 the address in
|
3423 |
|
|
which the @code{NUL} terminator was stored in the destination string.
|
3424 |
|
|
|
3425 |
|
|
@cindex @code{setmem@var{m}} instruction pattern
|
3426 |
|
|
@item @samp{setmem@var{m}}
|
3427 |
|
|
Block set instruction. The destination string is the first operand,
|
3428 |
|
|
given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
|
3429 |
|
|
number of bytes to set is the second operand, in mode @var{m}. The value to
|
3430 |
|
|
initialize the memory with is the third operand. Targets that only support the
|
3431 |
|
|
clearing of memory should reject any value that is not the constant 0. See
|
3432 |
|
|
@samp{movmem@var{m}} for a discussion of the choice of mode.
|
3433 |
|
|
|
3434 |
|
|
The fourth operand is the known alignment of the destination, in the form
|
3435 |
|
|
of a @code{const_int} rtx. Thus, if the compiler knows that the
|
3436 |
|
|
destination is word-aligned, it may provide the value 4 for this
|
3437 |
|
|
operand.
|
3438 |
|
|
|
3439 |
|
|
The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
|
3440 |
|
|
|
3441 |
|
|
@cindex @code{cmpstrn@var{m}} instruction pattern
|
3442 |
|
|
@item @samp{cmpstrn@var{m}}
|
3443 |
|
|
String compare instruction, with five operands. Operand 0 is the output;
|
3444 |
|
|
it has mode @var{m}. The remaining four operands are like the operands
|
3445 |
|
|
of @samp{movmem@var{m}}. The two memory blocks specified are compared
|
3446 |
|
|
byte by byte in lexicographic order starting at the beginning of each
|
3447 |
|
|
string. The instruction is not allowed to prefetch more than one byte
|
3448 |
|
|
at a time since either string may end in the first byte and reading past
|
3449 |
|
|
that may access an invalid page or segment and cause a fault. The
|
3450 |
|
|
effect of the instruction is to store a value in operand 0 whose sign
|
3451 |
|
|
indicates the result of the comparison.
|
3452 |
|
|
|
3453 |
|
|
@cindex @code{cmpstr@var{m}} instruction pattern
|
3454 |
|
|
@item @samp{cmpstr@var{m}}
|
3455 |
|
|
String compare instruction, without known maximum length. Operand 0 is the
|
3456 |
|
|
output; it has mode @var{m}. The second and third operand are the blocks of
|
3457 |
|
|
memory to be compared; both are @code{mem:BLK} with an address in mode
|
3458 |
|
|
@code{Pmode}.
|
3459 |
|
|
|
3460 |
|
|
The fourth operand is the known shared alignment of the source and
|
3461 |
|
|
destination, in the form of a @code{const_int} rtx. Thus, if the
|
3462 |
|
|
compiler knows that both source and destination are word-aligned,
|
3463 |
|
|
it may provide the value 4 for this operand.
|
3464 |
|
|
|
3465 |
|
|
The two memory blocks specified are compared byte by byte in lexicographic
|
3466 |
|
|
order starting at the beginning of each string. The instruction is not allowed
|
3467 |
|
|
to prefetch more than one byte at a time since either string may end in the
|
3468 |
|
|
first byte and reading past that may access an invalid page or segment and
|
3469 |
|
|
cause a fault. The effect of the instruction is to store a value in operand 0
|
3470 |
|
|
whose sign indicates the result of the comparison.
|
3471 |
|
|
|
3472 |
|
|
@cindex @code{cmpmem@var{m}} instruction pattern
|
3473 |
|
|
@item @samp{cmpmem@var{m}}
|
3474 |
|
|
Block compare instruction, with five operands like the operands
|
3475 |
|
|
of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
|
3476 |
|
|
byte by byte in lexicographic order starting at the beginning of each
|
3477 |
|
|
block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
|
3478 |
|
|
any bytes in the two memory blocks. The effect of the instruction is
|
3479 |
|
|
to store a value in operand 0 whose sign indicates the result of the
|
3480 |
|
|
comparison.
|
3481 |
|
|
|
3482 |
|
|
@cindex @code{strlen@var{m}} instruction pattern
|
3483 |
|
|
@item @samp{strlen@var{m}}
|
3484 |
|
|
Compute the length of a string, with three operands.
|
3485 |
|
|
Operand 0 is the result (of mode @var{m}), operand 1 is
|
3486 |
|
|
a @code{mem} referring to the first character of the string,
|
3487 |
|
|
operand 2 is the character to search for (normally zero),
|
3488 |
|
|
and operand 3 is a constant describing the known alignment
|
3489 |
|
|
of the beginning of the string.
|
3490 |
|
|
|
3491 |
|
|
@cindex @code{float@var{mn}2} instruction pattern
|
3492 |
|
|
@item @samp{float@var{m}@var{n}2}
|
3493 |
|
|
Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
|
3494 |
|
|
floating point mode @var{n} and store in operand 0 (which has mode
|
3495 |
|
|
@var{n}).
|
3496 |
|
|
|
3497 |
|
|
@cindex @code{floatuns@var{mn}2} instruction pattern
|
3498 |
|
|
@item @samp{floatuns@var{m}@var{n}2}
|
3499 |
|
|
Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
|
3500 |
|
|
to floating point mode @var{n} and store in operand 0 (which has mode
|
3501 |
|
|
@var{n}).
|
3502 |
|
|
|
3503 |
|
|
@cindex @code{fix@var{mn}2} instruction pattern
|
3504 |
|
|
@item @samp{fix@var{m}@var{n}2}
|
3505 |
|
|
Convert operand 1 (valid for floating point mode @var{m}) to fixed
|
3506 |
|
|
point mode @var{n} as a signed number and store in operand 0 (which
|
3507 |
|
|
has mode @var{n}). This instruction's result is defined only when
|
3508 |
|
|
the value of operand 1 is an integer.
|
3509 |
|
|
|
3510 |
|
|
If the machine description defines this pattern, it also needs to
|
3511 |
|
|
define the @code{ftrunc} pattern.
|
3512 |
|
|
|
3513 |
|
|
@cindex @code{fixuns@var{mn}2} instruction pattern
|
3514 |
|
|
@item @samp{fixuns@var{m}@var{n}2}
|
3515 |
|
|
Convert operand 1 (valid for floating point mode @var{m}) to fixed
|
3516 |
|
|
point mode @var{n} as an unsigned number and store in operand 0 (which
|
3517 |
|
|
has mode @var{n}). This instruction's result is defined only when the
|
3518 |
|
|
value of operand 1 is an integer.
|
3519 |
|
|
|
3520 |
|
|
@cindex @code{ftrunc@var{m}2} instruction pattern
|
3521 |
|
|
@item @samp{ftrunc@var{m}2}
|
3522 |
|
|
Convert operand 1 (valid for floating point mode @var{m}) to an
|
3523 |
|
|
integer value, still represented in floating point mode @var{m}, and
|
3524 |
|
|
store it in operand 0 (valid for floating point mode @var{m}).
|
3525 |
|
|
|
3526 |
|
|
@cindex @code{fix_trunc@var{mn}2} instruction pattern
|
3527 |
|
|
@item @samp{fix_trunc@var{m}@var{n}2}
|
3528 |
|
|
Like @samp{fix@var{m}@var{n}2} but works for any floating point value
|
3529 |
|
|
of mode @var{m} by converting the value to an integer.
|
3530 |
|
|
|
3531 |
|
|
@cindex @code{fixuns_trunc@var{mn}2} instruction pattern
|
3532 |
|
|
@item @samp{fixuns_trunc@var{m}@var{n}2}
|
3533 |
|
|
Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
|
3534 |
|
|
value of mode @var{m} by converting the value to an integer.
|
3535 |
|
|
|
3536 |
|
|
@cindex @code{trunc@var{mn}2} instruction pattern
|
3537 |
|
|
@item @samp{trunc@var{m}@var{n}2}
|
3538 |
|
|
Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
|
3539 |
|
|
store in operand 0 (which has mode @var{n}). Both modes must be fixed
|
3540 |
|
|
point or both floating point.
|
3541 |
|
|
|
3542 |
|
|
@cindex @code{extend@var{mn}2} instruction pattern
|
3543 |
|
|
@item @samp{extend@var{m}@var{n}2}
|
3544 |
|
|
Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
|
3545 |
|
|
store in operand 0 (which has mode @var{n}). Both modes must be fixed
|
3546 |
|
|
point or both floating point.
|
3547 |
|
|
|
3548 |
|
|
@cindex @code{zero_extend@var{mn}2} instruction pattern
|
3549 |
|
|
@item @samp{zero_extend@var{m}@var{n}2}
|
3550 |
|
|
Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
|
3551 |
|
|
store in operand 0 (which has mode @var{n}). Both modes must be fixed
|
3552 |
|
|
point.
|
3553 |
|
|
|
3554 |
|
|
@cindex @code{extv} instruction pattern
|
3555 |
|
|
@item @samp{extv}
|
3556 |
|
|
Extract a bit-field from operand 1 (a register or memory operand), where
|
3557 |
|
|
operand 2 specifies the width in bits and operand 3 the starting bit,
|
3558 |
|
|
and store it in operand 0. Operand 0 must have mode @code{word_mode}.
|
3559 |
|
|
Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
|
3560 |
|
|
@code{word_mode} is allowed only for registers. Operands 2 and 3 must
|
3561 |
|
|
be valid for @code{word_mode}.
|
3562 |
|
|
|
3563 |
|
|
The RTL generation pass generates this instruction only with constants
|
3564 |
|
|
for operands 2 and 3 and the constant is never zero for operand 2.
|
3565 |
|
|
|
3566 |
|
|
The bit-field value is sign-extended to a full word integer
|
3567 |
|
|
before it is stored in operand 0.
|
3568 |
|
|
|
3569 |
|
|
@cindex @code{extzv} instruction pattern
|
3570 |
|
|
@item @samp{extzv}
|
3571 |
|
|
Like @samp{extv} except that the bit-field value is zero-extended.
|
3572 |
|
|
|
3573 |
|
|
@cindex @code{insv} instruction pattern
|
3574 |
|
|
@item @samp{insv}
|
3575 |
|
|
Store operand 3 (which must be valid for @code{word_mode}) into a
|
3576 |
|
|
bit-field in operand 0, where operand 1 specifies the width in bits and
|
3577 |
|
|
operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
|
3578 |
|
|
@code{word_mode}; often @code{word_mode} is allowed only for registers.
|
3579 |
|
|
Operands 1 and 2 must be valid for @code{word_mode}.
|
3580 |
|
|
|
3581 |
|
|
The RTL generation pass generates this instruction only with constants
|
3582 |
|
|
for operands 1 and 2 and the constant is never zero for operand 1.
|
3583 |
|
|
|
3584 |
|
|
@cindex @code{mov@var{mode}cc} instruction pattern
|
3585 |
|
|
@item @samp{mov@var{mode}cc}
|
3586 |
|
|
Conditionally move operand 2 or operand 3 into operand 0 according to the
|
3587 |
|
|
comparison in operand 1. If the comparison is true, operand 2 is moved
|
3588 |
|
|
into operand 0, otherwise operand 3 is moved.
|
3589 |
|
|
|
3590 |
|
|
The mode of the operands being compared need not be the same as the operands
|
3591 |
|
|
being moved. Some machines, sparc64 for example, have instructions that
|
3592 |
|
|
conditionally move an integer value based on the floating point condition
|
3593 |
|
|
codes and vice versa.
|
3594 |
|
|
|
3595 |
|
|
If the machine does not have conditional move instructions, do not
|
3596 |
|
|
define these patterns.
|
3597 |
|
|
|
3598 |
|
|
@cindex @code{add@var{mode}cc} instruction pattern
|
3599 |
|
|
@item @samp{add@var{mode}cc}
|
3600 |
|
|
Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
|
3601 |
|
|
move operand 2 or (operands 2 + operand 3) into operand 0 according to the
|
3602 |
|
|
comparison in operand 1. If the comparison is true, operand 2 is moved into
|
3603 |
|
|
operand 0, otherwise (operand 2 + operand 3) is moved.
|
3604 |
|
|
|
3605 |
|
|
@cindex @code{s@var{cond}} instruction pattern
|
3606 |
|
|
@item @samp{s@var{cond}}
|
3607 |
|
|
Store zero or nonzero in the operand according to the condition codes.
|
3608 |
|
|
Value stored is nonzero iff the condition @var{cond} is true.
|
3609 |
|
|
@var{cond} is the name of a comparison operation expression code, such
|
3610 |
|
|
as @code{eq}, @code{lt} or @code{leu}.
|
3611 |
|
|
|
3612 |
|
|
You specify the mode that the operand must have when you write the
|
3613 |
|
|
@code{match_operand} expression. The compiler automatically sees
|
3614 |
|
|
which mode you have used and supplies an operand of that mode.
|
3615 |
|
|
|
3616 |
|
|
The value stored for a true condition must have 1 as its low bit, or
|
3617 |
|
|
else must be negative. Otherwise the instruction is not suitable and
|
3618 |
|
|
you should omit it from the machine description. You describe to the
|
3619 |
|
|
compiler exactly which value is stored by defining the macro
|
3620 |
|
|
@code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
|
3621 |
|
|
found that can be used for all the @samp{s@var{cond}} patterns, you
|
3622 |
|
|
should omit those operations from the machine description.
|
3623 |
|
|
|
3624 |
|
|
These operations may fail, but should do so only in relatively
|
3625 |
|
|
uncommon cases; if they would fail for common cases involving
|
3626 |
|
|
integer comparisons, it is best to omit these patterns.
|
3627 |
|
|
|
3628 |
|
|
If these operations are omitted, the compiler will usually generate code
|
3629 |
|
|
that copies the constant one to the target and branches around an
|
3630 |
|
|
assignment of zero to the target. If this code is more efficient than
|
3631 |
|
|
the potential instructions used for the @samp{s@var{cond}} pattern
|
3632 |
|
|
followed by those required to convert the result into a 1 or a zero in
|
3633 |
|
|
@code{SImode}, you should omit the @samp{s@var{cond}} operations from
|
3634 |
|
|
the machine description.
|
3635 |
|
|
|
3636 |
|
|
@cindex @code{b@var{cond}} instruction pattern
|
3637 |
|
|
@item @samp{b@var{cond}}
|
3638 |
|
|
Conditional branch instruction. Operand 0 is a @code{label_ref} that
|
3639 |
|
|
refers to the label to jump to. Jump if the condition codes meet
|
3640 |
|
|
condition @var{cond}.
|
3641 |
|
|
|
3642 |
|
|
Some machines do not follow the model assumed here where a comparison
|
3643 |
|
|
instruction is followed by a conditional branch instruction. In that
|
3644 |
|
|
case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
|
3645 |
|
|
simply store the operands away and generate all the required insns in a
|
3646 |
|
|
@code{define_expand} (@pxref{Expander Definitions}) for the conditional
|
3647 |
|
|
branch operations. All calls to expand @samp{b@var{cond}} patterns are
|
3648 |
|
|
immediately preceded by calls to expand either a @samp{cmp@var{m}}
|
3649 |
|
|
pattern or a @samp{tst@var{m}} pattern.
|
3650 |
|
|
|
3651 |
|
|
Machines that use a pseudo register for the condition code value, or
|
3652 |
|
|
where the mode used for the comparison depends on the condition being
|
3653 |
|
|
tested, should also use the above mechanism. @xref{Jump Patterns}.
|
3654 |
|
|
|
3655 |
|
|
The above discussion also applies to the @samp{mov@var{mode}cc} and
|
3656 |
|
|
@samp{s@var{cond}} patterns.
|
3657 |
|
|
|
3658 |
|
|
@cindex @code{cbranch@var{mode}4} instruction pattern
|
3659 |
|
|
@item @samp{cbranch@var{mode}4}
|
3660 |
|
|
Conditional branch instruction combined with a compare instruction.
|
3661 |
|
|
Operand 0 is a comparison operator. Operand 1 and operand 2 are the
|
3662 |
|
|
first and second operands of the comparison, respectively. Operand 3
|
3663 |
|
|
is a @code{label_ref} that refers to the label to jump to.
|
3664 |
|
|
|
3665 |
|
|
@cindex @code{jump} instruction pattern
|
3666 |
|
|
@item @samp{jump}
|
3667 |
|
|
A jump inside a function; an unconditional branch. Operand 0 is the
|
3668 |
|
|
@code{label_ref} of the label to jump to. This pattern name is mandatory
|
3669 |
|
|
on all machines.
|
3670 |
|
|
|
3671 |
|
|
@cindex @code{call} instruction pattern
|
3672 |
|
|
@item @samp{call}
|
3673 |
|
|
Subroutine call instruction returning no value. Operand 0 is the
|
3674 |
|
|
function to call; operand 1 is the number of bytes of arguments pushed
|
3675 |
|
|
as a @code{const_int}; operand 2 is the number of registers used as
|
3676 |
|
|
operands.
|
3677 |
|
|
|
3678 |
|
|
On most machines, operand 2 is not actually stored into the RTL
|
3679 |
|
|
pattern. It is supplied for the sake of some RISC machines which need
|
3680 |
|
|
to put this information into the assembler code; they can put it in
|
3681 |
|
|
the RTL instead of operand 1.
|
3682 |
|
|
|
3683 |
|
|
Operand 0 should be a @code{mem} RTX whose address is the address of the
|
3684 |
|
|
function. Note, however, that this address can be a @code{symbol_ref}
|
3685 |
|
|
expression even if it would not be a legitimate memory address on the
|
3686 |
|
|
target machine. If it is also not a valid argument for a call
|
3687 |
|
|
instruction, the pattern for this operation should be a
|
3688 |
|
|
@code{define_expand} (@pxref{Expander Definitions}) that places the
|
3689 |
|
|
address into a register and uses that register in the call instruction.
|
3690 |
|
|
|
3691 |
|
|
@cindex @code{call_value} instruction pattern
|
3692 |
|
|
@item @samp{call_value}
|
3693 |
|
|
Subroutine call instruction returning a value. Operand 0 is the hard
|
3694 |
|
|
register in which the value is returned. There are three more
|
3695 |
|
|
operands, the same as the three operands of the @samp{call}
|
3696 |
|
|
instruction (but with numbers increased by one).
|
3697 |
|
|
|
3698 |
|
|
Subroutines that return @code{BLKmode} objects use the @samp{call}
|
3699 |
|
|
insn.
|
3700 |
|
|
|
3701 |
|
|
@cindex @code{call_pop} instruction pattern
|
3702 |
|
|
@cindex @code{call_value_pop} instruction pattern
|
3703 |
|
|
@item @samp{call_pop}, @samp{call_value_pop}
|
3704 |
|
|
Similar to @samp{call} and @samp{call_value}, except used if defined and
|
3705 |
|
|
if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
|
3706 |
|
|
that contains both the function call and a @code{set} to indicate the
|
3707 |
|
|
adjustment made to the frame pointer.
|
3708 |
|
|
|
3709 |
|
|
For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
|
3710 |
|
|
patterns increases the number of functions for which the frame pointer
|
3711 |
|
|
can be eliminated, if desired.
|
3712 |
|
|
|
3713 |
|
|
@cindex @code{untyped_call} instruction pattern
|
3714 |
|
|
@item @samp{untyped_call}
|
3715 |
|
|
Subroutine call instruction returning a value of any type. Operand 0 is
|
3716 |
|
|
the function to call; operand 1 is a memory location where the result of
|
3717 |
|
|
calling the function is to be stored; operand 2 is a @code{parallel}
|
3718 |
|
|
expression where each element is a @code{set} expression that indicates
|
3719 |
|
|
the saving of a function return value into the result block.
|
3720 |
|
|
|
3721 |
|
|
This instruction pattern should be defined to support
|
3722 |
|
|
@code{__builtin_apply} on machines where special instructions are needed
|
3723 |
|
|
to call a subroutine with arbitrary arguments or to save the value
|
3724 |
|
|
returned. This instruction pattern is required on machines that have
|
3725 |
|
|
multiple registers that can hold a return value
|
3726 |
|
|
(i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
|
3727 |
|
|
|
3728 |
|
|
@cindex @code{return} instruction pattern
|
3729 |
|
|
@item @samp{return}
|
3730 |
|
|
Subroutine return instruction. This instruction pattern name should be
|
3731 |
|
|
defined only if a single instruction can do all the work of returning
|
3732 |
|
|
from a function.
|
3733 |
|
|
|
3734 |
|
|
Like the @samp{mov@var{m}} patterns, this pattern is also used after the
|
3735 |
|
|
RTL generation phase. In this case it is to support machines where
|
3736 |
|
|
multiple instructions are usually needed to return from a function, but
|
3737 |
|
|
some class of functions only requires one instruction to implement a
|
3738 |
|
|
return. Normally, the applicable functions are those which do not need
|
3739 |
|
|
to save any registers or allocate stack space.
|
3740 |
|
|
|
3741 |
|
|
@findex reload_completed
|
3742 |
|
|
@findex leaf_function_p
|
3743 |
|
|
For such machines, the condition specified in this pattern should only
|
3744 |
|
|
be true when @code{reload_completed} is nonzero and the function's
|
3745 |
|
|
epilogue would only be a single instruction. For machines with register
|
3746 |
|
|
windows, the routine @code{leaf_function_p} may be used to determine if
|
3747 |
|
|
a register window push is required.
|
3748 |
|
|
|
3749 |
|
|
Machines that have conditional return instructions should define patterns
|
3750 |
|
|
such as
|
3751 |
|
|
|
3752 |
|
|
@smallexample
|
3753 |
|
|
(define_insn ""
|
3754 |
|
|
[(set (pc)
|
3755 |
|
|
(if_then_else (match_operator
|
3756 |
|
|
|
3757 |
|
|
[(cc0) (const_int 0)])
|
3758 |
|
|
(return)
|
3759 |
|
|
(pc)))]
|
3760 |
|
|
"@var{condition}"
|
3761 |
|
|
"@dots{}")
|
3762 |
|
|
@end smallexample
|
3763 |
|
|
|
3764 |
|
|
where @var{condition} would normally be the same condition specified on the
|
3765 |
|
|
named @samp{return} pattern.
|
3766 |
|
|
|
3767 |
|
|
@cindex @code{untyped_return} instruction pattern
|
3768 |
|
|
@item @samp{untyped_return}
|
3769 |
|
|
Untyped subroutine return instruction. This instruction pattern should
|
3770 |
|
|
be defined to support @code{__builtin_return} on machines where special
|
3771 |
|
|
instructions are needed to return a value of any type.
|
3772 |
|
|
|
3773 |
|
|
Operand 0 is a memory location where the result of calling a function
|
3774 |
|
|
with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
|
3775 |
|
|
expression where each element is a @code{set} expression that indicates
|
3776 |
|
|
the restoring of a function return value from the result block.
|
3777 |
|
|
|
3778 |
|
|
@cindex @code{nop} instruction pattern
|
3779 |
|
|
@item @samp{nop}
|
3780 |
|
|
No-op instruction. This instruction pattern name should always be defined
|
3781 |
|
|
to output a no-op in assembler code. @code{(const_int 0)} will do as an
|
3782 |
|
|
RTL pattern.
|
3783 |
|
|
|
3784 |
|
|
@cindex @code{indirect_jump} instruction pattern
|
3785 |
|
|
@item @samp{indirect_jump}
|
3786 |
|
|
An instruction to jump to an address which is operand zero.
|
3787 |
|
|
This pattern name is mandatory on all machines.
|
3788 |
|
|
|
3789 |
|
|
@cindex @code{casesi} instruction pattern
|
3790 |
|
|
@item @samp{casesi}
|
3791 |
|
|
Instruction to jump through a dispatch table, including bounds checking.
|
3792 |
|
|
This instruction takes five operands:
|
3793 |
|
|
|
3794 |
|
|
@enumerate
|
3795 |
|
|
@item
|
3796 |
|
|
The index to dispatch on, which has mode @code{SImode}.
|
3797 |
|
|
|
3798 |
|
|
@item
|
3799 |
|
|
The lower bound for indices in the table, an integer constant.
|
3800 |
|
|
|
3801 |
|
|
@item
|
3802 |
|
|
The total range of indices in the table---the largest index
|
3803 |
|
|
minus the smallest one (both inclusive).
|
3804 |
|
|
|
3805 |
|
|
@item
|
3806 |
|
|
A label that precedes the table itself.
|
3807 |
|
|
|
3808 |
|
|
@item
|
3809 |
|
|
A label to jump to if the index has a value outside the bounds.
|
3810 |
|
|
@end enumerate
|
3811 |
|
|
|
3812 |
|
|
The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
|
3813 |
|
|
@code{jump_insn}. The number of elements in the table is one plus the
|
3814 |
|
|
difference between the upper bound and the lower bound.
|
3815 |
|
|
|
3816 |
|
|
@cindex @code{tablejump} instruction pattern
|
3817 |
|
|
@item @samp{tablejump}
|
3818 |
|
|
Instruction to jump to a variable address. This is a low-level
|
3819 |
|
|
capability which can be used to implement a dispatch table when there
|
3820 |
|
|
is no @samp{casesi} pattern.
|
3821 |
|
|
|
3822 |
|
|
This pattern requires two operands: the address or offset, and a label
|
3823 |
|
|
which should immediately precede the jump table. If the macro
|
3824 |
|
|
@code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
|
3825 |
|
|
operand is an offset which counts from the address of the table; otherwise,
|
3826 |
|
|
it is an absolute address to jump to. In either case, the first operand has
|
3827 |
|
|
mode @code{Pmode}.
|
3828 |
|
|
|
3829 |
|
|
The @samp{tablejump} insn is always the last insn before the jump
|
3830 |
|
|
table it uses. Its assembler code normally has no need to use the
|
3831 |
|
|
second operand, but you should incorporate it in the RTL pattern so
|
3832 |
|
|
that the jump optimizer will not delete the table as unreachable code.
|
3833 |
|
|
|
3834 |
|
|
|
3835 |
|
|
@cindex @code{decrement_and_branch_until_zero} instruction pattern
|
3836 |
|
|
@item @samp{decrement_and_branch_until_zero}
|
3837 |
|
|
Conditional branch instruction that decrements a register and
|
3838 |
|
|
jumps if the register is nonzero. Operand 0 is the register to
|
3839 |
|
|
decrement and test; operand 1 is the label to jump to if the
|
3840 |
|
|
register is nonzero. @xref{Looping Patterns}.
|
3841 |
|
|
|
3842 |
|
|
This optional instruction pattern is only used by the combiner,
|
3843 |
|
|
typically for loops reversed by the loop optimizer when strength
|
3844 |
|
|
reduction is enabled.
|
3845 |
|
|
|
3846 |
|
|
@cindex @code{doloop_end} instruction pattern
|
3847 |
|
|
@item @samp{doloop_end}
|
3848 |
|
|
Conditional branch instruction that decrements a register and jumps if
|
3849 |
|
|
the register is nonzero. This instruction takes five operands: Operand
|
3850 |
|
|
|
3851 |
|
|
iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
|
3852 |
|
|
determined until run-time; operand 2 is the actual or estimated maximum
|
3853 |
|
|
number of iterations as a @code{const_int}; operand 3 is the number of
|
3854 |
|
|
enclosed loops as a @code{const_int} (an innermost loop has a value of
|
3855 |
|
|
1); operand 4 is the label to jump to if the register is nonzero.
|
3856 |
|
|
@xref{Looping Patterns}.
|
3857 |
|
|
|
3858 |
|
|
This optional instruction pattern should be defined for machines with
|
3859 |
|
|
low-overhead looping instructions as the loop optimizer will try to
|
3860 |
|
|
modify suitable loops to utilize it. If nested low-overhead looping is
|
3861 |
|
|
not supported, use a @code{define_expand} (@pxref{Expander Definitions})
|
3862 |
|
|
and make the pattern fail if operand 3 is not @code{const1_rtx}.
|
3863 |
|
|
Similarly, if the actual or estimated maximum number of iterations is
|
3864 |
|
|
too large for this instruction, make it fail.
|
3865 |
|
|
|
3866 |
|
|
@cindex @code{doloop_begin} instruction pattern
|
3867 |
|
|
@item @samp{doloop_begin}
|
3868 |
|
|
Companion instruction to @code{doloop_end} required for machines that
|
3869 |
|
|
need to perform some initialization, such as loading special registers
|
3870 |
|
|
used by a low-overhead looping instruction. If initialization insns do
|
3871 |
|
|
not always need to be emitted, use a @code{define_expand}
|
3872 |
|
|
(@pxref{Expander Definitions}) and make it fail.
|
3873 |
|
|
|
3874 |
|
|
|
3875 |
|
|
@cindex @code{canonicalize_funcptr_for_compare} instruction pattern
|
3876 |
|
|
@item @samp{canonicalize_funcptr_for_compare}
|
3877 |
|
|
Canonicalize the function pointer in operand 1 and store the result
|
3878 |
|
|
into operand 0.
|
3879 |
|
|
|
3880 |
|
|
Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
|
3881 |
|
|
may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
|
3882 |
|
|
and also has mode @code{Pmode}.
|
3883 |
|
|
|
3884 |
|
|
Canonicalization of a function pointer usually involves computing
|
3885 |
|
|
the address of the function which would be called if the function
|
3886 |
|
|
pointer were used in an indirect call.
|
3887 |
|
|
|
3888 |
|
|
Only define this pattern if function pointers on the target machine
|
3889 |
|
|
can have different values but still call the same function when
|
3890 |
|
|
used in an indirect call.
|
3891 |
|
|
|
3892 |
|
|
@cindex @code{save_stack_block} instruction pattern
|
3893 |
|
|
@cindex @code{save_stack_function} instruction pattern
|
3894 |
|
|
@cindex @code{save_stack_nonlocal} instruction pattern
|
3895 |
|
|
@cindex @code{restore_stack_block} instruction pattern
|
3896 |
|
|
@cindex @code{restore_stack_function} instruction pattern
|
3897 |
|
|
@cindex @code{restore_stack_nonlocal} instruction pattern
|
3898 |
|
|
@item @samp{save_stack_block}
|
3899 |
|
|
@itemx @samp{save_stack_function}
|
3900 |
|
|
@itemx @samp{save_stack_nonlocal}
|
3901 |
|
|
@itemx @samp{restore_stack_block}
|
3902 |
|
|
@itemx @samp{restore_stack_function}
|
3903 |
|
|
@itemx @samp{restore_stack_nonlocal}
|
3904 |
|
|
Most machines save and restore the stack pointer by copying it to or
|
3905 |
|
|
from an object of mode @code{Pmode}. Do not define these patterns on
|
3906 |
|
|
such machines.
|
3907 |
|
|
|
3908 |
|
|
Some machines require special handling for stack pointer saves and
|
3909 |
|
|
restores. On those machines, define the patterns corresponding to the
|
3910 |
|
|
non-standard cases by using a @code{define_expand} (@pxref{Expander
|
3911 |
|
|
Definitions}) that produces the required insns. The three types of
|
3912 |
|
|
saves and restores are:
|
3913 |
|
|
|
3914 |
|
|
@enumerate
|
3915 |
|
|
@item
|
3916 |
|
|
@samp{save_stack_block} saves the stack pointer at the start of a block
|
3917 |
|
|
that allocates a variable-sized object, and @samp{restore_stack_block}
|
3918 |
|
|
restores the stack pointer when the block is exited.
|
3919 |
|
|
|
3920 |
|
|
@item
|
3921 |
|
|
@samp{save_stack_function} and @samp{restore_stack_function} do a
|
3922 |
|
|
similar job for the outermost block of a function and are used when the
|
3923 |
|
|
function allocates variable-sized objects or calls @code{alloca}. Only
|
3924 |
|
|
the epilogue uses the restored stack pointer, allowing a simpler save or
|
3925 |
|
|
restore sequence on some machines.
|
3926 |
|
|
|
3927 |
|
|
@item
|
3928 |
|
|
@samp{save_stack_nonlocal} is used in functions that contain labels
|
3929 |
|
|
branched to by nested functions. It saves the stack pointer in such a
|
3930 |
|
|
way that the inner function can use @samp{restore_stack_nonlocal} to
|
3931 |
|
|
restore the stack pointer. The compiler generates code to restore the
|
3932 |
|
|
frame and argument pointer registers, but some machines require saving
|
3933 |
|
|
and restoring additional data such as register window information or
|
3934 |
|
|
stack backchains. Place insns in these patterns to save and restore any
|
3935 |
|
|
such required data.
|
3936 |
|
|
@end enumerate
|
3937 |
|
|
|
3938 |
|
|
When saving the stack pointer, operand 0 is the save area and operand 1
|
3939 |
|
|
is the stack pointer. The mode used to allocate the save area defaults
|
3940 |
|
|
to @code{Pmode} but you can override that choice by defining the
|
3941 |
|
|
@code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
|
3942 |
|
|
specify an integral mode, or @code{VOIDmode} if no save area is needed
|
3943 |
|
|
for a particular type of save (either because no save is needed or
|
3944 |
|
|
because a machine-specific save area can be used). Operand 0 is the
|
3945 |
|
|
stack pointer and operand 1 is the save area for restore operations. If
|
3946 |
|
|
@samp{save_stack_block} is defined, operand 0 must not be
|
3947 |
|
|
@code{VOIDmode} since these saves can be arbitrarily nested.
|
3948 |
|
|
|
3949 |
|
|
A save area is a @code{mem} that is at a constant offset from
|
3950 |
|
|
@code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
|
3951 |
|
|
nonlocal gotos and a @code{reg} in the other two cases.
|
3952 |
|
|
|
3953 |
|
|
@cindex @code{allocate_stack} instruction pattern
|
3954 |
|
|
@item @samp{allocate_stack}
|
3955 |
|
|
Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
|
3956 |
|
|
the stack pointer to create space for dynamically allocated data.
|
3957 |
|
|
|
3958 |
|
|
Store the resultant pointer to this space into operand 0. If you
|
3959 |
|
|
are allocating space from the main stack, do this by emitting a
|
3960 |
|
|
move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
|
3961 |
|
|
If you are allocating the space elsewhere, generate code to copy the
|
3962 |
|
|
location of the space to operand 0. In the latter case, you must
|
3963 |
|
|
ensure this space gets freed when the corresponding space on the main
|
3964 |
|
|
stack is free.
|
3965 |
|
|
|
3966 |
|
|
Do not define this pattern if all that must be done is the subtraction.
|
3967 |
|
|
Some machines require other operations such as stack probes or
|
3968 |
|
|
maintaining the back chain. Define this pattern to emit those
|
3969 |
|
|
operations in addition to updating the stack pointer.
|
3970 |
|
|
|
3971 |
|
|
@cindex @code{check_stack} instruction pattern
|
3972 |
|
|
@item @samp{check_stack}
|
3973 |
|
|
If stack checking cannot be done on your system by probing the stack with
|
3974 |
|
|
a load or store instruction (@pxref{Stack Checking}), define this pattern
|
3975 |
|
|
to perform the needed check and signaling an error if the stack
|
3976 |
|
|
has overflowed. The single operand is the location in the stack furthest
|
3977 |
|
|
from the current stack pointer that you need to validate. Normally,
|
3978 |
|
|
on machines where this pattern is needed, you would obtain the stack
|
3979 |
|
|
limit from a global or thread-specific variable or register.
|
3980 |
|
|
|
3981 |
|
|
@cindex @code{nonlocal_goto} instruction pattern
|
3982 |
|
|
@item @samp{nonlocal_goto}
|
3983 |
|
|
Emit code to generate a non-local goto, e.g., a jump from one function
|
3984 |
|
|
to a label in an outer function. This pattern has four arguments,
|
3985 |
|
|
each representing a value to be used in the jump. The first
|
3986 |
|
|
argument is to be loaded into the frame pointer, the second is
|
3987 |
|
|
the address to branch to (code to dispatch to the actual label),
|
3988 |
|
|
the third is the address of a location where the stack is saved,
|
3989 |
|
|
and the last is the address of the label, to be placed in the
|
3990 |
|
|
location for the incoming static chain.
|
3991 |
|
|
|
3992 |
|
|
On most machines you need not define this pattern, since GCC will
|
3993 |
|
|
already generate the correct code, which is to load the frame pointer
|
3994 |
|
|
and static chain, restore the stack (using the
|
3995 |
|
|
@samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
|
3996 |
|
|
to the dispatcher. You need only define this pattern if this code will
|
3997 |
|
|
not work on your machine.
|
3998 |
|
|
|
3999 |
|
|
@cindex @code{nonlocal_goto_receiver} instruction pattern
|
4000 |
|
|
@item @samp{nonlocal_goto_receiver}
|
4001 |
|
|
This pattern, if defined, contains code needed at the target of a
|
4002 |
|
|
nonlocal goto after the code already generated by GCC@. You will not
|
4003 |
|
|
normally need to define this pattern. A typical reason why you might
|
4004 |
|
|
need this pattern is if some value, such as a pointer to a global table,
|
4005 |
|
|
must be restored when the frame pointer is restored. Note that a nonlocal
|
4006 |
|
|
goto only occurs within a unit-of-translation, so a global table pointer
|
4007 |
|
|
that is shared by all functions of a given module need not be restored.
|
4008 |
|
|
There are no arguments.
|
4009 |
|
|
|
4010 |
|
|
@cindex @code{exception_receiver} instruction pattern
|
4011 |
|
|
@item @samp{exception_receiver}
|
4012 |
|
|
This pattern, if defined, contains code needed at the site of an
|
4013 |
|
|
exception handler that isn't needed at the site of a nonlocal goto. You
|
4014 |
|
|
will not normally need to define this pattern. A typical reason why you
|
4015 |
|
|
might need this pattern is if some value, such as a pointer to a global
|
4016 |
|
|
table, must be restored after control flow is branched to the handler of
|
4017 |
|
|
an exception. There are no arguments.
|
4018 |
|
|
|
4019 |
|
|
@cindex @code{builtin_setjmp_setup} instruction pattern
|
4020 |
|
|
@item @samp{builtin_setjmp_setup}
|
4021 |
|
|
This pattern, if defined, contains additional code needed to initialize
|
4022 |
|
|
the @code{jmp_buf}. You will not normally need to define this pattern.
|
4023 |
|
|
A typical reason why you might need this pattern is if some value, such
|
4024 |
|
|
as a pointer to a global table, must be restored. Though it is
|
4025 |
|
|
preferred that the pointer value be recalculated if possible (given the
|
4026 |
|
|
address of a label for instance). The single argument is a pointer to
|
4027 |
|
|
the @code{jmp_buf}. Note that the buffer is five words long and that
|
4028 |
|
|
the first three are normally used by the generic mechanism.
|
4029 |
|
|
|
4030 |
|
|
@cindex @code{builtin_setjmp_receiver} instruction pattern
|
4031 |
|
|
@item @samp{builtin_setjmp_receiver}
|
4032 |
|
|
This pattern, if defined, contains code needed at the site of an
|
4033 |
|
|
built-in setjmp that isn't needed at the site of a nonlocal goto. You
|
4034 |
|
|
will not normally need to define this pattern. A typical reason why you
|
4035 |
|
|
might need this pattern is if some value, such as a pointer to a global
|
4036 |
|
|
table, must be restored. It takes one argument, which is the label
|
4037 |
|
|
to which builtin_longjmp transfered control; this pattern may be emitted
|
4038 |
|
|
at a small offset from that label.
|
4039 |
|
|
|
4040 |
|
|
@cindex @code{builtin_longjmp} instruction pattern
|
4041 |
|
|
@item @samp{builtin_longjmp}
|
4042 |
|
|
This pattern, if defined, performs the entire action of the longjmp.
|
4043 |
|
|
You will not normally need to define this pattern unless you also define
|
4044 |
|
|
@code{builtin_setjmp_setup}. The single argument is a pointer to the
|
4045 |
|
|
@code{jmp_buf}.
|
4046 |
|
|
|
4047 |
|
|
@cindex @code{eh_return} instruction pattern
|
4048 |
|
|
@item @samp{eh_return}
|
4049 |
|
|
This pattern, if defined, affects the way @code{__builtin_eh_return},
|
4050 |
|
|
and thence the call frame exception handling library routines, are
|
4051 |
|
|
built. It is intended to handle non-trivial actions needed along
|
4052 |
|
|
the abnormal return path.
|
4053 |
|
|
|
4054 |
|
|
The address of the exception handler to which the function should return
|
4055 |
|
|
is passed as operand to this pattern. It will normally need to copied by
|
4056 |
|
|
the pattern to some special register or memory location.
|
4057 |
|
|
If the pattern needs to determine the location of the target call
|
4058 |
|
|
frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
|
4059 |
|
|
if defined; it will have already been assigned.
|
4060 |
|
|
|
4061 |
|
|
If this pattern is not defined, the default action will be to simply
|
4062 |
|
|
copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
|
4063 |
|
|
that macro or this pattern needs to be defined if call frame exception
|
4064 |
|
|
handling is to be used.
|
4065 |
|
|
|
4066 |
|
|
@cindex @code{prologue} instruction pattern
|
4067 |
|
|
@anchor{prologue instruction pattern}
|
4068 |
|
|
@item @samp{prologue}
|
4069 |
|
|
This pattern, if defined, emits RTL for entry to a function. The function
|
4070 |
|
|
entry is responsible for setting up the stack frame, initializing the frame
|
4071 |
|
|
pointer register, saving callee saved registers, etc.
|
4072 |
|
|
|
4073 |
|
|
Using a prologue pattern is generally preferred over defining
|
4074 |
|
|
@code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
|
4075 |
|
|
|
4076 |
|
|
The @code{prologue} pattern is particularly useful for targets which perform
|
4077 |
|
|
instruction scheduling.
|
4078 |
|
|
|
4079 |
|
|
@cindex @code{epilogue} instruction pattern
|
4080 |
|
|
@anchor{epilogue instruction pattern}
|
4081 |
|
|
@item @samp{epilogue}
|
4082 |
|
|
This pattern emits RTL for exit from a function. The function
|
4083 |
|
|
exit is responsible for deallocating the stack frame, restoring callee saved
|
4084 |
|
|
registers and emitting the return instruction.
|
4085 |
|
|
|
4086 |
|
|
Using an epilogue pattern is generally preferred over defining
|
4087 |
|
|
@code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
|
4088 |
|
|
|
4089 |
|
|
The @code{epilogue} pattern is particularly useful for targets which perform
|
4090 |
|
|
instruction scheduling or which have delay slots for their return instruction.
|
4091 |
|
|
|
4092 |
|
|
@cindex @code{sibcall_epilogue} instruction pattern
|
4093 |
|
|
@item @samp{sibcall_epilogue}
|
4094 |
|
|
This pattern, if defined, emits RTL for exit from a function without the final
|
4095 |
|
|
branch back to the calling function. This pattern will be emitted before any
|
4096 |
|
|
sibling call (aka tail call) sites.
|
4097 |
|
|
|
4098 |
|
|
The @code{sibcall_epilogue} pattern must not clobber any arguments used for
|
4099 |
|
|
parameter passing or any stack slots for arguments passed to the current
|
4100 |
|
|
function.
|
4101 |
|
|
|
4102 |
|
|
@cindex @code{trap} instruction pattern
|
4103 |
|
|
@item @samp{trap}
|
4104 |
|
|
This pattern, if defined, signals an error, typically by causing some
|
4105 |
|
|
kind of signal to be raised. Among other places, it is used by the Java
|
4106 |
|
|
front end to signal `invalid array index' exceptions.
|
4107 |
|
|
|
4108 |
|
|
@cindex @code{conditional_trap} instruction pattern
|
4109 |
|
|
@item @samp{conditional_trap}
|
4110 |
|
|
Conditional trap instruction. Operand 0 is a piece of RTL which
|
4111 |
|
|
performs a comparison. Operand 1 is the trap code, an integer.
|
4112 |
|
|
|
4113 |
|
|
A typical @code{conditional_trap} pattern looks like
|
4114 |
|
|
|
4115 |
|
|
@smallexample
|
4116 |
|
|
(define_insn "conditional_trap"
|
4117 |
|
|
[(trap_if (match_operator 0 "trap_operator"
|
4118 |
|
|
[(cc0) (const_int 0)])
|
4119 |
|
|
(match_operand 1 "const_int_operand" "i"))]
|
4120 |
|
|
""
|
4121 |
|
|
"@dots{}")
|
4122 |
|
|
@end smallexample
|
4123 |
|
|
|
4124 |
|
|
@cindex @code{prefetch} instruction pattern
|
4125 |
|
|
@item @samp{prefetch}
|
4126 |
|
|
|
4127 |
|
|
This pattern, if defined, emits code for a non-faulting data prefetch
|
4128 |
|
|
instruction. Operand 0 is the address of the memory to prefetch. Operand 1
|
4129 |
|
|
is a constant 1 if the prefetch is preparing for a write to the memory
|
4130 |
|
|
address, or a constant 0 otherwise. Operand 2 is the expected degree of
|
4131 |
|
|
temporal locality of the data and is a value between 0 and 3, inclusive; 0
|
4132 |
|
|
means that the data has no temporal locality, so it need not be left in the
|
4133 |
|
|
cache after the access; 3 means that the data has a high degree of temporal
|
4134 |
|
|
locality and should be left in all levels of cache possible; 1 and 2 mean,
|
4135 |
|
|
respectively, a low or moderate degree of temporal locality.
|
4136 |
|
|
|
4137 |
|
|
Targets that do not support write prefetches or locality hints can ignore
|
4138 |
|
|
the values of operands 1 and 2.
|
4139 |
|
|
|
4140 |
|
|
@cindex @code{memory_barrier} instruction pattern
|
4141 |
|
|
@item @samp{memory_barrier}
|
4142 |
|
|
|
4143 |
|
|
If the target memory model is not fully synchronous, then this pattern
|
4144 |
|
|
should be defined to an instruction that orders both loads and stores
|
4145 |
|
|
before the instruction with respect to loads and stores after the instruction.
|
4146 |
|
|
This pattern has no operands.
|
4147 |
|
|
|
4148 |
|
|
@cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
|
4149 |
|
|
@item @samp{sync_compare_and_swap@var{mode}}
|
4150 |
|
|
|
4151 |
|
|
This pattern, if defined, emits code for an atomic compare-and-swap
|
4152 |
|
|
operation. Operand 1 is the memory on which the atomic operation is
|
4153 |
|
|
performed. Operand 2 is the ``old'' value to be compared against the
|
4154 |
|
|
current contents of the memory location. Operand 3 is the ``new'' value
|
4155 |
|
|
to store in the memory if the compare succeeds. Operand 0 is the result
|
4156 |
|
|
of the operation; it should contain the contents of the memory
|
4157 |
|
|
before the operation. If the compare succeeds, this should obviously be
|
4158 |
|
|
a copy of operand 2.
|
4159 |
|
|
|
4160 |
|
|
This pattern must show that both operand 0 and operand 1 are modified.
|
4161 |
|
|
|
4162 |
|
|
This pattern must issue any memory barrier instructions such that all
|
4163 |
|
|
memory operations before the atomic operation occur before the atomic
|
4164 |
|
|
operation and all memory operations after the atomic operation occur
|
4165 |
|
|
after the atomic operation.
|
4166 |
|
|
|
4167 |
|
|
@cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
|
4168 |
|
|
@item @samp{sync_compare_and_swap_cc@var{mode}}
|
4169 |
|
|
|
4170 |
|
|
This pattern is just like @code{sync_compare_and_swap@var{mode}}, except
|
4171 |
|
|
it should act as if compare part of the compare-and-swap were issued via
|
4172 |
|
|
@code{cmp@var{m}}. This comparison will only be used with @code{EQ} and
|
4173 |
|
|
@code{NE} branches and @code{setcc} operations.
|
4174 |
|
|
|
4175 |
|
|
Some targets do expose the success or failure of the compare-and-swap
|
4176 |
|
|
operation via the status flags. Ideally we wouldn't need a separate
|
4177 |
|
|
named pattern in order to take advantage of this, but the combine pass
|
4178 |
|
|
does not handle patterns with multiple sets, which is required by
|
4179 |
|
|
definition for @code{sync_compare_and_swap@var{mode}}.
|
4180 |
|
|
|
4181 |
|
|
@cindex @code{sync_add@var{mode}} instruction pattern
|
4182 |
|
|
@cindex @code{sync_sub@var{mode}} instruction pattern
|
4183 |
|
|
@cindex @code{sync_ior@var{mode}} instruction pattern
|
4184 |
|
|
@cindex @code{sync_and@var{mode}} instruction pattern
|
4185 |
|
|
@cindex @code{sync_xor@var{mode}} instruction pattern
|
4186 |
|
|
@cindex @code{sync_nand@var{mode}} instruction pattern
|
4187 |
|
|
@item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
|
4188 |
|
|
@itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
|
4189 |
|
|
@itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
|
4190 |
|
|
|
4191 |
|
|
These patterns emit code for an atomic operation on memory.
|
4192 |
|
|
Operand 0 is the memory on which the atomic operation is performed.
|
4193 |
|
|
Operand 1 is the second operand to the binary operator.
|
4194 |
|
|
|
4195 |
|
|
The ``nand'' operation is @code{~op0 & op1}.
|
4196 |
|
|
|
4197 |
|
|
This pattern must issue any memory barrier instructions such that all
|
4198 |
|
|
memory operations before the atomic operation occur before the atomic
|
4199 |
|
|
operation and all memory operations after the atomic operation occur
|
4200 |
|
|
after the atomic operation.
|
4201 |
|
|
|
4202 |
|
|
If these patterns are not defined, the operation will be constructed
|
4203 |
|
|
from a compare-and-swap operation, if defined.
|
4204 |
|
|
|
4205 |
|
|
@cindex @code{sync_old_add@var{mode}} instruction pattern
|
4206 |
|
|
@cindex @code{sync_old_sub@var{mode}} instruction pattern
|
4207 |
|
|
@cindex @code{sync_old_ior@var{mode}} instruction pattern
|
4208 |
|
|
@cindex @code{sync_old_and@var{mode}} instruction pattern
|
4209 |
|
|
@cindex @code{sync_old_xor@var{mode}} instruction pattern
|
4210 |
|
|
@cindex @code{sync_old_nand@var{mode}} instruction pattern
|
4211 |
|
|
@item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
|
4212 |
|
|
@itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
|
4213 |
|
|
@itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
|
4214 |
|
|
|
4215 |
|
|
These patterns are emit code for an atomic operation on memory,
|
4216 |
|
|
and return the value that the memory contained before the operation.
|
4217 |
|
|
Operand 0 is the result value, operand 1 is the memory on which the
|
4218 |
|
|
atomic operation is performed, and operand 2 is the second operand
|
4219 |
|
|
to the binary operator.
|
4220 |
|
|
|
4221 |
|
|
This pattern must issue any memory barrier instructions such that all
|
4222 |
|
|
memory operations before the atomic operation occur before the atomic
|
4223 |
|
|
operation and all memory operations after the atomic operation occur
|
4224 |
|
|
after the atomic operation.
|
4225 |
|
|
|
4226 |
|
|
If these patterns are not defined, the operation will be constructed
|
4227 |
|
|
from a compare-and-swap operation, if defined.
|
4228 |
|
|
|
4229 |
|
|
@cindex @code{sync_new_add@var{mode}} instruction pattern
|
4230 |
|
|
@cindex @code{sync_new_sub@var{mode}} instruction pattern
|
4231 |
|
|
@cindex @code{sync_new_ior@var{mode}} instruction pattern
|
4232 |
|
|
@cindex @code{sync_new_and@var{mode}} instruction pattern
|
4233 |
|
|
@cindex @code{sync_new_xor@var{mode}} instruction pattern
|
4234 |
|
|
@cindex @code{sync_new_nand@var{mode}} instruction pattern
|
4235 |
|
|
@item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
|
4236 |
|
|
@itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
|
4237 |
|
|
@itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
|
4238 |
|
|
|
4239 |
|
|
These patterns are like their @code{sync_old_@var{op}} counterparts,
|
4240 |
|
|
except that they return the value that exists in the memory location
|
4241 |
|
|
after the operation, rather than before the operation.
|
4242 |
|
|
|
4243 |
|
|
@cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
|
4244 |
|
|
@item @samp{sync_lock_test_and_set@var{mode}}
|
4245 |
|
|
|
4246 |
|
|
This pattern takes two forms, based on the capabilities of the target.
|
4247 |
|
|
In either case, operand 0 is the result of the operand, operand 1 is
|
4248 |
|
|
the memory on which the atomic operation is performed, and operand 2
|
4249 |
|
|
is the value to set in the lock.
|
4250 |
|
|
|
4251 |
|
|
In the ideal case, this operation is an atomic exchange operation, in
|
4252 |
|
|
which the previous value in memory operand is copied into the result
|
4253 |
|
|
operand, and the value operand is stored in the memory operand.
|
4254 |
|
|
|
4255 |
|
|
For less capable targets, any value operand that is not the constant 1
|
4256 |
|
|
should be rejected with @code{FAIL}. In this case the target may use
|
4257 |
|
|
an atomic test-and-set bit operation. The result operand should contain
|
4258 |
|
|
1 if the bit was previously set and 0 if the bit was previously clear.
|
4259 |
|
|
The true contents of the memory operand are implementation defined.
|
4260 |
|
|
|
4261 |
|
|
This pattern must issue any memory barrier instructions such that the
|
4262 |
|
|
pattern as a whole acts as an acquire barrier, that is all memory
|
4263 |
|
|
operations after the pattern do not occur until the lock is acquired.
|
4264 |
|
|
|
4265 |
|
|
If this pattern is not defined, the operation will be constructed from
|
4266 |
|
|
a compare-and-swap operation, if defined.
|
4267 |
|
|
|
4268 |
|
|
@cindex @code{sync_lock_release@var{mode}} instruction pattern
|
4269 |
|
|
@item @samp{sync_lock_release@var{mode}}
|
4270 |
|
|
|
4271 |
|
|
This pattern, if defined, releases a lock set by
|
4272 |
|
|
@code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
|
4273 |
|
|
that contains the lock; operand 1 is the value to store in the lock.
|
4274 |
|
|
|
4275 |
|
|
If the target doesn't implement full semantics for
|
4276 |
|
|
@code{sync_lock_test_and_set@var{mode}}, any value operand which is not
|
4277 |
|
|
the constant 0 should be rejected with @code{FAIL}, and the true contents
|
4278 |
|
|
of the memory operand are implementation defined.
|
4279 |
|
|
|
4280 |
|
|
This pattern must issue any memory barrier instructions such that the
|
4281 |
|
|
pattern as a whole acts as a release barrier, that is the lock is
|
4282 |
|
|
released only after all previous memory operations have completed.
|
4283 |
|
|
|
4284 |
|
|
If this pattern is not defined, then a @code{memory_barrier} pattern
|
4285 |
|
|
will be emitted, followed by a store of the value to the memory operand.
|
4286 |
|
|
|
4287 |
|
|
@cindex @code{stack_protect_set} instruction pattern
|
4288 |
|
|
@item @samp{stack_protect_set}
|
4289 |
|
|
|
4290 |
|
|
This pattern, if defined, moves a @code{Pmode} value from the memory
|
4291 |
|
|
in operand 1 to the memory in operand 0 without leaving the value in
|
4292 |
|
|
a register afterward. This is to avoid leaking the value some place
|
4293 |
|
|
that an attacker might use to rewrite the stack guard slot after
|
4294 |
|
|
having clobbered it.
|
4295 |
|
|
|
4296 |
|
|
If this pattern is not defined, then a plain move pattern is generated.
|
4297 |
|
|
|
4298 |
|
|
@cindex @code{stack_protect_test} instruction pattern
|
4299 |
|
|
@item @samp{stack_protect_test}
|
4300 |
|
|
|
4301 |
|
|
This pattern, if defined, compares a @code{Pmode} value from the
|
4302 |
|
|
memory in operand 1 with the memory in operand 0 without leaving the
|
4303 |
|
|
value in a register afterward and branches to operand 2 if the values
|
4304 |
|
|
weren't equal.
|
4305 |
|
|
|
4306 |
|
|
If this pattern is not defined, then a plain compare pattern and
|
4307 |
|
|
conditional branch pattern is used.
|
4308 |
|
|
|
4309 |
|
|
@end table
|
4310 |
|
|
|
4311 |
|
|
@end ifset
|
4312 |
|
|
@c Each of the following nodes are wrapped in separate
|
4313 |
|
|
@c "@ifset INTERNALS" to work around memory limits for the default
|
4314 |
|
|
@c configuration in older tetex distributions. Known to not work:
|
4315 |
|
|
@c tetex-1.0.7, known to work: tetex-2.0.2.
|
4316 |
|
|
@ifset INTERNALS
|
4317 |
|
|
@node Pattern Ordering
|
4318 |
|
|
@section When the Order of Patterns Matters
|
4319 |
|
|
@cindex Pattern Ordering
|
4320 |
|
|
@cindex Ordering of Patterns
|
4321 |
|
|
|
4322 |
|
|
Sometimes an insn can match more than one instruction pattern. Then the
|
4323 |
|
|
pattern that appears first in the machine description is the one used.
|
4324 |
|
|
Therefore, more specific patterns (patterns that will match fewer things)
|
4325 |
|
|
and faster instructions (those that will produce better code when they
|
4326 |
|
|
do match) should usually go first in the description.
|
4327 |
|
|
|
4328 |
|
|
In some cases the effect of ordering the patterns can be used to hide
|
4329 |
|
|
a pattern when it is not valid. For example, the 68000 has an
|
4330 |
|
|
instruction for converting a fullword to floating point and another
|
4331 |
|
|
for converting a byte to floating point. An instruction converting
|
4332 |
|
|
an integer to floating point could match either one. We put the
|
4333 |
|
|
pattern to convert the fullword first to make sure that one will
|
4334 |
|
|
be used rather than the other. (Otherwise a large integer might
|
4335 |
|
|
be generated as a single-byte immediate quantity, which would not work.)
|
4336 |
|
|
Instead of using this pattern ordering it would be possible to make the
|
4337 |
|
|
pattern for convert-a-byte smart enough to deal properly with any
|
4338 |
|
|
constant value.
|
4339 |
|
|
|
4340 |
|
|
@end ifset
|
4341 |
|
|
@ifset INTERNALS
|
4342 |
|
|
@node Dependent Patterns
|
4343 |
|
|
@section Interdependence of Patterns
|
4344 |
|
|
@cindex Dependent Patterns
|
4345 |
|
|
@cindex Interdependence of Patterns
|
4346 |
|
|
|
4347 |
|
|
Every machine description must have a named pattern for each of the
|
4348 |
|
|
conditional branch names @samp{b@var{cond}}. The recognition template
|
4349 |
|
|
must always have the form
|
4350 |
|
|
|
4351 |
|
|
@smallexample
|
4352 |
|
|
(set (pc)
|
4353 |
|
|
(if_then_else (@var{cond} (cc0) (const_int 0))
|
4354 |
|
|
(label_ref (match_operand 0 "" ""))
|
4355 |
|
|
(pc)))
|
4356 |
|
|
@end smallexample
|
4357 |
|
|
|
4358 |
|
|
@noindent
|
4359 |
|
|
In addition, every machine description must have an anonymous pattern
|
4360 |
|
|
for each of the possible reverse-conditional branches. Their templates
|
4361 |
|
|
look like
|
4362 |
|
|
|
4363 |
|
|
@smallexample
|
4364 |
|
|
(set (pc)
|
4365 |
|
|
(if_then_else (@var{cond} (cc0) (const_int 0))
|
4366 |
|
|
(pc)
|
4367 |
|
|
(label_ref (match_operand 0 "" ""))))
|
4368 |
|
|
@end smallexample
|
4369 |
|
|
|
4370 |
|
|
@noindent
|
4371 |
|
|
They are necessary because jump optimization can turn direct-conditional
|
4372 |
|
|
branches into reverse-conditional branches.
|
4373 |
|
|
|
4374 |
|
|
It is often convenient to use the @code{match_operator} construct to
|
4375 |
|
|
reduce the number of patterns that must be specified for branches. For
|
4376 |
|
|
example,
|
4377 |
|
|
|
4378 |
|
|
@smallexample
|
4379 |
|
|
(define_insn ""
|
4380 |
|
|
[(set (pc)
|
4381 |
|
|
(if_then_else (match_operator 0 "comparison_operator"
|
4382 |
|
|
[(cc0) (const_int 0)])
|
4383 |
|
|
(pc)
|
4384 |
|
|
(label_ref (match_operand 1 "" ""))))]
|
4385 |
|
|
"@var{condition}"
|
4386 |
|
|
"@dots{}")
|
4387 |
|
|
@end smallexample
|
4388 |
|
|
|
4389 |
|
|
In some cases machines support instructions identical except for the
|
4390 |
|
|
machine mode of one or more operands. For example, there may be
|
4391 |
|
|
``sign-extend halfword'' and ``sign-extend byte'' instructions whose
|
4392 |
|
|
patterns are
|
4393 |
|
|
|
4394 |
|
|
@smallexample
|
4395 |
|
|
(set (match_operand:SI 0 @dots{})
|
4396 |
|
|
(extend:SI (match_operand:HI 1 @dots{})))
|
4397 |
|
|
|
4398 |
|
|
(set (match_operand:SI 0 @dots{})
|
4399 |
|
|
(extend:SI (match_operand:QI 1 @dots{})))
|
4400 |
|
|
@end smallexample
|
4401 |
|
|
|
4402 |
|
|
@noindent
|
4403 |
|
|
Constant integers do not specify a machine mode, so an instruction to
|
4404 |
|
|
extend a constant value could match either pattern. The pattern it
|
4405 |
|
|
actually will match is the one that appears first in the file. For correct
|
4406 |
|
|
results, this must be the one for the widest possible mode (@code{HImode},
|
4407 |
|
|
here). If the pattern matches the @code{QImode} instruction, the results
|
4408 |
|
|
will be incorrect if the constant value does not actually fit that mode.
|
4409 |
|
|
|
4410 |
|
|
Such instructions to extend constants are rarely generated because they are
|
4411 |
|
|
optimized away, but they do occasionally happen in nonoptimized
|
4412 |
|
|
compilations.
|
4413 |
|
|
|
4414 |
|
|
If a constraint in a pattern allows a constant, the reload pass may
|
4415 |
|
|
replace a register with a constant permitted by the constraint in some
|
4416 |
|
|
cases. Similarly for memory references. Because of this substitution,
|
4417 |
|
|
you should not provide separate patterns for increment and decrement
|
4418 |
|
|
instructions. Instead, they should be generated from the same pattern
|
4419 |
|
|
that supports register-register add insns by examining the operands and
|
4420 |
|
|
generating the appropriate machine instruction.
|
4421 |
|
|
|
4422 |
|
|
@end ifset
|
4423 |
|
|
@ifset INTERNALS
|
4424 |
|
|
@node Jump Patterns
|
4425 |
|
|
@section Defining Jump Instruction Patterns
|
4426 |
|
|
@cindex jump instruction patterns
|
4427 |
|
|
@cindex defining jump instruction patterns
|
4428 |
|
|
|
4429 |
|
|
For most machines, GCC assumes that the machine has a condition code.
|
4430 |
|
|
A comparison insn sets the condition code, recording the results of both
|
4431 |
|
|
signed and unsigned comparison of the given operands. A separate branch
|
4432 |
|
|
insn tests the condition code and branches or not according its value.
|
4433 |
|
|
The branch insns come in distinct signed and unsigned flavors. Many
|
4434 |
|
|
common machines, such as the VAX, the 68000 and the 32000, work this
|
4435 |
|
|
way.
|
4436 |
|
|
|
4437 |
|
|
Some machines have distinct signed and unsigned compare instructions, and
|
4438 |
|
|
only one set of conditional branch instructions. The easiest way to handle
|
4439 |
|
|
these machines is to treat them just like the others until the final stage
|
4440 |
|
|
where assembly code is written. At this time, when outputting code for the
|
4441 |
|
|
compare instruction, peek ahead at the following branch using
|
4442 |
|
|
@code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
|
4443 |
|
|
being output, in the output-writing code in an instruction pattern.) If
|
4444 |
|
|
the RTL says that is an unsigned branch, output an unsigned compare;
|
4445 |
|
|
otherwise output a signed compare. When the branch itself is output, you
|
4446 |
|
|
can treat signed and unsigned branches identically.
|
4447 |
|
|
|
4448 |
|
|
The reason you can do this is that GCC always generates a pair of
|
4449 |
|
|
consecutive RTL insns, possibly separated by @code{note} insns, one to
|
4450 |
|
|
set the condition code and one to test it, and keeps the pair inviolate
|
4451 |
|
|
until the end.
|
4452 |
|
|
|
4453 |
|
|
To go with this technique, you must define the machine-description macro
|
4454 |
|
|
@code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
|
4455 |
|
|
compare instruction is superfluous.
|
4456 |
|
|
|
4457 |
|
|
Some machines have compare-and-branch instructions and no condition code.
|
4458 |
|
|
A similar technique works for them. When it is time to ``output'' a
|
4459 |
|
|
compare instruction, record its operands in two static variables. When
|
4460 |
|
|
outputting the branch-on-condition-code instruction that follows, actually
|
4461 |
|
|
output a compare-and-branch instruction that uses the remembered operands.
|
4462 |
|
|
|
4463 |
|
|
It also works to define patterns for compare-and-branch instructions.
|
4464 |
|
|
In optimizing compilation, the pair of compare and branch instructions
|
4465 |
|
|
will be combined according to these patterns. But this does not happen
|
4466 |
|
|
if optimization is not requested. So you must use one of the solutions
|
4467 |
|
|
above in addition to any special patterns you define.
|
4468 |
|
|
|
4469 |
|
|
In many RISC machines, most instructions do not affect the condition
|
4470 |
|
|
code and there may not even be a separate condition code register. On
|
4471 |
|
|
these machines, the restriction that the definition and use of the
|
4472 |
|
|
condition code be adjacent insns is not necessary and can prevent
|
4473 |
|
|
important optimizations. For example, on the IBM RS/6000, there is a
|
4474 |
|
|
delay for taken branches unless the condition code register is set three
|
4475 |
|
|
instructions earlier than the conditional branch. The instruction
|
4476 |
|
|
scheduler cannot perform this optimization if it is not permitted to
|
4477 |
|
|
separate the definition and use of the condition code register.
|
4478 |
|
|
|
4479 |
|
|
On these machines, do not use @code{(cc0)}, but instead use a register
|
4480 |
|
|
to represent the condition code. If there is a specific condition code
|
4481 |
|
|
register in the machine, use a hard register. If the condition code or
|
4482 |
|
|
comparison result can be placed in any general register, or if there are
|
4483 |
|
|
multiple condition registers, use a pseudo register.
|
4484 |
|
|
|
4485 |
|
|
@findex prev_cc0_setter
|
4486 |
|
|
@findex next_cc0_user
|
4487 |
|
|
On some machines, the type of branch instruction generated may depend on
|
4488 |
|
|
the way the condition code was produced; for example, on the 68k and
|
4489 |
|
|
SPARC, setting the condition code directly from an add or subtract
|
4490 |
|
|
instruction does not clear the overflow bit the way that a test
|
4491 |
|
|
instruction does, so a different branch instruction must be used for
|
4492 |
|
|
some conditional branches. For machines that use @code{(cc0)}, the set
|
4493 |
|
|
and use of the condition code must be adjacent (separated only by
|
4494 |
|
|
@code{note} insns) allowing flags in @code{cc_status} to be used.
|
4495 |
|
|
(@xref{Condition Code}.) Also, the comparison and branch insns can be
|
4496 |
|
|
located from each other by using the functions @code{prev_cc0_setter}
|
4497 |
|
|
and @code{next_cc0_user}.
|
4498 |
|
|
|
4499 |
|
|
However, this is not true on machines that do not use @code{(cc0)}. On
|
4500 |
|
|
those machines, no assumptions can be made about the adjacency of the
|
4501 |
|
|
compare and branch insns and the above methods cannot be used. Instead,
|
4502 |
|
|
we use the machine mode of the condition code register to record
|
4503 |
|
|
different formats of the condition code register.
|
4504 |
|
|
|
4505 |
|
|
Registers used to store the condition code value should have a mode that
|
4506 |
|
|
is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
|
4507 |
|
|
additional modes are required (as for the add example mentioned above in
|
4508 |
|
|
the SPARC), define them in @file{@var{machine}-modes.def}
|
4509 |
|
|
(@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose
|
4510 |
|
|
a mode given an operand of a compare.
|
4511 |
|
|
|
4512 |
|
|
If it is known during RTL generation that a different mode will be
|
4513 |
|
|
required (for example, if the machine has separate compare instructions
|
4514 |
|
|
for signed and unsigned quantities, like most IBM processors), they can
|
4515 |
|
|
be specified at that time.
|
4516 |
|
|
|
4517 |
|
|
If the cases that require different modes would be made by instruction
|
4518 |
|
|
combination, the macro @code{SELECT_CC_MODE} determines which machine
|
4519 |
|
|
mode should be used for the comparison result. The patterns should be
|
4520 |
|
|
written using that mode. To support the case of the add on the SPARC
|
4521 |
|
|
discussed above, we have the pattern
|
4522 |
|
|
|
4523 |
|
|
@smallexample
|
4524 |
|
|
(define_insn ""
|
4525 |
|
|
[(set (reg:CC_NOOV 0)
|
4526 |
|
|
(compare:CC_NOOV
|
4527 |
|
|
(plus:SI (match_operand:SI 0 "register_operand" "%r")
|
4528 |
|
|
(match_operand:SI 1 "arith_operand" "rI"))
|
4529 |
|
|
(const_int 0)))]
|
4530 |
|
|
""
|
4531 |
|
|
"@dots{}")
|
4532 |
|
|
@end smallexample
|
4533 |
|
|
|
4534 |
|
|
The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
|
4535 |
|
|
for comparisons whose argument is a @code{plus}.
|
4536 |
|
|
|
4537 |
|
|
@end ifset
|
4538 |
|
|
@ifset INTERNALS
|
4539 |
|
|
@node Looping Patterns
|
4540 |
|
|
@section Defining Looping Instruction Patterns
|
4541 |
|
|
@cindex looping instruction patterns
|
4542 |
|
|
@cindex defining looping instruction patterns
|
4543 |
|
|
|
4544 |
|
|
Some machines have special jump instructions that can be utilized to
|
4545 |
|
|
make loops more efficient. A common example is the 68000 @samp{dbra}
|
4546 |
|
|
instruction which performs a decrement of a register and a branch if the
|
4547 |
|
|
result was greater than zero. Other machines, in particular digital
|
4548 |
|
|
signal processors (DSPs), have special block repeat instructions to
|
4549 |
|
|
provide low-overhead loop support. For example, the TI TMS320C3x/C4x
|
4550 |
|
|
DSPs have a block repeat instruction that loads special registers to
|
4551 |
|
|
mark the top and end of a loop and to count the number of loop
|
4552 |
|
|
iterations. This avoids the need for fetching and executing a
|
4553 |
|
|
@samp{dbra}-like instruction and avoids pipeline stalls associated with
|
4554 |
|
|
the jump.
|
4555 |
|
|
|
4556 |
|
|
GCC has three special named patterns to support low overhead looping.
|
4557 |
|
|
They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
|
4558 |
|
|
and @samp{doloop_end}. The first pattern,
|
4559 |
|
|
@samp{decrement_and_branch_until_zero}, is not emitted during RTL
|
4560 |
|
|
generation but may be emitted during the instruction combination phase.
|
4561 |
|
|
This requires the assistance of the loop optimizer, using information
|
4562 |
|
|
collected during strength reduction, to reverse a loop to count down to
|
4563 |
|
|
zero. Some targets also require the loop optimizer to add a
|
4564 |
|
|
@code{REG_NONNEG} note to indicate that the iteration count is always
|
4565 |
|
|
positive. This is needed if the target performs a signed loop
|
4566 |
|
|
termination test. For example, the 68000 uses a pattern similar to the
|
4567 |
|
|
following for its @code{dbra} instruction:
|
4568 |
|
|
|
4569 |
|
|
@smallexample
|
4570 |
|
|
@group
|
4571 |
|
|
(define_insn "decrement_and_branch_until_zero"
|
4572 |
|
|
[(set (pc)
|
4573 |
|
|
(if_then_else
|
4574 |
|
|
(ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
|
4575 |
|
|
(const_int -1))
|
4576 |
|
|
(const_int 0))
|
4577 |
|
|
(label_ref (match_operand 1 "" ""))
|
4578 |
|
|
(pc)))
|
4579 |
|
|
(set (match_dup 0)
|
4580 |
|
|
(plus:SI (match_dup 0)
|
4581 |
|
|
(const_int -1)))]
|
4582 |
|
|
"find_reg_note (insn, REG_NONNEG, 0)"
|
4583 |
|
|
"@dots{}")
|
4584 |
|
|
@end group
|
4585 |
|
|
@end smallexample
|
4586 |
|
|
|
4587 |
|
|
Note that since the insn is both a jump insn and has an output, it must
|
4588 |
|
|
deal with its own reloads, hence the `m' constraints. Also note that
|
4589 |
|
|
since this insn is generated by the instruction combination phase
|
4590 |
|
|
combining two sequential insns together into an implicit parallel insn,
|
4591 |
|
|
the iteration counter needs to be biased by the same amount as the
|
4592 |
|
|
decrement operation, in this case @minus{}1. Note that the following similar
|
4593 |
|
|
pattern will not be matched by the combiner.
|
4594 |
|
|
|
4595 |
|
|
@smallexample
|
4596 |
|
|
@group
|
4597 |
|
|
(define_insn "decrement_and_branch_until_zero"
|
4598 |
|
|
[(set (pc)
|
4599 |
|
|
(if_then_else
|
4600 |
|
|
(ge (match_operand:SI 0 "general_operand" "+d*am")
|
4601 |
|
|
(const_int 1))
|
4602 |
|
|
(label_ref (match_operand 1 "" ""))
|
4603 |
|
|
(pc)))
|
4604 |
|
|
(set (match_dup 0)
|
4605 |
|
|
(plus:SI (match_dup 0)
|
4606 |
|
|
(const_int -1)))]
|
4607 |
|
|
"find_reg_note (insn, REG_NONNEG, 0)"
|
4608 |
|
|
"@dots{}")
|
4609 |
|
|
@end group
|
4610 |
|
|
@end smallexample
|
4611 |
|
|
|
4612 |
|
|
The other two special looping patterns, @samp{doloop_begin} and
|
4613 |
|
|
@samp{doloop_end}, are emitted by the loop optimizer for certain
|
4614 |
|
|
well-behaved loops with a finite number of loop iterations using
|
4615 |
|
|
information collected during strength reduction.
|
4616 |
|
|
|
4617 |
|
|
The @samp{doloop_end} pattern describes the actual looping instruction
|
4618 |
|
|
(or the implicit looping operation) and the @samp{doloop_begin} pattern
|
4619 |
|
|
is an optional companion pattern that can be used for initialization
|
4620 |
|
|
needed for some low-overhead looping instructions.
|
4621 |
|
|
|
4622 |
|
|
Note that some machines require the actual looping instruction to be
|
4623 |
|
|
emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
|
4624 |
|
|
the true RTL for a looping instruction at the top of the loop can cause
|
4625 |
|
|
problems with flow analysis. So instead, a dummy @code{doloop} insn is
|
4626 |
|
|
emitted at the end of the loop. The machine dependent reorg pass checks
|
4627 |
|
|
for the presence of this @code{doloop} insn and then searches back to
|
4628 |
|
|
the top of the loop, where it inserts the true looping insn (provided
|
4629 |
|
|
there are no instructions in the loop which would cause problems). Any
|
4630 |
|
|
additional labels can be emitted at this point. In addition, if the
|
4631 |
|
|
desired special iteration counter register was not allocated, this
|
4632 |
|
|
machine dependent reorg pass could emit a traditional compare and jump
|
4633 |
|
|
instruction pair.
|
4634 |
|
|
|
4635 |
|
|
The essential difference between the
|
4636 |
|
|
@samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
|
4637 |
|
|
patterns is that the loop optimizer allocates an additional pseudo
|
4638 |
|
|
register for the latter as an iteration counter. This pseudo register
|
4639 |
|
|
cannot be used within the loop (i.e., general induction variables cannot
|
4640 |
|
|
be derived from it), however, in many cases the loop induction variable
|
4641 |
|
|
may become redundant and removed by the flow pass.
|
4642 |
|
|
|
4643 |
|
|
|
4644 |
|
|
@end ifset
|
4645 |
|
|
@ifset INTERNALS
|
4646 |
|
|
@node Insn Canonicalizations
|
4647 |
|
|
@section Canonicalization of Instructions
|
4648 |
|
|
@cindex canonicalization of instructions
|
4649 |
|
|
@cindex insn canonicalization
|
4650 |
|
|
|
4651 |
|
|
There are often cases where multiple RTL expressions could represent an
|
4652 |
|
|
operation performed by a single machine instruction. This situation is
|
4653 |
|
|
most commonly encountered with logical, branch, and multiply-accumulate
|
4654 |
|
|
instructions. In such cases, the compiler attempts to convert these
|
4655 |
|
|
multiple RTL expressions into a single canonical form to reduce the
|
4656 |
|
|
number of insn patterns required.
|
4657 |
|
|
|
4658 |
|
|
In addition to algebraic simplifications, following canonicalizations
|
4659 |
|
|
are performed:
|
4660 |
|
|
|
4661 |
|
|
@itemize @bullet
|
4662 |
|
|
@item
|
4663 |
|
|
For commutative and comparison operators, a constant is always made the
|
4664 |
|
|
second operand. If a machine only supports a constant as the second
|
4665 |
|
|
operand, only patterns that match a constant in the second operand need
|
4666 |
|
|
be supplied.
|
4667 |
|
|
|
4668 |
|
|
@item
|
4669 |
|
|
For associative operators, a sequence of operators will always chain
|
4670 |
|
|
to the left; for instance, only the left operand of an integer @code{plus}
|
4671 |
|
|
can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
|
4672 |
|
|
@code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
|
4673 |
|
|
@code{umax} are associative when applied to integers, and sometimes to
|
4674 |
|
|
floating-point.
|
4675 |
|
|
|
4676 |
|
|
@item
|
4677 |
|
|
@cindex @code{neg}, canonicalization of
|
4678 |
|
|
@cindex @code{not}, canonicalization of
|
4679 |
|
|
@cindex @code{mult}, canonicalization of
|
4680 |
|
|
@cindex @code{plus}, canonicalization of
|
4681 |
|
|
@cindex @code{minus}, canonicalization of
|
4682 |
|
|
For these operators, if only one operand is a @code{neg}, @code{not},
|
4683 |
|
|
@code{mult}, @code{plus}, or @code{minus} expression, it will be the
|
4684 |
|
|
first operand.
|
4685 |
|
|
|
4686 |
|
|
@item
|
4687 |
|
|
In combinations of @code{neg}, @code{mult}, @code{plus}, and
|
4688 |
|
|
@code{minus}, the @code{neg} operations (if any) will be moved inside
|
4689 |
|
|
the operations as far as possible. For instance,
|
4690 |
|
|
@code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
|
4691 |
|
|
@code{(plus (mult (neg A) B) C)} is canonicalized as
|
4692 |
|
|
@code{(minus A (mult B C))}.
|
4693 |
|
|
|
4694 |
|
|
@cindex @code{compare}, canonicalization of
|
4695 |
|
|
@item
|
4696 |
|
|
For the @code{compare} operator, a constant is always the second operand
|
4697 |
|
|
on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
|
4698 |
|
|
machines, there are rare cases where the compiler might want to construct
|
4699 |
|
|
a @code{compare} with a constant as the first operand. However, these
|
4700 |
|
|
cases are not common enough for it to be worthwhile to provide a pattern
|
4701 |
|
|
matching a constant as the first operand unless the machine actually has
|
4702 |
|
|
such an instruction.
|
4703 |
|
|
|
4704 |
|
|
An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
|
4705 |
|
|
@code{minus} is made the first operand under the same conditions as
|
4706 |
|
|
above.
|
4707 |
|
|
|
4708 |
|
|
@item
|
4709 |
|
|
@code{(minus @var{x} (const_int @var{n}))} is converted to
|
4710 |
|
|
@code{(plus @var{x} (const_int @var{-n}))}.
|
4711 |
|
|
|
4712 |
|
|
@item
|
4713 |
|
|
Within address computations (i.e., inside @code{mem}), a left shift is
|
4714 |
|
|
converted into the appropriate multiplication by a power of two.
|
4715 |
|
|
|
4716 |
|
|
@cindex @code{ior}, canonicalization of
|
4717 |
|
|
@cindex @code{and}, canonicalization of
|
4718 |
|
|
@cindex De Morgan's law
|
4719 |
|
|
@item
|
4720 |
|
|
De Morgan's Law is used to move bitwise negation inside a bitwise
|
4721 |
|
|
logical-and or logical-or operation. If this results in only one
|
4722 |
|
|
operand being a @code{not} expression, it will be the first one.
|
4723 |
|
|
|
4724 |
|
|
A machine that has an instruction that performs a bitwise logical-and of one
|
4725 |
|
|
operand with the bitwise negation of the other should specify the pattern
|
4726 |
|
|
for that instruction as
|
4727 |
|
|
|
4728 |
|
|
@smallexample
|
4729 |
|
|
(define_insn ""
|
4730 |
|
|
[(set (match_operand:@var{m} 0 @dots{})
|
4731 |
|
|
(and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
|
4732 |
|
|
(match_operand:@var{m} 2 @dots{})))]
|
4733 |
|
|
"@dots{}"
|
4734 |
|
|
"@dots{}")
|
4735 |
|
|
@end smallexample
|
4736 |
|
|
|
4737 |
|
|
@noindent
|
4738 |
|
|
Similarly, a pattern for a ``NAND'' instruction should be written
|
4739 |
|
|
|
4740 |
|
|
@smallexample
|
4741 |
|
|
(define_insn ""
|
4742 |
|
|
[(set (match_operand:@var{m} 0 @dots{})
|
4743 |
|
|
(ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
|
4744 |
|
|
(not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
|
4745 |
|
|
"@dots{}"
|
4746 |
|
|
"@dots{}")
|
4747 |
|
|
@end smallexample
|
4748 |
|
|
|
4749 |
|
|
In both cases, it is not necessary to include patterns for the many
|
4750 |
|
|
logically equivalent RTL expressions.
|
4751 |
|
|
|
4752 |
|
|
@cindex @code{xor}, canonicalization of
|
4753 |
|
|
@item
|
4754 |
|
|
The only possible RTL expressions involving both bitwise exclusive-or
|
4755 |
|
|
and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
|
4756 |
|
|
and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
|
4757 |
|
|
|
4758 |
|
|
@item
|
4759 |
|
|
The sum of three items, one of which is a constant, will only appear in
|
4760 |
|
|
the form
|
4761 |
|
|
|
4762 |
|
|
@smallexample
|
4763 |
|
|
(plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
|
4764 |
|
|
@end smallexample
|
4765 |
|
|
|
4766 |
|
|
@item
|
4767 |
|
|
On machines that do not use @code{cc0},
|
4768 |
|
|
@code{(compare @var{x} (const_int 0))} will be converted to
|
4769 |
|
|
@var{x}.
|
4770 |
|
|
|
4771 |
|
|
@cindex @code{zero_extract}, canonicalization of
|
4772 |
|
|
@cindex @code{sign_extract}, canonicalization of
|
4773 |
|
|
@item
|
4774 |
|
|
Equality comparisons of a group of bits (usually a single bit) with zero
|
4775 |
|
|
will be written using @code{zero_extract} rather than the equivalent
|
4776 |
|
|
@code{and} or @code{sign_extract} operations.
|
4777 |
|
|
|
4778 |
|
|
@end itemize
|
4779 |
|
|
|
4780 |
|
|
@end ifset
|
4781 |
|
|
@ifset INTERNALS
|
4782 |
|
|
@node Expander Definitions
|
4783 |
|
|
@section Defining RTL Sequences for Code Generation
|
4784 |
|
|
@cindex expander definitions
|
4785 |
|
|
@cindex code generation RTL sequences
|
4786 |
|
|
@cindex defining RTL sequences for code generation
|
4787 |
|
|
|
4788 |
|
|
On some target machines, some standard pattern names for RTL generation
|
4789 |
|
|
cannot be handled with single insn, but a sequence of RTL insns can
|
4790 |
|
|
represent them. For these target machines, you can write a
|
4791 |
|
|
@code{define_expand} to specify how to generate the sequence of RTL@.
|
4792 |
|
|
|
4793 |
|
|
@findex define_expand
|
4794 |
|
|
A @code{define_expand} is an RTL expression that looks almost like a
|
4795 |
|
|
@code{define_insn}; but, unlike the latter, a @code{define_expand} is used
|
4796 |
|
|
only for RTL generation and it can produce more than one RTL insn.
|
4797 |
|
|
|
4798 |
|
|
A @code{define_expand} RTX has four operands:
|
4799 |
|
|
|
4800 |
|
|
@itemize @bullet
|
4801 |
|
|
@item
|
4802 |
|
|
The name. Each @code{define_expand} must have a name, since the only
|
4803 |
|
|
use for it is to refer to it by name.
|
4804 |
|
|
|
4805 |
|
|
@item
|
4806 |
|
|
The RTL template. This is a vector of RTL expressions representing
|
4807 |
|
|
a sequence of separate instructions. Unlike @code{define_insn}, there
|
4808 |
|
|
is no implicit surrounding @code{PARALLEL}.
|
4809 |
|
|
|
4810 |
|
|
@item
|
4811 |
|
|
The condition, a string containing a C expression. This expression is
|
4812 |
|
|
used to express how the availability of this pattern depends on
|
4813 |
|
|
subclasses of target machine, selected by command-line options when GCC
|
4814 |
|
|
is run. This is just like the condition of a @code{define_insn} that
|
4815 |
|
|
has a standard name. Therefore, the condition (if present) may not
|
4816 |
|
|
depend on the data in the insn being matched, but only the
|
4817 |
|
|
target-machine-type flags. The compiler needs to test these conditions
|
4818 |
|
|
during initialization in order to learn exactly which named instructions
|
4819 |
|
|
are available in a particular run.
|
4820 |
|
|
|
4821 |
|
|
@item
|
4822 |
|
|
The preparation statements, a string containing zero or more C
|
4823 |
|
|
statements which are to be executed before RTL code is generated from
|
4824 |
|
|
the RTL template.
|
4825 |
|
|
|
4826 |
|
|
Usually these statements prepare temporary registers for use as
|
4827 |
|
|
internal operands in the RTL template, but they can also generate RTL
|
4828 |
|
|
insns directly by calling routines such as @code{emit_insn}, etc.
|
4829 |
|
|
Any such insns precede the ones that come from the RTL template.
|
4830 |
|
|
@end itemize
|
4831 |
|
|
|
4832 |
|
|
Every RTL insn emitted by a @code{define_expand} must match some
|
4833 |
|
|
@code{define_insn} in the machine description. Otherwise, the compiler
|
4834 |
|
|
will crash when trying to generate code for the insn or trying to optimize
|
4835 |
|
|
it.
|
4836 |
|
|
|
4837 |
|
|
The RTL template, in addition to controlling generation of RTL insns,
|
4838 |
|
|
also describes the operands that need to be specified when this pattern
|
4839 |
|
|
is used. In particular, it gives a predicate for each operand.
|
4840 |
|
|
|
4841 |
|
|
A true operand, which needs to be specified in order to generate RTL from
|
4842 |
|
|
the pattern, should be described with a @code{match_operand} in its first
|
4843 |
|
|
occurrence in the RTL template. This enters information on the operand's
|
4844 |
|
|
predicate into the tables that record such things. GCC uses the
|
4845 |
|
|
information to preload the operand into a register if that is required for
|
4846 |
|
|
valid RTL code. If the operand is referred to more than once, subsequent
|
4847 |
|
|
references should use @code{match_dup}.
|
4848 |
|
|
|
4849 |
|
|
The RTL template may also refer to internal ``operands'' which are
|
4850 |
|
|
temporary registers or labels used only within the sequence made by the
|
4851 |
|
|
@code{define_expand}. Internal operands are substituted into the RTL
|
4852 |
|
|
template with @code{match_dup}, never with @code{match_operand}. The
|
4853 |
|
|
values of the internal operands are not passed in as arguments by the
|
4854 |
|
|
compiler when it requests use of this pattern. Instead, they are computed
|
4855 |
|
|
within the pattern, in the preparation statements. These statements
|
4856 |
|
|
compute the values and store them into the appropriate elements of
|
4857 |
|
|
@code{operands} so that @code{match_dup} can find them.
|
4858 |
|
|
|
4859 |
|
|
There are two special macros defined for use in the preparation statements:
|
4860 |
|
|
@code{DONE} and @code{FAIL}. Use them with a following semicolon,
|
4861 |
|
|
as a statement.
|
4862 |
|
|
|
4863 |
|
|
@table @code
|
4864 |
|
|
|
4865 |
|
|
@findex DONE
|
4866 |
|
|
@item DONE
|
4867 |
|
|
Use the @code{DONE} macro to end RTL generation for the pattern. The
|
4868 |
|
|
only RTL insns resulting from the pattern on this occasion will be
|
4869 |
|
|
those already emitted by explicit calls to @code{emit_insn} within the
|
4870 |
|
|
preparation statements; the RTL template will not be generated.
|
4871 |
|
|
|
4872 |
|
|
@findex FAIL
|
4873 |
|
|
@item FAIL
|
4874 |
|
|
Make the pattern fail on this occasion. When a pattern fails, it means
|
4875 |
|
|
that the pattern was not truly available. The calling routines in the
|
4876 |
|
|
compiler will try other strategies for code generation using other patterns.
|
4877 |
|
|
|
4878 |
|
|
Failure is currently supported only for binary (addition, multiplication,
|
4879 |
|
|
shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
|
4880 |
|
|
operations.
|
4881 |
|
|
@end table
|
4882 |
|
|
|
4883 |
|
|
If the preparation falls through (invokes neither @code{DONE} nor
|
4884 |
|
|
@code{FAIL}), then the @code{define_expand} acts like a
|
4885 |
|
|
@code{define_insn} in that the RTL template is used to generate the
|
4886 |
|
|
insn.
|
4887 |
|
|
|
4888 |
|
|
The RTL template is not used for matching, only for generating the
|
4889 |
|
|
initial insn list. If the preparation statement always invokes
|
4890 |
|
|
@code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
|
4891 |
|
|
list of operands, such as this example:
|
4892 |
|
|
|
4893 |
|
|
@smallexample
|
4894 |
|
|
@group
|
4895 |
|
|
(define_expand "addsi3"
|
4896 |
|
|
[(match_operand:SI 0 "register_operand" "")
|
4897 |
|
|
(match_operand:SI 1 "register_operand" "")
|
4898 |
|
|
(match_operand:SI 2 "register_operand" "")]
|
4899 |
|
|
@end group
|
4900 |
|
|
@group
|
4901 |
|
|
""
|
4902 |
|
|
"
|
4903 |
|
|
@{
|
4904 |
|
|
handle_add (operands[0], operands[1], operands[2]);
|
4905 |
|
|
DONE;
|
4906 |
|
|
@}")
|
4907 |
|
|
@end group
|
4908 |
|
|
@end smallexample
|
4909 |
|
|
|
4910 |
|
|
Here is an example, the definition of left-shift for the SPUR chip:
|
4911 |
|
|
|
4912 |
|
|
@smallexample
|
4913 |
|
|
@group
|
4914 |
|
|
(define_expand "ashlsi3"
|
4915 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
4916 |
|
|
(ashift:SI
|
4917 |
|
|
@end group
|
4918 |
|
|
@group
|
4919 |
|
|
(match_operand:SI 1 "register_operand" "")
|
4920 |
|
|
(match_operand:SI 2 "nonmemory_operand" "")))]
|
4921 |
|
|
""
|
4922 |
|
|
"
|
4923 |
|
|
@end group
|
4924 |
|
|
@end smallexample
|
4925 |
|
|
|
4926 |
|
|
@smallexample
|
4927 |
|
|
@group
|
4928 |
|
|
@{
|
4929 |
|
|
if (GET_CODE (operands[2]) != CONST_INT
|
4930 |
|
|
|| (unsigned) INTVAL (operands[2]) > 3)
|
4931 |
|
|
FAIL;
|
4932 |
|
|
@}")
|
4933 |
|
|
@end group
|
4934 |
|
|
@end smallexample
|
4935 |
|
|
|
4936 |
|
|
@noindent
|
4937 |
|
|
This example uses @code{define_expand} so that it can generate an RTL insn
|
4938 |
|
|
for shifting when the shift-count is in the supported range of 0 to 3 but
|
4939 |
|
|
fail in other cases where machine insns aren't available. When it fails,
|
4940 |
|
|
the compiler tries another strategy using different patterns (such as, a
|
4941 |
|
|
library call).
|
4942 |
|
|
|
4943 |
|
|
If the compiler were able to handle nontrivial condition-strings in
|
4944 |
|
|
patterns with names, then it would be possible to use a
|
4945 |
|
|
@code{define_insn} in that case. Here is another case (zero-extension
|
4946 |
|
|
on the 68000) which makes more use of the power of @code{define_expand}:
|
4947 |
|
|
|
4948 |
|
|
@smallexample
|
4949 |
|
|
(define_expand "zero_extendhisi2"
|
4950 |
|
|
[(set (match_operand:SI 0 "general_operand" "")
|
4951 |
|
|
(const_int 0))
|
4952 |
|
|
(set (strict_low_part
|
4953 |
|
|
(subreg:HI
|
4954 |
|
|
(match_dup 0)
|
4955 |
|
|
0))
|
4956 |
|
|
(match_operand:HI 1 "general_operand" ""))]
|
4957 |
|
|
""
|
4958 |
|
|
"operands[1] = make_safe_from (operands[1], operands[0]);")
|
4959 |
|
|
@end smallexample
|
4960 |
|
|
|
4961 |
|
|
@noindent
|
4962 |
|
|
@findex make_safe_from
|
4963 |
|
|
Here two RTL insns are generated, one to clear the entire output operand
|
4964 |
|
|
and the other to copy the input operand into its low half. This sequence
|
4965 |
|
|
is incorrect if the input operand refers to [the old value of] the output
|
4966 |
|
|
operand, so the preparation statement makes sure this isn't so. The
|
4967 |
|
|
function @code{make_safe_from} copies the @code{operands[1]} into a
|
4968 |
|
|
temporary register if it refers to @code{operands[0]}. It does this
|
4969 |
|
|
by emitting another RTL insn.
|
4970 |
|
|
|
4971 |
|
|
Finally, a third example shows the use of an internal operand.
|
4972 |
|
|
Zero-extension on the SPUR chip is done by @code{and}-ing the result
|
4973 |
|
|
against a halfword mask. But this mask cannot be represented by a
|
4974 |
|
|
@code{const_int} because the constant value is too large to be legitimate
|
4975 |
|
|
on this machine. So it must be copied into a register with
|
4976 |
|
|
@code{force_reg} and then the register used in the @code{and}.
|
4977 |
|
|
|
4978 |
|
|
@smallexample
|
4979 |
|
|
(define_expand "zero_extendhisi2"
|
4980 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
4981 |
|
|
(and:SI (subreg:SI
|
4982 |
|
|
(match_operand:HI 1 "register_operand" "")
|
4983 |
|
|
0)
|
4984 |
|
|
(match_dup 2)))]
|
4985 |
|
|
""
|
4986 |
|
|
"operands[2]
|
4987 |
|
|
= force_reg (SImode, GEN_INT (65535)); ")
|
4988 |
|
|
@end smallexample
|
4989 |
|
|
|
4990 |
|
|
@emph{Note:} If the @code{define_expand} is used to serve a
|
4991 |
|
|
standard binary or unary arithmetic operation or a bit-field operation,
|
4992 |
|
|
then the last insn it generates must not be a @code{code_label},
|
4993 |
|
|
@code{barrier} or @code{note}. It must be an @code{insn},
|
4994 |
|
|
@code{jump_insn} or @code{call_insn}. If you don't need a real insn
|
4995 |
|
|
at the end, emit an insn to copy the result of the operation into
|
4996 |
|
|
itself. Such an insn will generate no code, but it can avoid problems
|
4997 |
|
|
in the compiler.
|
4998 |
|
|
|
4999 |
|
|
@end ifset
|
5000 |
|
|
@ifset INTERNALS
|
5001 |
|
|
@node Insn Splitting
|
5002 |
|
|
@section Defining How to Split Instructions
|
5003 |
|
|
@cindex insn splitting
|
5004 |
|
|
@cindex instruction splitting
|
5005 |
|
|
@cindex splitting instructions
|
5006 |
|
|
|
5007 |
|
|
There are two cases where you should specify how to split a pattern
|
5008 |
|
|
into multiple insns. On machines that have instructions requiring
|
5009 |
|
|
delay slots (@pxref{Delay Slots}) or that have instructions whose
|
5010 |
|
|
output is not available for multiple cycles (@pxref{Processor pipeline
|
5011 |
|
|
description}), the compiler phases that optimize these cases need to
|
5012 |
|
|
be able to move insns into one-instruction delay slots. However, some
|
5013 |
|
|
insns may generate more than one machine instruction. These insns
|
5014 |
|
|
cannot be placed into a delay slot.
|
5015 |
|
|
|
5016 |
|
|
Often you can rewrite the single insn as a list of individual insns,
|
5017 |
|
|
each corresponding to one machine instruction. The disadvantage of
|
5018 |
|
|
doing so is that it will cause the compilation to be slower and require
|
5019 |
|
|
more space. If the resulting insns are too complex, it may also
|
5020 |
|
|
suppress some optimizations. The compiler splits the insn if there is a
|
5021 |
|
|
reason to believe that it might improve instruction or delay slot
|
5022 |
|
|
scheduling.
|
5023 |
|
|
|
5024 |
|
|
The insn combiner phase also splits putative insns. If three insns are
|
5025 |
|
|
merged into one insn with a complex expression that cannot be matched by
|
5026 |
|
|
some @code{define_insn} pattern, the combiner phase attempts to split
|
5027 |
|
|
the complex pattern into two insns that are recognized. Usually it can
|
5028 |
|
|
break the complex pattern into two patterns by splitting out some
|
5029 |
|
|
subexpression. However, in some other cases, such as performing an
|
5030 |
|
|
addition of a large constant in two insns on a RISC machine, the way to
|
5031 |
|
|
split the addition into two insns is machine-dependent.
|
5032 |
|
|
|
5033 |
|
|
@findex define_split
|
5034 |
|
|
The @code{define_split} definition tells the compiler how to split a
|
5035 |
|
|
complex insn into several simpler insns. It looks like this:
|
5036 |
|
|
|
5037 |
|
|
@smallexample
|
5038 |
|
|
(define_split
|
5039 |
|
|
[@var{insn-pattern}]
|
5040 |
|
|
"@var{condition}"
|
5041 |
|
|
[@var{new-insn-pattern-1}
|
5042 |
|
|
@var{new-insn-pattern-2}
|
5043 |
|
|
@dots{}]
|
5044 |
|
|
"@var{preparation-statements}")
|
5045 |
|
|
@end smallexample
|
5046 |
|
|
|
5047 |
|
|
@var{insn-pattern} is a pattern that needs to be split and
|
5048 |
|
|
@var{condition} is the final condition to be tested, as in a
|
5049 |
|
|
@code{define_insn}. When an insn matching @var{insn-pattern} and
|
5050 |
|
|
satisfying @var{condition} is found, it is replaced in the insn list
|
5051 |
|
|
with the insns given by @var{new-insn-pattern-1},
|
5052 |
|
|
@var{new-insn-pattern-2}, etc.
|
5053 |
|
|
|
5054 |
|
|
The @var{preparation-statements} are similar to those statements that
|
5055 |
|
|
are specified for @code{define_expand} (@pxref{Expander Definitions})
|
5056 |
|
|
and are executed before the new RTL is generated to prepare for the
|
5057 |
|
|
generated code or emit some insns whose pattern is not fixed. Unlike
|
5058 |
|
|
those in @code{define_expand}, however, these statements must not
|
5059 |
|
|
generate any new pseudo-registers. Once reload has completed, they also
|
5060 |
|
|
must not allocate any space in the stack frame.
|
5061 |
|
|
|
5062 |
|
|
Patterns are matched against @var{insn-pattern} in two different
|
5063 |
|
|
circumstances. If an insn needs to be split for delay slot scheduling
|
5064 |
|
|
or insn scheduling, the insn is already known to be valid, which means
|
5065 |
|
|
that it must have been matched by some @code{define_insn} and, if
|
5066 |
|
|
@code{reload_completed} is nonzero, is known to satisfy the constraints
|
5067 |
|
|
of that @code{define_insn}. In that case, the new insn patterns must
|
5068 |
|
|
also be insns that are matched by some @code{define_insn} and, if
|
5069 |
|
|
@code{reload_completed} is nonzero, must also satisfy the constraints
|
5070 |
|
|
of those definitions.
|
5071 |
|
|
|
5072 |
|
|
As an example of this usage of @code{define_split}, consider the following
|
5073 |
|
|
example from @file{a29k.md}, which splits a @code{sign_extend} from
|
5074 |
|
|
@code{HImode} to @code{SImode} into a pair of shift insns:
|
5075 |
|
|
|
5076 |
|
|
@smallexample
|
5077 |
|
|
(define_split
|
5078 |
|
|
[(set (match_operand:SI 0 "gen_reg_operand" "")
|
5079 |
|
|
(sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
|
5080 |
|
|
""
|
5081 |
|
|
[(set (match_dup 0)
|
5082 |
|
|
(ashift:SI (match_dup 1)
|
5083 |
|
|
(const_int 16)))
|
5084 |
|
|
(set (match_dup 0)
|
5085 |
|
|
(ashiftrt:SI (match_dup 0)
|
5086 |
|
|
(const_int 16)))]
|
5087 |
|
|
"
|
5088 |
|
|
@{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
|
5089 |
|
|
@end smallexample
|
5090 |
|
|
|
5091 |
|
|
When the combiner phase tries to split an insn pattern, it is always the
|
5092 |
|
|
case that the pattern is @emph{not} matched by any @code{define_insn}.
|
5093 |
|
|
The combiner pass first tries to split a single @code{set} expression
|
5094 |
|
|
and then the same @code{set} expression inside a @code{parallel}, but
|
5095 |
|
|
followed by a @code{clobber} of a pseudo-reg to use as a scratch
|
5096 |
|
|
register. In these cases, the combiner expects exactly two new insn
|
5097 |
|
|
patterns to be generated. It will verify that these patterns match some
|
5098 |
|
|
@code{define_insn} definitions, so you need not do this test in the
|
5099 |
|
|
@code{define_split} (of course, there is no point in writing a
|
5100 |
|
|
@code{define_split} that will never produce insns that match).
|
5101 |
|
|
|
5102 |
|
|
Here is an example of this use of @code{define_split}, taken from
|
5103 |
|
|
@file{rs6000.md}:
|
5104 |
|
|
|
5105 |
|
|
@smallexample
|
5106 |
|
|
(define_split
|
5107 |
|
|
[(set (match_operand:SI 0 "gen_reg_operand" "")
|
5108 |
|
|
(plus:SI (match_operand:SI 1 "gen_reg_operand" "")
|
5109 |
|
|
(match_operand:SI 2 "non_add_cint_operand" "")))]
|
5110 |
|
|
""
|
5111 |
|
|
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
|
5112 |
|
|
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
|
5113 |
|
|
"
|
5114 |
|
|
@{
|
5115 |
|
|
int low = INTVAL (operands[2]) & 0xffff;
|
5116 |
|
|
int high = (unsigned) INTVAL (operands[2]) >> 16;
|
5117 |
|
|
|
5118 |
|
|
if (low & 0x8000)
|
5119 |
|
|
high++, low |= 0xffff0000;
|
5120 |
|
|
|
5121 |
|
|
operands[3] = GEN_INT (high << 16);
|
5122 |
|
|
operands[4] = GEN_INT (low);
|
5123 |
|
|
@}")
|
5124 |
|
|
@end smallexample
|
5125 |
|
|
|
5126 |
|
|
Here the predicate @code{non_add_cint_operand} matches any
|
5127 |
|
|
@code{const_int} that is @emph{not} a valid operand of a single add
|
5128 |
|
|
insn. The add with the smaller displacement is written so that it
|
5129 |
|
|
can be substituted into the address of a subsequent operation.
|
5130 |
|
|
|
5131 |
|
|
An example that uses a scratch register, from the same file, generates
|
5132 |
|
|
an equality comparison of a register and a large constant:
|
5133 |
|
|
|
5134 |
|
|
@smallexample
|
5135 |
|
|
(define_split
|
5136 |
|
|
[(set (match_operand:CC 0 "cc_reg_operand" "")
|
5137 |
|
|
(compare:CC (match_operand:SI 1 "gen_reg_operand" "")
|
5138 |
|
|
(match_operand:SI 2 "non_short_cint_operand" "")))
|
5139 |
|
|
(clobber (match_operand:SI 3 "gen_reg_operand" ""))]
|
5140 |
|
|
"find_single_use (operands[0], insn, 0)
|
5141 |
|
|
&& (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
|
5142 |
|
|
|| GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
|
5143 |
|
|
[(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
|
5144 |
|
|
(set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
|
5145 |
|
|
"
|
5146 |
|
|
@{
|
5147 |
|
|
/* @r{Get the constant we are comparing against, C, and see what it
|
5148 |
|
|
looks like sign-extended to 16 bits. Then see what constant
|
5149 |
|
|
could be XOR'ed with C to get the sign-extended value.} */
|
5150 |
|
|
|
5151 |
|
|
int c = INTVAL (operands[2]);
|
5152 |
|
|
int sextc = (c << 16) >> 16;
|
5153 |
|
|
int xorv = c ^ sextc;
|
5154 |
|
|
|
5155 |
|
|
operands[4] = GEN_INT (xorv);
|
5156 |
|
|
operands[5] = GEN_INT (sextc);
|
5157 |
|
|
@}")
|
5158 |
|
|
@end smallexample
|
5159 |
|
|
|
5160 |
|
|
To avoid confusion, don't write a single @code{define_split} that
|
5161 |
|
|
accepts some insns that match some @code{define_insn} as well as some
|
5162 |
|
|
insns that don't. Instead, write two separate @code{define_split}
|
5163 |
|
|
definitions, one for the insns that are valid and one for the insns that
|
5164 |
|
|
are not valid.
|
5165 |
|
|
|
5166 |
|
|
The splitter is allowed to split jump instructions into sequence of
|
5167 |
|
|
jumps or create new jumps in while splitting non-jump instructions. As
|
5168 |
|
|
the central flowgraph and branch prediction information needs to be updated,
|
5169 |
|
|
several restriction apply.
|
5170 |
|
|
|
5171 |
|
|
Splitting of jump instruction into sequence that over by another jump
|
5172 |
|
|
instruction is always valid, as compiler expect identical behavior of new
|
5173 |
|
|
jump. When new sequence contains multiple jump instructions or new labels,
|
5174 |
|
|
more assistance is needed. Splitter is required to create only unconditional
|
5175 |
|
|
jumps, or simple conditional jump instructions. Additionally it must attach a
|
5176 |
|
|
@code{REG_BR_PROB} note to each conditional jump. A global variable
|
5177 |
|
|
@code{split_branch_probability} holds the probability of the original branch in case
|
5178 |
|
|
it was an simple conditional jump, @minus{}1 otherwise. To simplify
|
5179 |
|
|
recomputing of edge frequencies, the new sequence is required to have only
|
5180 |
|
|
forward jumps to the newly created labels.
|
5181 |
|
|
|
5182 |
|
|
@findex define_insn_and_split
|
5183 |
|
|
For the common case where the pattern of a define_split exactly matches the
|
5184 |
|
|
pattern of a define_insn, use @code{define_insn_and_split}. It looks like
|
5185 |
|
|
this:
|
5186 |
|
|
|
5187 |
|
|
@smallexample
|
5188 |
|
|
(define_insn_and_split
|
5189 |
|
|
[@var{insn-pattern}]
|
5190 |
|
|
"@var{condition}"
|
5191 |
|
|
"@var{output-template}"
|
5192 |
|
|
"@var{split-condition}"
|
5193 |
|
|
[@var{new-insn-pattern-1}
|
5194 |
|
|
@var{new-insn-pattern-2}
|
5195 |
|
|
@dots{}]
|
5196 |
|
|
"@var{preparation-statements}"
|
5197 |
|
|
[@var{insn-attributes}])
|
5198 |
|
|
|
5199 |
|
|
@end smallexample
|
5200 |
|
|
|
5201 |
|
|
@var{insn-pattern}, @var{condition}, @var{output-template}, and
|
5202 |
|
|
@var{insn-attributes} are used as in @code{define_insn}. The
|
5203 |
|
|
@var{new-insn-pattern} vector and the @var{preparation-statements} are used as
|
5204 |
|
|
in a @code{define_split}. The @var{split-condition} is also used as in
|
5205 |
|
|
@code{define_split}, with the additional behavior that if the condition starts
|
5206 |
|
|
with @samp{&&}, the condition used for the split will be the constructed as a
|
5207 |
|
|
logical ``and'' of the split condition with the insn condition. For example,
|
5208 |
|
|
from i386.md:
|
5209 |
|
|
|
5210 |
|
|
@smallexample
|
5211 |
|
|
(define_insn_and_split "zero_extendhisi2_and"
|
5212 |
|
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
5213 |
|
|
(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
|
5214 |
|
|
(clobber (reg:CC 17))]
|
5215 |
|
|
"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
|
5216 |
|
|
"#"
|
5217 |
|
|
"&& reload_completed"
|
5218 |
|
|
[(parallel [(set (match_dup 0)
|
5219 |
|
|
(and:SI (match_dup 0) (const_int 65535)))
|
5220 |
|
|
(clobber (reg:CC 17))])]
|
5221 |
|
|
""
|
5222 |
|
|
[(set_attr "type" "alu1")])
|
5223 |
|
|
|
5224 |
|
|
@end smallexample
|
5225 |
|
|
|
5226 |
|
|
In this case, the actual split condition will be
|
5227 |
|
|
@samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
|
5228 |
|
|
|
5229 |
|
|
The @code{define_insn_and_split} construction provides exactly the same
|
5230 |
|
|
functionality as two separate @code{define_insn} and @code{define_split}
|
5231 |
|
|
patterns. It exists for compactness, and as a maintenance tool to prevent
|
5232 |
|
|
having to ensure the two patterns' templates match.
|
5233 |
|
|
|
5234 |
|
|
@end ifset
|
5235 |
|
|
@ifset INTERNALS
|
5236 |
|
|
@node Including Patterns
|
5237 |
|
|
@section Including Patterns in Machine Descriptions.
|
5238 |
|
|
@cindex insn includes
|
5239 |
|
|
|
5240 |
|
|
@findex include
|
5241 |
|
|
The @code{include} pattern tells the compiler tools where to
|
5242 |
|
|
look for patterns that are in files other than in the file
|
5243 |
|
|
@file{.md}. This is used only at build time and there is no preprocessing allowed.
|
5244 |
|
|
|
5245 |
|
|
It looks like:
|
5246 |
|
|
|
5247 |
|
|
@smallexample
|
5248 |
|
|
|
5249 |
|
|
(include
|
5250 |
|
|
@var{pathname})
|
5251 |
|
|
@end smallexample
|
5252 |
|
|
|
5253 |
|
|
For example:
|
5254 |
|
|
|
5255 |
|
|
@smallexample
|
5256 |
|
|
|
5257 |
|
|
(include "filestuff")
|
5258 |
|
|
|
5259 |
|
|
@end smallexample
|
5260 |
|
|
|
5261 |
|
|
Where @var{pathname} is a string that specifies the location of the file,
|
5262 |
|
|
specifies the include file to be in @file{gcc/config/target/filestuff}. The
|
5263 |
|
|
directory @file{gcc/config/target} is regarded as the default directory.
|
5264 |
|
|
|
5265 |
|
|
|
5266 |
|
|
Machine descriptions may be split up into smaller more manageable subsections
|
5267 |
|
|
and placed into subdirectories.
|
5268 |
|
|
|
5269 |
|
|
By specifying:
|
5270 |
|
|
|
5271 |
|
|
@smallexample
|
5272 |
|
|
|
5273 |
|
|
(include "BOGUS/filestuff")
|
5274 |
|
|
|
5275 |
|
|
@end smallexample
|
5276 |
|
|
|
5277 |
|
|
the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
|
5278 |
|
|
|
5279 |
|
|
Specifying an absolute path for the include file such as;
|
5280 |
|
|
@smallexample
|
5281 |
|
|
|
5282 |
|
|
(include "/u2/BOGUS/filestuff")
|
5283 |
|
|
|
5284 |
|
|
@end smallexample
|
5285 |
|
|
is permitted but is not encouraged.
|
5286 |
|
|
|
5287 |
|
|
@subsection RTL Generation Tool Options for Directory Search
|
5288 |
|
|
@cindex directory options .md
|
5289 |
|
|
@cindex options, directory search
|
5290 |
|
|
@cindex search options
|
5291 |
|
|
|
5292 |
|
|
The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
|
5293 |
|
|
For example:
|
5294 |
|
|
|
5295 |
|
|
@smallexample
|
5296 |
|
|
|
5297 |
|
|
genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
|
5298 |
|
|
|
5299 |
|
|
@end smallexample
|
5300 |
|
|
|
5301 |
|
|
|
5302 |
|
|
Add the directory @var{dir} to the head of the list of directories to be
|
5303 |
|
|
searched for header files. This can be used to override a system machine definition
|
5304 |
|
|
file, substituting your own version, since these directories are
|
5305 |
|
|
searched before the default machine description file directories. If you use more than
|
5306 |
|
|
one @option{-I} option, the directories are scanned in left-to-right
|
5307 |
|
|
order; the standard default directory come after.
|
5308 |
|
|
|
5309 |
|
|
|
5310 |
|
|
@end ifset
|
5311 |
|
|
@ifset INTERNALS
|
5312 |
|
|
@node Peephole Definitions
|
5313 |
|
|
@section Machine-Specific Peephole Optimizers
|
5314 |
|
|
@cindex peephole optimizer definitions
|
5315 |
|
|
@cindex defining peephole optimizers
|
5316 |
|
|
|
5317 |
|
|
In addition to instruction patterns the @file{md} file may contain
|
5318 |
|
|
definitions of machine-specific peephole optimizations.
|
5319 |
|
|
|
5320 |
|
|
The combiner does not notice certain peephole optimizations when the data
|
5321 |
|
|
flow in the program does not suggest that it should try them. For example,
|
5322 |
|
|
sometimes two consecutive insns related in purpose can be combined even
|
5323 |
|
|
though the second one does not appear to use a register computed in the
|
5324 |
|
|
first one. A machine-specific peephole optimizer can detect such
|
5325 |
|
|
opportunities.
|
5326 |
|
|
|
5327 |
|
|
There are two forms of peephole definitions that may be used. The
|
5328 |
|
|
original @code{define_peephole} is run at assembly output time to
|
5329 |
|
|
match insns and substitute assembly text. Use of @code{define_peephole}
|
5330 |
|
|
is deprecated.
|
5331 |
|
|
|
5332 |
|
|
A newer @code{define_peephole2} matches insns and substitutes new
|
5333 |
|
|
insns. The @code{peephole2} pass is run after register allocation
|
5334 |
|
|
but before scheduling, which may result in much better code for
|
5335 |
|
|
targets that do scheduling.
|
5336 |
|
|
|
5337 |
|
|
@menu
|
5338 |
|
|
* define_peephole:: RTL to Text Peephole Optimizers
|
5339 |
|
|
* define_peephole2:: RTL to RTL Peephole Optimizers
|
5340 |
|
|
@end menu
|
5341 |
|
|
|
5342 |
|
|
@end ifset
|
5343 |
|
|
@ifset INTERNALS
|
5344 |
|
|
@node define_peephole
|
5345 |
|
|
@subsection RTL to Text Peephole Optimizers
|
5346 |
|
|
@findex define_peephole
|
5347 |
|
|
|
5348 |
|
|
@need 1000
|
5349 |
|
|
A definition looks like this:
|
5350 |
|
|
|
5351 |
|
|
@smallexample
|
5352 |
|
|
(define_peephole
|
5353 |
|
|
[@var{insn-pattern-1}
|
5354 |
|
|
@var{insn-pattern-2}
|
5355 |
|
|
@dots{}]
|
5356 |
|
|
"@var{condition}"
|
5357 |
|
|
"@var{template}"
|
5358 |
|
|
"@var{optional-insn-attributes}")
|
5359 |
|
|
@end smallexample
|
5360 |
|
|
|
5361 |
|
|
@noindent
|
5362 |
|
|
The last string operand may be omitted if you are not using any
|
5363 |
|
|
machine-specific information in this machine description. If present,
|
5364 |
|
|
it must obey the same rules as in a @code{define_insn}.
|
5365 |
|
|
|
5366 |
|
|
In this skeleton, @var{insn-pattern-1} and so on are patterns to match
|
5367 |
|
|
consecutive insns. The optimization applies to a sequence of insns when
|
5368 |
|
|
@var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
|
5369 |
|
|
the next, and so on.
|
5370 |
|
|
|
5371 |
|
|
Each of the insns matched by a peephole must also match a
|
5372 |
|
|
@code{define_insn}. Peepholes are checked only at the last stage just
|
5373 |
|
|
before code generation, and only optionally. Therefore, any insn which
|
5374 |
|
|
would match a peephole but no @code{define_insn} will cause a crash in code
|
5375 |
|
|
generation in an unoptimized compilation, or at various optimization
|
5376 |
|
|
stages.
|
5377 |
|
|
|
5378 |
|
|
The operands of the insns are matched with @code{match_operands},
|
5379 |
|
|
@code{match_operator}, and @code{match_dup}, as usual. What is not
|
5380 |
|
|
usual is that the operand numbers apply to all the insn patterns in the
|
5381 |
|
|
definition. So, you can check for identical operands in two insns by
|
5382 |
|
|
using @code{match_operand} in one insn and @code{match_dup} in the
|
5383 |
|
|
other.
|
5384 |
|
|
|
5385 |
|
|
The operand constraints used in @code{match_operand} patterns do not have
|
5386 |
|
|
any direct effect on the applicability of the peephole, but they will
|
5387 |
|
|
be validated afterward, so make sure your constraints are general enough
|
5388 |
|
|
to apply whenever the peephole matches. If the peephole matches
|
5389 |
|
|
but the constraints are not satisfied, the compiler will crash.
|
5390 |
|
|
|
5391 |
|
|
It is safe to omit constraints in all the operands of the peephole; or
|
5392 |
|
|
you can write constraints which serve as a double-check on the criteria
|
5393 |
|
|
previously tested.
|
5394 |
|
|
|
5395 |
|
|
Once a sequence of insns matches the patterns, the @var{condition} is
|
5396 |
|
|
checked. This is a C expression which makes the final decision whether to
|
5397 |
|
|
perform the optimization (we do so if the expression is nonzero). If
|
5398 |
|
|
@var{condition} is omitted (in other words, the string is empty) then the
|
5399 |
|
|
optimization is applied to every sequence of insns that matches the
|
5400 |
|
|
patterns.
|
5401 |
|
|
|
5402 |
|
|
The defined peephole optimizations are applied after register allocation
|
5403 |
|
|
is complete. Therefore, the peephole definition can check which
|
5404 |
|
|
operands have ended up in which kinds of registers, just by looking at
|
5405 |
|
|
the operands.
|
5406 |
|
|
|
5407 |
|
|
@findex prev_active_insn
|
5408 |
|
|
The way to refer to the operands in @var{condition} is to write
|
5409 |
|
|
@code{operands[@var{i}]} for operand number @var{i} (as matched by
|
5410 |
|
|
@code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
|
5411 |
|
|
to refer to the last of the insns being matched; use
|
5412 |
|
|
@code{prev_active_insn} to find the preceding insns.
|
5413 |
|
|
|
5414 |
|
|
@findex dead_or_set_p
|
5415 |
|
|
When optimizing computations with intermediate results, you can use
|
5416 |
|
|
@var{condition} to match only when the intermediate results are not used
|
5417 |
|
|
elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
|
5418 |
|
|
@var{op})}, where @var{insn} is the insn in which you expect the value
|
5419 |
|
|
to be used for the last time (from the value of @code{insn}, together
|
5420 |
|
|
with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
|
5421 |
|
|
value (from @code{operands[@var{i}]}).
|
5422 |
|
|
|
5423 |
|
|
Applying the optimization means replacing the sequence of insns with one
|
5424 |
|
|
new insn. The @var{template} controls ultimate output of assembler code
|
5425 |
|
|
for this combined insn. It works exactly like the template of a
|
5426 |
|
|
@code{define_insn}. Operand numbers in this template are the same ones
|
5427 |
|
|
used in matching the original sequence of insns.
|
5428 |
|
|
|
5429 |
|
|
The result of a defined peephole optimizer does not need to match any of
|
5430 |
|
|
the insn patterns in the machine description; it does not even have an
|
5431 |
|
|
opportunity to match them. The peephole optimizer definition itself serves
|
5432 |
|
|
as the insn pattern to control how the insn is output.
|
5433 |
|
|
|
5434 |
|
|
Defined peephole optimizers are run as assembler code is being output,
|
5435 |
|
|
so the insns they produce are never combined or rearranged in any way.
|
5436 |
|
|
|
5437 |
|
|
Here is an example, taken from the 68000 machine description:
|
5438 |
|
|
|
5439 |
|
|
@smallexample
|
5440 |
|
|
(define_peephole
|
5441 |
|
|
[(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
|
5442 |
|
|
(set (match_operand:DF 0 "register_operand" "=f")
|
5443 |
|
|
(match_operand:DF 1 "register_operand" "ad"))]
|
5444 |
|
|
"FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
|
5445 |
|
|
@{
|
5446 |
|
|
rtx xoperands[2];
|
5447 |
|
|
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
|
5448 |
|
|
#ifdef MOTOROLA
|
5449 |
|
|
output_asm_insn ("move.l %1,(sp)", xoperands);
|
5450 |
|
|
output_asm_insn ("move.l %1,-(sp)", operands);
|
5451 |
|
|
return "fmove.d (sp)+,%0";
|
5452 |
|
|
#else
|
5453 |
|
|
output_asm_insn ("movel %1,sp@@", xoperands);
|
5454 |
|
|
output_asm_insn ("movel %1,sp@@-", operands);
|
5455 |
|
|
return "fmoved sp@@+,%0";
|
5456 |
|
|
#endif
|
5457 |
|
|
@})
|
5458 |
|
|
@end smallexample
|
5459 |
|
|
|
5460 |
|
|
@need 1000
|
5461 |
|
|
The effect of this optimization is to change
|
5462 |
|
|
|
5463 |
|
|
@smallexample
|
5464 |
|
|
@group
|
5465 |
|
|
jbsr _foobar
|
5466 |
|
|
addql #4,sp
|
5467 |
|
|
movel d1,sp@@-
|
5468 |
|
|
movel d0,sp@@-
|
5469 |
|
|
fmoved sp@@+,fp0
|
5470 |
|
|
@end group
|
5471 |
|
|
@end smallexample
|
5472 |
|
|
|
5473 |
|
|
@noindent
|
5474 |
|
|
into
|
5475 |
|
|
|
5476 |
|
|
@smallexample
|
5477 |
|
|
@group
|
5478 |
|
|
jbsr _foobar
|
5479 |
|
|
movel d1,sp@@
|
5480 |
|
|
movel d0,sp@@-
|
5481 |
|
|
fmoved sp@@+,fp0
|
5482 |
|
|
@end group
|
5483 |
|
|
@end smallexample
|
5484 |
|
|
|
5485 |
|
|
@ignore
|
5486 |
|
|
@findex CC_REVERSED
|
5487 |
|
|
If a peephole matches a sequence including one or more jump insns, you must
|
5488 |
|
|
take account of the flags such as @code{CC_REVERSED} which specify that the
|
5489 |
|
|
condition codes are represented in an unusual manner. The compiler
|
5490 |
|
|
automatically alters any ordinary conditional jumps which occur in such
|
5491 |
|
|
situations, but the compiler cannot alter jumps which have been replaced by
|
5492 |
|
|
peephole optimizations. So it is up to you to alter the assembler code
|
5493 |
|
|
that the peephole produces. Supply C code to write the assembler output,
|
5494 |
|
|
and in this C code check the condition code status flags and change the
|
5495 |
|
|
assembler code as appropriate.
|
5496 |
|
|
@end ignore
|
5497 |
|
|
|
5498 |
|
|
@var{insn-pattern-1} and so on look @emph{almost} like the second
|
5499 |
|
|
operand of @code{define_insn}. There is one important difference: the
|
5500 |
|
|
second operand of @code{define_insn} consists of one or more RTX's
|
5501 |
|
|
enclosed in square brackets. Usually, there is only one: then the same
|
5502 |
|
|
action can be written as an element of a @code{define_peephole}. But
|
5503 |
|
|
when there are multiple actions in a @code{define_insn}, they are
|
5504 |
|
|
implicitly enclosed in a @code{parallel}. Then you must explicitly
|
5505 |
|
|
write the @code{parallel}, and the square brackets within it, in the
|
5506 |
|
|
@code{define_peephole}. Thus, if an insn pattern looks like this,
|
5507 |
|
|
|
5508 |
|
|
@smallexample
|
5509 |
|
|
(define_insn "divmodsi4"
|
5510 |
|
|
[(set (match_operand:SI 0 "general_operand" "=d")
|
5511 |
|
|
(div:SI (match_operand:SI 1 "general_operand" "0")
|
5512 |
|
|
(match_operand:SI 2 "general_operand" "dmsK")))
|
5513 |
|
|
(set (match_operand:SI 3 "general_operand" "=d")
|
5514 |
|
|
(mod:SI (match_dup 1) (match_dup 2)))]
|
5515 |
|
|
"TARGET_68020"
|
5516 |
|
|
"divsl%.l %2,%3:%0")
|
5517 |
|
|
@end smallexample
|
5518 |
|
|
|
5519 |
|
|
@noindent
|
5520 |
|
|
then the way to mention this insn in a peephole is as follows:
|
5521 |
|
|
|
5522 |
|
|
@smallexample
|
5523 |
|
|
(define_peephole
|
5524 |
|
|
[@dots{}
|
5525 |
|
|
(parallel
|
5526 |
|
|
[(set (match_operand:SI 0 "general_operand" "=d")
|
5527 |
|
|
(div:SI (match_operand:SI 1 "general_operand" "0")
|
5528 |
|
|
(match_operand:SI 2 "general_operand" "dmsK")))
|
5529 |
|
|
(set (match_operand:SI 3 "general_operand" "=d")
|
5530 |
|
|
(mod:SI (match_dup 1) (match_dup 2)))])
|
5531 |
|
|
@dots{}]
|
5532 |
|
|
@dots{})
|
5533 |
|
|
@end smallexample
|
5534 |
|
|
|
5535 |
|
|
@end ifset
|
5536 |
|
|
@ifset INTERNALS
|
5537 |
|
|
@node define_peephole2
|
5538 |
|
|
@subsection RTL to RTL Peephole Optimizers
|
5539 |
|
|
@findex define_peephole2
|
5540 |
|
|
|
5541 |
|
|
The @code{define_peephole2} definition tells the compiler how to
|
5542 |
|
|
substitute one sequence of instructions for another sequence,
|
5543 |
|
|
what additional scratch registers may be needed and what their
|
5544 |
|
|
lifetimes must be.
|
5545 |
|
|
|
5546 |
|
|
@smallexample
|
5547 |
|
|
(define_peephole2
|
5548 |
|
|
[@var{insn-pattern-1}
|
5549 |
|
|
@var{insn-pattern-2}
|
5550 |
|
|
@dots{}]
|
5551 |
|
|
"@var{condition}"
|
5552 |
|
|
[@var{new-insn-pattern-1}
|
5553 |
|
|
@var{new-insn-pattern-2}
|
5554 |
|
|
@dots{}]
|
5555 |
|
|
"@var{preparation-statements}")
|
5556 |
|
|
@end smallexample
|
5557 |
|
|
|
5558 |
|
|
The definition is almost identical to @code{define_split}
|
5559 |
|
|
(@pxref{Insn Splitting}) except that the pattern to match is not a
|
5560 |
|
|
single instruction, but a sequence of instructions.
|
5561 |
|
|
|
5562 |
|
|
It is possible to request additional scratch registers for use in the
|
5563 |
|
|
output template. If appropriate registers are not free, the pattern
|
5564 |
|
|
will simply not match.
|
5565 |
|
|
|
5566 |
|
|
@findex match_scratch
|
5567 |
|
|
@findex match_dup
|
5568 |
|
|
Scratch registers are requested with a @code{match_scratch} pattern at
|
5569 |
|
|
the top level of the input pattern. The allocated register (initially) will
|
5570 |
|
|
be dead at the point requested within the original sequence. If the scratch
|
5571 |
|
|
is used at more than a single point, a @code{match_dup} pattern at the
|
5572 |
|
|
top level of the input pattern marks the last position in the input sequence
|
5573 |
|
|
at which the register must be available.
|
5574 |
|
|
|
5575 |
|
|
Here is an example from the IA-32 machine description:
|
5576 |
|
|
|
5577 |
|
|
@smallexample
|
5578 |
|
|
(define_peephole2
|
5579 |
|
|
[(match_scratch:SI 2 "r")
|
5580 |
|
|
(parallel [(set (match_operand:SI 0 "register_operand" "")
|
5581 |
|
|
(match_operator:SI 3 "arith_or_logical_operator"
|
5582 |
|
|
[(match_dup 0)
|
5583 |
|
|
(match_operand:SI 1 "memory_operand" "")]))
|
5584 |
|
|
(clobber (reg:CC 17))])]
|
5585 |
|
|
"! optimize_size && ! TARGET_READ_MODIFY"
|
5586 |
|
|
[(set (match_dup 2) (match_dup 1))
|
5587 |
|
|
(parallel [(set (match_dup 0)
|
5588 |
|
|
(match_op_dup 3 [(match_dup 0) (match_dup 2)]))
|
5589 |
|
|
(clobber (reg:CC 17))])]
|
5590 |
|
|
"")
|
5591 |
|
|
@end smallexample
|
5592 |
|
|
|
5593 |
|
|
@noindent
|
5594 |
|
|
This pattern tries to split a load from its use in the hopes that we'll be
|
5595 |
|
|
able to schedule around the memory load latency. It allocates a single
|
5596 |
|
|
@code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
|
5597 |
|
|
to be live only at the point just before the arithmetic.
|
5598 |
|
|
|
5599 |
|
|
A real example requiring extended scratch lifetimes is harder to come by,
|
5600 |
|
|
so here's a silly made-up example:
|
5601 |
|
|
|
5602 |
|
|
@smallexample
|
5603 |
|
|
(define_peephole2
|
5604 |
|
|
[(match_scratch:SI 4 "r")
|
5605 |
|
|
(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
|
5606 |
|
|
(set (match_operand:SI 2 "" "") (match_dup 1))
|
5607 |
|
|
(match_dup 4)
|
5608 |
|
|
(set (match_operand:SI 3 "" "") (match_dup 1))]
|
5609 |
|
|
"/* @r{determine 1 does not overlap 0 and 2} */"
|
5610 |
|
|
[(set (match_dup 4) (match_dup 1))
|
5611 |
|
|
(set (match_dup 0) (match_dup 4))
|
5612 |
|
|
(set (match_dup 2) (match_dup 4))]
|
5613 |
|
|
(set (match_dup 3) (match_dup 4))]
|
5614 |
|
|
"")
|
5615 |
|
|
@end smallexample
|
5616 |
|
|
|
5617 |
|
|
@noindent
|
5618 |
|
|
If we had not added the @code{(match_dup 4)} in the middle of the input
|
5619 |
|
|
sequence, it might have been the case that the register we chose at the
|
5620 |
|
|
beginning of the sequence is killed by the first or second @code{set}.
|
5621 |
|
|
|
5622 |
|
|
@end ifset
|
5623 |
|
|
@ifset INTERNALS
|
5624 |
|
|
@node Insn Attributes
|
5625 |
|
|
@section Instruction Attributes
|
5626 |
|
|
@cindex insn attributes
|
5627 |
|
|
@cindex instruction attributes
|
5628 |
|
|
|
5629 |
|
|
In addition to describing the instruction supported by the target machine,
|
5630 |
|
|
the @file{md} file also defines a group of @dfn{attributes} and a set of
|
5631 |
|
|
values for each. Every generated insn is assigned a value for each attribute.
|
5632 |
|
|
One possible attribute would be the effect that the insn has on the machine's
|
5633 |
|
|
condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
|
5634 |
|
|
to track the condition codes.
|
5635 |
|
|
|
5636 |
|
|
@menu
|
5637 |
|
|
* Defining Attributes:: Specifying attributes and their values.
|
5638 |
|
|
* Expressions:: Valid expressions for attribute values.
|
5639 |
|
|
* Tagging Insns:: Assigning attribute values to insns.
|
5640 |
|
|
* Attr Example:: An example of assigning attributes.
|
5641 |
|
|
* Insn Lengths:: Computing the length of insns.
|
5642 |
|
|
* Constant Attributes:: Defining attributes that are constant.
|
5643 |
|
|
* Delay Slots:: Defining delay slots required for a machine.
|
5644 |
|
|
* Processor pipeline description:: Specifying information for insn scheduling.
|
5645 |
|
|
@end menu
|
5646 |
|
|
|
5647 |
|
|
@end ifset
|
5648 |
|
|
@ifset INTERNALS
|
5649 |
|
|
@node Defining Attributes
|
5650 |
|
|
@subsection Defining Attributes and their Values
|
5651 |
|
|
@cindex defining attributes and their values
|
5652 |
|
|
@cindex attributes, defining
|
5653 |
|
|
|
5654 |
|
|
@findex define_attr
|
5655 |
|
|
The @code{define_attr} expression is used to define each attribute required
|
5656 |
|
|
by the target machine. It looks like:
|
5657 |
|
|
|
5658 |
|
|
@smallexample
|
5659 |
|
|
(define_attr @var{name} @var{list-of-values} @var{default})
|
5660 |
|
|
@end smallexample
|
5661 |
|
|
|
5662 |
|
|
@var{name} is a string specifying the name of the attribute being defined.
|
5663 |
|
|
|
5664 |
|
|
@var{list-of-values} is either a string that specifies a comma-separated
|
5665 |
|
|
list of values that can be assigned to the attribute, or a null string to
|
5666 |
|
|
indicate that the attribute takes numeric values.
|
5667 |
|
|
|
5668 |
|
|
@var{default} is an attribute expression that gives the value of this
|
5669 |
|
|
attribute for insns that match patterns whose definition does not include
|
5670 |
|
|
an explicit value for this attribute. @xref{Attr Example}, for more
|
5671 |
|
|
information on the handling of defaults. @xref{Constant Attributes},
|
5672 |
|
|
for information on attributes that do not depend on any particular insn.
|
5673 |
|
|
|
5674 |
|
|
@findex insn-attr.h
|
5675 |
|
|
For each defined attribute, a number of definitions are written to the
|
5676 |
|
|
@file{insn-attr.h} file. For cases where an explicit set of values is
|
5677 |
|
|
specified for an attribute, the following are defined:
|
5678 |
|
|
|
5679 |
|
|
@itemize @bullet
|
5680 |
|
|
@item
|
5681 |
|
|
A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
|
5682 |
|
|
|
5683 |
|
|
@item
|
5684 |
|
|
An enumerated class is defined for @samp{attr_@var{name}} with
|
5685 |
|
|
elements of the form @samp{@var{upper-name}_@var{upper-value}} where
|
5686 |
|
|
the attribute name and value are first converted to uppercase.
|
5687 |
|
|
|
5688 |
|
|
@item
|
5689 |
|
|
A function @samp{get_attr_@var{name}} is defined that is passed an insn and
|
5690 |
|
|
returns the attribute value for that insn.
|
5691 |
|
|
@end itemize
|
5692 |
|
|
|
5693 |
|
|
For example, if the following is present in the @file{md} file:
|
5694 |
|
|
|
5695 |
|
|
@smallexample
|
5696 |
|
|
(define_attr "type" "branch,fp,load,store,arith" @dots{})
|
5697 |
|
|
@end smallexample
|
5698 |
|
|
|
5699 |
|
|
@noindent
|
5700 |
|
|
the following lines will be written to the file @file{insn-attr.h}.
|
5701 |
|
|
|
5702 |
|
|
@smallexample
|
5703 |
|
|
#define HAVE_ATTR_type
|
5704 |
|
|
enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
|
5705 |
|
|
TYPE_STORE, TYPE_ARITH@};
|
5706 |
|
|
extern enum attr_type get_attr_type ();
|
5707 |
|
|
@end smallexample
|
5708 |
|
|
|
5709 |
|
|
If the attribute takes numeric values, no @code{enum} type will be
|
5710 |
|
|
defined and the function to obtain the attribute's value will return
|
5711 |
|
|
@code{int}.
|
5712 |
|
|
|
5713 |
|
|
@end ifset
|
5714 |
|
|
@ifset INTERNALS
|
5715 |
|
|
@node Expressions
|
5716 |
|
|
@subsection Attribute Expressions
|
5717 |
|
|
@cindex attribute expressions
|
5718 |
|
|
|
5719 |
|
|
RTL expressions used to define attributes use the codes described above
|
5720 |
|
|
plus a few specific to attribute definitions, to be discussed below.
|
5721 |
|
|
Attribute value expressions must have one of the following forms:
|
5722 |
|
|
|
5723 |
|
|
@table @code
|
5724 |
|
|
@cindex @code{const_int} and attributes
|
5725 |
|
|
@item (const_int @var{i})
|
5726 |
|
|
The integer @var{i} specifies the value of a numeric attribute. @var{i}
|
5727 |
|
|
must be non-negative.
|
5728 |
|
|
|
5729 |
|
|
The value of a numeric attribute can be specified either with a
|
5730 |
|
|
@code{const_int}, or as an integer represented as a string in
|
5731 |
|
|
@code{const_string}, @code{eq_attr} (see below), @code{attr},
|
5732 |
|
|
@code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
|
5733 |
|
|
overrides on specific instructions (@pxref{Tagging Insns}).
|
5734 |
|
|
|
5735 |
|
|
@cindex @code{const_string} and attributes
|
5736 |
|
|
@item (const_string @var{value})
|
5737 |
|
|
The string @var{value} specifies a constant attribute value.
|
5738 |
|
|
If @var{value} is specified as @samp{"*"}, it means that the default value of
|
5739 |
|
|
the attribute is to be used for the insn containing this expression.
|
5740 |
|
|
@samp{"*"} obviously cannot be used in the @var{default} expression
|
5741 |
|
|
of a @code{define_attr}.
|
5742 |
|
|
|
5743 |
|
|
If the attribute whose value is being specified is numeric, @var{value}
|
5744 |
|
|
must be a string containing a non-negative integer (normally
|
5745 |
|
|
@code{const_int} would be used in this case). Otherwise, it must
|
5746 |
|
|
contain one of the valid values for the attribute.
|
5747 |
|
|
|
5748 |
|
|
@cindex @code{if_then_else} and attributes
|
5749 |
|
|
@item (if_then_else @var{test} @var{true-value} @var{false-value})
|
5750 |
|
|
@var{test} specifies an attribute test, whose format is defined below.
|
5751 |
|
|
The value of this expression is @var{true-value} if @var{test} is true,
|
5752 |
|
|
otherwise it is @var{false-value}.
|
5753 |
|
|
|
5754 |
|
|
@cindex @code{cond} and attributes
|
5755 |
|
|
@item (cond [@var{test1} @var{value1} @dots{}] @var{default})
|
5756 |
|
|
The first operand of this expression is a vector containing an even
|
5757 |
|
|
number of expressions and consisting of pairs of @var{test} and @var{value}
|
5758 |
|
|
expressions. The value of the @code{cond} expression is that of the
|
5759 |
|
|
@var{value} corresponding to the first true @var{test} expression. If
|
5760 |
|
|
none of the @var{test} expressions are true, the value of the @code{cond}
|
5761 |
|
|
expression is that of the @var{default} expression.
|
5762 |
|
|
@end table
|
5763 |
|
|
|
5764 |
|
|
@var{test} expressions can have one of the following forms:
|
5765 |
|
|
|
5766 |
|
|
@table @code
|
5767 |
|
|
@cindex @code{const_int} and attribute tests
|
5768 |
|
|
@item (const_int @var{i})
|
5769 |
|
|
This test is true if @var{i} is nonzero and false otherwise.
|
5770 |
|
|
|
5771 |
|
|
@cindex @code{not} and attributes
|
5772 |
|
|
@cindex @code{ior} and attributes
|
5773 |
|
|
@cindex @code{and} and attributes
|
5774 |
|
|
@item (not @var{test})
|
5775 |
|
|
@itemx (ior @var{test1} @var{test2})
|
5776 |
|
|
@itemx (and @var{test1} @var{test2})
|
5777 |
|
|
These tests are true if the indicated logical function is true.
|
5778 |
|
|
|
5779 |
|
|
@cindex @code{match_operand} and attributes
|
5780 |
|
|
@item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
|
5781 |
|
|
This test is true if operand @var{n} of the insn whose attribute value
|
5782 |
|
|
is being determined has mode @var{m} (this part of the test is ignored
|
5783 |
|
|
if @var{m} is @code{VOIDmode}) and the function specified by the string
|
5784 |
|
|
@var{pred} returns a nonzero value when passed operand @var{n} and mode
|
5785 |
|
|
@var{m} (this part of the test is ignored if @var{pred} is the null
|
5786 |
|
|
string).
|
5787 |
|
|
|
5788 |
|
|
The @var{constraints} operand is ignored and should be the null string.
|
5789 |
|
|
|
5790 |
|
|
@cindex @code{le} and attributes
|
5791 |
|
|
@cindex @code{leu} and attributes
|
5792 |
|
|
@cindex @code{lt} and attributes
|
5793 |
|
|
@cindex @code{gt} and attributes
|
5794 |
|
|
@cindex @code{gtu} and attributes
|
5795 |
|
|
@cindex @code{ge} and attributes
|
5796 |
|
|
@cindex @code{geu} and attributes
|
5797 |
|
|
@cindex @code{ne} and attributes
|
5798 |
|
|
@cindex @code{eq} and attributes
|
5799 |
|
|
@cindex @code{plus} and attributes
|
5800 |
|
|
@cindex @code{minus} and attributes
|
5801 |
|
|
@cindex @code{mult} and attributes
|
5802 |
|
|
@cindex @code{div} and attributes
|
5803 |
|
|
@cindex @code{mod} and attributes
|
5804 |
|
|
@cindex @code{abs} and attributes
|
5805 |
|
|
@cindex @code{neg} and attributes
|
5806 |
|
|
@cindex @code{ashift} and attributes
|
5807 |
|
|
@cindex @code{lshiftrt} and attributes
|
5808 |
|
|
@cindex @code{ashiftrt} and attributes
|
5809 |
|
|
@item (le @var{arith1} @var{arith2})
|
5810 |
|
|
@itemx (leu @var{arith1} @var{arith2})
|
5811 |
|
|
@itemx (lt @var{arith1} @var{arith2})
|
5812 |
|
|
@itemx (ltu @var{arith1} @var{arith2})
|
5813 |
|
|
@itemx (gt @var{arith1} @var{arith2})
|
5814 |
|
|
@itemx (gtu @var{arith1} @var{arith2})
|
5815 |
|
|
@itemx (ge @var{arith1} @var{arith2})
|
5816 |
|
|
@itemx (geu @var{arith1} @var{arith2})
|
5817 |
|
|
@itemx (ne @var{arith1} @var{arith2})
|
5818 |
|
|
@itemx (eq @var{arith1} @var{arith2})
|
5819 |
|
|
These tests are true if the indicated comparison of the two arithmetic
|
5820 |
|
|
expressions is true. Arithmetic expressions are formed with
|
5821 |
|
|
@code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
|
5822 |
|
|
@code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
|
5823 |
|
|
@code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
|
5824 |
|
|
|
5825 |
|
|
@findex get_attr
|
5826 |
|
|
@code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
|
5827 |
|
|
Lengths},for additional forms). @code{symbol_ref} is a string
|
5828 |
|
|
denoting a C expression that yields an @code{int} when evaluated by the
|
5829 |
|
|
@samp{get_attr_@dots{}} routine. It should normally be a global
|
5830 |
|
|
variable.
|
5831 |
|
|
|
5832 |
|
|
@findex eq_attr
|
5833 |
|
|
@item (eq_attr @var{name} @var{value})
|
5834 |
|
|
@var{name} is a string specifying the name of an attribute.
|
5835 |
|
|
|
5836 |
|
|
@var{value} is a string that is either a valid value for attribute
|
5837 |
|
|
@var{name}, a comma-separated list of values, or @samp{!} followed by a
|
5838 |
|
|
value or list. If @var{value} does not begin with a @samp{!}, this
|
5839 |
|
|
test is true if the value of the @var{name} attribute of the current
|
5840 |
|
|
insn is in the list specified by @var{value}. If @var{value} begins
|
5841 |
|
|
with a @samp{!}, this test is true if the attribute's value is
|
5842 |
|
|
@emph{not} in the specified list.
|
5843 |
|
|
|
5844 |
|
|
For example,
|
5845 |
|
|
|
5846 |
|
|
@smallexample
|
5847 |
|
|
(eq_attr "type" "load,store")
|
5848 |
|
|
@end smallexample
|
5849 |
|
|
|
5850 |
|
|
@noindent
|
5851 |
|
|
is equivalent to
|
5852 |
|
|
|
5853 |
|
|
@smallexample
|
5854 |
|
|
(ior (eq_attr "type" "load") (eq_attr "type" "store"))
|
5855 |
|
|
@end smallexample
|
5856 |
|
|
|
5857 |
|
|
If @var{name} specifies an attribute of @samp{alternative}, it refers to the
|
5858 |
|
|
value of the compiler variable @code{which_alternative}
|
5859 |
|
|
(@pxref{Output Statement}) and the values must be small integers. For
|
5860 |
|
|
example,
|
5861 |
|
|
|
5862 |
|
|
@smallexample
|
5863 |
|
|
(eq_attr "alternative" "2,3")
|
5864 |
|
|
@end smallexample
|
5865 |
|
|
|
5866 |
|
|
@noindent
|
5867 |
|
|
is equivalent to
|
5868 |
|
|
|
5869 |
|
|
@smallexample
|
5870 |
|
|
(ior (eq (symbol_ref "which_alternative") (const_int 2))
|
5871 |
|
|
(eq (symbol_ref "which_alternative") (const_int 3)))
|
5872 |
|
|
@end smallexample
|
5873 |
|
|
|
5874 |
|
|
Note that, for most attributes, an @code{eq_attr} test is simplified in cases
|
5875 |
|
|
where the value of the attribute being tested is known for all insns matching
|
5876 |
|
|
a particular pattern. This is by far the most common case.
|
5877 |
|
|
|
5878 |
|
|
@findex attr_flag
|
5879 |
|
|
@item (attr_flag @var{name})
|
5880 |
|
|
The value of an @code{attr_flag} expression is true if the flag
|
5881 |
|
|
specified by @var{name} is true for the @code{insn} currently being
|
5882 |
|
|
scheduled.
|
5883 |
|
|
|
5884 |
|
|
@var{name} is a string specifying one of a fixed set of flags to test.
|
5885 |
|
|
Test the flags @code{forward} and @code{backward} to determine the
|
5886 |
|
|
direction of a conditional branch. Test the flags @code{very_likely},
|
5887 |
|
|
@code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
|
5888 |
|
|
if a conditional branch is expected to be taken.
|
5889 |
|
|
|
5890 |
|
|
If the @code{very_likely} flag is true, then the @code{likely} flag is also
|
5891 |
|
|
true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
|
5892 |
|
|
|
5893 |
|
|
This example describes a conditional branch delay slot which
|
5894 |
|
|
can be nullified for forward branches that are taken (annul-true) or
|
5895 |
|
|
for backward branches which are not taken (annul-false).
|
5896 |
|
|
|
5897 |
|
|
@smallexample
|
5898 |
|
|
(define_delay (eq_attr "type" "cbranch")
|
5899 |
|
|
[(eq_attr "in_branch_delay" "true")
|
5900 |
|
|
(and (eq_attr "in_branch_delay" "true")
|
5901 |
|
|
(attr_flag "forward"))
|
5902 |
|
|
(and (eq_attr "in_branch_delay" "true")
|
5903 |
|
|
(attr_flag "backward"))])
|
5904 |
|
|
@end smallexample
|
5905 |
|
|
|
5906 |
|
|
The @code{forward} and @code{backward} flags are false if the current
|
5907 |
|
|
@code{insn} being scheduled is not a conditional branch.
|
5908 |
|
|
|
5909 |
|
|
The @code{very_likely} and @code{likely} flags are true if the
|
5910 |
|
|
@code{insn} being scheduled is not a conditional branch.
|
5911 |
|
|
The @code{very_unlikely} and @code{unlikely} flags are false if the
|
5912 |
|
|
@code{insn} being scheduled is not a conditional branch.
|
5913 |
|
|
|
5914 |
|
|
@code{attr_flag} is only used during delay slot scheduling and has no
|
5915 |
|
|
meaning to other passes of the compiler.
|
5916 |
|
|
|
5917 |
|
|
@findex attr
|
5918 |
|
|
@item (attr @var{name})
|
5919 |
|
|
The value of another attribute is returned. This is most useful
|
5920 |
|
|
for numeric attributes, as @code{eq_attr} and @code{attr_flag}
|
5921 |
|
|
produce more efficient code for non-numeric attributes.
|
5922 |
|
|
@end table
|
5923 |
|
|
|
5924 |
|
|
@end ifset
|
5925 |
|
|
@ifset INTERNALS
|
5926 |
|
|
@node Tagging Insns
|
5927 |
|
|
@subsection Assigning Attribute Values to Insns
|
5928 |
|
|
@cindex tagging insns
|
5929 |
|
|
@cindex assigning attribute values to insns
|
5930 |
|
|
|
5931 |
|
|
The value assigned to an attribute of an insn is primarily determined by
|
5932 |
|
|
which pattern is matched by that insn (or which @code{define_peephole}
|
5933 |
|
|
generated it). Every @code{define_insn} and @code{define_peephole} can
|
5934 |
|
|
have an optional last argument to specify the values of attributes for
|
5935 |
|
|
matching insns. The value of any attribute not specified in a particular
|
5936 |
|
|
insn is set to the default value for that attribute, as specified in its
|
5937 |
|
|
@code{define_attr}. Extensive use of default values for attributes
|
5938 |
|
|
permits the specification of the values for only one or two attributes
|
5939 |
|
|
in the definition of most insn patterns, as seen in the example in the
|
5940 |
|
|
next section.
|
5941 |
|
|
|
5942 |
|
|
The optional last argument of @code{define_insn} and
|
5943 |
|
|
@code{define_peephole} is a vector of expressions, each of which defines
|
5944 |
|
|
the value for a single attribute. The most general way of assigning an
|
5945 |
|
|
attribute's value is to use a @code{set} expression whose first operand is an
|
5946 |
|
|
@code{attr} expression giving the name of the attribute being set. The
|
5947 |
|
|
second operand of the @code{set} is an attribute expression
|
5948 |
|
|
(@pxref{Expressions}) giving the value of the attribute.
|
5949 |
|
|
|
5950 |
|
|
When the attribute value depends on the @samp{alternative} attribute
|
5951 |
|
|
(i.e., which is the applicable alternative in the constraint of the
|
5952 |
|
|
insn), the @code{set_attr_alternative} expression can be used. It
|
5953 |
|
|
allows the specification of a vector of attribute expressions, one for
|
5954 |
|
|
each alternative.
|
5955 |
|
|
|
5956 |
|
|
@findex set_attr
|
5957 |
|
|
When the generality of arbitrary attribute expressions is not required,
|
5958 |
|
|
the simpler @code{set_attr} expression can be used, which allows
|
5959 |
|
|
specifying a string giving either a single attribute value or a list
|
5960 |
|
|
of attribute values, one for each alternative.
|
5961 |
|
|
|
5962 |
|
|
The form of each of the above specifications is shown below. In each case,
|
5963 |
|
|
@var{name} is a string specifying the attribute to be set.
|
5964 |
|
|
|
5965 |
|
|
@table @code
|
5966 |
|
|
@item (set_attr @var{name} @var{value-string})
|
5967 |
|
|
@var{value-string} is either a string giving the desired attribute value,
|
5968 |
|
|
or a string containing a comma-separated list giving the values for
|
5969 |
|
|
succeeding alternatives. The number of elements must match the number
|
5970 |
|
|
of alternatives in the constraint of the insn pattern.
|
5971 |
|
|
|
5972 |
|
|
Note that it may be useful to specify @samp{*} for some alternative, in
|
5973 |
|
|
which case the attribute will assume its default value for insns matching
|
5974 |
|
|
that alternative.
|
5975 |
|
|
|
5976 |
|
|
@findex set_attr_alternative
|
5977 |
|
|
@item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
|
5978 |
|
|
Depending on the alternative of the insn, the value will be one of the
|
5979 |
|
|
specified values. This is a shorthand for using a @code{cond} with
|
5980 |
|
|
tests on the @samp{alternative} attribute.
|
5981 |
|
|
|
5982 |
|
|
@findex attr
|
5983 |
|
|
@item (set (attr @var{name}) @var{value})
|
5984 |
|
|
The first operand of this @code{set} must be the special RTL expression
|
5985 |
|
|
@code{attr}, whose sole operand is a string giving the name of the
|
5986 |
|
|
attribute being set. @var{value} is the value of the attribute.
|
5987 |
|
|
@end table
|
5988 |
|
|
|
5989 |
|
|
The following shows three different ways of representing the same
|
5990 |
|
|
attribute value specification:
|
5991 |
|
|
|
5992 |
|
|
@smallexample
|
5993 |
|
|
(set_attr "type" "load,store,arith")
|
5994 |
|
|
|
5995 |
|
|
(set_attr_alternative "type"
|
5996 |
|
|
[(const_string "load") (const_string "store")
|
5997 |
|
|
(const_string "arith")])
|
5998 |
|
|
|
5999 |
|
|
(set (attr "type")
|
6000 |
|
|
(cond [(eq_attr "alternative" "1") (const_string "load")
|
6001 |
|
|
(eq_attr "alternative" "2") (const_string "store")]
|
6002 |
|
|
(const_string "arith")))
|
6003 |
|
|
@end smallexample
|
6004 |
|
|
|
6005 |
|
|
@need 1000
|
6006 |
|
|
@findex define_asm_attributes
|
6007 |
|
|
The @code{define_asm_attributes} expression provides a mechanism to
|
6008 |
|
|
specify the attributes assigned to insns produced from an @code{asm}
|
6009 |
|
|
statement. It has the form:
|
6010 |
|
|
|
6011 |
|
|
@smallexample
|
6012 |
|
|
(define_asm_attributes [@var{attr-sets}])
|
6013 |
|
|
@end smallexample
|
6014 |
|
|
|
6015 |
|
|
@noindent
|
6016 |
|
|
where @var{attr-sets} is specified the same as for both the
|
6017 |
|
|
@code{define_insn} and the @code{define_peephole} expressions.
|
6018 |
|
|
|
6019 |
|
|
These values will typically be the ``worst case'' attribute values. For
|
6020 |
|
|
example, they might indicate that the condition code will be clobbered.
|
6021 |
|
|
|
6022 |
|
|
A specification for a @code{length} attribute is handled specially. The
|
6023 |
|
|
way to compute the length of an @code{asm} insn is to multiply the
|
6024 |
|
|
length specified in the expression @code{define_asm_attributes} by the
|
6025 |
|
|
number of machine instructions specified in the @code{asm} statement,
|
6026 |
|
|
determined by counting the number of semicolons and newlines in the
|
6027 |
|
|
string. Therefore, the value of the @code{length} attribute specified
|
6028 |
|
|
in a @code{define_asm_attributes} should be the maximum possible length
|
6029 |
|
|
of a single machine instruction.
|
6030 |
|
|
|
6031 |
|
|
@end ifset
|
6032 |
|
|
@ifset INTERNALS
|
6033 |
|
|
@node Attr Example
|
6034 |
|
|
@subsection Example of Attribute Specifications
|
6035 |
|
|
@cindex attribute specifications example
|
6036 |
|
|
@cindex attribute specifications
|
6037 |
|
|
|
6038 |
|
|
The judicious use of defaulting is important in the efficient use of
|
6039 |
|
|
insn attributes. Typically, insns are divided into @dfn{types} and an
|
6040 |
|
|
attribute, customarily called @code{type}, is used to represent this
|
6041 |
|
|
value. This attribute is normally used only to define the default value
|
6042 |
|
|
for other attributes. An example will clarify this usage.
|
6043 |
|
|
|
6044 |
|
|
Assume we have a RISC machine with a condition code and in which only
|
6045 |
|
|
full-word operations are performed in registers. Let us assume that we
|
6046 |
|
|
can divide all insns into loads, stores, (integer) arithmetic
|
6047 |
|
|
operations, floating point operations, and branches.
|
6048 |
|
|
|
6049 |
|
|
Here we will concern ourselves with determining the effect of an insn on
|
6050 |
|
|
the condition code and will limit ourselves to the following possible
|
6051 |
|
|
effects: The condition code can be set unpredictably (clobbered), not
|
6052 |
|
|
be changed, be set to agree with the results of the operation, or only
|
6053 |
|
|
changed if the item previously set into the condition code has been
|
6054 |
|
|
modified.
|
6055 |
|
|
|
6056 |
|
|
Here is part of a sample @file{md} file for such a machine:
|
6057 |
|
|
|
6058 |
|
|
@smallexample
|
6059 |
|
|
(define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
|
6060 |
|
|
|
6061 |
|
|
(define_attr "cc" "clobber,unchanged,set,change0"
|
6062 |
|
|
(cond [(eq_attr "type" "load")
|
6063 |
|
|
(const_string "change0")
|
6064 |
|
|
(eq_attr "type" "store,branch")
|
6065 |
|
|
(const_string "unchanged")
|
6066 |
|
|
(eq_attr "type" "arith")
|
6067 |
|
|
(if_then_else (match_operand:SI 0 "" "")
|
6068 |
|
|
(const_string "set")
|
6069 |
|
|
(const_string "clobber"))]
|
6070 |
|
|
(const_string "clobber")))
|
6071 |
|
|
|
6072 |
|
|
(define_insn ""
|
6073 |
|
|
[(set (match_operand:SI 0 "general_operand" "=r,r,m")
|
6074 |
|
|
(match_operand:SI 1 "general_operand" "r,m,r"))]
|
6075 |
|
|
""
|
6076 |
|
|
"@@
|
6077 |
|
|
move %0,%1
|
6078 |
|
|
load %0,%1
|
6079 |
|
|
store %0,%1"
|
6080 |
|
|
[(set_attr "type" "arith,load,store")])
|
6081 |
|
|
@end smallexample
|
6082 |
|
|
|
6083 |
|
|
Note that we assume in the above example that arithmetic operations
|
6084 |
|
|
performed on quantities smaller than a machine word clobber the condition
|
6085 |
|
|
code since they will set the condition code to a value corresponding to the
|
6086 |
|
|
full-word result.
|
6087 |
|
|
|
6088 |
|
|
@end ifset
|
6089 |
|
|
@ifset INTERNALS
|
6090 |
|
|
@node Insn Lengths
|
6091 |
|
|
@subsection Computing the Length of an Insn
|
6092 |
|
|
@cindex insn lengths, computing
|
6093 |
|
|
@cindex computing the length of an insn
|
6094 |
|
|
|
6095 |
|
|
For many machines, multiple types of branch instructions are provided, each
|
6096 |
|
|
for different length branch displacements. In most cases, the assembler
|
6097 |
|
|
will choose the correct instruction to use. However, when the assembler
|
6098 |
|
|
cannot do so, GCC can when a special attribute, the @code{length}
|
6099 |
|
|
attribute, is defined. This attribute must be defined to have numeric
|
6100 |
|
|
values by specifying a null string in its @code{define_attr}.
|
6101 |
|
|
|
6102 |
|
|
In the case of the @code{length} attribute, two additional forms of
|
6103 |
|
|
arithmetic terms are allowed in test expressions:
|
6104 |
|
|
|
6105 |
|
|
@table @code
|
6106 |
|
|
@cindex @code{match_dup} and attributes
|
6107 |
|
|
@item (match_dup @var{n})
|
6108 |
|
|
This refers to the address of operand @var{n} of the current insn, which
|
6109 |
|
|
must be a @code{label_ref}.
|
6110 |
|
|
|
6111 |
|
|
@cindex @code{pc} and attributes
|
6112 |
|
|
@item (pc)
|
6113 |
|
|
This refers to the address of the @emph{current} insn. It might have
|
6114 |
|
|
been more consistent with other usage to make this the address of the
|
6115 |
|
|
@emph{next} insn but this would be confusing because the length of the
|
6116 |
|
|
current insn is to be computed.
|
6117 |
|
|
@end table
|
6118 |
|
|
|
6119 |
|
|
@cindex @code{addr_vec}, length of
|
6120 |
|
|
@cindex @code{addr_diff_vec}, length of
|
6121 |
|
|
For normal insns, the length will be determined by value of the
|
6122 |
|
|
@code{length} attribute. In the case of @code{addr_vec} and
|
6123 |
|
|
@code{addr_diff_vec} insn patterns, the length is computed as
|
6124 |
|
|
the number of vectors multiplied by the size of each vector.
|
6125 |
|
|
|
6126 |
|
|
Lengths are measured in addressable storage units (bytes).
|
6127 |
|
|
|
6128 |
|
|
The following macros can be used to refine the length computation:
|
6129 |
|
|
|
6130 |
|
|
@table @code
|
6131 |
|
|
@findex ADJUST_INSN_LENGTH
|
6132 |
|
|
@item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
|
6133 |
|
|
If defined, modifies the length assigned to instruction @var{insn} as a
|
6134 |
|
|
function of the context in which it is used. @var{length} is an lvalue
|
6135 |
|
|
that contains the initially computed length of the insn and should be
|
6136 |
|
|
updated with the correct length of the insn.
|
6137 |
|
|
|
6138 |
|
|
This macro will normally not be required. A case in which it is
|
6139 |
|
|
required is the ROMP@. On this machine, the size of an @code{addr_vec}
|
6140 |
|
|
insn must be increased by two to compensate for the fact that alignment
|
6141 |
|
|
may be required.
|
6142 |
|
|
@end table
|
6143 |
|
|
|
6144 |
|
|
@findex get_attr_length
|
6145 |
|
|
The routine that returns @code{get_attr_length} (the value of the
|
6146 |
|
|
@code{length} attribute) can be used by the output routine to
|
6147 |
|
|
determine the form of the branch instruction to be written, as the
|
6148 |
|
|
example below illustrates.
|
6149 |
|
|
|
6150 |
|
|
As an example of the specification of variable-length branches, consider
|
6151 |
|
|
the IBM 360. If we adopt the convention that a register will be set to
|
6152 |
|
|
the starting address of a function, we can jump to labels within 4k of
|
6153 |
|
|
the start using a four-byte instruction. Otherwise, we need a six-byte
|
6154 |
|
|
sequence to load the address from memory and then branch to it.
|
6155 |
|
|
|
6156 |
|
|
On such a machine, a pattern for a branch instruction might be specified
|
6157 |
|
|
as follows:
|
6158 |
|
|
|
6159 |
|
|
@smallexample
|
6160 |
|
|
(define_insn "jump"
|
6161 |
|
|
[(set (pc)
|
6162 |
|
|
(label_ref (match_operand 0 "" "")))]
|
6163 |
|
|
""
|
6164 |
|
|
@{
|
6165 |
|
|
return (get_attr_length (insn) == 4
|
6166 |
|
|
? "b %l0" : "l r15,=a(%l0); br r15");
|
6167 |
|
|
@}
|
6168 |
|
|
[(set (attr "length")
|
6169 |
|
|
(if_then_else (lt (match_dup 0) (const_int 4096))
|
6170 |
|
|
(const_int 4)
|
6171 |
|
|
(const_int 6)))])
|
6172 |
|
|
@end smallexample
|
6173 |
|
|
|
6174 |
|
|
@end ifset
|
6175 |
|
|
@ifset INTERNALS
|
6176 |
|
|
@node Constant Attributes
|
6177 |
|
|
@subsection Constant Attributes
|
6178 |
|
|
@cindex constant attributes
|
6179 |
|
|
|
6180 |
|
|
A special form of @code{define_attr}, where the expression for the
|
6181 |
|
|
default value is a @code{const} expression, indicates an attribute that
|
6182 |
|
|
is constant for a given run of the compiler. Constant attributes may be
|
6183 |
|
|
used to specify which variety of processor is used. For example,
|
6184 |
|
|
|
6185 |
|
|
@smallexample
|
6186 |
|
|
(define_attr "cpu" "m88100,m88110,m88000"
|
6187 |
|
|
(const
|
6188 |
|
|
(cond [(symbol_ref "TARGET_88100") (const_string "m88100")
|
6189 |
|
|
(symbol_ref "TARGET_88110") (const_string "m88110")]
|
6190 |
|
|
(const_string "m88000"))))
|
6191 |
|
|
|
6192 |
|
|
(define_attr "memory" "fast,slow"
|
6193 |
|
|
(const
|
6194 |
|
|
(if_then_else (symbol_ref "TARGET_FAST_MEM")
|
6195 |
|
|
(const_string "fast")
|
6196 |
|
|
(const_string "slow"))))
|
6197 |
|
|
@end smallexample
|
6198 |
|
|
|
6199 |
|
|
The routine generated for constant attributes has no parameters as it
|
6200 |
|
|
does not depend on any particular insn. RTL expressions used to define
|
6201 |
|
|
the value of a constant attribute may use the @code{symbol_ref} form,
|
6202 |
|
|
but may not use either the @code{match_operand} form or @code{eq_attr}
|
6203 |
|
|
forms involving insn attributes.
|
6204 |
|
|
|
6205 |
|
|
@end ifset
|
6206 |
|
|
@ifset INTERNALS
|
6207 |
|
|
@node Delay Slots
|
6208 |
|
|
@subsection Delay Slot Scheduling
|
6209 |
|
|
@cindex delay slots, defining
|
6210 |
|
|
|
6211 |
|
|
The insn attribute mechanism can be used to specify the requirements for
|
6212 |
|
|
delay slots, if any, on a target machine. An instruction is said to
|
6213 |
|
|
require a @dfn{delay slot} if some instructions that are physically
|
6214 |
|
|
after the instruction are executed as if they were located before it.
|
6215 |
|
|
Classic examples are branch and call instructions, which often execute
|
6216 |
|
|
the following instruction before the branch or call is performed.
|
6217 |
|
|
|
6218 |
|
|
On some machines, conditional branch instructions can optionally
|
6219 |
|
|
@dfn{annul} instructions in the delay slot. This means that the
|
6220 |
|
|
instruction will not be executed for certain branch outcomes. Both
|
6221 |
|
|
instructions that annul if the branch is true and instructions that
|
6222 |
|
|
annul if the branch is false are supported.
|
6223 |
|
|
|
6224 |
|
|
Delay slot scheduling differs from instruction scheduling in that
|
6225 |
|
|
determining whether an instruction needs a delay slot is dependent only
|
6226 |
|
|
on the type of instruction being generated, not on data flow between the
|
6227 |
|
|
instructions. See the next section for a discussion of data-dependent
|
6228 |
|
|
instruction scheduling.
|
6229 |
|
|
|
6230 |
|
|
@findex define_delay
|
6231 |
|
|
The requirement of an insn needing one or more delay slots is indicated
|
6232 |
|
|
via the @code{define_delay} expression. It has the following form:
|
6233 |
|
|
|
6234 |
|
|
@smallexample
|
6235 |
|
|
(define_delay @var{test}
|
6236 |
|
|
[@var{delay-1} @var{annul-true-1} @var{annul-false-1}
|
6237 |
|
|
@var{delay-2} @var{annul-true-2} @var{annul-false-2}
|
6238 |
|
|
@dots{}])
|
6239 |
|
|
@end smallexample
|
6240 |
|
|
|
6241 |
|
|
@var{test} is an attribute test that indicates whether this
|
6242 |
|
|
@code{define_delay} applies to a particular insn. If so, the number of
|
6243 |
|
|
required delay slots is determined by the length of the vector specified
|
6244 |
|
|
as the second argument. An insn placed in delay slot @var{n} must
|
6245 |
|
|
satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
|
6246 |
|
|
attribute test that specifies which insns may be annulled if the branch
|
6247 |
|
|
is true. Similarly, @var{annul-false-n} specifies which insns in the
|
6248 |
|
|
delay slot may be annulled if the branch is false. If annulling is not
|
6249 |
|
|
supported for that delay slot, @code{(nil)} should be coded.
|
6250 |
|
|
|
6251 |
|
|
For example, in the common case where branch and call insns require
|
6252 |
|
|
a single delay slot, which may contain any insn other than a branch or
|
6253 |
|
|
call, the following would be placed in the @file{md} file:
|
6254 |
|
|
|
6255 |
|
|
@smallexample
|
6256 |
|
|
(define_delay (eq_attr "type" "branch,call")
|
6257 |
|
|
[(eq_attr "type" "!branch,call") (nil) (nil)])
|
6258 |
|
|
@end smallexample
|
6259 |
|
|
|
6260 |
|
|
Multiple @code{define_delay} expressions may be specified. In this
|
6261 |
|
|
case, each such expression specifies different delay slot requirements
|
6262 |
|
|
and there must be no insn for which tests in two @code{define_delay}
|
6263 |
|
|
expressions are both true.
|
6264 |
|
|
|
6265 |
|
|
For example, if we have a machine that requires one delay slot for branches
|
6266 |
|
|
but two for calls, no delay slot can contain a branch or call insn,
|
6267 |
|
|
and any valid insn in the delay slot for the branch can be annulled if the
|
6268 |
|
|
branch is true, we might represent this as follows:
|
6269 |
|
|
|
6270 |
|
|
@smallexample
|
6271 |
|
|
(define_delay (eq_attr "type" "branch")
|
6272 |
|
|
[(eq_attr "type" "!branch,call")
|
6273 |
|
|
(eq_attr "type" "!branch,call")
|
6274 |
|
|
(nil)])
|
6275 |
|
|
|
6276 |
|
|
(define_delay (eq_attr "type" "call")
|
6277 |
|
|
[(eq_attr "type" "!branch,call") (nil) (nil)
|
6278 |
|
|
(eq_attr "type" "!branch,call") (nil) (nil)])
|
6279 |
|
|
@end smallexample
|
6280 |
|
|
@c the above is *still* too long. --mew 4feb93
|
6281 |
|
|
|
6282 |
|
|
@end ifset
|
6283 |
|
|
@ifset INTERNALS
|
6284 |
|
|
@node Processor pipeline description
|
6285 |
|
|
@subsection Specifying processor pipeline description
|
6286 |
|
|
@cindex processor pipeline description
|
6287 |
|
|
@cindex processor functional units
|
6288 |
|
|
@cindex instruction latency time
|
6289 |
|
|
@cindex interlock delays
|
6290 |
|
|
@cindex data dependence delays
|
6291 |
|
|
@cindex reservation delays
|
6292 |
|
|
@cindex pipeline hazard recognizer
|
6293 |
|
|
@cindex automaton based pipeline description
|
6294 |
|
|
@cindex regular expressions
|
6295 |
|
|
@cindex deterministic finite state automaton
|
6296 |
|
|
@cindex automaton based scheduler
|
6297 |
|
|
@cindex RISC
|
6298 |
|
|
@cindex VLIW
|
6299 |
|
|
|
6300 |
|
|
To achieve better performance, most modern processors
|
6301 |
|
|
(super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
|
6302 |
|
|
processors) have many @dfn{functional units} on which several
|
6303 |
|
|
instructions can be executed simultaneously. An instruction starts
|
6304 |
|
|
execution if its issue conditions are satisfied. If not, the
|
6305 |
|
|
instruction is stalled until its conditions are satisfied. Such
|
6306 |
|
|
@dfn{interlock (pipeline) delay} causes interruption of the fetching
|
6307 |
|
|
of successor instructions (or demands nop instructions, e.g.@: for some
|
6308 |
|
|
MIPS processors).
|
6309 |
|
|
|
6310 |
|
|
There are two major kinds of interlock delays in modern processors.
|
6311 |
|
|
The first one is a data dependence delay determining @dfn{instruction
|
6312 |
|
|
latency time}. The instruction execution is not started until all
|
6313 |
|
|
source data have been evaluated by prior instructions (there are more
|
6314 |
|
|
complex cases when the instruction execution starts even when the data
|
6315 |
|
|
are not available but will be ready in given time after the
|
6316 |
|
|
instruction execution start). Taking the data dependence delays into
|
6317 |
|
|
account is simple. The data dependence (true, output, and
|
6318 |
|
|
anti-dependence) delay between two instructions is given by a
|
6319 |
|
|
constant. In most cases this approach is adequate. The second kind
|
6320 |
|
|
of interlock delays is a reservation delay. The reservation delay
|
6321 |
|
|
means that two instructions under execution will be in need of shared
|
6322 |
|
|
processors resources, i.e.@: buses, internal registers, and/or
|
6323 |
|
|
functional units, which are reserved for some time. Taking this kind
|
6324 |
|
|
of delay into account is complex especially for modern @acronym{RISC}
|
6325 |
|
|
processors.
|
6326 |
|
|
|
6327 |
|
|
The task of exploiting more processor parallelism is solved by an
|
6328 |
|
|
instruction scheduler. For a better solution to this problem, the
|
6329 |
|
|
instruction scheduler has to have an adequate description of the
|
6330 |
|
|
processor parallelism (or @dfn{pipeline description}). GCC
|
6331 |
|
|
machine descriptions describe processor parallelism and functional
|
6332 |
|
|
unit reservations for groups of instructions with the aid of
|
6333 |
|
|
@dfn{regular expressions}.
|
6334 |
|
|
|
6335 |
|
|
The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
|
6336 |
|
|
figure out the possibility of the instruction issue by the processor
|
6337 |
|
|
on a given simulated processor cycle. The pipeline hazard recognizer is
|
6338 |
|
|
automatically generated from the processor pipeline description. The
|
6339 |
|
|
pipeline hazard recognizer generated from the machine description
|
6340 |
|
|
is based on a deterministic finite state automaton (@acronym{DFA}):
|
6341 |
|
|
the instruction issue is possible if there is a transition from one
|
6342 |
|
|
automaton state to another one. This algorithm is very fast, and
|
6343 |
|
|
furthermore, its speed is not dependent on processor
|
6344 |
|
|
complexity@footnote{However, the size of the automaton depends on
|
6345 |
|
|
processor complexity. To limit this effect, machine descriptions
|
6346 |
|
|
can split orthogonal parts of the machine description among several
|
6347 |
|
|
automata: but then, since each of these must be stepped independently,
|
6348 |
|
|
this does cause a small decrease in the algorithm's performance.}.
|
6349 |
|
|
|
6350 |
|
|
@cindex automaton based pipeline description
|
6351 |
|
|
The rest of this section describes the directives that constitute
|
6352 |
|
|
an automaton-based processor pipeline description. The order of
|
6353 |
|
|
these constructions within the machine description file is not
|
6354 |
|
|
important.
|
6355 |
|
|
|
6356 |
|
|
@findex define_automaton
|
6357 |
|
|
@cindex pipeline hazard recognizer
|
6358 |
|
|
The following optional construction describes names of automata
|
6359 |
|
|
generated and used for the pipeline hazards recognition. Sometimes
|
6360 |
|
|
the generated finite state automaton used by the pipeline hazard
|
6361 |
|
|
recognizer is large. If we use more than one automaton and bind functional
|
6362 |
|
|
units to the automata, the total size of the automata is usually
|
6363 |
|
|
less than the size of the single automaton. If there is no one such
|
6364 |
|
|
construction, only one finite state automaton is generated.
|
6365 |
|
|
|
6366 |
|
|
@smallexample
|
6367 |
|
|
(define_automaton @var{automata-names})
|
6368 |
|
|
@end smallexample
|
6369 |
|
|
|
6370 |
|
|
@var{automata-names} is a string giving names of the automata. The
|
6371 |
|
|
names are separated by commas. All the automata should have unique names.
|
6372 |
|
|
The automaton name is used in the constructions @code{define_cpu_unit} and
|
6373 |
|
|
@code{define_query_cpu_unit}.
|
6374 |
|
|
|
6375 |
|
|
@findex define_cpu_unit
|
6376 |
|
|
@cindex processor functional units
|
6377 |
|
|
Each processor functional unit used in the description of instruction
|
6378 |
|
|
reservations should be described by the following construction.
|
6379 |
|
|
|
6380 |
|
|
@smallexample
|
6381 |
|
|
(define_cpu_unit @var{unit-names} [@var{automaton-name}])
|
6382 |
|
|
@end smallexample
|
6383 |
|
|
|
6384 |
|
|
@var{unit-names} is a string giving the names of the functional units
|
6385 |
|
|
separated by commas. Don't use name @samp{nothing}, it is reserved
|
6386 |
|
|
for other goals.
|
6387 |
|
|
|
6388 |
|
|
@var{automaton-name} is a string giving the name of the automaton with
|
6389 |
|
|
which the unit is bound. The automaton should be described in
|
6390 |
|
|
construction @code{define_automaton}. You should give
|
6391 |
|
|
@dfn{automaton-name}, if there is a defined automaton.
|
6392 |
|
|
|
6393 |
|
|
The assignment of units to automata are constrained by the uses of the
|
6394 |
|
|
units in insn reservations. The most important constraint is: if a
|
6395 |
|
|
unit reservation is present on a particular cycle of an alternative
|
6396 |
|
|
for an insn reservation, then some unit from the same automaton must
|
6397 |
|
|
be present on the same cycle for the other alternatives of the insn
|
6398 |
|
|
reservation. The rest of the constraints are mentioned in the
|
6399 |
|
|
description of the subsequent constructions.
|
6400 |
|
|
|
6401 |
|
|
@findex define_query_cpu_unit
|
6402 |
|
|
@cindex querying function unit reservations
|
6403 |
|
|
The following construction describes CPU functional units analogously
|
6404 |
|
|
to @code{define_cpu_unit}. The reservation of such units can be
|
6405 |
|
|
queried for an automaton state. The instruction scheduler never
|
6406 |
|
|
queries reservation of functional units for given automaton state. So
|
6407 |
|
|
as a rule, you don't need this construction. This construction could
|
6408 |
|
|
be used for future code generation goals (e.g.@: to generate
|
6409 |
|
|
@acronym{VLIW} insn templates).
|
6410 |
|
|
|
6411 |
|
|
@smallexample
|
6412 |
|
|
(define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
|
6413 |
|
|
@end smallexample
|
6414 |
|
|
|
6415 |
|
|
@var{unit-names} is a string giving names of the functional units
|
6416 |
|
|
separated by commas.
|
6417 |
|
|
|
6418 |
|
|
@var{automaton-name} is a string giving the name of the automaton with
|
6419 |
|
|
which the unit is bound.
|
6420 |
|
|
|
6421 |
|
|
@findex define_insn_reservation
|
6422 |
|
|
@cindex instruction latency time
|
6423 |
|
|
@cindex regular expressions
|
6424 |
|
|
@cindex data bypass
|
6425 |
|
|
The following construction is the major one to describe pipeline
|
6426 |
|
|
characteristics of an instruction.
|
6427 |
|
|
|
6428 |
|
|
@smallexample
|
6429 |
|
|
(define_insn_reservation @var{insn-name} @var{default_latency}
|
6430 |
|
|
@var{condition} @var{regexp})
|
6431 |
|
|
@end smallexample
|
6432 |
|
|
|
6433 |
|
|
@var{default_latency} is a number giving latency time of the
|
6434 |
|
|
instruction. There is an important difference between the old
|
6435 |
|
|
description and the automaton based pipeline description. The latency
|
6436 |
|
|
time is used for all dependencies when we use the old description. In
|
6437 |
|
|
the automaton based pipeline description, the given latency time is only
|
6438 |
|
|
used for true dependencies. The cost of anti-dependencies is always
|
6439 |
|
|
zero and the cost of output dependencies is the difference between
|
6440 |
|
|
latency times of the producing and consuming insns (if the difference
|
6441 |
|
|
is negative, the cost is considered to be zero). You can always
|
6442 |
|
|
change the default costs for any description by using the target hook
|
6443 |
|
|
@code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
|
6444 |
|
|
|
6445 |
|
|
@var{insn-name} is a string giving the internal name of the insn. The
|
6446 |
|
|
internal names are used in constructions @code{define_bypass} and in
|
6447 |
|
|
the automaton description file generated for debugging. The internal
|
6448 |
|
|
name has nothing in common with the names in @code{define_insn}. It is a
|
6449 |
|
|
good practice to use insn classes described in the processor manual.
|
6450 |
|
|
|
6451 |
|
|
@var{condition} defines what RTL insns are described by this
|
6452 |
|
|
construction. You should remember that you will be in trouble if
|
6453 |
|
|
@var{condition} for two or more different
|
6454 |
|
|
@code{define_insn_reservation} constructions is TRUE for an insn. In
|
6455 |
|
|
this case what reservation will be used for the insn is not defined.
|
6456 |
|
|
Such cases are not checked during generation of the pipeline hazards
|
6457 |
|
|
recognizer because in general recognizing that two conditions may have
|
6458 |
|
|
the same value is quite difficult (especially if the conditions
|
6459 |
|
|
contain @code{symbol_ref}). It is also not checked during the
|
6460 |
|
|
pipeline hazard recognizer work because it would slow down the
|
6461 |
|
|
recognizer considerably.
|
6462 |
|
|
|
6463 |
|
|
@var{regexp} is a string describing the reservation of the cpu's functional
|
6464 |
|
|
units by the instruction. The reservations are described by a regular
|
6465 |
|
|
expression according to the following syntax:
|
6466 |
|
|
|
6467 |
|
|
@smallexample
|
6468 |
|
|
regexp = regexp "," oneof
|
6469 |
|
|
| oneof
|
6470 |
|
|
|
6471 |
|
|
oneof = oneof "|" allof
|
6472 |
|
|
| allof
|
6473 |
|
|
|
6474 |
|
|
allof = allof "+" repeat
|
6475 |
|
|
| repeat
|
6476 |
|
|
|
6477 |
|
|
repeat = element "*" number
|
6478 |
|
|
| element
|
6479 |
|
|
|
6480 |
|
|
element = cpu_function_unit_name
|
6481 |
|
|
| reservation_name
|
6482 |
|
|
| result_name
|
6483 |
|
|
| "nothing"
|
6484 |
|
|
| "(" regexp ")"
|
6485 |
|
|
@end smallexample
|
6486 |
|
|
|
6487 |
|
|
@itemize @bullet
|
6488 |
|
|
@item
|
6489 |
|
|
@samp{,} is used for describing the start of the next cycle in
|
6490 |
|
|
the reservation.
|
6491 |
|
|
|
6492 |
|
|
@item
|
6493 |
|
|
@samp{|} is used for describing a reservation described by the first
|
6494 |
|
|
regular expression @strong{or} a reservation described by the second
|
6495 |
|
|
regular expression @strong{or} etc.
|
6496 |
|
|
|
6497 |
|
|
@item
|
6498 |
|
|
@samp{+} is used for describing a reservation described by the first
|
6499 |
|
|
regular expression @strong{and} a reservation described by the
|
6500 |
|
|
second regular expression @strong{and} etc.
|
6501 |
|
|
|
6502 |
|
|
@item
|
6503 |
|
|
@samp{*} is used for convenience and simply means a sequence in which
|
6504 |
|
|
the regular expression are repeated @var{number} times with cycle
|
6505 |
|
|
advancing (see @samp{,}).
|
6506 |
|
|
|
6507 |
|
|
@item
|
6508 |
|
|
@samp{cpu_function_unit_name} denotes reservation of the named
|
6509 |
|
|
functional unit.
|
6510 |
|
|
|
6511 |
|
|
@item
|
6512 |
|
|
@samp{reservation_name} --- see description of construction
|
6513 |
|
|
@samp{define_reservation}.
|
6514 |
|
|
|
6515 |
|
|
@item
|
6516 |
|
|
@samp{nothing} denotes no unit reservations.
|
6517 |
|
|
@end itemize
|
6518 |
|
|
|
6519 |
|
|
@findex define_reservation
|
6520 |
|
|
Sometimes unit reservations for different insns contain common parts.
|
6521 |
|
|
In such case, you can simplify the pipeline description by describing
|
6522 |
|
|
the common part by the following construction
|
6523 |
|
|
|
6524 |
|
|
@smallexample
|
6525 |
|
|
(define_reservation @var{reservation-name} @var{regexp})
|
6526 |
|
|
@end smallexample
|
6527 |
|
|
|
6528 |
|
|
@var{reservation-name} is a string giving name of @var{regexp}.
|
6529 |
|
|
Functional unit names and reservation names are in the same name
|
6530 |
|
|
space. So the reservation names should be different from the
|
6531 |
|
|
functional unit names and can not be the reserved name @samp{nothing}.
|
6532 |
|
|
|
6533 |
|
|
@findex define_bypass
|
6534 |
|
|
@cindex instruction latency time
|
6535 |
|
|
@cindex data bypass
|
6536 |
|
|
The following construction is used to describe exceptions in the
|
6537 |
|
|
latency time for given instruction pair. This is so called bypasses.
|
6538 |
|
|
|
6539 |
|
|
@smallexample
|
6540 |
|
|
(define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
|
6541 |
|
|
[@var{guard}])
|
6542 |
|
|
@end smallexample
|
6543 |
|
|
|
6544 |
|
|
@var{number} defines when the result generated by the instructions
|
6545 |
|
|
given in string @var{out_insn_names} will be ready for the
|
6546 |
|
|
instructions given in string @var{in_insn_names}. The instructions in
|
6547 |
|
|
the string are separated by commas.
|
6548 |
|
|
|
6549 |
|
|
@var{guard} is an optional string giving the name of a C function which
|
6550 |
|
|
defines an additional guard for the bypass. The function will get the
|
6551 |
|
|
two insns as parameters. If the function returns zero the bypass will
|
6552 |
|
|
be ignored for this case. The additional guard is necessary to
|
6553 |
|
|
recognize complicated bypasses, e.g.@: when the consumer is only an address
|
6554 |
|
|
of insn @samp{store} (not a stored value).
|
6555 |
|
|
|
6556 |
|
|
@findex exclusion_set
|
6557 |
|
|
@findex presence_set
|
6558 |
|
|
@findex final_presence_set
|
6559 |
|
|
@findex absence_set
|
6560 |
|
|
@findex final_absence_set
|
6561 |
|
|
@cindex VLIW
|
6562 |
|
|
@cindex RISC
|
6563 |
|
|
The following five constructions are usually used to describe
|
6564 |
|
|
@acronym{VLIW} processors, or more precisely, to describe a placement
|
6565 |
|
|
of small instructions into @acronym{VLIW} instruction slots. They
|
6566 |
|
|
can be used for @acronym{RISC} processors, too.
|
6567 |
|
|
|
6568 |
|
|
@smallexample
|
6569 |
|
|
(exclusion_set @var{unit-names} @var{unit-names})
|
6570 |
|
|
(presence_set @var{unit-names} @var{patterns})
|
6571 |
|
|
(final_presence_set @var{unit-names} @var{patterns})
|
6572 |
|
|
(absence_set @var{unit-names} @var{patterns})
|
6573 |
|
|
(final_absence_set @var{unit-names} @var{patterns})
|
6574 |
|
|
@end smallexample
|
6575 |
|
|
|
6576 |
|
|
@var{unit-names} is a string giving names of functional units
|
6577 |
|
|
separated by commas.
|
6578 |
|
|
|
6579 |
|
|
@var{patterns} is a string giving patterns of functional units
|
6580 |
|
|
separated by comma. Currently pattern is one unit or units
|
6581 |
|
|
separated by white-spaces.
|
6582 |
|
|
|
6583 |
|
|
The first construction (@samp{exclusion_set}) means that each
|
6584 |
|
|
functional unit in the first string can not be reserved simultaneously
|
6585 |
|
|
with a unit whose name is in the second string and vice versa. For
|
6586 |
|
|
example, the construction is useful for describing processors
|
6587 |
|
|
(e.g.@: some SPARC processors) with a fully pipelined floating point
|
6588 |
|
|
functional unit which can execute simultaneously only single floating
|
6589 |
|
|
point insns or only double floating point insns.
|
6590 |
|
|
|
6591 |
|
|
The second construction (@samp{presence_set}) means that each
|
6592 |
|
|
functional unit in the first string can not be reserved unless at
|
6593 |
|
|
least one of pattern of units whose names are in the second string is
|
6594 |
|
|
reserved. This is an asymmetric relation. For example, it is useful
|
6595 |
|
|
for description that @acronym{VLIW} @samp{slot1} is reserved after
|
6596 |
|
|
@samp{slot0} reservation. We could describe it by the following
|
6597 |
|
|
construction
|
6598 |
|
|
|
6599 |
|
|
@smallexample
|
6600 |
|
|
(presence_set "slot1" "slot0")
|
6601 |
|
|
@end smallexample
|
6602 |
|
|
|
6603 |
|
|
Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
|
6604 |
|
|
reservation. In this case we could write
|
6605 |
|
|
|
6606 |
|
|
@smallexample
|
6607 |
|
|
(presence_set "slot1" "slot0 b0")
|
6608 |
|
|
@end smallexample
|
6609 |
|
|
|
6610 |
|
|
The third construction (@samp{final_presence_set}) is analogous to
|
6611 |
|
|
@samp{presence_set}. The difference between them is when checking is
|
6612 |
|
|
done. When an instruction is issued in given automaton state
|
6613 |
|
|
reflecting all current and planned unit reservations, the automaton
|
6614 |
|
|
state is changed. The first state is a source state, the second one
|
6615 |
|
|
is a result state. Checking for @samp{presence_set} is done on the
|
6616 |
|
|
source state reservation, checking for @samp{final_presence_set} is
|
6617 |
|
|
done on the result reservation. This construction is useful to
|
6618 |
|
|
describe a reservation which is actually two subsequent reservations.
|
6619 |
|
|
For example, if we use
|
6620 |
|
|
|
6621 |
|
|
@smallexample
|
6622 |
|
|
(presence_set "slot1" "slot0")
|
6623 |
|
|
@end smallexample
|
6624 |
|
|
|
6625 |
|
|
the following insn will be never issued (because @samp{slot1} requires
|
6626 |
|
|
@samp{slot0} which is absent in the source state).
|
6627 |
|
|
|
6628 |
|
|
@smallexample
|
6629 |
|
|
(define_reservation "insn_and_nop" "slot0 + slot1")
|
6630 |
|
|
@end smallexample
|
6631 |
|
|
|
6632 |
|
|
but it can be issued if we use analogous @samp{final_presence_set}.
|
6633 |
|
|
|
6634 |
|
|
The forth construction (@samp{absence_set}) means that each functional
|
6635 |
|
|
unit in the first string can be reserved only if each pattern of units
|
6636 |
|
|
whose names are in the second string is not reserved. This is an
|
6637 |
|
|
asymmetric relation (actually @samp{exclusion_set} is analogous to
|
6638 |
|
|
this one but it is symmetric). For example, it is useful for
|
6639 |
|
|
description that @acronym{VLIW} @samp{slot0} can not be reserved after
|
6640 |
|
|
@samp{slot1} or @samp{slot2} reservation. We could describe it by the
|
6641 |
|
|
following construction
|
6642 |
|
|
|
6643 |
|
|
@smallexample
|
6644 |
|
|
(absence_set "slot2" "slot0, slot1")
|
6645 |
|
|
@end smallexample
|
6646 |
|
|
|
6647 |
|
|
Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
|
6648 |
|
|
are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
|
6649 |
|
|
this case we could write
|
6650 |
|
|
|
6651 |
|
|
@smallexample
|
6652 |
|
|
(absence_set "slot2" "slot0 b0, slot1 b1")
|
6653 |
|
|
@end smallexample
|
6654 |
|
|
|
6655 |
|
|
All functional units mentioned in a set should belong to the same
|
6656 |
|
|
automaton.
|
6657 |
|
|
|
6658 |
|
|
The last construction (@samp{final_absence_set}) is analogous to
|
6659 |
|
|
@samp{absence_set} but checking is done on the result (state)
|
6660 |
|
|
reservation. See comments for @samp{final_presence_set}.
|
6661 |
|
|
|
6662 |
|
|
@findex automata_option
|
6663 |
|
|
@cindex deterministic finite state automaton
|
6664 |
|
|
@cindex nondeterministic finite state automaton
|
6665 |
|
|
@cindex finite state automaton minimization
|
6666 |
|
|
You can control the generator of the pipeline hazard recognizer with
|
6667 |
|
|
the following construction.
|
6668 |
|
|
|
6669 |
|
|
@smallexample
|
6670 |
|
|
(automata_option @var{options})
|
6671 |
|
|
@end smallexample
|
6672 |
|
|
|
6673 |
|
|
@var{options} is a string giving options which affect the generated
|
6674 |
|
|
code. Currently there are the following options:
|
6675 |
|
|
|
6676 |
|
|
@itemize @bullet
|
6677 |
|
|
@item
|
6678 |
|
|
@dfn{no-minimization} makes no minimization of the automaton. This is
|
6679 |
|
|
only worth to do when we are debugging the description and need to
|
6680 |
|
|
look more accurately at reservations of states.
|
6681 |
|
|
|
6682 |
|
|
@item
|
6683 |
|
|
@dfn{time} means printing additional time statistics about
|
6684 |
|
|
generation of automata.
|
6685 |
|
|
|
6686 |
|
|
@item
|
6687 |
|
|
@dfn{v} means a generation of the file describing the result automata.
|
6688 |
|
|
The file has suffix @samp{.dfa} and can be used for the description
|
6689 |
|
|
verification and debugging.
|
6690 |
|
|
|
6691 |
|
|
@item
|
6692 |
|
|
@dfn{w} means a generation of warning instead of error for
|
6693 |
|
|
non-critical errors.
|
6694 |
|
|
|
6695 |
|
|
@item
|
6696 |
|
|
@dfn{ndfa} makes nondeterministic finite state automata. This affects
|
6697 |
|
|
the treatment of operator @samp{|} in the regular expressions. The
|
6698 |
|
|
usual treatment of the operator is to try the first alternative and,
|
6699 |
|
|
if the reservation is not possible, the second alternative. The
|
6700 |
|
|
nondeterministic treatment means trying all alternatives, some of them
|
6701 |
|
|
may be rejected by reservations in the subsequent insns.
|
6702 |
|
|
|
6703 |
|
|
@item
|
6704 |
|
|
@dfn{progress} means output of a progress bar showing how many states
|
6705 |
|
|
were generated so far for automaton being processed. This is useful
|
6706 |
|
|
during debugging a @acronym{DFA} description. If you see too many
|
6707 |
|
|
generated states, you could interrupt the generator of the pipeline
|
6708 |
|
|
hazard recognizer and try to figure out a reason for generation of the
|
6709 |
|
|
huge automaton.
|
6710 |
|
|
@end itemize
|
6711 |
|
|
|
6712 |
|
|
As an example, consider a superscalar @acronym{RISC} machine which can
|
6713 |
|
|
issue three insns (two integer insns and one floating point insn) on
|
6714 |
|
|
the cycle but can finish only two insns. To describe this, we define
|
6715 |
|
|
the following functional units.
|
6716 |
|
|
|
6717 |
|
|
@smallexample
|
6718 |
|
|
(define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
|
6719 |
|
|
(define_cpu_unit "port0, port1")
|
6720 |
|
|
@end smallexample
|
6721 |
|
|
|
6722 |
|
|
All simple integer insns can be executed in any integer pipeline and
|
6723 |
|
|
their result is ready in two cycles. The simple integer insns are
|
6724 |
|
|
issued into the first pipeline unless it is reserved, otherwise they
|
6725 |
|
|
are issued into the second pipeline. Integer division and
|
6726 |
|
|
multiplication insns can be executed only in the second integer
|
6727 |
|
|
pipeline and their results are ready correspondingly in 8 and 4
|
6728 |
|
|
cycles. The integer division is not pipelined, i.e.@: the subsequent
|
6729 |
|
|
integer division insn can not be issued until the current division
|
6730 |
|
|
insn finished. Floating point insns are fully pipelined and their
|
6731 |
|
|
results are ready in 3 cycles. Where the result of a floating point
|
6732 |
|
|
insn is used by an integer insn, an additional delay of one cycle is
|
6733 |
|
|
incurred. To describe all of this we could specify
|
6734 |
|
|
|
6735 |
|
|
@smallexample
|
6736 |
|
|
(define_cpu_unit "div")
|
6737 |
|
|
|
6738 |
|
|
(define_insn_reservation "simple" 2 (eq_attr "type" "int")
|
6739 |
|
|
"(i0_pipeline | i1_pipeline), (port0 | port1)")
|
6740 |
|
|
|
6741 |
|
|
(define_insn_reservation "mult" 4 (eq_attr "type" "mult")
|
6742 |
|
|
"i1_pipeline, nothing*2, (port0 | port1)")
|
6743 |
|
|
|
6744 |
|
|
(define_insn_reservation "div" 8 (eq_attr "type" "div")
|
6745 |
|
|
"i1_pipeline, div*7, div + (port0 | port1)")
|
6746 |
|
|
|
6747 |
|
|
(define_insn_reservation "float" 3 (eq_attr "type" "float")
|
6748 |
|
|
"f_pipeline, nothing, (port0 | port1))
|
6749 |
|
|
|
6750 |
|
|
(define_bypass 4 "float" "simple,mult,div")
|
6751 |
|
|
@end smallexample
|
6752 |
|
|
|
6753 |
|
|
To simplify the description we could describe the following reservation
|
6754 |
|
|
|
6755 |
|
|
@smallexample
|
6756 |
|
|
(define_reservation "finish" "port0|port1")
|
6757 |
|
|
@end smallexample
|
6758 |
|
|
|
6759 |
|
|
and use it in all @code{define_insn_reservation} as in the following
|
6760 |
|
|
construction
|
6761 |
|
|
|
6762 |
|
|
@smallexample
|
6763 |
|
|
(define_insn_reservation "simple" 2 (eq_attr "type" "int")
|
6764 |
|
|
"(i0_pipeline | i1_pipeline), finish")
|
6765 |
|
|
@end smallexample
|
6766 |
|
|
|
6767 |
|
|
|
6768 |
|
|
@end ifset
|
6769 |
|
|
@ifset INTERNALS
|
6770 |
|
|
@node Conditional Execution
|
6771 |
|
|
@section Conditional Execution
|
6772 |
|
|
@cindex conditional execution
|
6773 |
|
|
@cindex predication
|
6774 |
|
|
|
6775 |
|
|
A number of architectures provide for some form of conditional
|
6776 |
|
|
execution, or predication. The hallmark of this feature is the
|
6777 |
|
|
ability to nullify most of the instructions in the instruction set.
|
6778 |
|
|
When the instruction set is large and not entirely symmetric, it
|
6779 |
|
|
can be quite tedious to describe these forms directly in the
|
6780 |
|
|
@file{.md} file. An alternative is the @code{define_cond_exec} template.
|
6781 |
|
|
|
6782 |
|
|
@findex define_cond_exec
|
6783 |
|
|
@smallexample
|
6784 |
|
|
(define_cond_exec
|
6785 |
|
|
[@var{predicate-pattern}]
|
6786 |
|
|
"@var{condition}"
|
6787 |
|
|
"@var{output-template}")
|
6788 |
|
|
@end smallexample
|
6789 |
|
|
|
6790 |
|
|
@var{predicate-pattern} is the condition that must be true for the
|
6791 |
|
|
insn to be executed at runtime and should match a relational operator.
|
6792 |
|
|
One can use @code{match_operator} to match several relational operators
|
6793 |
|
|
at once. Any @code{match_operand} operands must have no more than one
|
6794 |
|
|
alternative.
|
6795 |
|
|
|
6796 |
|
|
@var{condition} is a C expression that must be true for the generated
|
6797 |
|
|
pattern to match.
|
6798 |
|
|
|
6799 |
|
|
@findex current_insn_predicate
|
6800 |
|
|
@var{output-template} is a string similar to the @code{define_insn}
|
6801 |
|
|
output template (@pxref{Output Template}), except that the @samp{*}
|
6802 |
|
|
and @samp{@@} special cases do not apply. This is only useful if the
|
6803 |
|
|
assembly text for the predicate is a simple prefix to the main insn.
|
6804 |
|
|
In order to handle the general case, there is a global variable
|
6805 |
|
|
@code{current_insn_predicate} that will contain the entire predicate
|
6806 |
|
|
if the current insn is predicated, and will otherwise be @code{NULL}.
|
6807 |
|
|
|
6808 |
|
|
When @code{define_cond_exec} is used, an implicit reference to
|
6809 |
|
|
the @code{predicable} instruction attribute is made.
|
6810 |
|
|
@xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
|
6811 |
|
|
exactly two elements in its @var{list-of-values}). Further, it must
|
6812 |
|
|
not be used with complex expressions. That is, the default and all
|
6813 |
|
|
uses in the insns must be a simple constant, not dependent on the
|
6814 |
|
|
alternative or anything else.
|
6815 |
|
|
|
6816 |
|
|
For each @code{define_insn} for which the @code{predicable}
|
6817 |
|
|
attribute is true, a new @code{define_insn} pattern will be
|
6818 |
|
|
generated that matches a predicated version of the instruction.
|
6819 |
|
|
For example,
|
6820 |
|
|
|
6821 |
|
|
@smallexample
|
6822 |
|
|
(define_insn "addsi"
|
6823 |
|
|
[(set (match_operand:SI 0 "register_operand" "r")
|
6824 |
|
|
(plus:SI (match_operand:SI 1 "register_operand" "r")
|
6825 |
|
|
(match_operand:SI 2 "register_operand" "r")))]
|
6826 |
|
|
"@var{test1}"
|
6827 |
|
|
"add %2,%1,%0")
|
6828 |
|
|
|
6829 |
|
|
(define_cond_exec
|
6830 |
|
|
[(ne (match_operand:CC 0 "register_operand" "c")
|
6831 |
|
|
(const_int 0))]
|
6832 |
|
|
"@var{test2}"
|
6833 |
|
|
"(%0)")
|
6834 |
|
|
@end smallexample
|
6835 |
|
|
|
6836 |
|
|
@noindent
|
6837 |
|
|
generates a new pattern
|
6838 |
|
|
|
6839 |
|
|
@smallexample
|
6840 |
|
|
(define_insn ""
|
6841 |
|
|
[(cond_exec
|
6842 |
|
|
(ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
|
6843 |
|
|
(set (match_operand:SI 0 "register_operand" "r")
|
6844 |
|
|
(plus:SI (match_operand:SI 1 "register_operand" "r")
|
6845 |
|
|
(match_operand:SI 2 "register_operand" "r"))))]
|
6846 |
|
|
"(@var{test2}) && (@var{test1})"
|
6847 |
|
|
"(%3) add %2,%1,%0")
|
6848 |
|
|
@end smallexample
|
6849 |
|
|
|
6850 |
|
|
@end ifset
|
6851 |
|
|
@ifset INTERNALS
|
6852 |
|
|
@node Constant Definitions
|
6853 |
|
|
@section Constant Definitions
|
6854 |
|
|
@cindex constant definitions
|
6855 |
|
|
@findex define_constants
|
6856 |
|
|
|
6857 |
|
|
Using literal constants inside instruction patterns reduces legibility and
|
6858 |
|
|
can be a maintenance problem.
|
6859 |
|
|
|
6860 |
|
|
To overcome this problem, you may use the @code{define_constants}
|
6861 |
|
|
expression. It contains a vector of name-value pairs. From that
|
6862 |
|
|
point on, wherever any of the names appears in the MD file, it is as
|
6863 |
|
|
if the corresponding value had been written instead. You may use
|
6864 |
|
|
@code{define_constants} multiple times; each appearance adds more
|
6865 |
|
|
constants to the table. It is an error to redefine a constant with
|
6866 |
|
|
a different value.
|
6867 |
|
|
|
6868 |
|
|
To come back to the a29k load multiple example, instead of
|
6869 |
|
|
|
6870 |
|
|
@smallexample
|
6871 |
|
|
(define_insn ""
|
6872 |
|
|
[(match_parallel 0 "load_multiple_operation"
|
6873 |
|
|
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
|
6874 |
|
|
(match_operand:SI 2 "memory_operand" "m"))
|
6875 |
|
|
(use (reg:SI 179))
|
6876 |
|
|
(clobber (reg:SI 179))])]
|
6877 |
|
|
""
|
6878 |
|
|
"loadm 0,0,%1,%2")
|
6879 |
|
|
@end smallexample
|
6880 |
|
|
|
6881 |
|
|
You could write:
|
6882 |
|
|
|
6883 |
|
|
@smallexample
|
6884 |
|
|
(define_constants [
|
6885 |
|
|
(R_BP 177)
|
6886 |
|
|
(R_FC 178)
|
6887 |
|
|
(R_CR 179)
|
6888 |
|
|
(R_Q 180)
|
6889 |
|
|
])
|
6890 |
|
|
|
6891 |
|
|
(define_insn ""
|
6892 |
|
|
[(match_parallel 0 "load_multiple_operation"
|
6893 |
|
|
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
|
6894 |
|
|
(match_operand:SI 2 "memory_operand" "m"))
|
6895 |
|
|
(use (reg:SI R_CR))
|
6896 |
|
|
(clobber (reg:SI R_CR))])]
|
6897 |
|
|
""
|
6898 |
|
|
"loadm 0,0,%1,%2")
|
6899 |
|
|
@end smallexample
|
6900 |
|
|
|
6901 |
|
|
The constants that are defined with a define_constant are also output
|
6902 |
|
|
in the insn-codes.h header file as #defines.
|
6903 |
|
|
@end ifset
|
6904 |
|
|
@ifset INTERNALS
|
6905 |
|
|
@node Macros
|
6906 |
|
|
@section Macros
|
6907 |
|
|
@cindex macros in @file{.md} files
|
6908 |
|
|
|
6909 |
|
|
Ports often need to define similar patterns for more than one machine
|
6910 |
|
|
mode or for more than one rtx code. GCC provides some simple macro
|
6911 |
|
|
facilities to make this process easier.
|
6912 |
|
|
|
6913 |
|
|
@menu
|
6914 |
|
|
* Mode Macros:: Generating variations of patterns for different modes.
|
6915 |
|
|
* Code Macros:: Doing the same for codes.
|
6916 |
|
|
@end menu
|
6917 |
|
|
|
6918 |
|
|
@node Mode Macros
|
6919 |
|
|
@subsection Mode Macros
|
6920 |
|
|
@cindex mode macros in @file{.md} files
|
6921 |
|
|
|
6922 |
|
|
Ports often need to define similar patterns for two or more different modes.
|
6923 |
|
|
For example:
|
6924 |
|
|
|
6925 |
|
|
@itemize @bullet
|
6926 |
|
|
@item
|
6927 |
|
|
If a processor has hardware support for both single and double
|
6928 |
|
|
floating-point arithmetic, the @code{SFmode} patterns tend to be
|
6929 |
|
|
very similar to the @code{DFmode} ones.
|
6930 |
|
|
|
6931 |
|
|
@item
|
6932 |
|
|
If a port uses @code{SImode} pointers in one configuration and
|
6933 |
|
|
@code{DImode} pointers in another, it will usually have very similar
|
6934 |
|
|
@code{SImode} and @code{DImode} patterns for manipulating pointers.
|
6935 |
|
|
@end itemize
|
6936 |
|
|
|
6937 |
|
|
Mode macros allow several patterns to be instantiated from one
|
6938 |
|
|
@file{.md} file template. They can be used with any type of
|
6939 |
|
|
rtx-based construct, such as a @code{define_insn},
|
6940 |
|
|
@code{define_split}, or @code{define_peephole2}.
|
6941 |
|
|
|
6942 |
|
|
@menu
|
6943 |
|
|
* Defining Mode Macros:: Defining a new mode macro.
|
6944 |
|
|
* Substitutions:: Combining mode macros with substitutions
|
6945 |
|
|
* Examples:: Examples
|
6946 |
|
|
@end menu
|
6947 |
|
|
|
6948 |
|
|
@node Defining Mode Macros
|
6949 |
|
|
@subsubsection Defining Mode Macros
|
6950 |
|
|
@findex define_mode_macro
|
6951 |
|
|
|
6952 |
|
|
The syntax for defining a mode macro is:
|
6953 |
|
|
|
6954 |
|
|
@smallexample
|
6955 |
|
|
(define_mode_macro @var{name} [(@var{mode1} "@var{cond1}") ... (@var{moden} "@var{condn}")])
|
6956 |
|
|
@end smallexample
|
6957 |
|
|
|
6958 |
|
|
This allows subsequent @file{.md} file constructs to use the mode suffix
|
6959 |
|
|
@code{:@var{name}}. Every construct that does so will be expanded
|
6960 |
|
|
@var{n} times, once with every use of @code{:@var{name}} replaced by
|
6961 |
|
|
@code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
|
6962 |
|
|
and so on. In the expansion for a particular @var{modei}, every
|
6963 |
|
|
C condition will also require that @var{condi} be true.
|
6964 |
|
|
|
6965 |
|
|
For example:
|
6966 |
|
|
|
6967 |
|
|
@smallexample
|
6968 |
|
|
(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
|
6969 |
|
|
@end smallexample
|
6970 |
|
|
|
6971 |
|
|
defines a new mode suffix @code{:P}. Every construct that uses
|
6972 |
|
|
@code{:P} will be expanded twice, once with every @code{:P} replaced
|
6973 |
|
|
by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
|
6974 |
|
|
The @code{:SI} version will only apply if @code{Pmode == SImode} and
|
6975 |
|
|
the @code{:DI} version will only apply if @code{Pmode == DImode}.
|
6976 |
|
|
|
6977 |
|
|
As with other @file{.md} conditions, an empty string is treated
|
6978 |
|
|
as ``always true''. @code{(@var{mode} "")} can also be abbreviated
|
6979 |
|
|
to @code{@var{mode}}. For example:
|
6980 |
|
|
|
6981 |
|
|
@smallexample
|
6982 |
|
|
(define_mode_macro GPR [SI (DI "TARGET_64BIT")])
|
6983 |
|
|
@end smallexample
|
6984 |
|
|
|
6985 |
|
|
means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
|
6986 |
|
|
but that the @code{:SI} expansion has no such constraint.
|
6987 |
|
|
|
6988 |
|
|
Macros are applied in the order they are defined. This can be
|
6989 |
|
|
significant if two macros are used in a construct that requires
|
6990 |
|
|
substitutions. @xref{Substitutions}.
|
6991 |
|
|
|
6992 |
|
|
@node Substitutions
|
6993 |
|
|
@subsubsection Substitution in Mode Macros
|
6994 |
|
|
@findex define_mode_attr
|
6995 |
|
|
|
6996 |
|
|
If an @file{.md} file construct uses mode macros, each version of the
|
6997 |
|
|
construct will often need slightly different strings or modes. For
|
6998 |
|
|
example:
|
6999 |
|
|
|
7000 |
|
|
@itemize @bullet
|
7001 |
|
|
@item
|
7002 |
|
|
When a @code{define_expand} defines several @code{add@var{m}3} patterns
|
7003 |
|
|
(@pxref{Standard Names}), each expander will need to use the
|
7004 |
|
|
appropriate mode name for @var{m}.
|
7005 |
|
|
|
7006 |
|
|
@item
|
7007 |
|
|
When a @code{define_insn} defines several instruction patterns,
|
7008 |
|
|
each instruction will often use a different assembler mnemonic.
|
7009 |
|
|
|
7010 |
|
|
@item
|
7011 |
|
|
When a @code{define_insn} requires operands with different modes,
|
7012 |
|
|
using a macro for one of the operand modes usually requires a specific
|
7013 |
|
|
mode for the other operand(s).
|
7014 |
|
|
@end itemize
|
7015 |
|
|
|
7016 |
|
|
GCC supports such variations through a system of ``mode attributes''.
|
7017 |
|
|
There are two standard attributes: @code{mode}, which is the name of
|
7018 |
|
|
the mode in lower case, and @code{MODE}, which is the same thing in
|
7019 |
|
|
upper case. You can define other attributes using:
|
7020 |
|
|
|
7021 |
|
|
@smallexample
|
7022 |
|
|
(define_mode_attr @var{name} [(@var{mode1} "@var{value1}") ... (@var{moden} "@var{valuen}")])
|
7023 |
|
|
@end smallexample
|
7024 |
|
|
|
7025 |
|
|
where @var{name} is the name of the attribute and @var{valuei}
|
7026 |
|
|
is the value associated with @var{modei}.
|
7027 |
|
|
|
7028 |
|
|
When GCC replaces some @var{:macro} with @var{:mode}, it will scan
|
7029 |
|
|
each string and mode in the pattern for sequences of the form
|
7030 |
|
|
@code{<@var{macro}:@var{attr}>}, where @var{attr} is the name of a
|
7031 |
|
|
mode attribute. If the attribute is defined for @var{mode}, the whole
|
7032 |
|
|
@code{<...>} sequence will be replaced by the appropriate attribute
|
7033 |
|
|
value.
|
7034 |
|
|
|
7035 |
|
|
For example, suppose an @file{.md} file has:
|
7036 |
|
|
|
7037 |
|
|
@smallexample
|
7038 |
|
|
(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
|
7039 |
|
|
(define_mode_attr load [(SI "lw") (DI "ld")])
|
7040 |
|
|
@end smallexample
|
7041 |
|
|
|
7042 |
|
|
If one of the patterns that uses @code{:P} contains the string
|
7043 |
|
|
@code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
|
7044 |
|
|
will use @code{"lw\t%0,%1"} and the @code{DI} version will use
|
7045 |
|
|
@code{"ld\t%0,%1"}.
|
7046 |
|
|
|
7047 |
|
|
Here is an example of using an attribute for a mode:
|
7048 |
|
|
|
7049 |
|
|
@smallexample
|
7050 |
|
|
(define_mode_macro LONG [SI DI])
|
7051 |
|
|
(define_mode_attr SHORT [(SI "HI") (DI "SI")])
|
7052 |
|
|
(define_insn ...
|
7053 |
|
|
(sign_extend:LONG (match_operand:<LONG:SHORT> ...)) ...)
|
7054 |
|
|
@end smallexample
|
7055 |
|
|
|
7056 |
|
|
The @code{@var{macro}:} prefix may be omitted, in which case the
|
7057 |
|
|
substitution will be attempted for every macro expansion.
|
7058 |
|
|
|
7059 |
|
|
@node Examples
|
7060 |
|
|
@subsubsection Mode Macro Examples
|
7061 |
|
|
|
7062 |
|
|
Here is an example from the MIPS port. It defines the following
|
7063 |
|
|
modes and attributes (among others):
|
7064 |
|
|
|
7065 |
|
|
@smallexample
|
7066 |
|
|
(define_mode_macro GPR [SI (DI "TARGET_64BIT")])
|
7067 |
|
|
(define_mode_attr d [(SI "") (DI "d")])
|
7068 |
|
|
@end smallexample
|
7069 |
|
|
|
7070 |
|
|
and uses the following template to define both @code{subsi3}
|
7071 |
|
|
and @code{subdi3}:
|
7072 |
|
|
|
7073 |
|
|
@smallexample
|
7074 |
|
|
(define_insn "sub<mode>3"
|
7075 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
7076 |
|
|
(minus:GPR (match_operand:GPR 1 "register_operand" "d")
|
7077 |
|
|
(match_operand:GPR 2 "register_operand" "d")))]
|
7078 |
|
|
""
|
7079 |
|
|
"<d>subu\t%0,%1,%2"
|
7080 |
|
|
[(set_attr "type" "arith")
|
7081 |
|
|
(set_attr "mode" "<MODE>")])
|
7082 |
|
|
@end smallexample
|
7083 |
|
|
|
7084 |
|
|
This is exactly equivalent to:
|
7085 |
|
|
|
7086 |
|
|
@smallexample
|
7087 |
|
|
(define_insn "subsi3"
|
7088 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
7089 |
|
|
(minus:SI (match_operand:SI 1 "register_operand" "d")
|
7090 |
|
|
(match_operand:SI 2 "register_operand" "d")))]
|
7091 |
|
|
""
|
7092 |
|
|
"subu\t%0,%1,%2"
|
7093 |
|
|
[(set_attr "type" "arith")
|
7094 |
|
|
(set_attr "mode" "SI")])
|
7095 |
|
|
|
7096 |
|
|
(define_insn "subdi3"
|
7097 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
7098 |
|
|
(minus:DI (match_operand:DI 1 "register_operand" "d")
|
7099 |
|
|
(match_operand:DI 2 "register_operand" "d")))]
|
7100 |
|
|
""
|
7101 |
|
|
"dsubu\t%0,%1,%2"
|
7102 |
|
|
[(set_attr "type" "arith")
|
7103 |
|
|
(set_attr "mode" "DI")])
|
7104 |
|
|
@end smallexample
|
7105 |
|
|
|
7106 |
|
|
@node Code Macros
|
7107 |
|
|
@subsection Code Macros
|
7108 |
|
|
@cindex code macros in @file{.md} files
|
7109 |
|
|
@findex define_code_macro
|
7110 |
|
|
@findex define_code_attr
|
7111 |
|
|
|
7112 |
|
|
Code macros operate in a similar way to mode macros. @xref{Mode Macros}.
|
7113 |
|
|
|
7114 |
|
|
The construct:
|
7115 |
|
|
|
7116 |
|
|
@smallexample
|
7117 |
|
|
(define_code_macro @var{name} [(@var{code1} "@var{cond1}") ... (@var{coden} "@var{condn}")])
|
7118 |
|
|
@end smallexample
|
7119 |
|
|
|
7120 |
|
|
defines a pseudo rtx code @var{name} that can be instantiated as
|
7121 |
|
|
@var{codei} if condition @var{condi} is true. Each @var{codei}
|
7122 |
|
|
must have the same rtx format. @xref{RTL Classes}.
|
7123 |
|
|
|
7124 |
|
|
As with mode macros, each pattern that uses @var{name} will be
|
7125 |
|
|
expanded @var{n} times, once with all uses of @var{name} replaced by
|
7126 |
|
|
@var{code1}, once with all uses replaced by @var{code2}, and so on.
|
7127 |
|
|
@xref{Defining Mode Macros}.
|
7128 |
|
|
|
7129 |
|
|
It is possible to define attributes for codes as well as for modes.
|
7130 |
|
|
There are two standard code attributes: @code{code}, the name of the
|
7131 |
|
|
code in lower case, and @code{CODE}, the name of the code in upper case.
|
7132 |
|
|
Other attributes are defined using:
|
7133 |
|
|
|
7134 |
|
|
@smallexample
|
7135 |
|
|
(define_code_attr @var{name} [(@var{code1} "@var{value1}") ... (@var{coden} "@var{valuen}")])
|
7136 |
|
|
@end smallexample
|
7137 |
|
|
|
7138 |
|
|
Here's an example of code macros in action, taken from the MIPS port:
|
7139 |
|
|
|
7140 |
|
|
@smallexample
|
7141 |
|
|
(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
|
7142 |
|
|
eq ne gt ge lt le gtu geu ltu leu])
|
7143 |
|
|
|
7144 |
|
|
(define_expand "b<code>"
|
7145 |
|
|
[(set (pc)
|
7146 |
|
|
(if_then_else (any_cond:CC (cc0)
|
7147 |
|
|
(const_int 0))
|
7148 |
|
|
(label_ref (match_operand 0 ""))
|
7149 |
|
|
(pc)))]
|
7150 |
|
|
""
|
7151 |
|
|
@{
|
7152 |
|
|
gen_conditional_branch (operands, <CODE>);
|
7153 |
|
|
DONE;
|
7154 |
|
|
@})
|
7155 |
|
|
@end smallexample
|
7156 |
|
|
|
7157 |
|
|
This is equivalent to:
|
7158 |
|
|
|
7159 |
|
|
@smallexample
|
7160 |
|
|
(define_expand "bunordered"
|
7161 |
|
|
[(set (pc)
|
7162 |
|
|
(if_then_else (unordered:CC (cc0)
|
7163 |
|
|
(const_int 0))
|
7164 |
|
|
(label_ref (match_operand 0 ""))
|
7165 |
|
|
(pc)))]
|
7166 |
|
|
""
|
7167 |
|
|
@{
|
7168 |
|
|
gen_conditional_branch (operands, UNORDERED);
|
7169 |
|
|
DONE;
|
7170 |
|
|
@})
|
7171 |
|
|
|
7172 |
|
|
(define_expand "bordered"
|
7173 |
|
|
[(set (pc)
|
7174 |
|
|
(if_then_else (ordered:CC (cc0)
|
7175 |
|
|
(const_int 0))
|
7176 |
|
|
(label_ref (match_operand 0 ""))
|
7177 |
|
|
(pc)))]
|
7178 |
|
|
""
|
7179 |
|
|
@{
|
7180 |
|
|
gen_conditional_branch (operands, ORDERED);
|
7181 |
|
|
DONE;
|
7182 |
|
|
@})
|
7183 |
|
|
|
7184 |
|
|
...
|
7185 |
|
|
@end smallexample
|
7186 |
|
|
|
7187 |
|
|
@end ifset
|