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/* Instruction scheduling pass.

   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998,

   1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.

   Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,

   and currently maintained by, Jim Wilson (wilson@cygnus.com)

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it under

the terms of the GNU General Public License as published by the Free

Software Foundation; either version 2, or (at your option) any later

version.

GCC is distributed in the hope that it will be useful, but WITHOUT ANY

WARRANTY; without even the implied warranty of MERCHANTABILITY or

FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

for more details.

You should have received a copy of the GNU General Public License

along with GCC; see the file COPYING.  If not, write to the Free

Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA

02110-1301, USA.  */

/* Instruction scheduling pass.  This file, along with sched-deps.c,

   contains the generic parts.  The actual entry point is found for

   the normal instruction scheduling pass is found in sched-rgn.c.

   We compute insn priorities based on data dependencies.  Flow

   analysis only creates a fraction of the data-dependencies we must

   observe: namely, only those dependencies which the combiner can be

   expected to use.  For this pass, we must therefore create the

   remaining dependencies we need to observe: register dependencies,

   memory dependencies, dependencies to keep function calls in order,

   and the dependence between a conditional branch and the setting of

   condition codes are all dealt with here.

   The scheduler first traverses the data flow graph, starting with

   the last instruction, and proceeding to the first, assigning values

   to insn_priority as it goes.  This sorts the instructions

   topologically by data dependence.

   Once priorities have been established, we order the insns using

   list scheduling.  This works as follows: starting with a list of

   all the ready insns, and sorted according to priority number, we

   schedule the insn from the end of the list by placing its

   predecessors in the list according to their priority order.  We

   consider this insn scheduled by setting the pointer to the "end" of

   the list to point to the previous insn.  When an insn has no

   predecessors, we either queue it until sufficient time has elapsed

   or add it to the ready list.  As the instructions are scheduled or

   when stalls are introduced, the queue advances and dumps insns into

   the ready list.  When all insns down to the lowest priority have

   been scheduled, the critical path of the basic block has been made

   as short as possible.  The remaining insns are then scheduled in

   remaining slots.

   The following list shows the order in which we want to break ties

   among insns in the ready list:

   1.  choose insn with the longest path to end of bb, ties

   broken by

   2.  choose insn with least contribution to register pressure,

   ties broken by

   3.  prefer in-block upon interblock motion, ties broken by

   4.  prefer useful upon speculative motion, ties broken by

   5.  choose insn with largest control flow probability, ties

   broken by

   6.  choose insn with the least dependences upon the previously

   scheduled insn, or finally

   7   choose the insn which has the most insns dependent on it.

   8.  choose insn with lowest UID.

   Memory references complicate matters.  Only if we can be certain

   that memory references are not part of the data dependency graph

   (via true, anti, or output dependence), can we move operations past

   memory references.  To first approximation, reads can be done

   independently, while writes introduce dependencies.  Better

   approximations will yield fewer dependencies.

   Before reload, an extended analysis of interblock data dependences

   is required for interblock scheduling.  This is performed in

   compute_block_backward_dependences ().

   Dependencies set up by memory references are treated in exactly the

   same way as other dependencies, by using LOG_LINKS backward

   dependences.  LOG_LINKS are translated into INSN_DEPEND forward

   dependences for the purpose of forward list scheduling.

   Having optimized the critical path, we may have also unduly

   extended the lifetimes of some registers.  If an operation requires

   that constants be loaded into registers, it is certainly desirable

   to load those constants as early as necessary, but no earlier.

   I.e., it will not do to load up a bunch of registers at the

   beginning of a basic block only to use them at the end, if they

   could be loaded later, since this may result in excessive register

   utilization.

   Note that since branches are never in basic blocks, but only end

   basic blocks, this pass will not move branches.  But that is ok,

   since we can use GNU's delayed branch scheduling pass to take care

   of this case.

   Also note that no further optimizations based on algebraic

   identities are performed, so this pass would be a good one to

   perform instruction splitting, such as breaking up a multiply

   instruction into shifts and adds where that is profitable.

   Given the memory aliasing analysis that this pass should perform,

   it should be possible to remove redundant stores to memory, and to

   load values from registers instead of hitting memory.

   Before reload, speculative insns are moved only if a 'proof' exists

   that no exception will be caused by this, and if no live registers

   exist that inhibit the motion (live registers constraints are not

   represented by data dependence edges).

   This pass must update information that subsequent passes expect to

   be correct.  Namely: reg_n_refs, reg_n_sets, reg_n_deaths,

   reg_n_calls_crossed, and reg_live_length.  Also, BB_HEAD, BB_END.

   The information in the line number notes is carefully retained by

   this pass.  Notes that refer to the starting and ending of

   exception regions are also carefully retained by this pass.  All

   other NOTE insns are grouped in their same relative order at the

   beginning of basic blocks and regions that have been scheduled.  */

#include "config.h"

#include "system.h"

#include "coretypes.h"

#include "tm.h"

#include "toplev.h"

#include "rtl.h"

#include "tm_p.h"

#include "hard-reg-set.h"

#include "regs.h"

#include "function.h"

#include "flags.h"

#include "insn-config.h"

#include "insn-attr.h"

#include "except.h"

#include "toplev.h"

#include "recog.h"

#include "sched-int.h"

#include "target.h"

#ifdef INSN_SCHEDULING

/* issue_rate is the number of insns that can be scheduled in the same

   machine cycle.  It can be defined in the config/mach/mach.h file,

   otherwise we set it to 1.  */

static int issue_rate;

/* sched-verbose controls the amount of debugging output the

   scheduler prints.  It is controlled by -fsched-verbose=N:

   N>0 and no -DSR : the output is directed to stderr.

   N>=10 will direct the printouts to stderr (regardless of -dSR).

   N=1: same as -dSR.

   N=2: bb's probabilities, detailed ready list info, unit/insn info.

   N=3: rtl at abort point, control-flow, regions info.

   N=5: dependences info.  */

static int sched_verbose_param = 0;

int sched_verbose = 0;

/* Debugging file.  All printouts are sent to dump, which is always set,

   either to stderr, or to the dump listing file (-dRS).  */

FILE *sched_dump = 0;

/* Highest uid before scheduling.  */

static int old_max_uid;

/* fix_sched_param() is called from toplev.c upon detection

   of the -fsched-verbose=N option.  */

void

fix_sched_param (const char *param, const char *val)

{

  if (!strcmp (param, "verbose"))

    sched_verbose_param = atoi (val);

  else

    warning (0, "fix_sched_param: unknown param: %s", param);

}

struct haifa_insn_data *h_i_d;

#define LINE_NOTE(INSN)         (h_i_d[INSN_UID (INSN)].line_note)

#define INSN_TICK(INSN)         (h_i_d[INSN_UID (INSN)].tick)

/* Vector indexed by basic block number giving the starting line-number

   for each basic block.  */

static rtx *line_note_head;

/* List of important notes we must keep around.  This is a pointer to the

   last element in the list.  */

static rtx note_list;

/* Queues, etc.  */

/* An instruction is ready to be scheduled when all insns preceding it

   have already been scheduled.  It is important to ensure that all

   insns which use its result will not be executed until its result

   has been computed.  An insn is maintained in one of four structures:

   (P) the "Pending" set of insns which cannot be scheduled until

   their dependencies have been satisfied.

   (Q) the "Queued" set of insns that can be scheduled when sufficient

   time has passed.

   (R) the "Ready" list of unscheduled, uncommitted insns.

   (S) the "Scheduled" list of insns.

   Initially, all insns are either "Pending" or "Ready" depending on

   whether their dependencies are satisfied.

   Insns move from the "Ready" list to the "Scheduled" list as they

   are committed to the schedule.  As this occurs, the insns in the

   "Pending" list have their dependencies satisfied and move to either

   the "Ready" list or the "Queued" set depending on whether

   sufficient time has passed to make them ready.  As time passes,

   insns move from the "Queued" set to the "Ready" list.

   The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled

   insns, i.e., those that are ready, queued, and pending.

   The "Queued" set (Q) is implemented by the variable `insn_queue'.

   The "Ready" list (R) is implemented by the variables `ready' and

   `n_ready'.

   The "Scheduled" list (S) is the new insn chain built by this pass.

   The transition (R->S) is implemented in the scheduling loop in

   `schedule_block' when the best insn to schedule is chosen.

   The transitions (P->R and P->Q) are implemented in `schedule_insn' as

   insns move from the ready list to the scheduled list.

   The transition (Q->R) is implemented in 'queue_to_insn' as time

   passes or stalls are introduced.  */

/* Implement a circular buffer to delay instructions until sufficient

   time has passed.  For the new pipeline description interface,

   MAX_INSN_QUEUE_INDEX is a power of two minus one which is larger

   than maximal time of instruction execution computed by genattr.c on

   the base maximal time of functional unit reservations and getting a

   result.  This is the longest time an insn may be queued.  */

static rtx *insn_queue;

static int q_ptr = 0;

static int q_size = 0;

#define NEXT_Q(X) (((X)+1) & max_insn_queue_index)

#define NEXT_Q_AFTER(X, C) (((X)+C) & max_insn_queue_index)

/* The following variable value refers for all current and future

   reservations of the processor units.  */

state_t curr_state;

/* The following variable value is size of memory representing all

   current and future reservations of the processor units.  */

static size_t dfa_state_size;

/* The following array is used to find the best insn from ready when

   the automaton pipeline interface is used.  */

static char *ready_try;

/* Describe the ready list of the scheduler.

   VEC holds space enough for all insns in the current region.  VECLEN

   says how many exactly.

   FIRST is the index of the element with the highest priority; i.e. the

   last one in the ready list, since elements are ordered by ascending

   priority.

   N_READY determines how many insns are on the ready list.  */

struct ready_list

{

  rtx *vec;

  int veclen;

  int first;

  int n_ready;

};

static int may_trap_exp (rtx, int);

/* Nonzero iff the address is comprised from at most 1 register.  */

#define CONST_BASED_ADDRESS_P(x)                        \

  (REG_P (x)                                    \

   || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS   \

        || (GET_CODE (x) == LO_SUM))                    \

       && (CONSTANT_P (XEXP (x, 0))                      \

           || CONSTANT_P (XEXP (x, 1)))))

/* Returns a class that insn with GET_DEST(insn)=x may belong to,

   as found by analyzing insn's expression.  */

static int

may_trap_exp (rtx x, int is_store)

{

  enum rtx_code code;

  if (x == 0)

    return TRAP_FREE;

  code = GET_CODE (x);

  if (is_store)

    {

      if (code == MEM && may_trap_p (x))

        return TRAP_RISKY;

      else

        return TRAP_FREE;

    }

  if (code == MEM)

    {

      /* The insn uses memory:  a volatile load.  */

      if (MEM_VOLATILE_P (x))

        return IRISKY;

      /* An exception-free load.  */

      if (!may_trap_p (x))

        return IFREE;

      /* A load with 1 base register, to be further checked.  */

      if (CONST_BASED_ADDRESS_P (XEXP (x, 0)))

        return PFREE_CANDIDATE;

      /* No info on the load, to be further checked.  */

      return PRISKY_CANDIDATE;

    }

  else

    {

      const char *fmt;

      int i, insn_class = TRAP_FREE;

      /* Neither store nor load, check if it may cause a trap.  */

      if (may_trap_p (x))

        return TRAP_RISKY;

      /* Recursive step: walk the insn...  */

      fmt = GET_RTX_FORMAT (code);

      for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)

        {

          if (fmt[i] == 'e')

            {

              int tmp_class = may_trap_exp (XEXP (x, i), is_store);

              insn_class = WORST_CLASS (insn_class, tmp_class);

            }

          else if (fmt[i] == 'E')

            {

              int j;

              for (j = 0; j < XVECLEN (x, i); j++)

                {

                  int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store);

                  insn_class = WORST_CLASS (insn_class, tmp_class);

                  if (insn_class == TRAP_RISKY || insn_class == IRISKY)

                    break;

                }

            }

          if (insn_class == TRAP_RISKY || insn_class == IRISKY)

            break;

        }

      return insn_class;

    }

}

/* Classifies insn for the purpose of verifying that it can be

   moved speculatively, by examining it's patterns, returning:

   TRAP_RISKY: store, or risky non-load insn (e.g. division by variable).

   TRAP_FREE: non-load insn.

   IFREE: load from a globally safe location.

   IRISKY: volatile load.

   PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for

   being either PFREE or PRISKY.  */

int

haifa_classify_insn (rtx insn)

{

  rtx pat = PATTERN (insn);

  int tmp_class = TRAP_FREE;

  int insn_class = TRAP_FREE;

  enum rtx_code code;

  if (GET_CODE (pat) == PARALLEL)

    {

      int i, len = XVECLEN (pat, 0);

      for (i = len - 1; i >= 0; i--)

        {

          code = GET_CODE (XVECEXP (pat, 0, i));

          switch (code)

            {

            case CLOBBER:

              /* Test if it is a 'store'.  */

              tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1);

              break;

            case SET:

              /* Test if it is a store.  */

              tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1);

              if (tmp_class == TRAP_RISKY)

                break;

              /* Test if it is a load.  */

              tmp_class

                = WORST_CLASS (tmp_class,

                               may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)),

                                             0));

              break;

            case COND_EXEC:

            case TRAP_IF:

              tmp_class = TRAP_RISKY;

              break;

            default:

              ;

            }

          insn_class = WORST_CLASS (insn_class, tmp_class);

          if (insn_class == TRAP_RISKY || insn_class == IRISKY)

            break;

        }

    }

  else

    {

      code = GET_CODE (pat);

      switch (code)

        {

        case CLOBBER:

          /* Test if it is a 'store'.  */

          tmp_class = may_trap_exp (XEXP (pat, 0), 1);

          break;

        case SET:

          /* Test if it is a store.  */

          tmp_class = may_trap_exp (SET_DEST (pat), 1);

          if (tmp_class == TRAP_RISKY)

            break;

          /* Test if it is a load.  */

          tmp_class =

            WORST_CLASS (tmp_class,

                         may_trap_exp (SET_SRC (pat), 0));

          break;

        case COND_EXEC:

        case TRAP_IF:

          tmp_class = TRAP_RISKY;

          break;

        default:;

        }

      insn_class = tmp_class;

    }

  return insn_class;

}

/* Forward declarations.  */

static int priority (rtx);

static int rank_for_schedule (const void *, const void *);

static void swap_sort (rtx *, int);

static void queue_insn (rtx, int);

static int schedule_insn (rtx, struct ready_list *, int);

static int find_set_reg_weight (rtx);

static void find_insn_reg_weight (int);

static void adjust_priority (rtx);

static void advance_one_cycle (void);

/* Notes handling mechanism:

   =========================

   Generally, NOTES are saved before scheduling and restored after scheduling.

   The scheduler distinguishes between three types of notes:

   (1) LINE_NUMBER notes, generated and used for debugging.  Here,

   before scheduling a region, a pointer to the LINE_NUMBER note is

   added to the insn following it (in save_line_notes()), and the note

   is removed (in rm_line_notes() and unlink_line_notes()).  After

   scheduling the region, this pointer is used for regeneration of

   the LINE_NUMBER note (in restore_line_notes()).

   (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:

   Before scheduling a region, a pointer to the note is added to the insn

   that follows or precedes it.  (This happens as part of the data dependence

   computation).  After scheduling an insn, the pointer contained in it is

   used for regenerating the corresponding note (in reemit_notes).

   (3) All other notes (e.g. INSN_DELETED):  Before scheduling a block,

   these notes are put in a list (in rm_other_notes() and

   unlink_other_notes ()).  After scheduling the block, these notes are

   inserted at the beginning of the block (in schedule_block()).  */

static rtx unlink_other_notes (rtx, rtx);

static rtx unlink_line_notes (rtx, rtx);

static rtx reemit_notes (rtx, rtx);

static rtx *ready_lastpos (struct ready_list *);

static void ready_sort (struct ready_list *);

static rtx ready_remove_first (struct ready_list *);

static void queue_to_ready (struct ready_list *);

static int early_queue_to_ready (state_t, struct ready_list *);

static void debug_ready_list (struct ready_list *);

static rtx move_insn1 (rtx, rtx);

static rtx move_insn (rtx, rtx);

/* The following functions are used to implement multi-pass scheduling

   on the first cycle.  */

static rtx ready_element (struct ready_list *, int);

static rtx ready_remove (struct ready_list *, int);

static int max_issue (struct ready_list *, int *);

static rtx choose_ready (struct ready_list *);

#endif /* INSN_SCHEDULING */

/* Point to state used for the current scheduling pass.  */

struct sched_info *current_sched_info;

#ifndef INSN_SCHEDULING

void

schedule_insns (FILE *dump_file ATTRIBUTE_UNUSED)

{

}

#else

/* Pointer to the last instruction scheduled.  Used by rank_for_schedule,

   so that insns independent of the last scheduled insn will be preferred

   over dependent instructions.  */

static rtx last_scheduled_insn;

/* Compute cost of executing INSN given the dependence LINK on the insn USED.

   This is the number of cycles between instruction issue and

   instruction results.  */

HAIFA_INLINE int

insn_cost (rtx insn, rtx link, rtx used)

{

  int cost = INSN_COST (insn);

  if (cost < 0)

    {

      /* A USE insn, or something else we don't need to

         understand.  We can't pass these directly to

         result_ready_cost or insn_default_latency because it will

         trigger a fatal error for unrecognizable insns.  */

      if (recog_memoized (insn) < 0)

        {

          INSN_COST (insn) = 0;

          return 0;

        }

      else

        {

          cost = insn_default_latency (insn);

          if (cost < 0)

            cost = 0;

          INSN_COST (insn) = cost;

        }

    }

  /* In this case estimate cost without caring how insn is used.  */

  if (link == 0 || used == 0)

    return cost;

  /* A USE insn should never require the value used to be computed.

     This allows the computation of a function's result and parameter

     values to overlap the return and call.  */

  if (recog_memoized (used) < 0)

    cost = 0;

  else

    {

      if (INSN_CODE (insn) >= 0)

        {

          if (REG_NOTE_KIND (link) == REG_DEP_ANTI)

            cost = 0;

          else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)

            {

              cost = (insn_default_latency (insn)

                      - insn_default_latency (used));

              if (cost <= 0)

                cost = 1;

            }

          else if (bypass_p (insn))

            cost = insn_latency (insn, used);

        }

      if (targetm.sched.adjust_cost)

        cost = targetm.sched.adjust_cost (used, link, insn, cost);

      if (cost < 0)

        cost = 0;

    }

  return cost;

}

/* Compute the priority number for INSN.  */

static int

priority (rtx insn)

{

  rtx link;

  if (! INSN_P (insn))

    return 0;

  if (! INSN_PRIORITY_KNOWN (insn))

    {

      int this_priority = 0;

      if (INSN_DEPEND (insn) == 0)

        this_priority = insn_cost (insn, 0, 0);

      else

        {

          for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))

            {

              rtx next;

              int next_priority;

              next = XEXP (link, 0);

              /* Critical path is meaningful in block boundaries only.  */

              if (! (*current_sched_info->contributes_to_priority) (next, insn))

                continue;

              next_priority = insn_cost (insn, link, next) + priority (next);

              if (next_priority > this_priority)

                this_priority = next_priority;

            }

        }

      INSN_PRIORITY (insn) = this_priority;

      INSN_PRIORITY_KNOWN (insn) = 1;

    }

  return INSN_PRIORITY (insn);

}

/* Macros and functions for keeping the priority queue sorted, and

   dealing with queuing and dequeuing of instructions.  */

#define SCHED_SORT(READY, N_READY)                                   \

do { if ((N_READY) == 2)                                             \

       swap_sort (READY, N_READY);                                   \

     else if ((N_READY) > 2)                                         \

         qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); }  \

while (0)

/* Returns a positive value if x is preferred; returns a negative value if

   y is preferred.  Should never return 0, since that will make the sort

   unstable.  */

static int

rank_for_schedule (const void *x, const void *y)

{

  rtx tmp = *(const rtx *) y;

  rtx tmp2 = *(const rtx *) x;

  rtx link;

  int tmp_class, tmp2_class, depend_count1, depend_count2;

  int val, priority_val, weight_val, info_val;

  /* The insn in a schedule group should be issued the first.  */

  if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))

    return SCHED_GROUP_P (tmp2) ? 1 : -1;

  /* Prefer insn with higher priority.  */

  priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp);

  if (priority_val)

    return priority_val;

  /* Prefer an insn with smaller contribution to registers-pressure.  */

  if (!reload_completed &&

      (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2)))

    return weight_val;

  info_val = (*current_sched_info->rank) (tmp, tmp2);

  if (info_val)

    return info_val;

  /* Compare insns based on their relation to the last-scheduled-insn.  */

  if (last_scheduled_insn)

    {

      /* Classify the instructions into three classes:

         1) Data dependent on last schedule insn.

         2) Anti/Output dependent on last scheduled insn.

         3) Independent of last scheduled insn, or has latency of one.

         Choose the insn from the highest numbered class if different.  */

      link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn));

      if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1)

        tmp_class = 3;

      else if (REG_NOTE_KIND (link) == 0)        /* Data dependence.  */

        tmp_class = 1;

      else

        tmp_class = 2;

      link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn));

      if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1)

        tmp2_class = 3;

      else if (REG_NOTE_KIND (link) == 0)        /* Data dependence.  */

        tmp2_class = 1;

      else

        tmp2_class = 2;

      if ((val = tmp2_class - tmp_class))

        return val;

    }

  /* Prefer the insn which has more later insns that depend on it.

     This gives the scheduler more freedom when scheduling later

     instructions at the expense of added register pressure.  */

  depend_count1 = 0;

  for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1))

    depend_count1++;

  depend_count2 = 0;

  for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1))

    depend_count2++;

  val = depend_count2 - depend_count1;

  if (val)

    return val;

  /* If insns are equally good, sort by INSN_LUID (original insn order),

     so that we make the sort stable.  This minimizes instruction movement,

     thus minimizing sched's effect on debugging and cross-jumping.  */

  return INSN_LUID (tmp) - INSN_LUID (tmp2);

}

/* Resort the array A in which only element at index N may be out of order.  */

HAIFA_INLINE static void

swap_sort (rtx *a, int n)

{

  rtx insn = a[n - 1];

  int i = n - 2;

  while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0)

    {

      a[i + 1] = a[i];

      i -= 1;

    }

  a[i + 1] = insn;

}

/* Add INSN to the insn queue so that it can be executed at least

   N_CYCLES after the currently executing insn.  Preserve insns

   chain for debugging purposes.  */

HAIFA_INLINE static void

queue_insn (rtx insn, int n_cycles)

{

  int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);

  rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]);

  insn_queue[next_q] = link;

  q_size += 1;