OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gcc/] [gcc-4.1.1/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20000827-1.c.27.combine] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 jlechner
 
2
;; Function foo (foo)
3
 
4
insn_cost 45: 20
5
insn_cost 46: 8
6
insn_cost 47: 28
7
insn_cost 48: 28
8
insn_cost 49: 20
9
insn_cost 21: 0
10
insn_cost 30: 4
11
insn_cost 36: 0
12
(note 2 0 7 NOTE_INSN_DELETED)
13
 
14
(note 7 2 50 NOTE_INSN_FUNCTION_BEG)
15
 
16
;; Start of basic block 0, registers live: 11 [r11] 12 [r12]
17
(note 50 7 45 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
18
 
19
(insn 45 50 46 0 (set (reg/v:SI 23 [ a ])
20
        (asm_operands:SI ("") ("=r") 0 []
21
             [] ("gcc/testsuite/gcc.c-torture/compile/20000827-1.c") 13)) -1 (nil)
22
    (nil))
23
 
24
(insn 46 45 47 0 (set (reg/v:QI 22 [ b ])
25
        (asm_operands:QI ("") ("=r") 0 []
26
             [] ("gcc/testsuite/gcc.c-torture/compile/20000827-1.c") 13)) -1 (nil)
27
    (nil))
28
 
29
(insn 47 46 48 0 (set (reg:SI 26)
30
        (ashift:SI (subreg:SI (reg/v:QI 22 [ b ]) 0)
31
            (const_int 24 [0x18]))) 32 {ashlsi3} (insn_list:REG_DEP_TRUE 46 (nil))
32
    (expr_list:REG_DEAD (reg/v:QI 22 [ b ])
33
        (nil)))
34
 
35
(insn 48 47 49 0 (set (reg:SI 26)
36
        (ashiftrt:SI (reg:SI 26)
37
            (const_int 24 [0x18]))) 31 {ashrsi3} (insn_list:REG_DEP_TRUE 47 (nil))
38
    (nil))
39
 
40
(insn 49 48 41 0 (set (reg:CC 16 cc)
41
        (compare:CC (reg:SI 26)
42
            (const_int 0 [0x0]))) 36 {cmpsi} (insn_list:REG_DEP_TRUE 48 (nil))
43
    (expr_list:REG_DEAD (reg:SI 26)
44
        (nil)))
45
;; End of basic block 0, registers live:
46
 11 [r11] 12 [r12] 16 [cc] 23
47
 
48
(note 41 49 12 NOTE_INSN_LOOP_BEG)
49
 
50
;; Start of basic block 1, registers live: 11 [r11] 12 [r12] 16 [cc] 23
51
(code_label 12 41 13 1 3 "" [1 uses])
52
 
53
(note 13 12 21 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
54
 
55
(jump_insn 21 13 42 1 (set (pc)
56
        (if_then_else (eq (reg:CC 16 cc)
57
                (const_int 0 [0x0]))
58
            (label_ref:SI 12)
59
            (pc))) 38 {beq} (nil)
60
    (expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
61
        (nil)))
62
;; End of basic block 1, registers live:
63
 11 [r11] 12 [r12] 16 [cc] 23
64
 
65
(note 42 21 27 NOTE_INSN_LOOP_END)
66
 
67
(note 27 42 23 NOTE_INSN_FUNCTION_END)
68
 
69
;; Start of basic block 2, registers live: 11 [r11] 12 [r12] 23
70
(note 23 27 30 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
71
 
72
(insn 30 23 36 2 (set (reg/i:SI 0 r0 [  ])
73
        (reg/v:SI 23 [ a ])) 13 {*movsi} (nil)
74
    (expr_list:REG_DEAD (reg/v:SI 23 [ a ])
75
        (nil)))
76
 
77
(insn 36 30 0 2 (use (reg/i:SI 0 r0 [  ])) -1 (insn_list:REG_DEP_TRUE 30 (nil))
78
    (nil))
79
;; End of basic block 2, registers live:
80
 
81
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.