OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gcc/] [gcc-4.1.1/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20000827-1.c.42.peephole2] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 jlechner
 
2
;; Function foo (foo)
3
 
4
(note 2 0 7 NOTE_INSN_DELETED)
5
 
6
(note 7 2 50 NOTE_INSN_FUNCTION_BEG)
7
 
8
;; Start of basic block 0, registers live: 12 [r12]
9
(note 50 7 45 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
10
 
11
(insn 45 50 46 0 (set (reg/v:SI 1 r1 [orig:23 a ] [23])
12
        (asm_operands:SI ("") ("=r") 0 []
13
             [] ("gcc/testsuite/gcc.c-torture/compile/20000827-1.c") 13)) -1 (nil)
14
    (nil))
15
 
16
(insn 46 45 57 0 (set (reg/v:QI 0 r0 [orig:22 b ] [22])
17
        (asm_operands:QI ("") ("=r") 0 []
18
             [] ("gcc/testsuite/gcc.c-torture/compile/20000827-1.c") 13)) -1 (nil)
19
    (nil))
20
 
21
(insn 57 46 47 0 (set (reg:SI 2 r2)
22
        (const_int 24 [0x18])) 13 {*movsi} (nil)
23
    (nil))
24
 
25
(insn 47 57 48 0 (set (reg:SI 0 r0 [26])
26
        (ashift:SI (reg:SI 0 r0 [orig:22 b ] [22])
27
            (reg:SI 2 r2))) 32 {ashlsi3} (insn_list:REG_DEP_TRUE 46 (nil))
28
    (nil))
29
 
30
(insn 48 47 49 0 (set (reg:SI 0 r0 [26])
31
        (ashiftrt:SI (reg:SI 0 r0 [26])
32
            (reg:SI 2 r2))) 31 {ashrsi3} (insn_list:REG_DEP_TRUE 47 (nil))
33
    (expr_list:REG_DEAD (reg:SI 2 r2)
34
        (nil)))
35
 
36
(insn 49 48 41 0 (set (reg:CC 16 cc)
37
        (compare:CC (reg:SI 0 r0 [26])
38
            (const_int 0 [0x0]))) 36 {cmpsi} (insn_list:REG_DEP_TRUE 48 (nil))
39
    (expr_list:REG_DEAD (reg:SI 0 r0 [26])
40
        (nil)))
41
;; End of basic block 0, registers live:
42
 1 [r1] 12 [r12] 16 [cc]
43
 
44
(note 41 49 12 NOTE_INSN_LOOP_BEG)
45
 
46
;; Start of basic block 1, registers live: 1 [r1] 12 [r12] 16 [cc]
47
(code_label 12 41 13 1 3 "" [1 uses])
48
 
49
(note 13 12 21 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
50
 
51
(jump_insn 21 13 42 1 (set (pc)
52
        (if_then_else (eq (reg:CC 16 cc)
53
                (const_int 0 [0x0]))
54
            (label_ref:SI 12)
55
            (pc))) 38 {beq} (nil)
56
    (expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
57
        (nil)))
58
;; End of basic block 1, registers live:
59
 1 [r1] 12 [r12] 16 [cc]
60
 
61
(note 42 21 27 NOTE_INSN_LOOP_END)
62
 
63
(note 27 42 23 NOTE_INSN_FUNCTION_END)
64
 
65
;; Start of basic block 2, registers live: 1 [r1] 12 [r12]
66
(note 23 27 30 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
67
 
68
(insn 30 23 36 2 (set (reg/i:SI 0 r0 [  ])
69
        (reg/v:SI 1 r1 [orig:23 a ] [23])) 13 {*movsi} (nil)
70
    (expr_list:REG_DEAD (reg/v:SI 1 r1 [orig:23 a ] [23])
71
        (nil)))
72
 
73
(insn 36 30 56 2 (use (reg/i:SI 0 r0 [  ])) -1 (insn_list:REG_DEP_TRUE 30 (nil))
74
    (nil))
75
;; End of basic block 2, registers live:
76
 
77
 
78
(note 56 36 0 NOTE_INSN_DELETED)
79
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.