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jlechner |
// locks.h - Thread synchronization primitives. MIPS implementation.
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/* Copyright (C) 2003 Free Software Foundation
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This file is part of libgcj.
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This software is copyrighted work licensed under the terms of the
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Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
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details. */
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#ifndef __SYSDEP_LOCKS_H__
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#define __SYSDEP_LOCKS_H__
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/* Integer type big enough for object address. */
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typedef unsigned obj_addr_t __attribute__((__mode__(__pointer__)));
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// Atomically replace *addr by new_val if it was initially equal to old.
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// Return true if the comparison succeeded.
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// Assumed to have acquire semantics, i.e. later memory operations
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// cannot execute before the compare_and_swap finishes.
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inline static bool
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compare_and_swap(volatile obj_addr_t *addr,
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obj_addr_t old,
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obj_addr_t new_val)
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{
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long result;
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__asm__ __volatile__(".set\tpush\n\t"
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".set\tnoreorder\n\t"
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".set\tnomacro\n\t"
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"1:\n\t"
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"ll\t%[result],0(%[addr])\n\t"
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"bne\t%[result],%[old],2f\n\t"
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"move\t%[result],$0\n\t" // delay slot
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"move\t%[result],%[new_val]\n\t"
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"sc\t%[result],0(%[addr])\n\t"
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"beq\t%[result],$0,1b\n\t"
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"nop\n\t" // delay slot
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"2:\n\t"
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".set\tpop"
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: [result] "=&r" (result)
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: [addr] "r" (addr), [new_val] "r" (new_val), [old] "r"(old)
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: "memory");
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return (bool) result;
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}
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// Set *addr to new_val with release semantics, i.e. making sure
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// that prior loads and stores complete before this
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// assignment.
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inline static void
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release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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{
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__asm__ __volatile__(".set\tpush\n\t"
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"sync\n\t"
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".set\tpop" : : : "memory");
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*(addr) = new_val;
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}
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// Compare_and_swap with release semantics instead of acquire semantics.
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// On many architecture, the operation makes both guarantees, so the
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// implementation can be the same.
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inline static bool
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compare_and_swap_release(volatile obj_addr_t *addr,
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obj_addr_t old,
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obj_addr_t new_val)
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{
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__asm__ __volatile__(".set\tpush\n\t"
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"sync\n\t"
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".set\tpop" : : : "memory");
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return compare_and_swap(addr, old, new_val);
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}
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// Ensure that subsequent instructions do not execute on stale
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// data that was loaded from memory before the barrier.
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// On X86, the hardware ensures that reads are properly ordered.
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inline static void
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read_barrier()
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{
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__asm__ __volatile__(".set\tpush\n\t"
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"sync\n\t"
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".set\tpop" : : : "memory");
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}
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// Ensure that prior stores to memory are completed with respect to other
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// processors.
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inline static void
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write_barrier()
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{
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__asm__ __volatile__(".set\tpush\n\t"
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#if _MIPS_SIM == _ABIO32
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".set\tmips2\n\t"
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#endif
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"sync\n\t"
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".set\tpop" : : : "memory");
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}
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#endif // __SYSDEP_LOCKS_H__
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