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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [include/] [opcode/] [ChangeLog] - Blame information for rev 25

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Line No. Rev Author Line
1 25 jlechner
2008-02-18  M R Swami Reddy 
2
 
3
        * cr16.h (cr16_num_optab): Declared.
4
 
5
2008-02-14  Hakan Ardo  
6
 
7
        PR gas/2626
8
        * avr.h (AVR_ISA_2xxe): Define.
9
 
10
2008-02-04  Adam Nemet  
11
 
12
        * mips.h: Update copyright.
13
        (INSN_CHIP_MASK): New macro.
14
        (INSN_OCTEON): New macro.
15
        (CPU_OCTEON): New macro.
16
        (OPCODE_IS_MEMBER): Handle Octeon instructions.
17
 
18
2007-11-29  Mark Shinwell  
19
 
20
        * mips.h (INSN_LOONGSON_2E): New.
21
        (INSN_LOONGSON_2F): New.
22
        (CPU_LOONGSON_2E): New.
23
        (CPU_LOONGSON_2F): New.
24
        (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
25
 
26
2007-11-29  Mark Shinwell  
27
 
28
        * mips.h (INSN_ISA*): Redefine certain values as an
29
        enumeration.  Update comments.
30
        (mips_isa_table): New.
31
        (ISA_MIPS*): Redefine to match enumeration.
32
        (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
33
        values.
34
 
35
2007-08-08  Ben Elliston  
36
 
37
        * ppc.h (PPC_OPCODE_PPCPS): New.
38
 
39
2007-07-03  Nathan Sidwell  
40
 
41
        * m68k.h: Document j K & E.
42
 
43
2007-06-29  M R Swami Reddy  
44
 
45
        * cr16.h: New file for CR16 target.
46
 
47
2007-05-02  Alan Modra  
48
 
49
        * ppc.h (PPC_OPERAND_PLUS1): Update comment.
50
 
51
2007-04-23  Nathan Sidwell  
52
 
53
        * m68k.h (mcfisa_c): New.
54
        (mcfusp, mcf_mask): Adjust.
55
 
56
2007-04-20  Alan Modra  
57
 
58
        * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
59
        (num_powerpc_operands): Declare.
60
        (PPC_OPERAND_SIGNED et al): Redefine as hex.
61
        (PPC_OPERAND_PLUS1): Define.
62
 
63
2007-03-21  H.J. Lu  
64
 
65
        * i386.h (REX_MODE64): Renamed to ...
66
        (REX_W): This.
67
        (REX_EXTX): Renamed to ...
68
        (REX_R): This.
69
        (REX_EXTY): Renamed to ...
70
        (REX_X): This.
71
        (REX_EXTZ): Renamed to ...
72
        (REX_B): This.
73
 
74
2007-03-15  H.J. Lu  
75
 
76
        * i386.h: Add entries from config/tc-i386.h and move tables
77
        to opcodes/i386-opc.h.
78
 
79
2007-03-13  H.J. Lu  
80
 
81
        * i386.h (FloatDR): Removed.
82
        (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
83
 
84
2007-03-01  Alan Modra  
85
 
86
        * spu-insns.h: Add soma double-float insns.
87
 
88
2007-02-20  Thiemo Seufer  
89
            Chao-Ying Fu  
90
 
91
        * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
92
        (INSN_DSPR2): Add flag for DSP R2 instructions.
93
        (M_BALIGN): New macro.
94
 
95
2007-02-14  Alan Modra  
96
 
97
        * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
98
        and Seg3ShortFrom with Shortform.
99
 
100
2007-02-11  H.J. Lu  
101
 
102
        PR gas/4027
103
        * i386.h (i386_optab): Put the real "test" before the pseudo
104
        one.
105
 
106
2007-01-08  Kazu Hirata  
107
 
108
        * m68k.h (m68010up): OR fido_a.
109
 
110
2006-12-25  Kazu Hirata  
111
 
112
        * m68k.h (fido_a): New.
113
 
114
2006-12-24  Kazu Hirata  
115
 
116
        * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
117
        mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
118
        values.
119
 
120
2006-11-08  H.J. Lu  
121
 
122
        * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
123
 
124
2006-10-31  Mei Ligang  
125
 
126
        * score-inst.h (enum score_insn_type): Add Insn_internal.
127
 
128
2006-10-25  Trevor Smigiel  
129
            Yukishige Shibata  
130
            Nobuhisa Fujinami  
131
            Takeaki Fukuoka  
132
            Alan Modra  
133
 
134
        * spu-insns.h: New file.
135
        * spu.h: New file.
136
 
137
2006-10-24  Andrew Pinski  
138
 
139
        * ppc.h (PPC_OPCODE_CELL): Define.
140
 
141
2006-10-23  Dwarakanath Rajagopal  
142
 
143
        * i386.h :  Modify opcode to support for the change in POPCNT opcode
144
        in amdfam10 architecture.
145
 
146
2006-09-28  H.J. Lu  
147
 
148
        * i386.h: Replace CpuMNI with CpuSSSE3.
149
 
150
2006-09-26  Mark Shinwell  
151
            Joseph Myers  
152
            Ian Lance Taylor  
153
            Ben Elliston  
154
 
155
        * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
156
 
157
2006-09-17  Mei Ligang  
158
 
159
        * score-datadep.h: New file.
160
        * score-inst.h: New file.
161
 
162
2006-07-14  H.J. Lu  
163
 
164
        * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
165
        movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
166
        movdq2q and movq2dq.
167
 
168
2006-07-10 Dwarakanath Rajagopal        
169
           Michael Meissner             
170
 
171
        * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
172
 
173
2006-06-12  H.J. Lu  
174
 
175
        * i386.h (i386_optab): Add "nop" with memory reference.
176
 
177
2006-06-12  H.J. Lu  
178
 
179
        * i386.h (i386_optab): Update comment for 64bit NOP.
180
 
181
2006-06-06  Ben Elliston  
182
            Anton Blanchard  
183
 
184
        * ppc.h (PPC_OPCODE_POWER6): Define.
185
        Adjust whitespace.
186
 
187
2006-06-05  Thiemo Seufer  
188
 
189
        * mips.h: Improve description of MT flags.
190
 
191
2006-05-25  Richard Sandiford  
192
 
193
        * m68k.h (mcf_mask): Define.
194
 
195
2006-05-05  Thiemo Seufer  
196
            David Ung  
197
 
198
        * mips.h (enum): Add macro M_CACHE_AB.
199
 
200
2006-05-04  Thiemo Seufer  
201
            Nigel Stephens  
202
            David Ung  
203
 
204
        * mips.h: Add INSN_SMARTMIPS define.
205
 
206
2006-04-30  Thiemo Seufer  
207
            David Ung  
208
 
209
        * mips.h: Defines udi bits and masks.  Add description of
210
        characters which may appear in the args field of udi
211
        instructions.
212
 
213
2006-04-26  Thiemo Seufer  
214
 
215
        * mips.h: Improve comments describing the bitfield instruction
216
        fields.
217
 
218
2006-04-26  Julian Brown  
219
 
220
        * arm.h (FPU_VFP_EXT_V3): Define constant.
221
        (FPU_NEON_EXT_V1): Likewise.
222
        (FPU_VFP_HARD): Update.
223
        (FPU_VFP_V3): Define macro.
224
        (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
225
 
226
2006-04-07  Joerg Wunsch  
227
 
228
        * avr.h (AVR_ISA_PWMx): New.
229
 
230
2006-03-28  Nathan Sidwell  
231
 
232
        * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
233
        cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
234
        cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
235
        cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
236
        cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
237
 
238
2006-03-10  Paul Brook  
239
 
240
        * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
241
 
242
2006-03-04  John David Anglin  
243
 
244
        * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
245
        first.  Correct mask of bb "B" opcode.
246
 
247
2006-02-27  H.J. Lu 
248
 
249
        * i386.h (i386_optab): Support Intel Merom New Instructions.
250
 
251
2006-02-24  Paul Brook  
252
 
253
        * arm.h: Add V7 feature bits.
254
 
255
2006-02-23  H.J. Lu  
256
 
257
        * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
258
 
259
2006-01-31  Paul Brook  
260
        Richard Earnshaw 
261
 
262
        * arm.h: Use ARM_CPU_FEATURE.
263
        (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
264
        (arm_feature_set): Change to a structure.
265
        (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
266
        ARM_FEATURE): New macros.
267
 
268
2005-12-07  Hans-Peter Nilsson  
269
 
270
        * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
271
        (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
272
        (ADD_PC_INCR_OPCODE): Don't define.
273
 
274
2005-12-06  H.J. Lu  
275
 
276
        PR gas/1874
277
        * i386.h (i386_optab): Add 64bit support for monitor and mwait.
278
 
279
2005-11-14  David Ung  
280
 
281
        * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
282
        instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
283
        save/restore encoding of the args field.
284
 
285
2005-10-28  Dave Brolley  
286
 
287
        Contribute the following changes:
288
        2005-02-16  Dave Brolley  
289
 
290
        * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
291
        cgen_isa_mask_* to cgen_bitset_*.
292
        * cgen.h: Likewise.
293
 
294
        2003-10-21  Richard Sandiford  
295
 
296
        * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
297
        (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
298
        (CGEN_CPU_TABLE): Make isas a ponter.
299
 
300
        2003-09-29  Dave Brolley  
301
 
302
        * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
303
        (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
304
        (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
305
 
306
        2002-12-13  Dave Brolley  
307
 
308
        * cgen.h (symcat.h): #include it.
309
        (cgen-bitset.h): #include it.
310
        (CGEN_ATTR_VALUE_TYPE): Now a union.
311
        (CGEN_ATTR_VALUE): Reference macros generated in opcodes/-desc.h.
312
        (CGEN_ATTR_ENTRY): 'value' now unsigned.
313
        (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
314
        * cgen-bitset.h: New file.
315
 
316
2005-09-30  Catherine Moore  
317
 
318
        * bfin.h: New file.
319
 
320
2005-10-24  Jan Beulich  
321
 
322
        * ia64.h (enum ia64_opnd): Move memory operand out of set of
323
        indirect operands.
324
 
325
2005-10-16  John David Anglin  
326
 
327
        * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
328
        Add FLAG_STRICT to pa10 ftest opcode.
329
 
330
2005-10-12  John David Anglin  
331
 
332
        * hppa.h (pa_opcodes): Remove lha entries.
333
 
334
2005-10-08  John David Anglin  
335
 
336
        * hppa.h (FLAG_STRICT): Revise comment.
337
        (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
338
        before corresponding pa11 opcodes.  Add strict pa10 register-immediate
339
        entries for "fdc".
340
 
341
2005-09-24  John David Anglin  
342
 
343
        * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
344
 
345
2005-09-06  Chao-ying Fu  
346
 
347
        * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
348
        OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
349
        define.
350
        Document !, $, *, &, g, +t, +T operand formats for MT instructions.
351
        (INSN_ASE_MASK): Update to include INSN_MT.
352
        (INSN_MT): New define for MT ASE.
353
 
354
2005-08-25  Chao-ying Fu  
355
 
356
        * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
357
        OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
358
        OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
359
        OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
360
        OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
361
        Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
362
        instructions.
363
        (INSN_DSP): New define for DSP ASE.
364
 
365
2005-08-18  Alan Modra  
366
 
367
        * a29k.h: Delete.
368
 
369
2005-08-15  Daniel Jacobowitz  
370
 
371
        * ppc.h (PPC_OPCODE_E300): Define.
372
 
373
2005-08-12 Martin Schwidefsky  
374
 
375
        * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
376
 
377
2005-07-28  John David Anglin  
378
 
379
        PR gas/336
380
        * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
381
        and pitlb.
382
 
383
2005-07-27  Jan Beulich  
384
 
385
        * i386.h (i386_optab): Add comment to movd. Use LongMem for all
386
        movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
387
        Add movq-s as 64-bit variants of movd-s.
388
 
389
2005-07-18  John David Anglin  
390
 
391
        * hppa.h: Fix punctuation in comment.
392
 
393
        * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
394
        implicit space-register addressing.  Set space-register bits on opcodes
395
        using implicit space-register addressing.  Add various missing pa20
396
        long-immediate opcodes.  Remove various opcodes using implicit 3-bit
397
        space-register addressing.  Use "fE" instead of "fe" in various
398
        fstw opcodes.
399
 
400
2005-07-18  Jan Beulich  
401
 
402
        * i386.h (i386_optab): Operands of aam and aad are unsigned.
403
 
404
2007-07-15  H.J. Lu 
405
 
406
        * i386.h (i386_optab): Support Intel VMX Instructions.
407
 
408
2005-07-10  John David Anglin  
409
 
410
        * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
411
 
412
2005-07-05  Jan Beulich  
413
 
414
        * i386.h (i386_optab): Add new insns.
415
 
416
2005-07-01  Nick Clifton  
417
 
418
        * sparc.h: Add typedefs to structure declarations.
419
 
420
2005-06-20  H.J. Lu  
421
 
422
        PR 1013
423
        * i386.h (i386_optab): Update comments for 64bit addressing on
424
        mov. Allow 64bit addressing for mov and movq.
425
 
426
2005-06-11  John David Anglin  
427
 
428
        * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
429
        respectively, in various floating-point load and store patterns.
430
 
431
2005-05-23  John David Anglin  
432
 
433
        * hppa.h (FLAG_STRICT): Correct comment.
434
        (pa_opcodes): Update load and store entries to allow both PA 1.X and
435
        PA 2.0 mneumonics when equivalent.  Entries with cache control
436
        completers now require PA 1.1.  Adjust whitespace.
437
 
438
2005-05-19  Anton Blanchard  
439
 
440
        * ppc.h (PPC_OPCODE_POWER5): Define.
441
 
442
2005-05-10  Nick Clifton  
443
 
444
        * Update the address and phone number of the FSF organization in
445
        the GPL notices in the following files:
446
        a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
447
        crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
448
        i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
449
        mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
450
        pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
451
        tic54x.h, tic80.h, v850.h, vax.h
452
 
453
2005-05-09  Jan Beulich  
454
 
455
        * i386.h (i386_optab): Add ht and hnt.
456
 
457
2005-04-18  Mark Kettenis  
458
 
459
        * i386.h: Insert hyphens into selected VIA PadLock extensions.
460
        Add xcrypt-ctr.  Provide aliases without hyphens.
461
 
462
2005-04-13  H.J. Lu  
463
 
464
        Moved from ../ChangeLog
465
 
466
        2005-04-12  Paul Brook  
467
        * m88k.h: Rename psr macros to avoid conflicts.
468
 
469
        2005-03-12  Zack Weinberg  
470
        * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
471
        Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
472
        and ARM_ARCH_V6ZKT2.
473
 
474
        2004-11-29  Tomer Levi  
475
        * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
476
        Remove redundant instruction types.
477
        (struct argument): X_op - new field.
478
        (struct cst4_entry): Remove.
479
        (no_op_insn): Declare.
480
 
481
        2004-11-05  Tomer Levi  
482
        * crx.h (enum argtype): Rename types, remove unused types.
483
 
484
        2004-10-27  Tomer Levi  
485
        * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
486
        (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
487
        (enum operand_type): Rearrange operands, edit comments.
488
        replace us with ui for unsigned immediate.
489
        replace d with disps/dispu/dispe for signed/unsigned/escaped
490
        displacements (respectively).
491
        replace rbase_ridx_scl2_dispu with rindex_disps for register index.
492
        (instruction type): Add NO_TYPE_INS.
493
        (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
494
        (operand_entry): New field - 'flags'.
495
        (operand flags): New.
496
 
497
        2004-10-21  Tomer Levi  
498
        * crx.h (operand_type): Remove redundant types i3, i4,
499
        i5, i8, i12.
500
        Add new unsigned immediate types us3, us4, us5, us16.
501
 
502
2005-04-12  Mark Kettenis  
503
 
504
        * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
505
        adjust them accordingly.
506
 
507
2005-04-01  Jan Beulich  
508
 
509
        * i386.h (i386_optab): Add rdtscp.
510
 
511
2005-03-29  H.J. Lu  
512
 
513
        * i386.h (i386_optab): Don't allow the `l' suffix for moving
514
        between memory and segment register. Allow movq for moving between
515
        general-purpose register and segment register.
516
 
517
2005-02-09  Jan Beulich  
518
 
519
        PR gas/707
520
        * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
521
        FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
522
        fnstsw.
523
 
524
2006-02-07  Nathan Sidwell  
525
 
526
        * m68k.h (m68008, m68ec030, m68882): Remove.
527
        (m68k_mask): New.
528
        (cpu_m68k, cpu_cf): New.
529
        (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
530
        mcf5470, mcf5480): Rename to cpu_. Add m680x0 variants.
531
 
532
2005-01-25  Alexandre Oliva  
533
 
534
        2004-11-10  Alexandre Oliva  
535
        * cgen.h (enum cgen_parse_operand_type): Add
536
        CGEN_PARSE_OPERAND_SYMBOLIC.
537
 
538
2005-01-21  Fred Fish  
539
 
540
        * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
541
        Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
542
        Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
543
 
544
2005-01-19  Fred Fish  
545
 
546
        * mips.h (struct mips_opcode): Add new pinfo2 member.
547
        (INSN_ALIAS): New define for opcode table entries that are
548
        specific instances of another entry, such as 'move' for an 'or'
549
        with a zero operand.
550
        (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
551
        (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
552
 
553
2004-12-09  Ian Lance Taylor  
554
 
555
        * mips.h (CPU_RM9000): Define.
556
        (OPCODE_IS_MEMBER): Handle CPU_RM9000.
557
 
558
2004-11-25 Jan Beulich  
559
 
560
        * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
561
        to/from test registers are illegal in 64-bit mode. Add missing
562
        NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
563
        (previously one had to explicitly encode a rex64 prefix). Re-enable
564
        lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
565
        support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
566
 
567
2004-11-23 Jan Beulich  
568
 
569
        * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
570
        available only with SSE2. Change the MMX additions introduced by SSE
571
        and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
572
        instructions by their now designated identifier (since combining i686
573
        and 3DNow! does not really imply 3DNow!A).
574
 
575
2004-11-19  Alan Modra  
576
 
577
        * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
578
        struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
579
 
580
2004-11-08  Inderpreet Singh   
581
            Vineet Sharma      
582
 
583
        * maxq.h: New file: Disassembly information for the maxq port.
584
 
585
2004-11-05  H.J. Lu  
586
 
587
        * i386.h (i386_optab): Put back "movzb".
588
 
589
2004-11-04  Hans-Peter Nilsson  
590
 
591
        * cris.h (enum cris_insn_version_usage): Tweak formatting and
592
        comments.  Remove member cris_ver_sim.  Add members
593
        cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
594
        cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
595
        (struct cris_support_reg, struct cris_cond15): New types.
596
        (cris_conds15): Declare.
597
        (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
598
        (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
599
        (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
600
        (NOP_Z_BITS): Define in terms of NOP_OPCODE.
601
        (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
602
        SIZE_FIELD_UNSIGNED.
603
 
604
2004-11-04 Jan Beulich  
605
 
606
        * i386.h (sldx_Suf): Remove.
607
        (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
608
        (q_FP): Define, implying no REX64.
609
        (x_FP, sl_FP): Imply FloatMF.
610
        (i386_optab): Split reg and mem forms of moving from segment registers
611
        so that the memory forms can ignore the 16-/32-bit operand size
612
        distinction. Adjust a few others for Intel mode. Remove *FP uses from
613
        all non-floating-point instructions. Unite 32- and 64-bit forms of
614
        movsx, movzx, and movd. Adjust floating point operations for the above
615
        changes to the *FP macros. Add DefaultSize to floating point control
616
        insns operating on larger memory ranges. Remove left over comments
617
        hinting at certain insns being Intel-syntax ones where the ones
618
        actually meant are already gone.
619
 
620
2004-10-07  Tomer Levi  
621
 
622
        * crx.h: Add COPS_REG_INS - Coprocessor Special register
623
        instruction type.
624
 
625
2004-09-30  Paul Brook  
626
 
627
        * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
628
        (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
629
 
630
2004-09-11  Theodore A. Roth  
631
 
632
        * avr.h: Add support for
633
        atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
634
 
635
2004-09-09  Segher Boessenkool  
636
 
637
        * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
638
 
639
2004-08-24  Dmitry Diky  
640
 
641
        * msp430.h (msp430_opc): Add new instructions.
642
        (msp430_rcodes): Declare new instructions.
643
        (msp430_hcodes): Likewise..
644
 
645
2004-08-13  Nick Clifton  
646
 
647
        PR/301
648
        * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
649
        processors.
650
 
651
2004-08-30  Michal Ludvig  
652
 
653
        * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
654
 
655
2004-07-22  H.J. Lu  
656
 
657
        * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
658
 
659
2004-07-21  Jan Beulich  
660
 
661
        * i386.h: Adjust instruction descriptions to better match the
662
        specification.
663
 
664
2004-07-16  Richard Earnshaw  
665
 
666
        * arm.h: Remove all old content.  Replace with architecture defines
667
        from gas/config/tc-arm.c.
668
 
669
2004-07-09  Andreas Schwab  
670
 
671
        * m68k.h: Fix comment.
672
 
673
2004-07-07  Tomer Levi  
674
 
675
        * crx.h: New file.
676
 
677
2004-06-24  Alan Modra  
678
 
679
        * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
680
 
681
2004-05-24  Peter Barada  
682
 
683
        * m68k.h: Add 'size' to m68k_opcode.
684
 
685
2004-05-05  Peter Barada  
686
 
687
        * m68k.h: Switch from ColdFire chip name to core variant.
688
 
689
2004-04-22  Peter Barada  
690
 
691
        * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
692
        descriptions for new EMAC cases.
693
        Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
694
        handle Motorola MAC syntax.
695
        Allow disassembly of ColdFire V4e object files.
696
 
697
2004-03-16  Alan Modra  
698
 
699
        * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
700
 
701
2004-03-12  Jakub Jelinek  
702
 
703
        * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
704
 
705
2004-03-12  Michal Ludvig  
706
 
707
        * i386.h (i386_optab): Added xstore as an alias for xstorerng.
708
 
709
2004-03-12  Michal Ludvig  
710
 
711
        * i386.h (i386_optab): Added xstore/xcrypt insns.
712
 
713
2004-02-09  Anil Paranjpe  
714
 
715
        * h8300.h (32bit ldc/stc): Add relaxing support.
716
 
717
2004-01-12  Anil Paranjpe  
718
 
719
        * h8300.h (BITOP): Pass MEMRELAX flag.
720
 
721
2004-01-09  Anil Paranjpe  
722
 
723
        * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
724
        except for the H8S.
725
 
726
For older changes see ChangeLog-9103
727
 
728
Local Variables:
729
mode: change-log
730
left-margin: 8
731
fill-column: 74
732
version-control: never
733
End:

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