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jlechner |
# Makefile template for Configure for the m32r simulator
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# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2003, 2004, 2007, 2008
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# Free Software Foundation, Inc.
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# Contributed by Cygnus Support.
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#
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# This file is part of GDB, the GNU debugger.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see .
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## COMMON_PRE_CONFIG_FRAG
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M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
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M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
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M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
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TRAPS_OBJ = @traps_obj@
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CONFIG_DEVICES = dv-sockser.o
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CONFIG_DEVICES =
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SIM_OBJS = \
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$(SIM_NEW_COMMON_OBJS) \
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sim-cpu.o \
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sim-hload.o \
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sim-hrw.o \
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sim-model.o \
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sim-reg.o \
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cgen-utils.o cgen-trace.o cgen-scache.o \
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cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
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sim-if.o arch.o \
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$(M32R_OBJS) \
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$(M32RX_OBJS) \
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$(M32R2_OBJS) \
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$(TRAPS_OBJ) \
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devices.o \
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$(CONFIG_DEVICES)
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# Extra headers included by sim-main.h.
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SIM_EXTRA_DEPS = \
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$(CGEN_INCLUDE_DEPS) \
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arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h
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SIM_EXTRA_CFLAGS = @sim_extra_cflags@
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SIM_RUN_OBJS = nrun.o
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SIM_EXTRA_CLEAN = m32r-clean
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# This selects the m32r newlib/libgloss syscall definitions.
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NL_TARGET = -DNL_TARGET_m32r
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## COMMON_POST_CONFIG_FRAG
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arch = m32r
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sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
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arch.o: arch.c $(SIM_MAIN_DEPS)
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traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
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traps-linux.o: traps.c syscall.h targ-vals.h $(SIM_MAIN_DEPS)
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devices.o: devices.c $(SIM_MAIN_DEPS)
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# M32R objs
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M32RBF_INCLUDE_DEPS = \
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$(CGEN_MAIN_CPU_DEPS) \
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cpu.h decode.h eng.h
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m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)
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# FIXME: Use of `mono' is wip.
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mloop.c eng.h: stamp-mloop
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stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
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$(SHELL) $(srccom)/genmloop.sh \
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-mono -fast -pbb -switch sem-switch.c \
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-cpu m32rbf -infile $(srcdir)/mloop.in
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$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
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$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
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touch stamp-mloop
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mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)
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cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
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decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
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sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
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model.o: model.c $(M32RBF_INCLUDE_DEPS)
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# M32RX objs
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M32RXF_INCLUDE_DEPS = \
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$(CGEN_MAIN_CPU_DEPS) \
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cpux.h decodex.h engx.h
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m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)
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# FIXME: Use of `mono' is wip.
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mloopx.c engx.h: stamp-xmloop
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stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
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$(SHELL) $(srccom)/genmloop.sh \
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-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
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-cpu m32rxf -infile $(srcdir)/mloopx.in \
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-outfile-suffix x
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$(SHELL) $(srcroot)/move-if-change engx.hin engx.h
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$(SHELL) $(srcroot)/move-if-change mloopx.cin mloopx.c
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touch stamp-xmloop
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mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)
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cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
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decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
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semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
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modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
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# M32R2 objs
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M32R2F_INCLUDE_DEPS = \
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$(CGEN_MAIN_CPU_DEPS) \
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cpu2.h decode2.h eng2.h
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m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)
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# FIXME: Use of `mono' is wip.
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mloop2.c eng2.h: stamp-2mloop
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stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
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$(SHELL) $(srccom)/genmloop.sh \
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-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
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-cpu m32r2f -infile $(srcdir)/mloop2.in \
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-outfile-suffix 2
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$(SHELL) $(srcroot)/move-if-change eng2.hin eng2.h
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$(SHELL) $(srcroot)/move-if-change mloop2.cin mloop2.c
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touch stamp-2mloop
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mloop2.o: mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
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cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)
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decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
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sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)
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model2.o: model2.c $(M32R2F_INCLUDE_DEPS)
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m32r-clean:
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rm -f mloop.c eng.h stamp-mloop
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rm -f mloopx.c engx.h stamp-xmloop
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rm -f mloop2.c eng2.h stamp-2mloop
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rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
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rm -f tmp-*
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# cgen support, enable with --enable-cgen-maint
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CGEN_MAINT = ; @true
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# The following line is commented in or out depending upon --enable-cgen-maint.
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@CGEN_MAINT@CGEN_MAINT =
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stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/m32r.cpu
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$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
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archfile=$(CGEN_CPU_DIR)/m32r.cpu \
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FLAGS="with-scache with-profile=fn"
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touch stamp-arch
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arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
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stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
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$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
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cpu=m32rbf mach=m32r SUFFIX= \
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archfile=$(CGEN_CPU_DIR)/m32r.cpu \
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FLAGS="with-scache with-profile=fn" \
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EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
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touch stamp-cpu
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cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
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stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
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$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
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cpu=m32rxf mach=m32rx SUFFIX=x \
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archfile=$(CGEN_CPU_DIR)/m32r.cpu \
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FLAGS="with-scache with-profile=fn" \
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EXTRAFILES="$(CGEN_CPU_SEMSW)"
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touch stamp-xcpu
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cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
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stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
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$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
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cpu=m32r2f mach=m32r2 SUFFIX=2 \
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archfile=$(CGEN_CPU_DIR)/m32r.cpu \
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FLAGS="with-scache with-profile=fn" \
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EXTRAFILES="$(CGEN_CPU_SEMSW)"
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touch stamp-2cpu
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cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu
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