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# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global tmiaph
tmiaph:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        # Test Multilply Accumulate
 
        mvi_h_gr   r0, 0x11223344
        mvi_h_gr   r1, 0x55667788
        mvi_h_gr   r2, 0x12345678
        mvi_h_gr   r3, 0x9abcdef0
 
        tmcrr      wr0, r0, r1
 
        tmiaph     wr0, r2, r3
 
        tmrrc      r0, r1, wr0
 
        test_h_gr  r0, 0xfec3f9f4
        test_h_gr  r1, 0x55667787
        test_h_gr  r2, 0x12345678
        test_h_gr  r3, 0x9abcdef0
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global tmiaph`
10			`tmiaph:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`# Test Multilply Accumulate`
18
19			`mvi_h_gr r0, 0x11223344`
20			`mvi_h_gr r1, 0x55667788`
21			`mvi_h_gr r2, 0x12345678`
22			`mvi_h_gr r3, 0x9abcdef0`
23
24			`tmcrr wr0, r0, r1`
25
26			`tmiaph wr0, r2, r3`
27
28			`tmrrc r0, r1, wr0`
29
30			`test_h_gr r0, 0xfec3f9f4`
31			`test_h_gr r1, 0x55667787`
32			`test_h_gr r2, 0x12345678`
33			`test_h_gr r3, 0x9abcdef0`
34
35			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [tmiaph.cgs] - Blame information for rev 26