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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wror.cgs] - Blame information for rev 26

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# Intel(r) Wireless MMX(tm) technology testcase for WROR
# mach: xscale
# as: -mcpu=xscale+iwmmxt
 
        .include "testutils.inc"
 
        start
 
        .global wror
wror:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
 
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
 
        # Test Halfword wide rotate right by register
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x00000000
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wrorh      wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x00000000
        test_h_gr  r4, 0x091a2b3c
        test_h_gr  r5, 0x4d5e6f78
 
        # Test Halfword wide rotate right by CG register
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0
        mvi_h_gr   r4, 0
 
        tmcrr      wr0, r0, r1
        tmcr       wcgr0, r2
        tmcrr      wr1, r2, r3
 
        wrorhg     wr1, wr0, wcgr0
 
        tmrrc      r0, r1, wr0
        tmrc       r2, wcgr0
        tmrrc      r3, r4, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x091a2b3c
        test_h_gr  r4, 0x4d5e6f78
 
        # Test Word wide rotate right by register
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x00000000
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wrorw      wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x00000000
        test_h_gr  r4, 0x2b3c091a
        test_h_gr  r5, 0x6f784d5e
 
        # Test Word wide rotate right by CG register
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0
        mvi_h_gr   r4, 0
 
        tmcrr      wr0, r0, r1
        tmcr       wcgr0, r2
        tmcrr      wr1, r2, r3
 
        wrorwg     wr1, wr0, wcgr0
 
        tmrrc      r0, r1, wr0
        tmrc       r2, wcgr0
        tmrrc      r3, r4, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x2b3c091a
        test_h_gr  r4, 0x6f784d5e
 
        # Test Double Word wide rotate right by register
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x00000000
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
 
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
 
        wrord      wr2, wr0, wr1
 
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x00000000
        test_h_gr  r4, 0x6f78091a
        test_h_gr  r5, 0x2b3c4d5e
 
        # Test Double Word wide rotate right by CG register
 
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0
        mvi_h_gr   r4, 0
 
        tmcrr      wr0, r0, r1
        tmcr       wcgr0, r2
        tmcrr      wr1, r2, r3
 
        wrordg     wr1, wr0, wcgr0
 
        tmrrc      r0, r1, wr0
        tmrc       r2, wcgr0
        tmrrc      r3, r4, wr2
 
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x6f78091a
        test_h_gr  r4, 0x2b3c4d5e
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# Intel(r) Wireless MMX(tm) technology testcase for WROR`
2			`# mach: xscale`
3			`# as: -mcpu=xscale+iwmmxt`
4
5			`.include "testutils.inc"`
6
7			`start`
8
9			`.global wror`
10			`wror:`
11			`# Enable access to CoProcessors 0 & 1 before`
12			`# we attempt these instructions.`
13
14			`mvi_h_gr r1, 3`
15			`mcr p15, 0, r1, cr15, cr1, 0`
16
17			`# Test Halfword wide rotate right by register`
18
19			`mvi_h_gr r0, 0x12345678`
20			`mvi_h_gr r1, 0x9abcdef0`
21			`mvi_h_gr r2, 0x11111111`
22			`mvi_h_gr r3, 0x00000000`
23			`mvi_h_gr r4, 0`
24			`mvi_h_gr r5, 0`
25
26			`tmcrr wr0, r0, r1`
27			`tmcrr wr1, r2, r3`
28			`tmcrr wr2, r4, r5`
29
30			`wrorh wr2, wr0, wr1`
31
32			`tmrrc r0, r1, wr0`
33			`tmrrc r2, r3, wr1`
34			`tmrrc r4, r5, wr2`
35
36			`test_h_gr r0, 0x12345678`
37			`test_h_gr r1, 0x9abcdef0`
38			`test_h_gr r2, 0x11111111`
39			`test_h_gr r3, 0x00000000`
40			`test_h_gr r4, 0x091a2b3c`
41			`test_h_gr r5, 0x4d5e6f78`
42
43			`# Test Halfword wide rotate right by CG register`
44
45			`mvi_h_gr r0, 0x12345678`
46			`mvi_h_gr r1, 0x9abcdef0`
47			`mvi_h_gr r2, 0x11111111`
48			`mvi_h_gr r3, 0`
49			`mvi_h_gr r4, 0`
50
51			`tmcrr wr0, r0, r1`
52			`tmcr wcgr0, r2`
53			`tmcrr wr1, r2, r3`
54
55			`wrorhg wr1, wr0, wcgr0`
56
57			`tmrrc r0, r1, wr0`
58			`tmrc r2, wcgr0`
59			`tmrrc r3, r4, wr2`
60
61			`test_h_gr r0, 0x12345678`
62			`test_h_gr r1, 0x9abcdef0`
63			`test_h_gr r2, 0x11111111`
64			`test_h_gr r3, 0x091a2b3c`
65			`test_h_gr r4, 0x4d5e6f78`
66
67			`# Test Word wide rotate right by register`
68
69			`mvi_h_gr r0, 0x12345678`
70			`mvi_h_gr r1, 0x9abcdef0`
71			`mvi_h_gr r2, 0x11111111`
72			`mvi_h_gr r3, 0x00000000`
73			`mvi_h_gr r4, 0`
74			`mvi_h_gr r5, 0`
75
76			`tmcrr wr0, r0, r1`
77			`tmcrr wr1, r2, r3`
78			`tmcrr wr2, r4, r5`
79
80			`wrorw wr2, wr0, wr1`
81
82			`tmrrc r0, r1, wr0`
83			`tmrrc r2, r3, wr1`
84			`tmrrc r4, r5, wr2`
85
86			`test_h_gr r0, 0x12345678`
87			`test_h_gr r1, 0x9abcdef0`
88			`test_h_gr r2, 0x11111111`
89			`test_h_gr r3, 0x00000000`
90			`test_h_gr r4, 0x2b3c091a`
91			`test_h_gr r5, 0x6f784d5e`
92
93			`# Test Word wide rotate right by CG register`
94
95			`mvi_h_gr r0, 0x12345678`
96			`mvi_h_gr r1, 0x9abcdef0`
97			`mvi_h_gr r2, 0x11111111`
98			`mvi_h_gr r3, 0`
99			`mvi_h_gr r4, 0`
100
101			`tmcrr wr0, r0, r1`
102			`tmcr wcgr0, r2`
103			`tmcrr wr1, r2, r3`
104
105			`wrorwg wr1, wr0, wcgr0`
106
107			`tmrrc r0, r1, wr0`
108			`tmrc r2, wcgr0`
109			`tmrrc r3, r4, wr2`
110
111			`test_h_gr r0, 0x12345678`
112			`test_h_gr r1, 0x9abcdef0`
113			`test_h_gr r2, 0x11111111`
114			`test_h_gr r3, 0x2b3c091a`
115			`test_h_gr r4, 0x6f784d5e`
116
117			`# Test Double Word wide rotate right by register`
118
119			`mvi_h_gr r0, 0x12345678`
120			`mvi_h_gr r1, 0x9abcdef0`
121			`mvi_h_gr r2, 0x11111111`
122			`mvi_h_gr r3, 0x00000000`
123			`mvi_h_gr r4, 0`
124			`mvi_h_gr r5, 0`
125
126			`tmcrr wr0, r0, r1`
127			`tmcrr wr1, r2, r3`
128			`tmcrr wr2, r4, r5`
129
130			`wrord wr2, wr0, wr1`
131
132			`tmrrc r0, r1, wr0`
133			`tmrrc r2, r3, wr1`
134			`tmrrc r4, r5, wr2`
135
136			`test_h_gr r0, 0x12345678`
137			`test_h_gr r1, 0x9abcdef0`
138			`test_h_gr r2, 0x11111111`
139			`test_h_gr r3, 0x00000000`
140			`test_h_gr r4, 0x6f78091a`
141			`test_h_gr r5, 0x2b3c4d5e`
142
143			`# Test Double Word wide rotate right by CG register`
144
145			`mvi_h_gr r0, 0x12345678`
146			`mvi_h_gr r1, 0x9abcdef0`
147			`mvi_h_gr r2, 0x11111111`
148			`mvi_h_gr r3, 0`
149			`mvi_h_gr r4, 0`
150
151			`tmcrr wr0, r0, r1`
152			`tmcr wcgr0, r2`
153			`tmcrr wr1, r2, r3`
154
155			`wrordg wr1, wr0, wcgr0`
156
157			`tmrrc r0, r1, wr0`
158			`tmrc r2, wcgr0`
159			`tmrrc r3, r4, wr2`
160
161			`test_h_gr r0, 0x12345678`
162			`test_h_gr r1, 0x9abcdef0`
163			`test_h_gr r2, 0x11111111`
164			`test_h_gr r3, 0x6f78091a`
165			`test_h_gr r4, 0x2b3c4d5e`
166
167			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wror.cgs] - Blame information for rev 26