OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [testutils.inc] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 jlechner
# r0-r3 are used as tmps, consider them call clobbered by these macros.
2
# This uses the angel rom monitor calls.
3
# ??? How do we use the \@ facility of .macros ???
4
# @ is the comment char!
5
 
6
        .macro mvi_h_gr reg, val
7
        ldr \reg,[pc]
8
        b . + 8
9
        .word \val
10
        .endm
11
 
12
        .macro mvaddr_h_gr reg, addr
13
        ldr \reg,[pc]
14
        b . + 8
15
        .word \addr
16
        .endm
17
 
18
        .macro start
19
        .data
20
failmsg:
21
        .asciz "fail\n"
22
passmsg:
23
        .asciz "pass\n"
24
        .text
25
 
26
do_pass:
27
        ldr r1, passmsg_addr
28
        mov r0, #4
29
        swi #0x123456
30
        exit 0
31
passmsg_addr:
32
        .word passmsg
33
 
34
do_fail:
35
        ldr r1, failmsg_addr
36
        mov r0, #4
37
        swi #0x123456
38
        exit 1
39
failmsg_addr:
40
        .word failmsg
41
 
42
        .global _start
43
_start:
44
        .endm
45
 
46
# *** Other macros know pass/fail are 4 bytes in size!  Yuck.
47
 
48
        .macro pass
49
        b do_pass
50
        .endm
51
 
52
        .macro fail
53
        b do_fail
54
        .endm
55
 
56
        .macro exit rc
57
        # ??? This works with the ARMulator but maybe not others.
58
        #mov r0, #\rc
59
        #swi #1
60
        # This seems to be portable (though it ignores rc).
61
        mov r0,#0x18
62
        mvi_h_gr r1, 0x20026
63
        swi #0x123456
64
        # If that returns, punt with a sigill.
65
        stc 0,cr0,[r0]
66
        .endm
67
 
68
# Other macros know this only clobbers r0.
69
# WARNING: It also clobbers the condition codes (FIXME).
70
        .macro test_h_gr reg, val
71
        mvaddr_h_gr r0, \val
72
        cmp \reg, r0
73
        beq . + 8
74
        fail
75
        .endm
76
 
77
        .macro mvi_h_cnvz c, n, v, z
78
        mov r0, #0
79
        .if \c
80
        orr r0, r0, #0x20000000
81
        .endif
82
        .if \n
83
        orr r0, r0, #0x80000000
84
        .endif
85
        .if \v
86
        orr r0, r0, #0x10000000
87
        .endif
88
        .if \z
89
        orr r0, r0, #0x40000000
90
        .endif
91
        mrs r1, cpsr
92
        bic r1, r1, #0xf0000000
93
        orr r1, r1, r0
94
        msr cpsr, r1
95
        # ??? nops needed
96
        .endm
97
 
98
# ??? Preserve condition codes?
99
        .macro test_h_cnvz c, n, v, z
100
        mov r0, #0
101
        .if \c
102
        orr r0, r0, #0x20000000
103
        .endif
104
        .if \n
105
        orr r0, r0, #0x80000000
106
        .endif
107
        .if \v
108
        orr r0, r0, #0x10000000
109
        .endif
110
        .if \z
111
        orr r0, r0, #0x40000000
112
        .endif
113
        mrs r1, cpsr
114
        and r1, r1, #0xf0000000
115
        cmp r0, r1
116
        beq . + 8
117
        fail
118
        .endm

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.