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# frv testcase for bnclr $ICCi,$hint
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global bnclr
bnclr:
        set_spr_addr    ok1,lr
        set_icc         0x0 0
        bnclr           icc0,0
        fail
ok1:
        set_spr_addr    bad,lr
        set_icc         0x1 1
        bnclr           icc1,1
 
        set_spr_addr    ok3,lr
        set_icc         0x2 2
        bnclr           icc2,2
        fail
ok3:
        set_spr_addr    bad,lr
        set_icc         0x3 3
        bnclr           icc3,3
 
        set_spr_addr    ok5,lr
        set_icc         0x4 0
        bnclr           icc0,0
        fail
ok5:
        set_spr_addr    bad,lr
        set_icc         0x5 1
        bnclr           icc1,1
 
        set_spr_addr    ok7,lr
        set_icc         0x6 2
        bnclr           icc2,2
        fail
ok7:
        set_spr_addr    bad,lr
        set_icc         0x7 3
        bnclr           icc3,3
 
        set_spr_addr    ok9,lr
        set_icc         0x8 0
        bnclr           icc0,0
        fail
ok9:
        set_spr_addr    bad,lr
        set_icc         0x9 1
        bnclr           icc1,1
 
        set_spr_addr    okb,lr
        set_icc         0xa 2
        bnclr           icc2,2
        fail
okb:
        set_spr_addr    bad,lr
        set_icc         0xb 3
        bnclr           icc3,3
 
        set_spr_addr    okd,lr
        set_icc         0xc 0
        bnclr           icc0,0
        fail
okd:
        set_spr_addr    bad,lr
        set_icc         0xd 1
        bnclr           icc1,1
 
        set_spr_addr    okf,lr
        set_icc         0xe 2
        bnclr           icc2,2
        fail
okf:
        set_spr_addr    bad,lr
        set_icc         0xf 3
        bnclr           icc3,3
 
        pass
bad:
        fail

Line No.	Rev	Author	Line
1	26	jlechner	`# frv testcase for bnclr $ICCi,$hint`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global bnclr`
9			`bnclr:`
10			`set_spr_addr ok1,lr`
11			`set_icc 0x0 0`
12			`bnclr icc0,0`
13			`fail`
14			`ok1:`
15			`set_spr_addr bad,lr`
16			`set_icc 0x1 1`
17			`bnclr icc1,1`
18
19			`set_spr_addr ok3,lr`
20			`set_icc 0x2 2`
21			`bnclr icc2,2`
22			`fail`
23			`ok3:`
24			`set_spr_addr bad,lr`
25			`set_icc 0x3 3`
26			`bnclr icc3,3`
27
28			`set_spr_addr ok5,lr`
29			`set_icc 0x4 0`
30			`bnclr icc0,0`
31			`fail`
32			`ok5:`
33			`set_spr_addr bad,lr`
34			`set_icc 0x5 1`
35			`bnclr icc1,1`
36
37			`set_spr_addr ok7,lr`
38			`set_icc 0x6 2`
39			`bnclr icc2,2`
40			`fail`
41			`ok7:`
42			`set_spr_addr bad,lr`
43			`set_icc 0x7 3`
44			`bnclr icc3,3`
45
46			`set_spr_addr ok9,lr`
47			`set_icc 0x8 0`
48			`bnclr icc0,0`
49			`fail`
50			`ok9:`
51			`set_spr_addr bad,lr`
52			`set_icc 0x9 1`
53			`bnclr icc1,1`
54
55			`set_spr_addr okb,lr`
56			`set_icc 0xa 2`
57			`bnclr icc2,2`
58			`fail`
59			`okb:`
60			`set_spr_addr bad,lr`
61			`set_icc 0xb 3`
62			`bnclr icc3,3`
63
64			`set_spr_addr okd,lr`
65			`set_icc 0xc 0`
66			`bnclr icc0,0`
67			`fail`
68			`okd:`
69			`set_spr_addr bad,lr`
70			`set_icc 0xd 1`
71			`bnclr icc1,1`
72
73			`set_spr_addr okf,lr`
74			`set_icc 0xe 2`
75			`bnclr icc2,2`
76			`fail`
77			`okf:`
78			`set_spr_addr bad,lr`
79			`set_icc 0xf 3`
80			`bnclr icc3,3`
81
82			`pass`
83			`bad:`
84			`fail`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [bnclr.cgs] - Blame information for rev 26