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# FRV testcase for dci @(GRi,GRj)
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global dci
dci:
        or_spr_immed    0x08000000,hsr0 ; data cache: copy-back mode
 
        set_mem_immed   0xdeadbeef,sp
        test_mem_immed  0xdeadbeef,sp
 
        flush_data_cache sp
        set_mem_immed   0xbeefdead,sp
        test_mem_immed  0xbeefdead,sp
 
        dci             @(sp,gr0)
        test_mem_immed  0xdeadbeef,sp
 
        pass

Line No.	Rev	Author	Line
1	26	jlechner	`# FRV testcase for dci @(GRi,GRj)`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global dci`
9			`dci:`
10			`or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode`
11
12			`set_mem_immed 0xdeadbeef,sp`
13			`test_mem_immed 0xdeadbeef,sp`
14
15			`flush_data_cache sp`
16			`set_mem_immed 0xbeefdead,sp`
17			`test_mem_immed 0xbeefdead,sp`
18
19			`dci @(sp,gr0)`
20			`test_mem_immed 0xdeadbeef,sp`
21
22			`pass`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [dci.cgs] - Blame information for rev 26