URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [fmov.s] - Blame information for rev 26

Details | Compare with Previous | View Log


# sh testcase for all fmov instructions
# mach: sh
# as(sh):       -defsym sim_cpu=0
 
        .include "testutils.inc"
 
        .macro init
        fldi0   fr0
        fldi1   fr1
        fldi1   fr2
        fldi1   fr3
        .endm
 
        start
 
fmov1:  # Test fr -> fr.
        set_grs_a5a5
        set_fprs_a5a5
        init
        single_prec
        sz_32
        fmov    fr0, fr1
        # Ensure fr0 and fr1 are now equal.
        fcmp/eq fr0, fr1
        bt      fmov2
        fail
 
fmov2:  # Test dr -> dr.
        init
        double_prec
        sz_64
        fmov    dr0, dr2
        # Ensure dr0 and dr2 are now equal.
        fcmp/eq dr0, dr2
        bt      fmov3
        fail
 
fmov3:  # Test dr -> xd and xd -> dr.
        init
        sz_64
        fmov    dr0, xd0
        # Ensure dr0 and xd0 are now equal.
        fmov    xd0, dr2
        fcmp/eq dr0, dr2
        bt      fmov4
        fail
 
fmov4:  # Test xd -> xd.
        init
        sz_64
        double_prec
        fmov    dr0, xd0
        fmov    xd0, xd2
        fmov    xd2, dr2
        # Ensure dr0 and dr2 are now equal.
        fcmp/eq dr0, dr2
        bt      .L0
        fail
 
        # FIXME: test fmov.s fr -> @gr,      fmov dr -> @gr
        # FIXME: test fmov.s @gr -> fr,      fmov @gr -> dr
        # FIXME: test fmov.s @gr+ -> fr,     fmov @gr+ -> dr
        # FIXME: test fmov.s fr -> @-gr,     fmov dr -> @-gr
        # FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr
        # FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr)
 
.L0:
        test_grs_a5a5
        sz_32
        single_prec
        assert_fpreg_i  0, fr0
        assert_fpreg_i  1, fr1
        assert_fpreg_i  0, fr2
        assert_fpreg_i  1, fr3
        test_fpr_a5a5   fr4
        test_fpr_a5a5   fr5
        test_fpr_a5a5   fr6
        test_fpr_a5a5   fr7
        test_fpr_a5a5   fr8
        test_fpr_a5a5   fr9
        test_fpr_a5a5   fr10
        test_fpr_a5a5   fr11
        test_fpr_a5a5   fr12
        test_fpr_a5a5   fr13
        test_fpr_a5a5   fr14
        test_fpr_a5a5   fr15
 
fmov5:  # Test fr -> @rn and @rn -> fr.
        init
        sz_32
        single_prec
        # FIXME!  Use a reserved memory location!
        mov     #40, r0
        shll8   r0
        fmov    fr0, @r0
        fmov    @r0, fr1
        fcmp/eq fr0, fr1
        bt      fmov6
        fail
 
fmov6:  # Test dr -> @rn and @rn -> dr.
        init
        sz_64
        double_prec
        mov     #40, r0
        shll8   r0
        fmov    dr0, @r0
        fmov    @r0, dr2
        fcmp/eq dr0, dr2
        bt      fmov7
        fail
 
fmov7:  # Test xd -> @rn and @rn -> xd.
        init
        sz_64
        double_prec
        mov     #40, r0
        shll8   r0
        fmov    dr0, xd0
        fmov    xd0, @r0
        fmov    @r0, xd2
        fmov    xd2, dr2
        fcmp/eq dr0, dr2
        bt      fmov8
        fail
 
fmov8:  # Test fr -> @-rn.
        init
        sz_32
        single_prec
        mov     #40, r0
        shll8   r0
        # Preserve.
        mov     r0, r1
        fmov    fr0, @-r0
        fmov    @r0, fr2
        fcmp/eq fr0, fr2
        bt      f8b
        fail
f8b:    # check pre-dec.
        add     #4, r0
        cmp/eq  r0, r1
        bt      fmov9
        fail
 
fmov9:  # Test dr -> @-rn.
        init
        sz_64
        double_prec
        mov     #40, r0
        shll8   r0
        # Preserve r0.
        mov     r0, r1
        fmov    dr0, @-r0
        fmov    @r0, dr2
        fcmp/eq dr0, dr2
        bt      f9b
        fail
f9b:    # check pre-dec.
        add     #8, r0
        cmp/eq  r0, r1
        bt      fmov10
        fail
 
fmov10: # Test xd -> @-rn.
        init
        sz_64
        double_prec
        mov     #40, r0
        shll8   r0
        # Preserve r0.
        mov     r0, r1
        fmov    dr0, xd0
        fmov    xd0, @-r0
        fmov    @r0, xd2
        fmov    xd2, dr2
        fcmp/eq dr0, dr2
        bt      f10b
        fail
f10b:   # check pre-dec.
        add     #8, r0
        cmp/eq  r0, r1
        bt      fmov11
        fail
 
fmov11: # Test @rn+ -> fr.
        init
        sz_32
        single_prec
        mov     #40, r0
        shll8   r0
        # Preserve r0.
        mov     r0, r1
        fmov    fr0, @r0
        fmov    @r0+, fr2
        fcmp/eq fr0, fr2
        bt      f11b
        fail
f11b:   # check post-inc.
        add     #4, r1
        cmp/eq  r0, r1
        bt      fmov12
        fail
 
fmov12: # Test @rn+ -> dr.
        init
        sz_64
        double_prec
        mov     #40, r0
        shll8   r0
        # preserve r0.
        mov     r0, r1
        fmov    dr0, @r0
        fmov    @r0+, dr2
        fcmp/eq dr0, dr2
        bt      f12b
        fail
f12b:   # check post-inc.
        add     #8, r1
        cmp/eq  r0, r1
        bt      fmov13
        fail
 
fmov13: # Test @rn -> xd.
        init
        sz_64
        double_prec
        mov     #40, r0
        shll8   r0
        # Preserve r0.
        mov     r0, r1
        fmov    dr0, xd0
        fmov    xd0, @r0
        fmov    @r0+, xd2
        fmov    xd2, dr2
        fcmp/eq dr0, dr2
        bt      f13b
        fail
f13b:
        add     #8, r1
        cmp/eq  r0, r1
        bt      fmov14
        fail
 
fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr.
        init
        sz_32
        single_prec
        mov     #40, r0
        shll8   r0
        mov     #0, r1
        fmov    fr0, @(r0, r1)
        fmov    @(r0, r1), fr1
        fcmp/eq fr0, fr1
        bt      fmov15
        fail
 
fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr.
        init
        sz_64
        double_prec
        mov     #40, r0
        shll8   r0
        mov     #0, r1
        fmov    dr0, @(r0, r1)
        fmov    @(r0, r1), dr2
        fcmp/eq dr0, dr2
        bt      fmov16
        fail
 
fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd.
        init
        sz_64
        double_prec
        mov     #40, r0
        shll8   r0
        mov     #0, r1
        fmov    dr0, xd0
        fmov    xd0, @(r0, r1)
        fmov    @(r0, r1), xd2
        fmov    xd2, dr2
        fcmp/eq dr0, dr2
        bt      .L1
        fail
.L1:
        assertreg0      0x2800
        assertreg       0, r1
        test_gr_a5a5    r2
        test_gr_a5a5    r3
        test_gr_a5a5    r4
        test_gr_a5a5    r5
        test_gr_a5a5    r6
        test_gr_a5a5    r7
        test_gr_a5a5    r8
        test_gr_a5a5    r9
        test_gr_a5a5    r10
        test_gr_a5a5    r11
        test_gr_a5a5    r12
        test_gr_a5a5    r13
        test_gr_a5a5    r14
 
        sz_32
        single_prec
        assert_fpreg_i  0, fr0
        assert_fpreg_i  1, fr1
        assert_fpreg_i  0, fr2
        assert_fpreg_i  1, fr3
        test_fpr_a5a5   fr4
        test_fpr_a5a5   fr5
        test_fpr_a5a5   fr6
        test_fpr_a5a5   fr7
        test_fpr_a5a5   fr8
        test_fpr_a5a5   fr9
        test_fpr_a5a5   fr10
        test_fpr_a5a5   fr11
        test_fpr_a5a5   fr12
        test_fpr_a5a5   fr13
        test_fpr_a5a5   fr14
        test_fpr_a5a5   fr15
 
        pass
        exit 0

Browse

Tools

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [fmov.s] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jlechner	`# sh testcase for all fmov instructions`
2			`# mach: sh`
3			`# as(sh): -defsym sim_cpu=0`
4
5			`.include "testutils.inc"`
6
7			`.macro init`
8			`fldi0 fr0`
9			`fldi1 fr1`
10			`fldi1 fr2`
11			`fldi1 fr3`
12			`.endm`
13
14			`start`
15
16			`fmov1: # Test fr -> fr.`
17			`set_grs_a5a5`
18			`set_fprs_a5a5`
19			`init`
20			`single_prec`
21			`sz_32`
22			`fmov fr0, fr1`
23			`# Ensure fr0 and fr1 are now equal.`
24			`fcmp/eq fr0, fr1`
25			`bt fmov2`
26			`fail`
27
28			`fmov2: # Test dr -> dr.`
29			`init`
30			`double_prec`
31			`sz_64`
32			`fmov dr0, dr2`
33			`# Ensure dr0 and dr2 are now equal.`
34			`fcmp/eq dr0, dr2`
35			`bt fmov3`
36			`fail`
37
38			`fmov3: # Test dr -> xd and xd -> dr.`
39			`init`
40			`sz_64`
41			`fmov dr0, xd0`
42			`# Ensure dr0 and xd0 are now equal.`
43			`fmov xd0, dr2`
44			`fcmp/eq dr0, dr2`
45			`bt fmov4`
46			`fail`
47
48			`fmov4: # Test xd -> xd.`
49			`init`
50			`sz_64`
51			`double_prec`
52			`fmov dr0, xd0`
53			`fmov xd0, xd2`
54			`fmov xd2, dr2`
55			`# Ensure dr0 and dr2 are now equal.`
56			`fcmp/eq dr0, dr2`
57			`bt .L0`
58			`fail`
59
60			`# FIXME: test fmov.s fr -> @gr, fmov dr -> @gr`
61			`# FIXME: test fmov.s @gr -> fr, fmov @gr -> dr`
62			`# FIXME: test fmov.s @gr+ -> fr, fmov @gr+ -> dr`
63			`# FIXME: test fmov.s fr -> @-gr, fmov dr -> @-gr`
64			`# FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr`
65			`# FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr)`
66
67			`.L0:`
68			`test_grs_a5a5`
69			`sz_32`
70			`single_prec`
71			`assert_fpreg_i 0, fr0`
72			`assert_fpreg_i 1, fr1`
73			`assert_fpreg_i 0, fr2`
74			`assert_fpreg_i 1, fr3`
75			`test_fpr_a5a5 fr4`
76			`test_fpr_a5a5 fr5`
77			`test_fpr_a5a5 fr6`
78			`test_fpr_a5a5 fr7`
79			`test_fpr_a5a5 fr8`
80			`test_fpr_a5a5 fr9`
81			`test_fpr_a5a5 fr10`
82			`test_fpr_a5a5 fr11`
83			`test_fpr_a5a5 fr12`
84			`test_fpr_a5a5 fr13`
85			`test_fpr_a5a5 fr14`
86			`test_fpr_a5a5 fr15`
87
88			`fmov5: # Test fr -> @rn and @rn -> fr.`
89			`init`
90			`sz_32`
91			`single_prec`
92			`# FIXME! Use a reserved memory location!`
93			`mov #40, r0`
94			`shll8 r0`
95			`fmov fr0, @r0`
96			`fmov @r0, fr1`
97			`fcmp/eq fr0, fr1`
98			`bt fmov6`
99			`fail`
100
101			`fmov6: # Test dr -> @rn and @rn -> dr.`
102			`init`
103			`sz_64`
104			`double_prec`
105			`mov #40, r0`
106			`shll8 r0`
107			`fmov dr0, @r0`
108			`fmov @r0, dr2`
109			`fcmp/eq dr0, dr2`
110			`bt fmov7`
111			`fail`
112
113			`fmov7: # Test xd -> @rn and @rn -> xd.`
114			`init`
115			`sz_64`
116			`double_prec`
117			`mov #40, r0`
118			`shll8 r0`
119			`fmov dr0, xd0`
120			`fmov xd0, @r0`
121			`fmov @r0, xd2`
122			`fmov xd2, dr2`
123			`fcmp/eq dr0, dr2`
124			`bt fmov8`
125			`fail`
126
127			`fmov8: # Test fr -> @-rn.`
128			`init`
129			`sz_32`
130			`single_prec`
131			`mov #40, r0`
132			`shll8 r0`
133			`# Preserve.`
134			`mov r0, r1`
135			`fmov fr0, @-r0`
136			`fmov @r0, fr2`
137			`fcmp/eq fr0, fr2`
138			`bt f8b`
139			`fail`
140			`f8b: # check pre-dec.`
141			`add #4, r0`
142			`cmp/eq r0, r1`
143			`bt fmov9`
144			`fail`
145
146			`fmov9: # Test dr -> @-rn.`
147			`init`
148			`sz_64`
149			`double_prec`
150			`mov #40, r0`
151			`shll8 r0`
152			`# Preserve r0.`
153			`mov r0, r1`
154			`fmov dr0, @-r0`
155			`fmov @r0, dr2`
156			`fcmp/eq dr0, dr2`
157			`bt f9b`
158			`fail`
159			`f9b: # check pre-dec.`
160			`add #8, r0`
161			`cmp/eq r0, r1`
162			`bt fmov10`
163			`fail`
164
165			`fmov10: # Test xd -> @-rn.`
166			`init`
167			`sz_64`
168			`double_prec`
169			`mov #40, r0`
170			`shll8 r0`
171			`# Preserve r0.`
172			`mov r0, r1`
173			`fmov dr0, xd0`
174			`fmov xd0, @-r0`
175			`fmov @r0, xd2`
176			`fmov xd2, dr2`
177			`fcmp/eq dr0, dr2`
178			`bt f10b`
179			`fail`
180			`f10b: # check pre-dec.`
181			`add #8, r0`
182			`cmp/eq r0, r1`
183			`bt fmov11`
184			`fail`
185
186			`fmov11: # Test @rn+ -> fr.`
187			`init`
188			`sz_32`
189			`single_prec`
190			`mov #40, r0`
191			`shll8 r0`
192			`# Preserve r0.`
193			`mov r0, r1`
194			`fmov fr0, @r0`
195			`fmov @r0+, fr2`
196			`fcmp/eq fr0, fr2`
197			`bt f11b`
198			`fail`
199			`f11b: # check post-inc.`
200			`add #4, r1`
201			`cmp/eq r0, r1`
202			`bt fmov12`
203			`fail`
204
205			`fmov12: # Test @rn+ -> dr.`
206			`init`
207			`sz_64`
208			`double_prec`
209			`mov #40, r0`
210			`shll8 r0`
211			`# preserve r0.`
212			`mov r0, r1`
213			`fmov dr0, @r0`
214			`fmov @r0+, dr2`
215			`fcmp/eq dr0, dr2`
216			`bt f12b`
217			`fail`
218			`f12b: # check post-inc.`
219			`add #8, r1`
220			`cmp/eq r0, r1`
221			`bt fmov13`
222			`fail`
223
224			`fmov13: # Test @rn -> xd.`
225			`init`
226			`sz_64`
227			`double_prec`
228			`mov #40, r0`
229			`shll8 r0`
230			`# Preserve r0.`
231			`mov r0, r1`
232			`fmov dr0, xd0`
233			`fmov xd0, @r0`
234			`fmov @r0+, xd2`
235			`fmov xd2, dr2`
236			`fcmp/eq dr0, dr2`
237			`bt f13b`
238			`fail`
239			`f13b:`
240			`add #8, r1`
241			`cmp/eq r0, r1`
242			`bt fmov14`
243			`fail`
244
245			`fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr.`
246			`init`
247			`sz_32`
248			`single_prec`
249			`mov #40, r0`
250			`shll8 r0`
251			`mov #0, r1`
252			`fmov fr0, @(r0, r1)`
253			`fmov @(r0, r1), fr1`
254			`fcmp/eq fr0, fr1`
255			`bt fmov15`
256			`fail`
257
258			`fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr.`
259			`init`
260			`sz_64`
261			`double_prec`
262			`mov #40, r0`
263			`shll8 r0`
264			`mov #0, r1`
265			`fmov dr0, @(r0, r1)`
266			`fmov @(r0, r1), dr2`
267			`fcmp/eq dr0, dr2`
268			`bt fmov16`
269			`fail`
270
271			`fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd.`
272			`init`
273			`sz_64`
274			`double_prec`
275			`mov #40, r0`
276			`shll8 r0`
277			`mov #0, r1`
278			`fmov dr0, xd0`
279			`fmov xd0, @(r0, r1)`
280			`fmov @(r0, r1), xd2`
281			`fmov xd2, dr2`
282			`fcmp/eq dr0, dr2`
283			`bt .L1`
284			`fail`
285			`.L1:`
286			`assertreg0 0x2800`
287			`assertreg 0, r1`
288			`test_gr_a5a5 r2`
289			`test_gr_a5a5 r3`
290			`test_gr_a5a5 r4`
291			`test_gr_a5a5 r5`
292			`test_gr_a5a5 r6`
293			`test_gr_a5a5 r7`
294			`test_gr_a5a5 r8`
295			`test_gr_a5a5 r9`
296			`test_gr_a5a5 r10`
297			`test_gr_a5a5 r11`
298			`test_gr_a5a5 r12`
299			`test_gr_a5a5 r13`
300			`test_gr_a5a5 r14`
301
302			`sz_32`
303			`single_prec`
304			`assert_fpreg_i 0, fr0`
305			`assert_fpreg_i 1, fr1`
306			`assert_fpreg_i 0, fr2`
307			`assert_fpreg_i 1, fr3`
308			`test_fpr_a5a5 fr4`
309			`test_fpr_a5a5 fr5`
310			`test_fpr_a5a5 fr6`
311			`test_fpr_a5a5 fr7`
312			`test_fpr_a5a5 fr8`
313			`test_fpr_a5a5 fr9`
314			`test_fpr_a5a5 fr10`
315			`test_fpr_a5a5 fr11`
316			`test_fpr_a5a5 fr12`
317			`test_fpr_a5a5 fr13`
318			`test_fpr_a5a5 fr14`
319			`test_fpr_a5a5 fr15`
320
321			`pass`
322			`exit 0`