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# sh testcase for shll8
# mach: all
# as(sh):       -defsym sim_cpu=0
# as(shdsp):    -defsym sim_cpu=1 -dsp
 
        .include "testutils.inc"
 
        start
 
shll8:
        set_grs_a5a5
        mov #1, r1
        shll8 r1
        assertreg 0x100, r1
        shll8 r1
        assertreg 0x10000, r1
        shll8 r1
        assertreg 0x1000000, r1
        shll8 r1
        assertreg 0, r1
 
        # another:
        mov #1, r1
        shll8 r1
        mov #1, r2
        shll r2
        shll r2
        shll r2
        shll r2
        shll r2
        shll r2
        shll r2
        shll r2
        cmp/eq r1, r2
        bt   okay
        fail
okay:
        set_greg 0xa5a5a5a5, r1
        set_greg 0xa5a5a5a5, r2
        test_grs_a5a5
        pass
        exit 0

Line No.	Rev	Author	Line
1	26	jlechner	`# sh testcase for shll8`
2			`# mach: all`
3			`# as(sh): -defsym sim_cpu=0`
4			`# as(shdsp): -defsym sim_cpu=1 -dsp`
5
6			`.include "testutils.inc"`
7
8			`start`
9
10			`shll8:`
11			`set_grs_a5a5`
12			`mov #1, r1`
13			`shll8 r1`
14			`assertreg 0x100, r1`
15			`shll8 r1`
16			`assertreg 0x10000, r1`
17			`shll8 r1`
18			`assertreg 0x1000000, r1`
19			`shll8 r1`
20			`assertreg 0, r1`
21
22			`# another:`
23			`mov #1, r1`
24			`shll8 r1`
25			`mov #1, r2`
26			`shll r2`
27			`shll r2`
28			`shll r2`
29			`shll r2`
30			`shll r2`
31			`shll r2`
32			`shll r2`
33			`shll r2`
34			`cmp/eq r1, r2`
35			`bt okay`
36			`fail`
37			`okay:`
38			`set_greg 0xa5a5a5a5, r1`
39			`set_greg 0xa5a5a5a5, r2`
40			`test_grs_a5a5`
41			`pass`
42			`exit 0`

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[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [shll8.s] - Blame information for rev 26