OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [toolchain/] [scarts-gdb/] [sim-plugins/] [watchpoint/] [watchpoint.c] - Blame information for rev 27

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 jlechner
/* SCARTS watchpoint extension module code for the GNU simulator.
2
   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3
   Free Software Foundation, Inc.
4
   Contributed by Martin Walter <mwalter@opencores.org>
5
 
6
   This file is part of the GNU simulators.
7
 
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
 
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
#include <string.h>
21
#include "watchpoint.h"
22
 
23
/* Macros for machine type. */
24
#if defined __SCARTS_16__
25
  #define SCARTS_ADDR_CTYPE  uint16_t
26
#elif defined __SCARTS_32__
27
  #define SCARTS_ADDR_CTYPE  uint32_t
28
#else
29
  #error "Unsupported target machine type"
30
#endif
31
 
32
/* Macros for bit manipulations. */
33
#define read_bit(regfile, bitpos) (((regfile) >> (bitpos)) & 1)
34
#define write_bit(regfile, bitpos, value) (void)((value) ? ((regfile) |= (1 << (bitpos))) : ((regfile) &= ~(1 << (bitpos))))
35
 
36
static watchpoint_mem_t mem;
37
 
38
uint8_t*
39
get_mem (void)
40
{
41
  return mem.raw;
42
}
43
 
44
void
45
get_mem_map (SCARTS_ADDR_CTYPE* start, SCARTS_ADDR_CTYPE* size)
46
{
47
  *start = WATCHPOINT_BADDR;
48
  *size  = WATCHPOINT_SIZE;
49
}
50
 
51
uint8_t*
52
get_status (void)
53
{
54
  return &mem.regfile.STATUS;
55
}
56
 
57
int
58
mem_read (SCARTS_ADDR_CTYPE offset, uint8_t *value)
59
{
60
  if (offset >= WATCHPOINT_SIZE)
61
    return 0;
62
 
63
  *value = mem.raw[offset];
64
  return 1;
65
}
66
 
67
int
68
mem_write (SCARTS_ADDR_CTYPE offset, uint8_t value)
69
{
70
  if (offset >= WATCHPOINT_SIZE)
71
    return 0;
72
 
73
  mem.raw[offset] = value;
74
  return 1;
75
}
76
 
77
void
78
reset (void)
79
{
80
  memset (mem.raw, 0, WATCHPOINT_SIZE);
81
}
82
 
83
void
84
tick (SCARTS_ADDR_CTYPE pc)
85
{
86
  return;
87
}
88
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.