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[/] [scsi_chip/] [web_uploads/] [SRAM_controler.v] - Blame information for rev 6

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:28:22 08/05/2008 
// Design Name: 
// Module Name:    SRAM_controler 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
//Defines
`define WR_COUNT 1 //Number of write cycles needed
`define RD_COUNT 4 //Number of read cycles needed
`define CNT_BITS 2 //number of bits needed for the counter to count the cycles
`define DEL 1
 
module SRAM_controler(CLK, reset_n, as_n, rw, out_en, write_en, ack);
//INPUTS
    input CLK; //state machine clock
    input reset_n;//Synchronous reset
    input as_n;//address strobe
    input rw;//read/write command
 
//OUTPUTS
    output out_en;//output enable to memory
    output write_en;//write enable to memory
    output ack;//Acknowledge signal to processor
 
//SIGNAL DECLARATIONS
wire CLK;
wire reset_n;
wire as_n;
wire rw;
wire out_en;
wire write_en;
wire ack;
reg [1:0] state; //State machine
reg [`CNT_BITS-1:0] cnt;//cycle counter
//PARAMETERS
parameter[1:0] //state machine states
        IDLE = 0,
        WRITE = 1,
        READ = 2;
//ASSIGN STATEMENTS
                                        //creates the outputs from the states
assign out_en = state[1]; // output enable = LSB of state
assign write_en= state[0];//write enable = HSB of state
                                        //create the acknowledge combinatorially
assign #1 ack = ~as_n && ((~rw && (cnt == `WR_COUNT-1)) || (rw && (cnt == `RD_COUNT-1)));
 
//look at the rising edge of clock for state transitions 
always @(negedge CLK or negedge reset_n) begin
        if(~reset_n) begin
                state <= #1 IDLE;
                cnt <= #1 `CNT_BITS'h0;
        end
        else begin
                case (state)
                        IDLE: begin
                        //Look for address strobe to begin the access
                        if(~as_n)begin
                                if(rw) begin
                                        //This is a read access
                                        state <= #1 READ;
                                end
                                else begin
                                        //This is a write access
                                        state <= #1 WRITE;
                                end
                        end
                end
                        WRITE:begin
                        if ((cnt == `WR_COUNT-1) || as_n) begin
                        state <= #1 IDLE;
                        cnt <= #1 `CNT_BITS'h0;
                        end
                        else
                        cnt <= #1 cnt + 1;
                end
                   READ:begin
                        if((cnt == `RD_COUNT-1) || as_n) begin
                         state <= #1 IDLE;
                         cnt <= #`DEL `CNT_BITS'h0;
                        end
                        else
                         cnt <= #`DEL cnt +1;
                        end
        endcase
 end
end
endmodule

Line No.	Rev	Author	Line
1	6	root	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 13:28:22 08/05/2008`
7			`// Design Name:`
8			`// Module Name: SRAM_controler`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`//Defines`
22			`define WR_COUNT 1 //Number of write cycles needed
23			`define RD_COUNT 4 //Number of read cycles needed
24			`define CNT_BITS 2 //number of bits needed for the counter to count the cycles
25			`define DEL 1
26
27			`module SRAM_controler(CLK, reset_n, as_n, rw, out_en, write_en, ack);`
28			`//INPUTS`
29			`input CLK; //state machine clock`
30			`input reset_n;//Synchronous reset`
31			`input as_n;//address strobe`
32			`input rw;//read/write command`
33
34			`//OUTPUTS`
35			`output out_en;//output enable to memory`
36			`output write_en;//write enable to memory`
37			`output ack;//Acknowledge signal to processor`
38
39			`//SIGNAL DECLARATIONS`
40			`wire CLK;`
41			`wire reset_n;`
42			`wire as_n;`
43			`wire rw;`
44			`wire out_en;`
45			`wire write_en;`
46			`wire ack;`
47			`reg [1:0] state; //State machine`
48			reg [`CNT_BITS-1:0] cnt;//cycle counter
49			`//PARAMETERS`
50			`parameter[1:0] //state machine states`
51			`IDLE = 0,`
52			`WRITE = 1,`
53			`READ = 2;`
54			`//ASSIGN STATEMENTS`
55			`//creates the outputs from the states`
56			`assign out_en = state[1]; // output enable = LSB of state`
57			`assign write_en= state[0];//write enable = HSB of state`
58			`//create the acknowledge combinatorially`
59			assign #1 ack = ~as_n && ((~rw && (cnt == `WR_COUNT-1)) \|\| (rw && (cnt == `RD_COUNT-1)));
60
61			`//look at the rising edge of clock for state transitions`
62			`always @(negedge CLK or negedge reset_n) begin`
63			`if(~reset_n) begin`
64			`state <= #1 IDLE;`
65			cnt <= #1 `CNT_BITS'h0;
66			`end`
67			`else begin`
68			`case (state)`
69			`IDLE: begin`
70			`//Look for address strobe to begin the access`
71			`if(~as_n)begin`
72			`if(rw) begin`
73			`//This is a read access`
74			`state <= #1 READ;`
75			`end`
76			`else begin`
77			`//This is a write access`
78			`state <= #1 WRITE;`
79			`end`
80			`end`
81			`end`
82			`WRITE:begin`
83			if ((cnt == `WR_COUNT-1) \|\| as_n) begin
84			`state <= #1 IDLE;`
85			cnt <= #1 `CNT_BITS'h0;
86			`end`
87			`else`
88			`cnt <= #1 cnt + 1;`
89			`end`
90			`READ:begin`
91			if((cnt == `RD_COUNT-1) \|\| as_n) begin
92			`state <= #1 IDLE;`
93			cnt <= #`DEL `CNT_BITS'h0;
94			`end`
95			`else`
96			cnt <= #`DEL cnt +1;
97			`end`
98			`endcase`
99			`end`
100			`end`
101			`endmodule`

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[/] [scsi_chip/] [web_uploads/] [SRAM_controler.v] - Blame information for rev 6