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[/] [scsi_chip/] [web_uploads/] [registers_complex.v] - Blame information for rev 6

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:14:48 08/19/2008 
// Design Name: 
// Module Name:    Registers_file 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`define DATA_WIDTH 8
`define DATA_DEPTH 32
`define DEL 1
module Registers_file(D, WE_N, RE_N, ALE, A0, ADD_ext, EXT, CLK);
//INOUTS
    inout [`DATA_WIDTH-1:0] D;//Data bus
//INPUT
         input [`DATA_WIDTH-1:0]ADD_ext;//external address for acces the registers
         input WE_N;//write enable
         input RE_N;//read enable
         input A0;//used to access the internal register 
         input ALE;//with the trailing edge of ALE the addres in the local data bus is latched in to the addres register
         input EXT;
         input CLK;
//SIGNAL DECLARATIONS
         wire [`DATA_WIDTH-1:0]ADD_ext;
         reg [`DATA_WIDTH-1:0]ADD_int;
         wire [`DATA_WIDTH-1:0] D;
         wire [`DATA_WIDTH-1:0] ADD;
         wire [`DATA_WIDTH-1:0] D_IN;
         wire A0;
         wire ALE;
         wire EXT;
         reg [`DATA_WIDTH-1:0] D_OUT;
         reg [`DATA_WIDTH-1:0] registers [`DATA_DEPTH-1:0];
//ASSIGMENT STATEMENTS
         assign #`DEL D = RE_N ? D_IN : D_OUT;
         assign #`DEL ADD = EXT ? ADD_ext : ADD_int;
//MAIN CODE
always @(posedge ALE) begin
                registers[`DATA_WIDTH'h1A] <= #`DEL D_IN;
                end
always @(negedge CLK) begin
        if(EXT == 0) begin
                if(A0 == 0)begin
                        if(!WE_N && RE_N)begin
                                ADD_int <= #`DEL `DATA_WIDTH'h1A;
                                end
                        if((WE_N === 1'b1) && (RE_N === 1'b0) )begin
                                ADD_int  <= #`DEL `DATA_WIDTH'h1F;
                                end
                end
                else if(A0 == 1)begin
                        ADD_int <= #`DEL registers[`DATA_WIDTH'h1A];
                        if(~WE_N)begin
                                registers[ADD] <= D_IN;
                        end
                        if(~RE_N)begin
                                D_OUT <= registers[ADD];
                        end
                end
        end
        else if(EXT == 1)begin
                if(~WE_N)begin
                                registers[ADD] <= D_IN;
                        end
                if(~RE_N)begin
                                D_OUT <= registers[ADD];
                        end
        end
        end
always @(ADD)begin
        if((ADD == `DATA_WIDTH'h18)|| (ADD == `DATA_WIDTH'h19)||(ADD == `DATA_WIDTH'h1A)||(ADD == `DATA_WIDTH'h1F))begin
                registers[`DATA_WIDTH'h1A] <= registers[`DATA_WIDTH'h1A];
                end
        else begin
                registers[`DATA_WIDTH'h1A] <= registers[`DATA_WIDTH'h1A]+1;
                end
        end
endmodule
 

Line No.	Rev	Author	Line
1	6	root	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 10:14:48 08/19/2008`
7			`// Design Name:`
8			`// Module Name: Registers_file`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`define DATA_WIDTH 8
22			`define DATA_DEPTH 32
23			`define DEL 1
24			`module Registers_file(D, WE_N, RE_N, ALE, A0, ADD_ext, EXT, CLK);`
25			`//INOUTS`
26			inout [`DATA_WIDTH-1:0] D;//Data bus
27			`//INPUT`
28			input [`DATA_WIDTH-1:0]ADD_ext;//external address for acces the registers
29			`input WE_N;//write enable`
30			`input RE_N;//read enable`
31			`input A0;//used to access the internal register`
32			`input ALE;//with the trailing edge of ALE the addres in the local data bus is latched in to the addres register`
33			`input EXT;`
34			`input CLK;`
35			`//SIGNAL DECLARATIONS`
36			wire [`DATA_WIDTH-1:0]ADD_ext;
37			reg [`DATA_WIDTH-1:0]ADD_int;
38			wire [`DATA_WIDTH-1:0] D;
39			wire [`DATA_WIDTH-1:0] ADD;
40			wire [`DATA_WIDTH-1:0] D_IN;
41			`wire A0;`
42			`wire ALE;`
43			`wire EXT;`
44			reg [`DATA_WIDTH-1:0] D_OUT;
45			reg [`DATA_WIDTH-1:0] registers [`DATA_DEPTH-1:0];
46			`//ASSIGMENT STATEMENTS`
47			assign #`DEL D = RE_N ? D_IN : D_OUT;
48			assign #`DEL ADD = EXT ? ADD_ext : ADD_int;
49			`//MAIN CODE`
50			`always @(posedge ALE) begin`
51			registers[`DATA_WIDTH'h1A] <= #`DEL D_IN;
52			`end`
53			`always @(negedge CLK) begin`
54			`if(EXT == 0) begin`
55			`if(A0 == 0)begin`
56			`if(!WE_N && RE_N)begin`
57			ADD_int <= #`DEL `DATA_WIDTH'h1A;
58			`end`
59			`if((WE_N === 1'b1) && (RE_N === 1'b0) )begin`
60			ADD_int <= #`DEL `DATA_WIDTH'h1F;
61			`end`
62			`end`
63			`else if(A0 == 1)begin`
64			ADD_int <= #`DEL registers[`DATA_WIDTH'h1A];
65			`if(~WE_N)begin`
66			`registers[ADD] <= D_IN;`
67			`end`
68			`if(~RE_N)begin`
69			`D_OUT <= registers[ADD];`
70			`end`
71			`end`
72			`end`
73			`else if(EXT == 1)begin`
74			`if(~WE_N)begin`
75			`registers[ADD] <= D_IN;`
76			`end`
77			`if(~RE_N)begin`
78			`D_OUT <= registers[ADD];`
79			`end`
80			`end`
81			`end`
82			`always @(ADD)begin`
83			if((ADD == `DATA_WIDTH'h18)\|\| (ADD == `DATA_WIDTH'h19)\|\|(ADD == `DATA_WIDTH'h1A)\|\|(ADD == `DATA_WIDTH'h1F))begin
84			registers[`DATA_WIDTH'h1A] <= registers[`DATA_WIDTH'h1A];
85			`end`
86			`else begin`
87			registers[`DATA_WIDTH'h1A] <= registers[`DATA_WIDTH'h1A]+1;
88			`end`
89			`end`
90			`endmodule`
91

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[/] [scsi_chip/] [web_uploads/] [registers_complex.v] - Blame information for rev 6