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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%                                                              %%%%
%%%% WISHBONE SD Card Controller IP Core                          %%%%
%%%%                                                              %%%%
%%%% sw_if.tex                                                    %%%%
%%%%                                                              %%%%
%%%% This file is part of the WISHBONE SD Card                    %%%%
%%%% Controller IP Core project                                   %%%%
%%%% http://opencores.org/project,sd_card_controller              %%%%
%%%%                                                              %%%%
%%%% Description                                                  %%%%
%%%% documentation 'Software interface' chapter                   %%%%
%%%%                                                              %%%%
%%%% Author(s):                                                   %%%%
%%%%     - Marek Czerski, ma.czerski@gmail.com                    %%%%
%%%%                                                              %%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%                                                              %%%%
%%%% Copyright (C) 2013 Authors                                   %%%%
%%%%                                                              %%%%
%%%% This source file may be used and distributed without         %%%%
%%%% restriction provided that this copyright statement is not    %%%%
%%%% removed from the file and that any derivative work contains  %%%%
%%%% the original copyright notice and the associated disclaimer. %%%%
%%%%                                                              %%%%
%%%% This source file is free software; you can redistribute it   %%%%
%%%% and/or modify it under the terms of the GNU Lesser General   %%%%
%%%% Public License as published by the Free Software Foundation; %%%%
%%%% either version 2.1 of the License, or (at your option) any   %%%%
%%%% later version.                                               %%%%
%%%%                                                              %%%%
%%%% This source is distributed in the hope that it will be       %%%%
%%%% useful, but WITHOUT ANY WARRANTY; without even the implied   %%%%
%%%% warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      %%%%
%%%% PURPOSE. See the GNU Lesser General Public License for more  %%%%
%%%% details.                                                     %%%%
%%%%                                                              %%%%
%%%% You should have received a copy of the GNU Lesser General    %%%%
%%%% Public License along with this source; if not, download it   %%%%
%%%% from http://www.opencores.org/lgpl.shtml                     %%%%
%%%%                                                              %%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{Software interface}
\label{sec:sw_if}
 
    Access to IP core registers is provided through a Wishbone slave interface.
 
    \subsection{IP Core registers}
    \label{sec:regs}
 
    \begin{table}[H]
    \caption{List of registers}
        \begin{tabular}{l|l|l|l}
                \rowcolor[gray]{0.7} name & address & access & description \\ \hline \hline
                \texttt{argument} & \texttt{0x00} & RW & command argument \\ \hline
                \texttt{command} & \texttt{0x04} & RW & command transaction configuration \\ \hline
                \texttt{response0} & \texttt{0x08} & R & bits 31-0 of the response \\ \hline
                \texttt{response1} & \texttt{0x0C} & R & bits 63-32 of the response \\ \hline
                \texttt{response2} & \texttt{0x10} & R & bits 95-64 of the response \\ \hline
                \texttt{response3} & \texttt{0x14} & R & bits 119-96 of the response \\ \hline
                \texttt{control} & \texttt{0x1C} & RW & IP core control settings \\ \hline
                \texttt{timeout} & \texttt{0x20} & RW & timeout configuration \\ \hline
                \texttt{clock\_divider} & \texttt{0x24} & RW & MMC/SD interface clock divider \\ \hline
                \texttt{reset} & \texttt{0x28} & RW & software reset \\ \hline
                \texttt{voltage} & \texttt{0x2C} & R & power control information \\ \hline
                \texttt{capabilities} & \texttt{0x30} & R & capabilities information \\ \hline
                \texttt{cmd\_event\_status} & \texttt{0x34} & RW & command transaction events status / clear \\ \hline
                \texttt{cmd\_event\_enable} & \texttt{0x38} & RW & command transaction events enable \\ \hline
                \texttt{data\_event\_status} & \texttt{0x3C} & RW & data transaction events status / clear \\ \hline
                \texttt{data\_event\_enable} & \texttt{0x38} & RW & data transaction events enable \\ \hline
                \texttt{blkock\_size} & \texttt{0x44} & RW & read / write block transfer size \\ \hline
                \texttt{blkock\_count} & \texttt{0x48} & RW & read / write block count \\ \hline
                \texttt{dst\_src\_address} & \texttt{0x60} & RW & DMA destination / source address \\ \hline
                \hline
        \end{tabular}
        \label{tab:registers}
    \end{table}
 
    \subsubsection{Argument register}
    \label{sec:arg_reg}
 
    A write operation to this register triggers a command transaction (The command register has to be configured before writing to this register).
 
    \begin{table}[H]
    \caption{Argument register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:0]} & \texttt{0x00000000} & RW & command argument value. \\ \hline
                \hline
        \end{tabular}
        \label{tab:arg_reg}
    \end{table}
 
    \subsubsection{Command register}
    \label{sec:cmd_reg}
 
    This register configures all aspects of the command to be sent.
 
    \begin{table}[H]
    \caption{Command register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:14]} & &  & reserved \\ \hline
                \texttt{[13:8]} & \texttt{0x00} & RW & command index \\ \hline
                \texttt{[7]} & & & reserved \\ \hline
                \texttt{[6:5]} & \texttt{0x0} & RW & data transfer specification. 0x0 - no data transfer; 0x1 - triggers read data transaction after command transaction;
                0x2 - triggers write data transaction after command transaction\\ \hline
                \texttt{[4]} & \texttt{0x0} & RW & check response for correct command index \\ \hline
                \texttt{[3]} & \texttt{0x0} & RW & check response CRC \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & check for busy signal after command transaction (if busy signal will be asserted after command transaction,
                the core will wait for as long as the busy signal remains) \\ \hline
                \texttt{[1:0]} & \texttt{0x0} & RW & response check configuration. 0x0 - don't wait for response; 0x1 - wait for short response (48-bits);
                0x2 - wait for long response (136-bits) \\ \hline
                \hline
        \end{tabular}
        \label{tab:cmd_reg}
    \end{table}
 
    \subsubsection{Response register 0-3}
    \label{sec:resp_reg}
 
    Response registers 0-3 contain response data bits after a successful command transaction (if bits 1-0 of command register were configured to wait for response).
 
    \begin{table}[H]
    \caption{Response register 0-3}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:0]} & \texttt{0x00000000} & R & response data bits \\ \hline
                \hline
        \end{tabular}
        \label{tab:resp_reg}
    \end{table}
 
 
    \subsubsection{Control register}
    \label{sec:control_reg}
 
    \begin{table}[H]
    \caption{Control register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:1]} & & & reserved \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & MMC/SD bus width; 0x0 - 1-bit operation; 0x1 - 4-bit operation \\ \hline
                \hline
        \end{tabular}
        \label{tab:control_reg}
    \end{table}
 
    \subsubsection{Timeout register}
    \label{sec:timeout_reg}
 
    The timeout register configures the transaction watchdog counter. If any transaction lasts longer than the configured timeout, an interrupt will be generated.
    The value in the timeout register represents the number of \texttt{sd\_clk\_o\_pad} clock cycles. The register value is calculated by the following formula:
    \begin{equation}
    REG = \frac{timeout[s] * frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{(2*(\texttt{clock\_divider} + 1))}
    \end{equation}
 
    \begin{table}[H]
    \caption{Timeout register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:16]} & & & reserved \\ \hline
                \texttt{[15:0]} & \texttt{0x0} & RW & timeout value \\ \hline
                \hline
        \end{tabular}
        \label{tab:timeout_reg}
    \end{table}
 
    \subsubsection{Clock divider register}
    \label{sec:div_reg}
 
    The clock divider register controls division of the \texttt{sd\_clk\_i\_pad} signal frequency. The output of this divider is routed to the MMC/SD interface clock domain.
    The register value is calculated by following formula:
    \begin{equation}
    REG = \frac{frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{2*frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]} - 1
    \end{equation}
 
    \begin{table}[H]
    \caption{Clock divider register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:8]} & & & reserved \\ \hline
                \texttt{[7:0]} & \texttt{0x0} & RW & divider ratio \\ \hline
                \hline
        \end{tabular}
        \label{tab:div_reg}
    \end{table}
 
    \subsubsection{Software reset register}
    \label{sec:reset_reg}
 
    \begin{table}[H]
    \caption{Software reset register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:1]} & & & reserved \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & reset; 0x0 - no reset; 0x1 - reset applied \\ \hline
                \hline
        \end{tabular}
        \label{tab:reset_reg}
    \end{table}
 
    \subsubsection{Voltage information register}
    \label{sec:voltage_reg}
 
    This register contains the value of the card power supply voltage expressed in mV. It is a read-only register and its
    value is configured in HDL.
 
    \begin{table}[H]
    \caption{Software reset register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:0]} & & R & power supply voltage [mV] \\ \hline
                \hline
        \end{tabular}
        \label{tab:voltage_reg}
    \end{table}
 
    \subsubsection{Capabilities information register}
    \label{sec:capa_reg}
 
    \begin{table}[H]
    \caption{Capabilities information register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:0]} & & & reserved \\ \hline
                \hline
        \end{tabular}
        \label{tab:capa_reg}
    \end{table}
 
    \subsubsection{Command events status register}
    \label{sec:cmd_evt_reg}
 
    This register holds all pending event flags related to command transactions.  Any write operation to this register
    clears all flags.
 
    \begin{table}[H]
    \caption{Command events status register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:5]} & & & reserved \\ \hline
                \texttt{[4]} & \texttt{0x0} & RW & index error event \\ \hline
                \texttt{[3]} & \texttt{0x0} & RW & CRC error event \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & timeout error event \\ \hline
                \texttt{[1]} & \texttt{0x0} & RW & error event (logic sum of all error events) \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & command transaction succesful completion event \\ \hline
                \hline
        \end{tabular}
        \label{tab:cmd_evt_reg}
    \end{table}
 
    \subsubsection{Command transaction events enable register}
    \label{sec:cmd_ena_reg}
 
    This register acts as an event \textit{and} mask. To enable a given event, the corresponding bit must be set to 1.
 
    \begin{table}[H]
    \caption{Command transaction events enable register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:5]} & & & reserved \\ \hline
                \texttt{[4]} & \texttt{0x0} & RW & enable index error event \\ \hline
                \texttt{[3]} & \texttt{0x0} & RW & enable CRC error event \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & enable timeout error event \\ \hline
                \texttt{[1]} & \texttt{0x0} & RW & enable error event (logic sum of all error events) \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & enable command transaction successful completion event \\ \hline
                \hline
        \end{tabular}
        \label{tab:cmd_ena_reg}
    \end{table}
 
    \subsubsection{Data transaction events status register}
    \label{sec:data_evt_reg}
 
    This register holds all pending event flags related to data transactions. Any write operation to this register
    clears all flags.
 
    \begin{table}[H]
    \caption{Data transaction events status register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:3]} & & & reserved \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & fifo error event \\ \hline
                \texttt{[1]} & \texttt{0x0} & RW & CRC error event \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & data transaction successful completion event \\ \hline
                \hline
        \end{tabular}
        \label{tab:data_evt_reg}
    \end{table}
 
    \subsubsection{Data transaction events enable register}
    \label{sec:data_ena_reg}
 
    This register acts as an event \textit{and} mask. To enable a given event, the corresponding bit must be set to 1.
 
    \begin{table}[H]
    \caption{Data transaction events enable register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:3]} & & & reserved \\ \hline
                \texttt{[2]} & \texttt{0x0} & RW & enable fifo error event \\ \hline
                \texttt{[1]} & \texttt{0x0} & RW & enable CRC error event \\ \hline
                \texttt{[0]} & \texttt{0x0} & RW & enable data transaction successful completion event \\ \hline
                \hline
        \end{tabular}
        \label{tab:data_ena_reg}
    \end{table}
 
    \subsubsection{Block size register}
    \label{sec:blocksize_reg}
 
    This register controls the number of bytes to write/read in a single block. A data transaction will transmit a number of bytes equal to the block size times the block count.
 
    \begin{table}[H]
    \caption{Block size register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:12]} & & & reserved \\ \hline
                \texttt{[11:0]} & \texttt{0x200} & RW & number of bytes in a single block \\ \hline
                \hline
        \end{tabular}
        \label{tab:blocksize_reg}
    \end{table}
 
    \subsubsection{Block count register}
    \label{sec:blockcnt_reg}
 
    This register controls the number of blocks to write/read in a data transaction. A data transaction will transmit a number of bytes equal to the block count times block size.
    The register value is calculated by following formula:
    \begin{equation}
    REG = number\_of\_blocks - 1
    \end{equation}
 
    \begin{table}[H]
    \caption{Block count register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:16]} & & & reserved \\ \hline
                \texttt{[15:0]} & \texttt{0x0} & RW & number of blocks in data transaction plus 1 \\ \hline
                \hline
        \end{tabular}
        \label{tab:blockcnt_reg}
    \end{table}
 
    \subsubsection{DMA destination / source register}
    \label{sec:dst_src_reg}
 
    This registers configures the DMA source / destination address. For write transactions, this address points to the begining of the data block to be sent.
    For read transactions, this address points to the begining of data block to be received and written to RAM.
 
    \begin{table}[H]
    \caption{DMA destination / source register}
        \begin{tabular}{m{1.3cm}|m{2cm}|m{1cm}|m{8cm}}
                \rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline
                \texttt{[31:o]} & 0x00000000 & RW & address \\ \hline
                \hline
        \end{tabular}
        \label{tab:dst_src_reg}
    \end{table}
 

Line No.	Rev	Author	Line
1	3	rozpruwacz	`%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%`
2			`%%%% %%%%`
3			`%%%% WISHBONE SD Card Controller IP Core %%%%`
4			`%%%% %%%%`
5			`%%%% sw_if.tex %%%%`
6			`%%%% %%%%`
7			`%%%% This file is part of the WISHBONE SD Card %%%%`
8			`%%%% Controller IP Core project %%%%`
9	8	rozpruwacz	`%%%% http://opencores.org/project,sd_card_controller %%%%`
10	3	rozpruwacz	`%%%% %%%%`
11			`%%%% Description %%%%`
12			`%%%% documentation 'Software interface' chapter %%%%`
13			`%%%% %%%%`
14			`%%%% Author(s): %%%%`
15			`%%%% - Marek Czerski, ma.czerski@gmail.com %%%%`
16			`%%%% %%%%`
17			`%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%`
18			`%%%% %%%%`
19			`%%%% Copyright (C) 2013 Authors %%%%`
20			`%%%% %%%%`
21			`%%%% This source file may be used and distributed without %%%%`
22			`%%%% restriction provided that this copyright statement is not %%%%`
23			`%%%% removed from the file and that any derivative work contains %%%%`
24			`%%%% the original copyright notice and the associated disclaimer. %%%%`
25			`%%%% %%%%`
26			`%%%% This source file is free software; you can redistribute it %%%%`
27			`%%%% and/or modify it under the terms of the GNU Lesser General %%%%`
28			`%%%% Public License as published by the Free Software Foundation; %%%%`
29			`%%%% either version 2.1 of the License, or (at your option) any %%%%`
30			`%%%% later version. %%%%`
31			`%%%% %%%%`
32			`%%%% This source is distributed in the hope that it will be %%%%`
33			`%%%% useful, but WITHOUT ANY WARRANTY; without even the implied %%%%`
34			`%%%% warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR %%%%`
35			`%%%% PURPOSE. See the GNU Lesser General Public License for more %%%%`
36			`%%%% details. %%%%`
37			`%%%% %%%%`
38			`%%%% You should have received a copy of the GNU Lesser General %%%%`
39			`%%%% Public License along with this source; if not, download it %%%%`
40			`%%%% from http://www.opencores.org/lgpl.shtml %%%%`
41			`%%%% %%%%`
42			`%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%`
43			`\section{Software interface}`
44			`\label{sec:sw_if}`
45
46	13	jclaytons	`Access to IP core registers is provided through a Wishbone slave interface.`
47	3	rozpruwacz
48			`\subsection{IP Core registers}`
49			`\label{sec:regs}`
50
51			`\begin{table}[H]`
52			`\caption{List of registers}`
53			`\begin{tabular}{l\|l\|l\|l}`
54			`\rowcolor[gray]{0.7} name & address & access & description \\ \hline \hline`
55			`\texttt{argument} & \texttt{0x00} & RW & command argument \\ \hline`
56			`\texttt{command} & \texttt{0x04} & RW & command transaction configuration \\ \hline`
57			`\texttt{response0} & \texttt{0x08} & R & bits 31-0 of the response \\ \hline`
58			`\texttt{response1} & \texttt{0x0C} & R & bits 63-32 of the response \\ \hline`
59			`\texttt{response2} & \texttt{0x10} & R & bits 95-64 of the response \\ \hline`
60			`\texttt{response3} & \texttt{0x14} & R & bits 119-96 of the response \\ \hline`
61			`\texttt{control} & \texttt{0x1C} & RW & IP core control settings \\ \hline`
62			`\texttt{timeout} & \texttt{0x20} & RW & timeout configuration \\ \hline`
63	13	jclaytons	`\texttt{clock\_divider} & \texttt{0x24} & RW & MMC/SD interface clock divider \\ \hline`
64	3	rozpruwacz	`\texttt{reset} & \texttt{0x28} & RW & software reset \\ \hline`
65			`\texttt{voltage} & \texttt{0x2C} & R & power control information \\ \hline`
66			`\texttt{capabilities} & \texttt{0x30} & R & capabilities information \\ \hline`
67			`\texttt{cmd\_event\_status} & \texttt{0x34} & RW & command transaction events status / clear \\ \hline`
68			`\texttt{cmd\_event\_enable} & \texttt{0x38} & RW & command transaction events enable \\ \hline`
69			`\texttt{data\_event\_status} & \texttt{0x3C} & RW & data transaction events status / clear \\ \hline`
70			`\texttt{data\_event\_enable} & \texttt{0x38} & RW & data transaction events enable \\ \hline`
71			`\texttt{blkock\_size} & \texttt{0x44} & RW & read / write block transfer size \\ \hline`
72			`\texttt{blkock\_count} & \texttt{0x48} & RW & read / write block count \\ \hline`
73			`\texttt{dst\_src\_address} & \texttt{0x60} & RW & DMA destination / source address \\ \hline`
74			`\hline`
75			`\end{tabular}`
76			`\label{tab:registers}`
77			`\end{table}`
78
79			`\subsubsection{Argument register}`
80			`\label{sec:arg_reg}`
81
82	13	jclaytons	`A write operation to this register triggers a command transaction (The command register has to be configured before writing to this register).`
83	3	rozpruwacz
84			`\begin{table}[H]`
85			`\caption{Argument register}`
86			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
87			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
88			`\texttt{[31:0]} & \texttt{0x00000000} & RW & command argument value. \\ \hline`
89			`\hline`
90			`\end{tabular}`
91			`\label{tab:arg_reg}`
92			`\end{table}`
93
94			`\subsubsection{Command register}`
95			`\label{sec:cmd_reg}`
96
97	13	jclaytons	`This register configures all aspects of the command to be sent.`
98	3	rozpruwacz
99			`\begin{table}[H]`
100			`\caption{Command register}`
101			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
102			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
103			`\texttt{[31:14]} & & & reserved \\ \hline`
104			`\texttt{[13:8]} & \texttt{0x00} & RW & command index \\ \hline`
105			`\texttt{[7]} & & & reserved \\ \hline`
106			`\texttt{[6:5]} & \texttt{0x0} & RW & data transfer specification. 0x0 - no data transfer; 0x1 - triggers read data transaction after command transaction;`
107			`0x2 - triggers write data transaction after command transaction\\ \hline`
108			`\texttt{[4]} & \texttt{0x0} & RW & check response for correct command index \\ \hline`
109	13	jclaytons	`\texttt{[3]} & \texttt{0x0} & RW & check response CRC \\ \hline`
110	3	rozpruwacz	`\texttt{[2]} & \texttt{0x0} & RW & check for busy signal after command transaction (if busy signal will be asserted after command transaction,`
111	13	jclaytons	`the core will wait for as long as the busy signal remains) \\ \hline`
112	3	rozpruwacz	`\texttt{[1:0]} & \texttt{0x0} & RW & response check configuration. 0x0 - don't wait for response; 0x1 - wait for short response (48-bits);`
113			`0x2 - wait for long response (136-bits) \\ \hline`
114			`\hline`
115			`\end{tabular}`
116			`\label{tab:cmd_reg}`
117			`\end{table}`
118
119			`\subsubsection{Response register 0-3}`
120			`\label{sec:resp_reg}`
121
122	13	jclaytons	`Response registers 0-3 contain response data bits after a successful command transaction (if bits 1-0 of command register were configured to wait for response).`
123	3	rozpruwacz
124			`\begin{table}[H]`
125			`\caption{Response register 0-3}`
126			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
127			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
128			`\texttt{[31:0]} & \texttt{0x00000000} & R & response data bits \\ \hline`
129			`\hline`
130			`\end{tabular}`
131			`\label{tab:resp_reg}`
132			`\end{table}`
133
134
135			`\subsubsection{Control register}`
136			`\label{sec:control_reg}`
137
138			`\begin{table}[H]`
139			`\caption{Control register}`
140			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
141			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
142			`\texttt{[31:1]} & & & reserved \\ \hline`
143			`\texttt{[0]} & \texttt{0x0} & RW & MMC/SD bus width; 0x0 - 1-bit operation; 0x1 - 4-bit operation \\ \hline`
144			`\hline`
145			`\end{tabular}`
146			`\label{tab:control_reg}`
147			`\end{table}`
148
149			`\subsubsection{Timeout register}`
150			`\label{sec:timeout_reg}`
151
152	13	jclaytons	`The timeout register configures the transaction watchdog counter. If any transaction lasts longer than the configured timeout, an interrupt will be generated.`
153			`The value in the timeout register represents the number of \texttt{sd\_clk\_o\_pad} clock cycles. The register value is calculated by the following formula:`
154	3	rozpruwacz	`\begin{equation}`
155	13	jclaytons	`REG = \frac{timeout[s] * frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{(2*(\texttt{clock\_divider} + 1))}`
156	3	rozpruwacz	`\end{equation}`
157
158			`\begin{table}[H]`
159			`\caption{Timeout register}`
160			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
161			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
162			`\texttt{[31:16]} & & & reserved \\ \hline`
163			`\texttt{[15:0]} & \texttt{0x0} & RW & timeout value \\ \hline`
164			`\hline`
165			`\end{tabular}`
166			`\label{tab:timeout_reg}`
167			`\end{table}`
168
169	13	jclaytons	`\subsubsection{Clock divider register}`
170	3	rozpruwacz	`\label{sec:div_reg}`
171
172	13	jclaytons	`The clock divider register controls division of the \texttt{sd\_clk\_i\_pad} signal frequency. The output of this divider is routed to the MMC/SD interface clock domain.`
173			`The register value is calculated by following formula:`
174	3	rozpruwacz	`\begin{equation}`
175			`REG = \frac{frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]}{2*frequency_{\texttt{sd\_clk\_i\_pad}}[Hz]} - 1`
176			`\end{equation}`
177
178			`\begin{table}[H]`
179	13	jclaytons	`\caption{Clock divider register}`
180	3	rozpruwacz	`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
181			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
182			`\texttt{[31:8]} & & & reserved \\ \hline`
183	13	jclaytons	`\texttt{[7:0]} & \texttt{0x0} & RW & divider ratio \\ \hline`
184	3	rozpruwacz	`\hline`
185			`\end{tabular}`
186			`\label{tab:div_reg}`
187			`\end{table}`
188
189			`\subsubsection{Software reset register}`
190			`\label{sec:reset_reg}`
191
192			`\begin{table}[H]`
193			`\caption{Software reset register}`
194			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
195			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
196			`\texttt{[31:1]} & & & reserved \\ \hline`
197			`\texttt{[0]} & \texttt{0x0} & RW & reset; 0x0 - no reset; 0x1 - reset applied \\ \hline`
198			`\hline`
199			`\end{tabular}`
200			`\label{tab:reset_reg}`
201			`\end{table}`
202
203			`\subsubsection{Voltage information register}`
204			`\label{sec:voltage_reg}`
205
206	13	jclaytons	`This register contains the value of the card power supply voltage expressed in mV. It is a read-only register and its`
207	6	rozpruwacz	`value is configured in HDL.`
208
209	3	rozpruwacz	`\begin{table}[H]`
210			`\caption{Software reset register}`
211			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
212			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
213	6	rozpruwacz	`\texttt{[31:0]} & & R & power supply voltage [mV] \\ \hline`
214	3	rozpruwacz	`\hline`
215			`\end{tabular}`
216			`\label{tab:voltage_reg}`
217			`\end{table}`
218
219			`\subsubsection{Capabilities information register}`
220			`\label{sec:capa_reg}`
221
222			`\begin{table}[H]`
223			`\caption{Capabilities information register}`
224			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
225			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
226			`\texttt{[31:0]} & & & reserved \\ \hline`
227			`\hline`
228			`\end{tabular}`
229			`\label{tab:capa_reg}`
230			`\end{table}`
231
232			`\subsubsection{Command events status register}`
233			`\label{sec:cmd_evt_reg}`
234
235	13	jclaytons	`This register holds all pending event flags related to command transactions. Any write operation to this register`
236	3	rozpruwacz	`clears all flags.`
237
238			`\begin{table}[H]`
239			`\caption{Command events status register}`
240			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
241			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
242			`\texttt{[31:5]} & & & reserved \\ \hline`
243			`\texttt{[4]} & \texttt{0x0} & RW & index error event \\ \hline`
244	13	jclaytons	`\texttt{[3]} & \texttt{0x0} & RW & CRC error event \\ \hline`
245	3	rozpruwacz	`\texttt{[2]} & \texttt{0x0} & RW & timeout error event \\ \hline`
246			`\texttt{[1]} & \texttt{0x0} & RW & error event (logic sum of all error events) \\ \hline`
247			`\texttt{[0]} & \texttt{0x0} & RW & command transaction succesful completion event \\ \hline`
248			`\hline`
249			`\end{tabular}`
250			`\label{tab:cmd_evt_reg}`
251			`\end{table}`
252
253			`\subsubsection{Command transaction events enable register}`
254			`\label{sec:cmd_ena_reg}`
255
256	13	jclaytons	`This register acts as an event \textit{and} mask. To enable a given event, the corresponding bit must be set to 1.`
257	3	rozpruwacz
258			`\begin{table}[H]`
259			`\caption{Command transaction events enable register}`
260			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
261			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
262			`\texttt{[31:5]} & & & reserved \\ \hline`
263			`\texttt{[4]} & \texttt{0x0} & RW & enable index error event \\ \hline`
264	13	jclaytons	`\texttt{[3]} & \texttt{0x0} & RW & enable CRC error event \\ \hline`
265	3	rozpruwacz	`\texttt{[2]} & \texttt{0x0} & RW & enable timeout error event \\ \hline`
266			`\texttt{[1]} & \texttt{0x0} & RW & enable error event (logic sum of all error events) \\ \hline`
267	13	jclaytons	`\texttt{[0]} & \texttt{0x0} & RW & enable command transaction successful completion event \\ \hline`
268	3	rozpruwacz	`\hline`
269			`\end{tabular}`
270			`\label{tab:cmd_ena_reg}`
271			`\end{table}`
272
273			`\subsubsection{Data transaction events status register}`
274			`\label{sec:data_evt_reg}`
275
276	13	jclaytons	`This register holds all pending event flags related to data transactions. Any write operation to this register`
277	3	rozpruwacz	`clears all flags.`
278
279			`\begin{table}[H]`
280			`\caption{Data transaction events status register}`
281			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
282			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
283			`\texttt{[31:3]} & & & reserved \\ \hline`
284			`\texttt{[2]} & \texttt{0x0} & RW & fifo error event \\ \hline`
285	13	jclaytons	`\texttt{[1]} & \texttt{0x0} & RW & CRC error event \\ \hline`
286			`\texttt{[0]} & \texttt{0x0} & RW & data transaction successful completion event \\ \hline`
287	3	rozpruwacz	`\hline`
288			`\end{tabular}`
289			`\label{tab:data_evt_reg}`
290			`\end{table}`
291
292			`\subsubsection{Data transaction events enable register}`
293			`\label{sec:data_ena_reg}`
294
295	13	jclaytons	`This register acts as an event \textit{and} mask. To enable a given event, the corresponding bit must be set to 1.`
296	3	rozpruwacz
297			`\begin{table}[H]`
298			`\caption{Data transaction events enable register}`
299			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
300			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
301			`\texttt{[31:3]} & & & reserved \\ \hline`
302			`\texttt{[2]} & \texttt{0x0} & RW & enable fifo error event \\ \hline`
303	13	jclaytons	`\texttt{[1]} & \texttt{0x0} & RW & enable CRC error event \\ \hline`
304			`\texttt{[0]} & \texttt{0x0} & RW & enable data transaction successful completion event \\ \hline`
305	3	rozpruwacz	`\hline`
306			`\end{tabular}`
307			`\label{tab:data_ena_reg}`
308			`\end{table}`
309
310			`\subsubsection{Block size register}`
311			`\label{sec:blocksize_reg}`
312
313	13	jclaytons	`This register controls the number of bytes to write/read in a single block. A data transaction will transmit a number of bytes equal to the block size times the block count.`
314	3	rozpruwacz
315			`\begin{table}[H]`
316			`\caption{Block size register}`
317			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
318			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
319			`\texttt{[31:12]} & & & reserved \\ \hline`
320	13	jclaytons	`\texttt{[11:0]} & \texttt{0x200} & RW & number of bytes in a single block \\ \hline`
321	3	rozpruwacz	`\hline`
322			`\end{tabular}`
323			`\label{tab:blocksize_reg}`
324			`\end{table}`
325
326			`\subsubsection{Block count register}`
327			`\label{sec:blockcnt_reg}`
328
329	13	jclaytons	`This register controls the number of blocks to write/read in a data transaction. A data transaction will transmit a number of bytes equal to the block count times block size.`
330			`The register value is calculated by following formula:`
331	11	rozpruwacz	`\begin{equation}`
332			`REG = number\_of\_blocks - 1`
333			`\end{equation}`
334	3	rozpruwacz
335			`\begin{table}[H]`
336			`\caption{Block count register}`
337			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
338			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
339	11	rozpruwacz	`\texttt{[31:16]} & & & reserved \\ \hline`
340			`\texttt{[15:0]} & \texttt{0x0} & RW & number of blocks in data transaction plus 1 \\ \hline`
341	3	rozpruwacz	`\hline`
342			`\end{tabular}`
343			`\label{tab:blockcnt_reg}`
344			`\end{table}`
345
346			`\subsubsection{DMA destination / source register}`
347			`\label{sec:dst_src_reg}`
348
349	13	jclaytons	`This registers configures the DMA source / destination address. For write transactions, this address points to the begining of the data block to be sent.`
350			`For read transactions, this address points to the begining of data block to be received and written to RAM.`
351	3	rozpruwacz
352			`\begin{table}[H]`
353			`\caption{DMA destination / source register}`
354			`\begin{tabular}{m{1.3cm}\|m{2cm}\|m{1cm}\|m{8cm}}`
355			`\rowcolor[gray]{0.7} bit \# & reset value & access & description \\ \hline \hline`
356			`\texttt{[31:o]} & 0x00000000 & RW & address \\ \hline`
357			`\hline`
358			`\end{tabular}`
359			`\label{tab:dst_src_reg}`
360			`\end{table}`
361

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