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[/] [sd_card_controller/] [trunk/] [rtl/] [VHDL/] [block_ram_pack.vhd] - Blame information for rev 14

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1 14 jclaytons
library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
3
use IEEE.NUMERIC_STD.ALL;
4
use IEEE.MATH_REAL.ALL;
5
 
6
package block_ram_pack is
7
 
8
  component block_ram
9
    generic(
10
      WRITETHRU : integer; -- Set to nonzero value for writethrough mode
11
      USE_FILE  : integer; -- Set to nonzero value to use INIT_FILE
12
      INIT_VAL  : integer; -- Value used when INIT_FILE is not used
13
      INIT_FILE : string;  -- ASCII hexadecimal initialization file name
14
      FIL_WIDTH : integer; -- Bit width of init file lines
15
      ADR_WIDTH : integer;
16
      DAT_WIDTH : integer
17
    );
18
    port (
19
       clk_a    : in  std_logic;
20
       adr_a_i  : in  unsigned(adr_width-1 downto 0);
21
       we_a_i   : in  std_logic;
22
       en_a_i   : in  std_logic;
23
       dat_a_i  : in  unsigned(dat_width-1 downto 0);
24
       dat_a_o  : out unsigned(dat_width-1 downto 0);
25
 
26
       clk_b    : in  std_logic;
27
       adr_b_i  : in  unsigned(adr_width-1 downto 0);
28
       we_b_i   : in  std_logic;
29
       en_b_i   : in  std_logic;
30
       dat_b_i  : in  unsigned(dat_width-1 downto 0);
31
       dat_b_o  : out unsigned(dat_width-1 downto 0)
32
    );
33
  end component;
34
 
35
  component block_ram_async_reset
36
    generic(
37
      WRITETHRU : integer; -- Set to nonzero value for writethrough mode
38
      USE_FILE  : integer; -- Set to nonzero value to use INIT_FILE
39
      INIT_VAL  : integer; -- Value used when INIT_FILE is not used
40
      INIT_FILE : string;  -- ASCII hexadecimal initialization file name
41
      FIL_WIDTH : integer; -- Bit width of init file lines
42
      ADR_WIDTH : integer;
43
      DAT_WIDTH : integer
44
    );
45
    port (
46
       reset_a  : in std_logic;
47
       clk_a    : in  std_logic;
48
       adr_a_i  : in  unsigned(adr_width-1 downto 0);
49
       we_a_i   : in  std_logic;
50
       en_a_i   : in  std_logic;
51
       dat_a_i  : in  unsigned(dat_width-1 downto 0);
52
       dat_a_o  : out unsigned(dat_width-1 downto 0);
53
 
54
       reset_b  : in std_logic;
55
       clk_b    : in  std_logic;
56
       adr_b_i  : in  unsigned(adr_width-1 downto 0);
57
       we_b_i   : in  std_logic;
58
       en_b_i   : in  std_logic;
59
       dat_b_i  : in  unsigned(dat_width-1 downto 0);
60
       dat_b_o  : out unsigned(dat_width-1 downto 0)
61
    );
62
  end component;
63
 
64
  component swiss_army_ram
65
    generic(
66
      USE_BRAM  : integer; -- Set to nonzero value for BRAM, zero for distributed RAM
67
      WRITETHRU : integer; -- Set to nonzero value for writethrough mode
68
      USE_FILE  : integer; -- Set to nonzero value to use INIT_FILE
69
      INIT_VAL  : integer; -- Value used when INIT_FILE is not used
70
      INIT_SEL  : integer; -- Selects which segment of (larger) INIT_FILE to use
71
      INIT_FILE : string;  -- ASCII hexadecimal initialization file name
72
      FIL_WIDTH : integer; -- Bit width of init file lines
73
      ADR_WIDTH : integer;
74
      DAT_WIDTH : integer
75
    );
76
    port (
77
       clk_a    : in  std_logic;
78
       adr_a_i  : in  unsigned(adr_width-1 downto 0);
79
       we_a_i   : in  std_logic;
80
       en_a_i   : in  std_logic;
81
       dat_a_i  : in  unsigned(dat_width-1 downto 0);
82
       dat_a_o  : out unsigned(dat_width-1 downto 0);
83
 
84
       clk_b    : in  std_logic;
85
       adr_b_i  : in  unsigned(adr_width-1 downto 0);
86
       we_b_i   : in  std_logic;
87
       en_b_i   : in  std_logic;
88
       dat_b_i  : in  unsigned(dat_width-1 downto 0);
89
       dat_b_o  : out unsigned(dat_width-1 downto 0)
90
    );
91
  end component;
92
 
93
end block_ram_pack;
94
 
95
------------------------------------------------------------------
96
library IEEE;
97
use IEEE.STD_LOGIC_1164.ALL;
98
use IEEE.NUMERIC_STD.ALL;
99
use IEEE.MATH_REAL.ALL;
100
use IEEE.STD_LOGIC_TEXTIO.ALL;
101
 
102
library std ;
103
use std.textio.all;
104
 
105
entity block_ram is
106
    generic(
107
      WRITETHRU : integer := 1; -- Set to nonzero value for writethrough mode
108
      USE_FILE  : integer := 0; -- Set to nonzero value to use INIT_FILE
109
      INIT_VAL  : integer := 0; -- Value used when INIT_FILE is not used
110
      INIT_FILE : string  := ".\foo.txt";  -- ASCII hexadecimal initialization file name
111
      FIL_WIDTH : integer := 32; -- Bit width of init file lines
112
      ADR_WIDTH : integer := 3;
113
      DAT_WIDTH : integer := 32
114
    );
115
    port (
116
       clk_a    : in  std_logic;
117
       adr_a_i  : in  unsigned(adr_width-1 downto 0);
118
       we_a_i   : in  std_logic;
119
       en_a_i   : in  std_logic;
120
       dat_a_i  : in  unsigned(dat_width-1 downto 0);
121
       dat_a_o  : out unsigned(dat_width-1 downto 0);
122
 
123
       clk_b    : in  std_logic;
124
       adr_b_i  : in  unsigned(adr_width-1 downto 0);
125
       we_b_i   : in  std_logic;
126
       en_b_i   : in  std_logic;
127
       dat_b_i  : in  unsigned(dat_width-1 downto 0);
128
       dat_b_o  : out unsigned(dat_width-1 downto 0)
129
    );
130
end block_ram;
131
 
132
architecture beh of block_ram is
133
 
134
  -- Constants
135
 
136
  -- Functions & associated types
137
    type ram_array is array(0 to 2**ADR_WIDTH-1) of unsigned(DAT_WIDTH-1 downto 0);
138
    impure function ram_file_init (INIT_FILE : in string) return ram_array is
139
      FILE F1 : text is in INIT_FILE;
140
      variable ligne : line;
141
      variable rambo : ram_array;
142
      variable vect  : std_logic_vector(FIL_WIDTH-1 downto 0);
143
      variable uvect : unsigned(DAT_WIDTH-1 downto 0);
144
    begin
145
      for I in ram_array'range loop
146
        if (USE_FILE/=0) then
147
          readline(F1,ligne);
148
          hread(ligne,vect);
149
          for j in uvect'range loop
150
            if (vect(j)='1') then
151
              uvect(j):='1';
152
            else
153
              uvect(j):='0';
154
            end if;
155
          end loop;
156
        else
157
          uvect := to_unsigned(INIT_VAL,DAT_WIDTH);
158
        end if;
159
        rambo(I):=uvect;
160
      end loop;
161
      return rambo;
162
    end function;
163
 
164
  -- Variable Declarations
165
  shared variable ram1 : ram_array := ram_file_init(init_file);
166
 
167
  -- Signal Declarations
168
  signal dat_a_wt : unsigned(DAT_WIDTH-1 downto 0);
169
  signal dat_b_wt : unsigned(DAT_WIDTH-1 downto 0);
170
  signal dat_a_l  : unsigned(DAT_WIDTH-1 downto 0);
171
  signal dat_b_l  : unsigned(DAT_WIDTH-1 downto 0);
172
 
173
begin
174
 
175
process (clk_a)
176
variable i : integer;
177
begin
178
  if (clk_a'event and clk_a='1') then
179
    if (en_a_i='1') then
180
      dat_a_l <= ram1(to_integer(adr_a_i));
181
      if (we_a_i='1') then
182
        ram1(to_integer(adr_a_i)) := dat_a_i;
183
        dat_a_wt <= dat_a_i;
184
      else
185
        dat_a_wt <= ram1(to_integer(adr_a_i));
186
      end if;
187
    end if;
188
  end if;
189
end process;
190
dat_a_o <= dat_a_l when WRITETHRU=0 else dat_a_wt;
191
 
192
process (clk_b)
193
variable i : integer;
194
begin
195
  if (clk_b'event and clk_b='1') then
196
    if (en_b_i='1') then
197
      dat_b_l <= ram1(to_integer(adr_b_i));
198
      if (we_b_i='1') then
199
        ram1(to_integer(adr_b_i)) := dat_b_i;
200
        dat_b_wt <= dat_b_i;
201
      end if;
202
      dat_b_wt <= ram1(to_integer(adr_b_i));
203
    end if;
204
  end if;
205
end process;
206
dat_b_o <= dat_b_l when WRITETHRU=0 else dat_b_wt;
207
 
208
end beh;
209
 
210
------------------------------------------------------------------
211
library IEEE;
212
use IEEE.STD_LOGIC_1164.ALL;
213
use IEEE.NUMERIC_STD.ALL;
214
use IEEE.MATH_REAL.ALL;
215
use IEEE.STD_LOGIC_TEXTIO.ALL;
216
 
217
library std ;
218
use std.textio.all;
219
 
220
entity block_ram_async_reset is
221
    generic(
222
      WRITETHRU : integer := 1; -- Set to nonzero value for writethrough mode
223
      USE_FILE  : integer := 0; -- Set to nonzero value to use INIT_FILE
224
      INIT_VAL  : integer := 0; -- Value used when INIT_FILE is not used
225
      INIT_FILE : string  := ".\foo.txt";  -- ASCII hexadecimal initialization file name
226
      FIL_WIDTH : integer := 32; -- Bit width of init file lines
227
      ADR_WIDTH : integer := 3;
228
      DAT_WIDTH : integer := 32
229
    );
230
    port (
231
       reset_a  : in std_logic;
232
       clk_a    : in  std_logic;
233
       adr_a_i  : in  unsigned(adr_width-1 downto 0);
234
       we_a_i   : in  std_logic;
235
       en_a_i   : in  std_logic;
236
       dat_a_i  : in  unsigned(dat_width-1 downto 0);
237
       dat_a_o  : out unsigned(dat_width-1 downto 0);
238
 
239
       reset_b  : in std_logic;
240
       clk_b    : in  std_logic;
241
       adr_b_i  : in  unsigned(adr_width-1 downto 0);
242
       we_b_i   : in  std_logic;
243
       en_b_i   : in  std_logic;
244
       dat_b_i  : in  unsigned(dat_width-1 downto 0);
245
       dat_b_o  : out unsigned(dat_width-1 downto 0)
246
    );
247
end block_ram_async_reset;
248
 
249
architecture beh of block_ram_async_reset is
250
 
251
  -- Constants
252
 
253
  -- Functions & associated types
254
    type ram_array is array(0 to 2**ADR_WIDTH-1) of unsigned(DAT_WIDTH-1 downto 0);
255
    impure function ram_file_init (INIT_FILE : in string) return ram_array is
256
      FILE F1 : text is in INIT_FILE;
257
      variable ligne : line;
258
      variable rambo : ram_array;
259
      variable vect  : std_logic_vector(FIL_WIDTH-1 downto 0);
260
      variable uvect : unsigned(DAT_WIDTH-1 downto 0);
261
    begin
262
      for I in ram_array'range loop
263
        if (USE_FILE/=0) then
264
          readline(F1,ligne);
265
          hread(ligne,vect);
266
          for j in uvect'range loop
267
            if (vect(j)='1') then
268
              uvect(j):='1';
269
            else
270
              uvect(j):='0';
271
            end if;
272
          end loop;
273
        else
274
          uvect := to_unsigned(INIT_VAL,DAT_WIDTH);
275
        end if;
276
        rambo(I):=uvect;
277
      end loop;
278
      return rambo;
279
    end function;
280
 
281
  -- Variable Declarations
282
  shared variable ram1 : ram_array := ram_file_init(init_file);
283
 
284
  -- Signal Declarations
285
  signal dat_a_wt : unsigned(DAT_WIDTH-1 downto 0);
286
  signal dat_b_wt : unsigned(DAT_WIDTH-1 downto 0);
287
  signal dat_a_l  : unsigned(DAT_WIDTH-1 downto 0);
288
  signal dat_b_l  : unsigned(DAT_WIDTH-1 downto 0);
289
 
290
begin
291
 
292
process (clk_a)
293
variable i : integer;
294
begin
295
  if (reset_a = '1') then
296
    dat_a_l  <= (others=>'0');
297
    dat_a_wt <= (others=>'0');
298
  elsif (clk_a'event and clk_a='1') then
299
    if (en_a_i='1') then
300
      dat_a_l <= ram1(to_integer(adr_a_i));
301
      if (we_a_i='1') then
302
        ram1(to_integer(adr_a_i)) := dat_a_i;
303
        dat_a_wt <= dat_a_i;
304
      else
305
        dat_a_wt <= ram1(to_integer(adr_a_i));
306
      end if;
307
    end if;
308
  end if;
309
end process;
310
dat_a_o <= dat_a_l when WRITETHRU=0 else dat_a_wt;
311
 
312
process (clk_b)
313
variable i : integer;
314
begin
315
  if (reset_b = '1') then
316
    dat_b_l  <= (others=>'0');
317
    dat_b_wt <= (others=>'0');
318
  elsif (clk_b'event and clk_b='1') then
319
    if (en_b_i='1') then
320
      dat_b_l <= ram1(to_integer(adr_b_i));
321
      if (we_b_i='1') then
322
        ram1(to_integer(adr_b_i)) := dat_b_i;
323
        dat_b_wt <= dat_b_i;
324
      end if;
325
      dat_b_wt <= ram1(to_integer(adr_b_i));
326
    end if;
327
  end if;
328
end process;
329
dat_b_o <= dat_b_l when WRITETHRU=0 else dat_b_wt;
330
 
331
end beh;
332
 
333
------------------------------------------------------------------
334
library IEEE;
335
use IEEE.STD_LOGIC_1164.ALL;
336
use IEEE.NUMERIC_STD.ALL;
337
use IEEE.MATH_REAL.ALL;
338
use IEEE.STD_LOGIC_TEXTIO.ALL;
339
 
340
library std ;
341
use std.textio.all;
342
 
343
entity swiss_army_ram is
344
    generic(
345
      USE_BRAM  : integer := 0; -- Set to nonzero value for BRAM, zero for distributed RAM
346
      WRITETHRU : integer := 1; -- Set to nonzero value for writethrough mode
347
      USE_FILE  : integer := 0; -- Set to nonzero value to use INIT_FILE
348
      INIT_VAL  : integer := 0; -- Value used when INIT_FILE is not used
349
      INIT_SEL  : natural := 0; -- Can be used with generate loop variable to select a segment of the (larger) init file
350
      INIT_FILE : string  := ".\foo.txt";  -- ASCII hexadecimal initialization file name
351
      FIL_WIDTH : integer := 32; -- Bit width of init file lines
352
      ADR_WIDTH : integer := 3;
353
      DAT_WIDTH : integer := 32
354
    );
355
    port (
356
       clk_a    : in  std_logic;
357
       adr_a_i  : in  unsigned(adr_width-1 downto 0);
358
       we_a_i   : in  std_logic;
359
       en_a_i   : in  std_logic;
360
       dat_a_i  : in  unsigned(dat_width-1 downto 0);
361
       dat_a_o  : out unsigned(dat_width-1 downto 0);
362
 
363
       clk_b    : in  std_logic;
364
       adr_b_i  : in  unsigned(adr_width-1 downto 0);
365
       we_b_i   : in  std_logic;
366
       en_b_i   : in  std_logic;
367
       dat_b_i  : in  unsigned(dat_width-1 downto 0);
368
       dat_b_o  : out unsigned(dat_width-1 downto 0)
369
    );
370
end swiss_army_ram;
371
 
372
architecture beh of swiss_army_ram is
373
 
374
  -- Constants
375
 
376
  -- Functions & associated types
377
    type ram_array is array(0 to 2**ADR_WIDTH-1) of unsigned(DAT_WIDTH-1 downto 0);
378
    impure function ram_file_init (INIT_FILE : in string) return ram_array is
379
      FILE F1 : text is in INIT_FILE;
380
      variable ligne : line;
381
      variable rambo : ram_array;
382
      variable vect  : std_logic_vector(FIL_WIDTH-1 downto 0);
383
      variable uvect : unsigned(DAT_WIDTH-1 downto 0);
384
      variable I,J   : integer;
385
    begin
386
      -- If using the file, then index through the file to the desired selection
387
      if (USE_FILE/=0) then
388
        if (INIT_SEL>0) then
389
          for I in 0 to INIT_SEL-1 loop
390
            for J in ram_array'range loop
391
              readline(F1,ligne);
392
            end loop;
393
          end loop;
394
        end if;
395
      end if;
396
      -- Obtain the desired initialization values
397
      for I in ram_array'range loop
398
        if (USE_FILE/=0) then
399
          readline(F1,ligne);
400
          hread(ligne,vect);
401
          for J in uvect'range loop
402
            if (vect(J)='1') then
403
              uvect(J):='1';
404
            else
405
              uvect(J):='0';
406
            end if;
407
          end loop;
408
        else
409
          uvect := to_unsigned(INIT_VAL,DAT_WIDTH);
410
        end if;
411
        rambo(I):=uvect;
412
      end loop;
413
      return rambo;
414
    end function;
415
 
416
  -- Variable Declarations
417
  -- To run with RAM > 64k comment this initialization
418
  -- and un-comment the next line
419
  shared variable ram1 : ram_array := ram_file_init(init_file);
420
--  shared variable ram1 : ram_array; -- Initialization removed for this project due to Vivado 64K loop limit...
421
 
422
  -- Signal Declarations
423
  signal dat_a_wt : unsigned(DAT_WIDTH-1 downto 0);
424
  signal dat_b_wt : unsigned(DAT_WIDTH-1 downto 0);
425
  signal dat_a_l  : unsigned(DAT_WIDTH-1 downto 0);
426
  signal dat_b_l  : unsigned(DAT_WIDTH-1 downto 0);
427
 
428
begin
429
 
430
process (clk_a)
431
variable i : integer;
432
begin
433
  if (clk_a'event and clk_a='1') then
434
    if (en_a_i='1') then
435
      dat_a_l <= ram1(to_integer(adr_a_i));
436
      if (we_a_i='1') then
437
        ram1(to_integer(adr_a_i)) := dat_a_i;
438
        dat_a_wt <= dat_a_i;
439
      else
440
        dat_a_wt <= ram1(to_integer(adr_a_i));
441
      end if;
442
    end if;
443
  end if;
444
end process;
445
dat_a_o <= ram1(to_integer(adr_a_i)) when USE_BRAM=0   else
446
           dat_a_l                   when WRITETHRU=0  else
447
           dat_a_wt;
448
 
449
process (clk_b)
450
variable i : integer;
451
begin
452
  if (clk_b'event and clk_b='1') then
453
    if (en_b_i='1') then
454
      dat_b_l <= ram1(to_integer(adr_b_i));
455
      if (we_b_i='1') then
456
        ram1(to_integer(adr_b_i)) := dat_b_i;
457
        dat_b_wt <= dat_b_i;
458
      end if;
459
      dat_b_wt <= ram1(to_integer(adr_b_i));
460
    end if;
461
  end if;
462
end process;
463
dat_b_o <= ram1(to_integer(adr_b_i)) when USE_BRAM=0  else
464
           dat_b_l                   when WRITETHRU=0 else
465
           dat_b_wt;
466
 
467
end beh;
468
 

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