OpenCores
URL https://opencores.org/ocsvn/sd_card_controller/sd_card_controller/trunk

Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [rtl/] [verilog/] [sd_crc_16.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 rozpruwacz
// ==========================================================================
2
// CRC Generation Unit - Linear Feedback Shift Register implementation
3
// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
4
// ==========================================================================
5
module sd_crc_16(BITVAL, ENABLE, BITSTRB, CLEAR, CRC);
6
   input        BITVAL;                            // Next input bit
7
   input        ENABLE;                            // Enable calculation
8
   input        BITSTRB;                           // Current bit valid (Clock)
9
   input        CLEAR;                             // Init CRC value
10
   output [15:0] CRC;                               // Current output CRC value
11
 
12
   reg    [15:0] CRC;                               // We need output registers
13
   wire         inv;
14
 
15
   assign inv = BITVAL ^ CRC[15];                   // XOR required?
16
 
17
   always @(posedge BITSTRB or posedge CLEAR) begin
18
      if (CLEAR) begin
19
         CRC <= 0;                                  // Init before calculation
20
         end
21
      else begin
22
         if (ENABLE == 1) begin
23
             CRC[15] <= CRC[14];
24
             CRC[14] <= CRC[13];
25
             CRC[13] <= CRC[12];
26
             CRC[12] <= CRC[11] ^ inv;
27
             CRC[11] <= CRC[10];
28
             CRC[10] <= CRC[9];
29
             CRC[9] <= CRC[8];
30
             CRC[8] <= CRC[7];
31
             CRC[7] <= CRC[6];
32
             CRC[6] <= CRC[5];
33
             CRC[5] <= CRC[4] ^ inv;
34
             CRC[4] <= CRC[3];
35
             CRC[3] <= CRC[2];
36
             CRC[2] <= CRC[1];
37
             CRC[1] <= CRC[0];
38
             CRC[0] <= inv;
39
             end
40
         end
41
      end
42
 
43
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.