OpenCores
URL https://opencores.org/ocsvn/sd_card_controller/sd_card_controller/trunk

Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [sim/] [rtl_sim/] [bin/] [Makefile] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 rozpruwacz
######################################################################
2
####                                                              ####
3
#### WISHBONE SD Card Controller IP Core                          ####
4
####                                                              ####
5
#### Makefile                                                     ####
6
####                                                              ####
7
#### This file is part of the WISHBONE SD Card                    ####
8
#### Controller IP Core project                                   ####
9
#### http://www.opencores.org/cores/xxx/                          ####
10
####                                                              ####
11
#### Description                                                  ####
12
#### Simulation makefile                                          ####
13
####                                                              ####
14
#### Author(s):                                                   ####
15
####     - Marek Czerski, ma.czerski@gmail.com                    ####
16
####                                                              ####
17
######################################################################
18
####                                                              ####
19
#### Copyright (C) 2013 Authors                                   ####
20
####                                                              ####
21
#### This source file may be used and distributed without         ####
22
#### restriction provided that this copyright statement is not    ####
23
#### removed from the file and that any derivative work contains  ####
24
#### the original copyright notice and the associated disclaimer. ####
25
####                                                              ####
26
#### This source file is free software; you can redistribute it   ####
27
#### and/or modify it under the terms of the GNU Lesser General   ####
28
#### Public License as published by the Free Software Foundation; ####
29
#### either version 2.1 of the License, or (at your option) any   ####
30
#### later version.                                               ####
31
####                                                              ####
32
#### This source is distributed in the hope that it will be       ####
33
#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
34
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
35
#### PURPOSE. See the GNU Lesser General Public License for more  ####
36
#### details.                                                     ####
37
####                                                              ####
38
#### You should have received a copy of the GNU Lesser General    ####
39
#### Public License along with this source; if not, download it   ####
40
#### from http://www.opencores.org/lgpl.shtml                     ####
41
####                                                              ####
42
######################################################################
43
 
44
V ?= @
45
VCD ?= 0
46
 
47
MODELSIM_DIR ?= /opt/altera/11.0/modelsim_ase
48
 
49
VCOM = $(MODELSIM_DIR)/bin/vcom
50
VLOG = $(MODELSIM_DIR)/bin/vlog
51
VOPT = $(MODELSIM_DIR)/bin/vopt
52
SCCOM = $(MODELSIM_DIR)/bin/sccom
53
VLIB = $(MODELSIM_DIR)/bin/vlib
54
VMAP = $(MODELSIM_DIR)/bin/vmap
55
VSIM = $(MODELSIM_DIR)/bin/vsim
56
 
57
# Define path to each library
58
LIB_SV_STD = $(MODELSIM_DIR)/sv_std
59
LIB_WORK = work
60
LIB_TEST = test
61
 
62
RUN_DIR = $(shell pwd)
63
BIN_DIR = $(shell pwd)/../bin
64
LOG_DIR = $(shell pwd)/../log
65
OUT_DIR = $(shell pwd)/../out
66
 
67
WORK_DIR = ../../../rtl/verilog
68
TEST_DIR = ../../../bench/verilog
69
WORK_SOURCES = $(wildcard $(WORK_DIR)/*.v)
70
TEST_SOURCES = $(wildcard $(TEST_DIR)/*.sv) $(wildcard $(TEST_DIR)/*.v)
71
 
72
WORK_OBJECTS = $(shell echo $(WORK_SOURCES) | sed 's:$(WORK_DIR):./$(LIB_WORK):g' | sed 's:\.v:/_primary.dat:g')
73
TEST_OBJECTS = $(shell echo $(TEST_SOURCES) | sed 's:$(TEST_DIR):./$(LIB_TEST):g' | sed 's:\.sv:/_primary.dat:g')
74
 
75
all: simulate
76
 
77
work_library: $(LIB_WORK) $(WORK_OBJECTS)
78
 
79
#./$(LIB_WORK)/%/_primary.dat: $(WORK_DIR)/%.v
80
#       @echo $@
81
#       $(V)$(VLOG) -work $(LIB_WORK) +incdir+$(WORK_DIR) -nocovercells -O0 $^
82
$(WORK_OBJECTS): $(WORK_SOURCES)
83
        $(V)$(VLOG) -work $(LIB_WORK) +incdir+$(WORK_DIR) -nocovercells -O0 $?
84
 
85
$(LIB_WORK) :
86
        $(V)echo "creating library $@ ..."
87
        $(V)$(VLIB) $(LIB_WORK)
88
        $(V)$(VMAP) $(LIB_WORK) $(LIB_WORK)
89
 
90
test_library: $(LIB_TEST) $(TEST_OBJECTS)
91
 
92
$(TEST_OBJECTS): $(TEST_SOURCES)
93
        $(V)$(VLOG) -work $(LIB_TEST) +incdir+$(WORK_DIR) +incdir+$(TEST_DIR) -nocovercells -O0 $?
94
 
95
$(LIB_TEST) :
96
        $(V)echo "creating library $@ ..."
97
        $(V)$(VLIB) $(LIB_TEST)
98
        $(V)$(VMAP) $(LIB_TEST) $(LIB_TEST)
99
 
100
 
101
compile: work_library test_library
102
 
103
TESTBENCH_SOURCES = $(shell ls $(TEST_DIR)/*_tb.sv)
104
TESTBENCHES = $(shell echo $(TESTBENCH_SOURCES) | sed 's:$(TEST_DIR)/::g' | sed 's:\.sv::g')
105
 
106
ifeq ($(VCD), 1)
107
CLI_STARTUP_FILE = $(BIN_DIR)/vcd_startup.do
108
VCD_DIR = $(OUT_DIR)
109
else
110
CLI_STARTUP_FILE = $(BIN_DIR)/cli_startup.do
111
endif
112
 
113
$(OUT_DIR):
114
        $(V)mkdir $@
115
 
116
$(LOG_DIR):
117
        $(V)mkdir $@
118
 
119
%_tb: $(LOG_DIR) $(VCD_DIR) compile
120
        $(V)$(VSIM) -c -L $(RUN_DIR)/$(LIB_WORK) -do $(CLI_STARTUP_FILE) $(LIB_TEST).$@
121
        $(V)if [ $(VCD) = 1 ]; then mv tmp.vcd $(OUT_DIR)/$@.vcd; fi
122
 
123
simulate: $(TESTBENCHES)
124
 
125
modelsim: compile
126
        $(V)$(VSIM) -lib $(LIB_WORK)
127
 
128
%_tb_gui: $(LOG_DIR) compile
129
        $(V)$(VSIM) -L $(RUN_DIR)/$(LIB_WORK) -do $(BIN_DIR)/gui_startup.do $(LIB_TEST).$(shell echo $@ | sed 's:_gui::')
130
 
131
print_work_sources:
132
        $(V)@echo $(WORK_SOURCES)
133
 
134
print_test_sources:
135
        $(V)@echo $(TEST_SOURCES)
136
 
137
print_work_objects:
138
        $(V)@echo $(WORK_OBJECTS)
139
 
140
print_testbenches:
141
        $(V)@echo $(TESTBENCHES)
142
 
143
clean:
144
        $(V)rm -rfv $(LIB_WORK)
145
        $(V)rm -rfv $(LIB_TEST)
146
        $(V)rm -rfv $(LOG_DIR)
147
        $(V)rm -rfv $(OUT_DIR)
148
        $(V)rm -fv modelsim.ini *.wlf transcript

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.