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[/] [sd_card_controller/] [trunk/] [sw/] [example/] [src/] [ocsdc.c] - Blame information for rev 15

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/*
 * WISHBONE SD Card Controller IP Core
 *
 * ocsdc.c
 *
 * This file is part of the WISHBONE SD Card
 * Controller IP Core project
 * http://opencores.org/project,sd_card_controller
 *
 * Description
 * Driver for the WISHBONE SD Card Controller IP Core.
 *
 * Author(s):
 *     - Marek Czerski, ma.czerski@gmail.com
 */
/*
 *
 * Copyright (C) 2013 Authors
 *
 * This source file may be used and distributed without
 * restriction provided that this copyright statement is not
 * removed from the file and that any derivative work contains
 * the original copyright notice and the associated disclaimer.
 *
 * This source file is free software; you can redistribute it
 * and/or modify it under the terms of the GNU Lesser General
 * Public License as published by the Free Software Foundation;
 * either version 2.1 of the License, or (at your option) any
 * later version.
 *
 * This source is distributed in the hope that it will be
 * useful, but WITHOUT ANY WARRANTY; without even the implied
 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
 * PURPOSE. See the GNU Lesser General Public License for more
 * details.
 *
 * You should have received a copy of the GNU Lesser General
 * Public License along with this source; if not, download it
 * from http://www.opencores.org/lgpl.shtml
 */
 
#include "mmc.h"
#include <malloc.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <or1k-support.h>
 
// Register space
#define OCSDC_ARGUMENT           0x00
#define OCSDC_COMMAND            0x04
#define OCSDC_RESPONSE_1         0x08
#define OCSDC_RESPONSE_2         0x0c
#define OCSDC_RESPONSE_3         0x10
#define OCSDC_RESPONSE_4         0x14
#define OCSDC_CONTROL                    0x1C
#define OCSDC_TIMEOUT            0x20
#define OCSDC_CLOCK_DIVIDER      0x24
#define OCSDC_SOFTWARE_RESET     0x28
#define OCSDC_POWER_CONTROL      0x2C
#define OCSDC_CAPABILITY         0x30
#define OCSDC_CMD_INT_STATUS     0x34
#define OCSDC_CMD_INT_ENABLE     0x38
#define OCSDC_DAT_INT_STATUS     0x3C
#define OCSDC_DAT_INT_ENABLE     0x40
#define OCSDC_BLOCK_SIZE         0x44
#define OCSDC_BLOCK_COUNT        0x48
#define OCSDC_DST_SRC_ADDR       0x60
 
// OCSDC_CMD_INT_STATUS bits
#define OCSDC_CMD_INT_STATUS_CC   0x0001
#define OCSDC_CMD_INT_STATUS_EI   0x0002
#define OCSDC_CMD_INT_STATUS_CTE  0x0004
#define OCSDC_CMD_INT_STATUS_CCRC 0x0008
#define OCSDC_CMD_INT_STATUS_CIE  0x0010
 
// SDCMSC_DAT_INT_STATUS
#define SDCMSC_DAT_INT_STATUS_TRS 0x01
#define SDCMSC_DAT_INT_STATUS_CRC 0x02
#define SDCMSC_DAT_INT_STATUS_OV  0x04
 
struct ocsdc {
        int iobase;
        int clk_freq;
};
 
#define readl(addr) (*(volatile unsigned int *) (addr))
#define writel(b, addr) ((*(volatile unsigned int *) (addr)) = (b))
 
void flush_dcache_range(void * start, void * end) {
        while (start < end) {
                or1k_dcache_flush((unsigned long)start);
                start += 4;
        }
}
 
static inline uint32_t ocsdc_read(struct ocsdc *dev, int offset)
{
        return readl(dev->iobase + offset);
}
 
static inline void ocsdc_write(struct ocsdc *dev, int offset, uint32_t data)
{
        writel(data, dev->iobase + offset);
}
 
static void ocsdc_set_buswidth(struct ocsdc * dev, uint width) {
        if (width == 4)
                ocsdc_write(dev, OCSDC_CONTROL, 1);
        else if (width == 1)
                ocsdc_write(dev, OCSDC_CONTROL, 0);
}
 
/* Set clock prescalar value based on the required clock in HZ */
static void ocsdc_set_clock(struct ocsdc * dev, uint clock)
{
        int clk_div = dev->clk_freq / (2.0 * clock) - 1;
 
        printf("ocsdc_set_clock %d, div %d\n\r", clock, clk_div);
        //software reset
        ocsdc_write(dev, OCSDC_SOFTWARE_RESET, 1);
        //set clock devider
        ocsdc_write(dev, OCSDC_CLOCK_DIVIDER, clk_div);
        //clear software reset
        ocsdc_write(dev, OCSDC_SOFTWARE_RESET, 0);
}
 
static int ocsdc_finish(struct ocsdc * dev, struct mmc_cmd *cmd) {
 
        int retval = 0;
        while (1) {
                int r2 = ocsdc_read(dev, OCSDC_CMD_INT_STATUS);
                //printf("ocsdc_finish: cmd %d, status %x\n", cmd->cmdidx, r2);
                if (r2 & OCSDC_CMD_INT_STATUS_EI) {
                        //clear interrupts
                        ocsdc_write(dev, OCSDC_CMD_INT_STATUS, 0);
                        printf("ocsdc_finish: cmd %d, status %x\n\r", cmd->cmdidx, r2);
                        retval = -1;
                        break;
                }
                else if (r2 & OCSDC_CMD_INT_STATUS_CC) {
                        //clear interrupts
                        ocsdc_write(dev, OCSDC_CMD_INT_STATUS, 0);
                        //get response
                        cmd->response[0] = ocsdc_read(dev, OCSDC_RESPONSE_1);
                        if (cmd->resp_type & MMC_RSP_136) {
                                cmd->response[1] = ocsdc_read(dev, OCSDC_RESPONSE_2);
                                cmd->response[2] = ocsdc_read(dev, OCSDC_RESPONSE_3);
                                cmd->response[3] = ocsdc_read(dev, OCSDC_RESPONSE_4);
                        }
                        printf("ocsdc_finish:  %d ok\n\r", cmd->cmdidx);
                        retval = 0;
 
                        break;
                }
                //else if (!(r2 & OCSDC_CMD_INT_STATUS_CIE)) {
                //      printf("ocsdc_finish: cmd %d no exec %x\n", cmd->cmdidx, r2);
                //}
        }
        return retval;
}
 
static int ocsdc_data_finish(struct ocsdc * dev) {
        int status;
 
    while ((status = ocsdc_read(dev, OCSDC_DAT_INT_STATUS)) == 0);
    ocsdc_write(dev, OCSDC_DAT_INT_STATUS, 0);
 
    if (status & SDCMSC_DAT_INT_STATUS_TRS) {
        printf("ocsdc_data_finish: ok\n\r");
        return 0;
    }
    else {
        printf("ocsdc_data_finish: status %x\n\r", status);
        return -1;
    }
}
 
static void ocsdc_setup_data_xfer(struct ocsdc * dev, struct mmc_cmd *cmd, struct mmc_data *data) {
 
        //invalidate cache
        if (data->flags & MMC_DATA_READ) {
                flush_dcache_range(data->dest, data->dest+data->blocksize*data->blocks);
                ocsdc_write(dev, OCSDC_DST_SRC_ADDR, (uint32_t)data->dest);
        }
        else {
                flush_dcache_range((void *)data->src, (void *)data->src+data->blocksize*data->blocks);
                ocsdc_write(dev, OCSDC_DST_SRC_ADDR, (uint32_t)data->src);
        }
        ocsdc_write(dev, OCSDC_BLOCK_SIZE, data->blocksize);
        ocsdc_write(dev, OCSDC_BLOCK_COUNT, data->blocks-1);
 
        //printf("ocsdc_setup_read: addr: %x\n", (uint32_t)data->dest);
 
}
 
static int ocsdc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
        struct ocsdc * dev = mmc->priv;
 
        int command = (cmd->cmdidx << 8);
        if (cmd->resp_type & MMC_RSP_PRESENT) {
                if (cmd->resp_type & MMC_RSP_136)
                        command |= 2;
                else {
                        command |= 1;
                }
        }
        if (cmd->resp_type & MMC_RSP_BUSY)
                command |= (1 << 2);
        if (cmd->resp_type & MMC_RSP_CRC)
                command |= (1 << 3);
        if (cmd->resp_type & MMC_RSP_OPCODE)
                command |= (1 << 4);
 
        if (data && ((data->flags & MMC_DATA_READ) || ((data->flags & MMC_DATA_WRITE))) && data->blocks) {
                if (data->flags & MMC_DATA_READ)
                        command |= (1 << 5);
                if (data->flags & MMC_DATA_WRITE)
                        command |= (1 << 6);
                ocsdc_setup_data_xfer(dev, cmd, data);
        }
 
        printf("ocsdc_send_cmd %04x\n\r", command);
 
//      getc();
 
        ocsdc_write(dev, OCSDC_COMMAND, command);
        ocsdc_write(dev, OCSDC_ARGUMENT, cmd->cmdarg);
 
        if (ocsdc_finish(dev, cmd) < 0) return -1;
        if (data && data->blocks) return ocsdc_data_finish(dev);
        else return 0;
}
 
/* Initialize ocsdc controller */
static int ocsdc_init(struct mmc *mmc)
{
        struct ocsdc * dev = mmc->priv;
 
        //set timeout
        ocsdc_write(dev, OCSDC_TIMEOUT, 0x7FFF);
        //disable all interrupts
        ocsdc_write(dev, OCSDC_CMD_INT_ENABLE, 0);
        ocsdc_write(dev, OCSDC_DAT_INT_ENABLE, 0);
        //clear all interrupts
        ocsdc_write(dev, OCSDC_CMD_INT_STATUS, 0);
        ocsdc_write(dev, OCSDC_DAT_INT_STATUS, 0);
        //set clock to maximum (devide by 2)
        ocsdc_set_clock(dev, dev->clk_freq/2);
 
        return 0;
}
 
static void ocsdc_set_ios(struct mmc *mmc)
{
        /* Support only 4 bit if */
        ocsdc_set_buswidth(mmc->priv, mmc->bus_width);
 
        /* Set clock speed */
        if (mmc->clock)
                ocsdc_set_clock(mmc->priv, mmc->clock);
}
 
struct mmc * ocsdc_mmc_init(int base_addr, int clk_freq)
{
        struct mmc *mmc;
        struct ocsdc *priv;
 
        mmc = malloc(sizeof(struct mmc));
        if (!mmc) goto MMC_ALLOC;
        priv = malloc(sizeof(struct ocsdc));
        if (!priv) goto OCSDC_ALLOC;
 
        memset(mmc, 0, sizeof(struct mmc));
        memset(priv, 0, sizeof(struct ocsdc));
 
        priv->iobase = base_addr;
        priv->clk_freq = clk_freq;
 
        sprintf(mmc->name, "ocsdc");
        mmc->priv = priv;
        mmc->send_cmd = ocsdc_send_cmd;
        mmc->set_ios = ocsdc_set_ios;
        mmc->init = ocsdc_init;
        mmc->getcd = NULL;
 
        mmc->f_min = priv->clk_freq/6; /*maximum clock division 64 */
        mmc->f_max = priv->clk_freq/2; /*minimum clock division 2 */
        mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
        mmc->host_caps = MMC_MODE_4BIT;//MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 
        mmc->b_max = 256;
 
        return mmc;
 
OCSDC_ALLOC:
        free(mmc);
MMC_ALLOC:
        return NULL;
}

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Subversion Repositories sd_card_controller

[/] [sd_card_controller/] [trunk/] [sw/] [example/] [src/] [ocsdc.c] - Blame information for rev 15

Line No.	Rev	Author	Line
1	3	rozpruwacz	`/*`
2			`* WISHBONE SD Card Controller IP Core`
3			`*`
4			`* ocsdc.c`
5			`*`
6			`* This file is part of the WISHBONE SD Card`
7			`* Controller IP Core project`
8	8	rozpruwacz	`* http://opencores.org/project,sd_card_controller`
9	3	rozpruwacz	`*`
10			`* Description`
11			`* Driver for the WISHBONE SD Card Controller IP Core.`
12			`*`
13			`* Author(s):`
14			`* - Marek Czerski, ma.czerski@gmail.com`
15			`*/`
16			`/*`
17			`*`
18			`* Copyright (C) 2013 Authors`
19			`*`
20			`* This source file may be used and distributed without`
21			`* restriction provided that this copyright statement is not`
22			`* removed from the file and that any derivative work contains`
23			`* the original copyright notice and the associated disclaimer.`
24			`*`
25			`* This source file is free software; you can redistribute it`
26			`* and/or modify it under the terms of the GNU Lesser General`
27			`* Public License as published by the Free Software Foundation;`
28			`* either version 2.1 of the License, or (at your option) any`
29			`* later version.`
30			`*`
31			`* This source is distributed in the hope that it will be`
32			`* useful, but WITHOUT ANY WARRANTY; without even the implied`
33			`* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
34			`* PURPOSE. See the GNU Lesser General Public License for more`
35			`* details.`
36			`*`
37			`* You should have received a copy of the GNU Lesser General`
38			`* Public License along with this source; if not, download it`
39			`* from http://www.opencores.org/lgpl.shtml`
40			`*/`
41
42			`#include "mmc.h"`
43			`#include <malloc.h>`
44			`#include <stdint.h>`
45			`#include <stdlib.h>`
46			`#include <stdio.h>`
47			`#include <string.h>`
48			`#include <or1k-support.h>`
49
50			`// Register space`
51			`#define OCSDC_ARGUMENT 0x00`
52			`#define OCSDC_COMMAND 0x04`
53			`#define OCSDC_RESPONSE_1 0x08`
54			`#define OCSDC_RESPONSE_2 0x0c`
55			`#define OCSDC_RESPONSE_3 0x10`
56			`#define OCSDC_RESPONSE_4 0x14`
57			`#define OCSDC_CONTROL 0x1C`
58			`#define OCSDC_TIMEOUT 0x20`
59			`#define OCSDC_CLOCK_DIVIDER 0x24`
60			`#define OCSDC_SOFTWARE_RESET 0x28`
61			`#define OCSDC_POWER_CONTROL 0x2C`
62			`#define OCSDC_CAPABILITY 0x30`
63			`#define OCSDC_CMD_INT_STATUS 0x34`
64			`#define OCSDC_CMD_INT_ENABLE 0x38`
65			`#define OCSDC_DAT_INT_STATUS 0x3C`
66			`#define OCSDC_DAT_INT_ENABLE 0x40`
67			`#define OCSDC_BLOCK_SIZE 0x44`
68			`#define OCSDC_BLOCK_COUNT 0x48`
69			`#define OCSDC_DST_SRC_ADDR 0x60`
70
71			`// OCSDC_CMD_INT_STATUS bits`
72			`#define OCSDC_CMD_INT_STATUS_CC 0x0001`
73			`#define OCSDC_CMD_INT_STATUS_EI 0x0002`
74			`#define OCSDC_CMD_INT_STATUS_CTE 0x0004`
75			`#define OCSDC_CMD_INT_STATUS_CCRC 0x0008`
76			`#define OCSDC_CMD_INT_STATUS_CIE 0x0010`
77
78			`// SDCMSC_DAT_INT_STATUS`
79			`#define SDCMSC_DAT_INT_STATUS_TRS 0x01`
80			`#define SDCMSC_DAT_INT_STATUS_CRC 0x02`
81			`#define SDCMSC_DAT_INT_STATUS_OV 0x04`
82
83			`struct ocsdc {`
84			`int iobase;`
85			`int clk_freq;`
86			`};`
87
88			`#define readl(addr) ((volatile unsigned int ) (addr))`
89			`#define writel(b, addr) (((volatile unsigned int ) (addr)) = (b))`
90
91			`void flush_dcache_range(void * start, void * end) {`
92			`while (start < end) {`
93			`or1k_dcache_flush((unsigned long)start);`
94			`start += 4;`
95			`}`
96			`}`
97
98			`static inline uint32_t ocsdc_read(struct ocsdc *dev, int offset)`
99			`{`
100			`return readl(dev->iobase + offset);`
101			`}`
102
103			`static inline void ocsdc_write(struct ocsdc *dev, int offset, uint32_t data)`
104			`{`
105			`writel(data, dev->iobase + offset);`
106			`}`
107
108			`static void ocsdc_set_buswidth(struct ocsdc * dev, uint width) {`
109			`if (width == 4)`
110			`ocsdc_write(dev, OCSDC_CONTROL, 1);`
111			`else if (width == 1)`
112			`ocsdc_write(dev, OCSDC_CONTROL, 0);`
113			`}`
114
115			`/* Set clock prescalar value based on the required clock in HZ */`
116			`static void ocsdc_set_clock(struct ocsdc * dev, uint clock)`
117			`{`
118			`int clk_div = dev->clk_freq / (2.0 * clock) - 1;`
119
120			`printf("ocsdc_set_clock %d, div %d\n\r", clock, clk_div);`
121			`//software reset`
122			`ocsdc_write(dev, OCSDC_SOFTWARE_RESET, 1);`
123			`//set clock devider`
124			`ocsdc_write(dev, OCSDC_CLOCK_DIVIDER, clk_div);`
125			`//clear software reset`
126			`ocsdc_write(dev, OCSDC_SOFTWARE_RESET, 0);`
127			`}`
128
129			`static int ocsdc_finish(struct ocsdc * dev, struct mmc_cmd *cmd) {`
130
131			`int retval = 0;`
132			`while (1) {`
133			`int r2 = ocsdc_read(dev, OCSDC_CMD_INT_STATUS);`
134			`//printf("ocsdc_finish: cmd %d, status %x\n", cmd->cmdidx, r2);`
135			`if (r2 & OCSDC_CMD_INT_STATUS_EI) {`
136			`//clear interrupts`
137			`ocsdc_write(dev, OCSDC_CMD_INT_STATUS, 0);`
138			`printf("ocsdc_finish: cmd %d, status %x\n\r", cmd->cmdidx, r2);`
139			`retval = -1;`
140			`break;`
141			`}`
142			`else if (r2 & OCSDC_CMD_INT_STATUS_CC) {`
143			`//clear interrupts`
144			`ocsdc_write(dev, OCSDC_CMD_INT_STATUS, 0);`
145			`//get response`
146			`cmd->response[0] = ocsdc_read(dev, OCSDC_RESPONSE_1);`
147			`if (cmd->resp_type & MMC_RSP_136) {`
148			`cmd->response[1] = ocsdc_read(dev, OCSDC_RESPONSE_2);`
149			`cmd->response[2] = ocsdc_read(dev, OCSDC_RESPONSE_3);`
150			`cmd->response[3] = ocsdc_read(dev, OCSDC_RESPONSE_4);`
151			`}`
152			`printf("ocsdc_finish: %d ok\n\r", cmd->cmdidx);`
153			`retval = 0;`
154
155			`break;`
156			`}`
157			`//else if (!(r2 & OCSDC_CMD_INT_STATUS_CIE)) {`
158			`// printf("ocsdc_finish: cmd %d no exec %x\n", cmd->cmdidx, r2);`
159			`//}`
160			`}`
161			`return retval;`
162			`}`
163
164			`static int ocsdc_data_finish(struct ocsdc * dev) {`
165			`int status;`
166
167			`while ((status = ocsdc_read(dev, OCSDC_DAT_INT_STATUS)) == 0);`
168			`ocsdc_write(dev, OCSDC_DAT_INT_STATUS, 0);`
169
170			`if (status & SDCMSC_DAT_INT_STATUS_TRS) {`
171			`printf("ocsdc_data_finish: ok\n\r");`
172			`return 0;`
173			`}`
174			`else {`
175			`printf("ocsdc_data_finish: status %x\n\r", status);`
176			`return -1;`
177			`}`
178			`}`
179
180			`static void ocsdc_setup_data_xfer(struct ocsdc * dev, struct mmc_cmd cmd, struct mmc_data data) {`
181
182			`//invalidate cache`
183			`if (data->flags & MMC_DATA_READ) {`
184			`flush_dcache_range(data->dest, data->dest+data->blocksize*data->blocks);`
185			`ocsdc_write(dev, OCSDC_DST_SRC_ADDR, (uint32_t)data->dest);`
186			`}`
187			`else {`
188			`flush_dcache_range((void )data->src, (void )data->src+data->blocksize*data->blocks);`
189			`ocsdc_write(dev, OCSDC_DST_SRC_ADDR, (uint32_t)data->src);`
190			`}`
191			`ocsdc_write(dev, OCSDC_BLOCK_SIZE, data->blocksize);`
192			`ocsdc_write(dev, OCSDC_BLOCK_COUNT, data->blocks-1);`
193
194			`//printf("ocsdc_setup_read: addr: %x\n", (uint32_t)data->dest);`
195
196			`}`
197
198			`static int ocsdc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)`
199			`{`
200			`struct ocsdc * dev = mmc->priv;`
201
202			`int command = (cmd->cmdidx << 8);`
203			`if (cmd->resp_type & MMC_RSP_PRESENT) {`
204			`if (cmd->resp_type & MMC_RSP_136)`
205			`command \|= 2;`
206			`else {`
207			`command \|= 1;`
208			`}`
209			`}`
210			`if (cmd->resp_type & MMC_RSP_BUSY)`
211			`command \|= (1 << 2);`
212			`if (cmd->resp_type & MMC_RSP_CRC)`
213			`command \|= (1 << 3);`
214			`if (cmd->resp_type & MMC_RSP_OPCODE)`
215			`command \|= (1 << 4);`
216
217			`if (data && ((data->flags & MMC_DATA_READ) \|\| ((data->flags & MMC_DATA_WRITE))) && data->blocks) {`
218			`if (data->flags & MMC_DATA_READ)`
219			`command \|= (1 << 5);`
220			`if (data->flags & MMC_DATA_WRITE)`
221			`command \|= (1 << 6);`
222			`ocsdc_setup_data_xfer(dev, cmd, data);`
223			`}`
224
225			`printf("ocsdc_send_cmd %04x\n\r", command);`
226
227			`// getc();`
228
229			`ocsdc_write(dev, OCSDC_COMMAND, command);`
230			`ocsdc_write(dev, OCSDC_ARGUMENT, cmd->cmdarg);`
231
232			`if (ocsdc_finish(dev, cmd) < 0) return -1;`
233			`if (data && data->blocks) return ocsdc_data_finish(dev);`
234			`else return 0;`
235			`}`
236
237			`/* Initialize ocsdc controller */`
238			`static int ocsdc_init(struct mmc *mmc)`
239			`{`
240			`struct ocsdc * dev = mmc->priv;`
241
242			`//set timeout`
243			`ocsdc_write(dev, OCSDC_TIMEOUT, 0x7FFF);`
244			`//disable all interrupts`
245			`ocsdc_write(dev, OCSDC_CMD_INT_ENABLE, 0);`
246			`ocsdc_write(dev, OCSDC_DAT_INT_ENABLE, 0);`
247			`//clear all interrupts`
248			`ocsdc_write(dev, OCSDC_CMD_INT_STATUS, 0);`
249			`ocsdc_write(dev, OCSDC_DAT_INT_STATUS, 0);`
250			`//set clock to maximum (devide by 2)`
251			`ocsdc_set_clock(dev, dev->clk_freq/2);`
252
253			`return 0;`
254			`}`
255
256			`static void ocsdc_set_ios(struct mmc *mmc)`
257			`{`
258			`/* Support only 4 bit if */`
259			`ocsdc_set_buswidth(mmc->priv, mmc->bus_width);`
260
261			`/* Set clock speed */`
262			`if (mmc->clock)`
263			`ocsdc_set_clock(mmc->priv, mmc->clock);`
264			`}`
265
266			`struct mmc * ocsdc_mmc_init(int base_addr, int clk_freq)`
267			`{`
268			`struct mmc *mmc;`
269			`struct ocsdc *priv;`
270
271			`mmc = malloc(sizeof(struct mmc));`
272			`if (!mmc) goto MMC_ALLOC;`
273			`priv = malloc(sizeof(struct ocsdc));`
274			`if (!priv) goto OCSDC_ALLOC;`
275
276			`memset(mmc, 0, sizeof(struct mmc));`
277			`memset(priv, 0, sizeof(struct ocsdc));`
278
279			`priv->iobase = base_addr;`
280			`priv->clk_freq = clk_freq;`
281
282			`sprintf(mmc->name, "ocsdc");`
283			`mmc->priv = priv;`
284			`mmc->send_cmd = ocsdc_send_cmd;`
285			`mmc->set_ios = ocsdc_set_ios;`
286			`mmc->init = ocsdc_init;`
287			`mmc->getcd = NULL;`
288
289			`mmc->f_min = priv->clk_freq/6; /maximum clock division 64 /`
290			`mmc->f_max = priv->clk_freq/2; /minimum clock division 2 /`
291			`mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;`
292			`mmc->host_caps = MMC_MODE_4BIT;//MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT;`
293
294			`mmc->b_max = 256;`
295
296			`return mmc;`
297
298			`OCSDC_ALLOC:`
299			`free(mmc);`
300			`MMC_ALLOC:`
301			`return NULL;`
302			`}`