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rozpruwacz |
/*
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* WISHBONE SD Card Controller IP Core
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*
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* ocsdc.c
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*
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* This file is part of the WISHBONE SD Card
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* Controller IP Core project
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rozpruwacz |
* http://opencores.org/project,sd_card_controller
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rozpruwacz |
*
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* Description
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* Driver for the WISHBONE SD Card Controller IP Core.
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*
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* Author(s):
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* - Marek Czerski, ma.czerski@gmail.com
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*/
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/*
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*
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* Copyright (C) 2013 Authors
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*
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* This source file may be used and distributed without
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* restriction provided that this copyright statement is not
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* removed from the file and that any derivative work contains
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* the original copyright notice and the associated disclaimer.
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*
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* This source file is free software; you can redistribute it
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* and/or modify it under the terms of the GNU Lesser General
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* Public License as published by the Free Software Foundation;
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* either version 2.1 of the License, or (at your option) any
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* later version.
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*
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* This source is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU Lesser General Public License for more
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* details.
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*
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* You should have received a copy of the GNU Lesser General
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* Public License along with this source; if not, download it
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* from http://www.opencores.org/lgpl.shtml
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*/
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#include "mmc.h"
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#include <malloc.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <or1k-support.h>
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// Register space
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#define OCSDC_ARGUMENT 0x00
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#define OCSDC_COMMAND 0x04
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#define OCSDC_RESPONSE_1 0x08
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#define OCSDC_RESPONSE_2 0x0c
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#define OCSDC_RESPONSE_3 0x10
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#define OCSDC_RESPONSE_4 0x14
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#define OCSDC_CONTROL 0x1C
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#define OCSDC_TIMEOUT 0x20
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#define OCSDC_CLOCK_DIVIDER 0x24
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#define OCSDC_SOFTWARE_RESET 0x28
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#define OCSDC_POWER_CONTROL 0x2C
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#define OCSDC_CAPABILITY 0x30
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#define OCSDC_CMD_INT_STATUS 0x34
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#define OCSDC_CMD_INT_ENABLE 0x38
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#define OCSDC_DAT_INT_STATUS 0x3C
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#define OCSDC_DAT_INT_ENABLE 0x40
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#define OCSDC_BLOCK_SIZE 0x44
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#define OCSDC_BLOCK_COUNT 0x48
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#define OCSDC_DST_SRC_ADDR 0x60
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// OCSDC_CMD_INT_STATUS bits
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#define OCSDC_CMD_INT_STATUS_CC 0x0001
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#define OCSDC_CMD_INT_STATUS_EI 0x0002
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#define OCSDC_CMD_INT_STATUS_CTE 0x0004
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#define OCSDC_CMD_INT_STATUS_CCRC 0x0008
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#define OCSDC_CMD_INT_STATUS_CIE 0x0010
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// SDCMSC_DAT_INT_STATUS
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#define SDCMSC_DAT_INT_STATUS_TRS 0x01
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#define SDCMSC_DAT_INT_STATUS_CRC 0x02
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#define SDCMSC_DAT_INT_STATUS_OV 0x04
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struct ocsdc {
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int iobase;
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int clk_freq;
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};
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#define readl(addr) (*(volatile unsigned int *) (addr))
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#define writel(b, addr) ((*(volatile unsigned int *) (addr)) = (b))
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void flush_dcache_range(void * start, void * end) {
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while (start < end) {
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or1k_dcache_flush((unsigned long)start);
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start += 4;
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}
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}
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static inline uint32_t ocsdc_read(struct ocsdc *dev, int offset)
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{
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return readl(dev->iobase + offset);
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}
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static inline void ocsdc_write(struct ocsdc *dev, int offset, uint32_t data)
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{
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writel(data, dev->iobase + offset);
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}
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static void ocsdc_set_buswidth(struct ocsdc * dev, uint width) {
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if (width == 4)
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ocsdc_write(dev, OCSDC_CONTROL, 1);
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else if (width == 1)
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ocsdc_write(dev, OCSDC_CONTROL, 0);
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}
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/* Set clock prescalar value based on the required clock in HZ */
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static void ocsdc_set_clock(struct ocsdc * dev, uint clock)
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{
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int clk_div = dev->clk_freq / (2.0 * clock) - 1;
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printf("ocsdc_set_clock %d, div %d\n\r", clock, clk_div);
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//software reset
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ocsdc_write(dev, OCSDC_SOFTWARE_RESET, 1);
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//set clock devider
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ocsdc_write(dev, OCSDC_CLOCK_DIVIDER, clk_div);
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//clear software reset
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ocsdc_write(dev, OCSDC_SOFTWARE_RESET, 0);
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}
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static int ocsdc_finish(struct ocsdc * dev, struct mmc_cmd *cmd) {
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int retval = 0;
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while (1) {
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int r2 = ocsdc_read(dev, OCSDC_CMD_INT_STATUS);
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//printf("ocsdc_finish: cmd %d, status %x\n", cmd->cmdidx, r2);
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if (r2 & OCSDC_CMD_INT_STATUS_EI) {
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//clear interrupts
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ocsdc_write(dev, OCSDC_CMD_INT_STATUS, 0);
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printf("ocsdc_finish: cmd %d, status %x\n\r", cmd->cmdidx, r2);
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retval = -1;
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break;
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}
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else if (r2 & OCSDC_CMD_INT_STATUS_CC) {
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//clear interrupts
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ocsdc_write(dev, OCSDC_CMD_INT_STATUS, 0);
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//get response
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cmd->response[0] = ocsdc_read(dev, OCSDC_RESPONSE_1);
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[1] = ocsdc_read(dev, OCSDC_RESPONSE_2);
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cmd->response[2] = ocsdc_read(dev, OCSDC_RESPONSE_3);
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cmd->response[3] = ocsdc_read(dev, OCSDC_RESPONSE_4);
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}
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printf("ocsdc_finish: %d ok\n\r", cmd->cmdidx);
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retval = 0;
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break;
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}
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//else if (!(r2 & OCSDC_CMD_INT_STATUS_CIE)) {
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// printf("ocsdc_finish: cmd %d no exec %x\n", cmd->cmdidx, r2);
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//}
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}
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return retval;
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}
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static int ocsdc_data_finish(struct ocsdc * dev) {
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int status;
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while ((status = ocsdc_read(dev, OCSDC_DAT_INT_STATUS)) == 0);
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ocsdc_write(dev, OCSDC_DAT_INT_STATUS, 0);
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if (status & SDCMSC_DAT_INT_STATUS_TRS) {
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printf("ocsdc_data_finish: ok\n\r");
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return 0;
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}
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else {
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printf("ocsdc_data_finish: status %x\n\r", status);
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return -1;
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}
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}
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static void ocsdc_setup_data_xfer(struct ocsdc * dev, struct mmc_cmd *cmd, struct mmc_data *data) {
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//invalidate cache
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if (data->flags & MMC_DATA_READ) {
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flush_dcache_range(data->dest, data->dest+data->blocksize*data->blocks);
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ocsdc_write(dev, OCSDC_DST_SRC_ADDR, (uint32_t)data->dest);
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}
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else {
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flush_dcache_range((void *)data->src, (void *)data->src+data->blocksize*data->blocks);
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ocsdc_write(dev, OCSDC_DST_SRC_ADDR, (uint32_t)data->src);
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}
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ocsdc_write(dev, OCSDC_BLOCK_SIZE, data->blocksize);
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ocsdc_write(dev, OCSDC_BLOCK_COUNT, data->blocks-1);
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//printf("ocsdc_setup_read: addr: %x\n", (uint32_t)data->dest);
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}
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static int ocsdc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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{
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struct ocsdc * dev = mmc->priv;
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int command = (cmd->cmdidx << 8);
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136)
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command |= 2;
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else {
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command |= 1;
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}
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}
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if (cmd->resp_type & MMC_RSP_BUSY)
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command |= (1 << 2);
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if (cmd->resp_type & MMC_RSP_CRC)
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command |= (1 << 3);
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if (cmd->resp_type & MMC_RSP_OPCODE)
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command |= (1 << 4);
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if (data && ((data->flags & MMC_DATA_READ) || ((data->flags & MMC_DATA_WRITE))) && data->blocks) {
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if (data->flags & MMC_DATA_READ)
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command |= (1 << 5);
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if (data->flags & MMC_DATA_WRITE)
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command |= (1 << 6);
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ocsdc_setup_data_xfer(dev, cmd, data);
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}
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printf("ocsdc_send_cmd %04x\n\r", command);
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// getc();
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ocsdc_write(dev, OCSDC_COMMAND, command);
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ocsdc_write(dev, OCSDC_ARGUMENT, cmd->cmdarg);
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if (ocsdc_finish(dev, cmd) < 0) return -1;
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if (data && data->blocks) return ocsdc_data_finish(dev);
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else return 0;
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}
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/* Initialize ocsdc controller */
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static int ocsdc_init(struct mmc *mmc)
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{
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struct ocsdc * dev = mmc->priv;
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//set timeout
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ocsdc_write(dev, OCSDC_TIMEOUT, 0x7FFF);
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//disable all interrupts
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ocsdc_write(dev, OCSDC_CMD_INT_ENABLE, 0);
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ocsdc_write(dev, OCSDC_DAT_INT_ENABLE, 0);
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//clear all interrupts
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ocsdc_write(dev, OCSDC_CMD_INT_STATUS, 0);
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ocsdc_write(dev, OCSDC_DAT_INT_STATUS, 0);
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//set clock to maximum (devide by 2)
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ocsdc_set_clock(dev, dev->clk_freq/2);
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return 0;
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}
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static void ocsdc_set_ios(struct mmc *mmc)
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{
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/* Support only 4 bit if */
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ocsdc_set_buswidth(mmc->priv, mmc->bus_width);
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/* Set clock speed */
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if (mmc->clock)
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ocsdc_set_clock(mmc->priv, mmc->clock);
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}
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struct mmc * ocsdc_mmc_init(int base_addr, int clk_freq)
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{
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struct mmc *mmc;
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struct ocsdc *priv;
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mmc = malloc(sizeof(struct mmc));
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if (!mmc) goto MMC_ALLOC;
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priv = malloc(sizeof(struct ocsdc));
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if (!priv) goto OCSDC_ALLOC;
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memset(mmc, 0, sizeof(struct mmc));
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memset(priv, 0, sizeof(struct ocsdc));
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priv->iobase = base_addr;
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priv->clk_freq = clk_freq;
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sprintf(mmc->name, "ocsdc");
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mmc->priv = priv;
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mmc->send_cmd = ocsdc_send_cmd;
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mmc->set_ios = ocsdc_set_ios;
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mmc->init = ocsdc_init;
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mmc->getcd = NULL;
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289 |
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mmc->f_min = priv->clk_freq/6; /*maximum clock division 64 */
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mmc->f_max = priv->clk_freq/2; /*minimum clock division 2 */
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mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
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mmc->host_caps = MMC_MODE_4BIT;//MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
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mmc->b_max = 256;
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return mmc;
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OCSDC_ALLOC:
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free(mmc);
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MMC_ALLOC:
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301 |
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return NULL;
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}
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