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[/] [sd_mmc_emulator/] [trunk/] [rtl/] [registers_def.v] - Blame information for rev 2

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// $Id: registers_def.v 912 2015-05-14 21:41:57Z nxp20190 $
//
// @brief Sango X7 Main SPI registers definition.
//
// @Author Roger Williams <roger.williams@nxp.com>
//
// (c) 2015 NXP Semiconductors. All rights reserved.
//
// PROPRIETARY INFORMATION
//
// The information contained in this file is the property of NXP Semiconductors.
// Except as specifically authorized in writing by NXP, the holder of this file:
// (1) shall keep all information contained herein confidential and shall protect
// same in whole or in part from disclosure and dissemination to all third parties
// and (2) shall use same for operation and maintenance purposes only.
// -----------------------------------------------------------------------------
// 0.03.1  2015-05-14 (RAW) Hard-code some parameters to get this working today
// 0.03.0  2015-05-13 (RAW) Adapted from XCtrl4 code for initial X7
//------------------------------------------------------------------------------
 
// RW register definitions
/* -----\/----- EXCLUDED -----\/-----
`define TG_DAT_I_DLY_INDEX 15:0
`define TG_TCTRL_AD 4'h00
`define TG_TCTRL_INDEX 31:16
`define TG_TQUEUE_AD 4'h02
`define TG_TQUEUE_INDEX 63:32
`define TG_MCTRL_AD 4'h08
`define TG_MCTRL_INDEX 79:64
`define TG_MCONF_AD 4'h0a
`define TG_MCONF_INDEX 95:80
`define TG_DEBUG_AD 4'h0f
`define TG_DEBUG_INDEX 111:96
`define TG_REG_BITS_W 111:0
`define TG_REG_W_NBITS 112
 -----/\----- EXCLUDED -----/\----- */
`define TG_DAT_I_DLY_INDEX 15:0
`define TG_TCTRL_AD 4'h00
`define TG_TCTRL_INDEX 31:16
`define TG_TQUEUE_AD 4'h02
`define TG_TQUEUE_INDEX 47:32
`define TG_MCTRL_AD 4'h08
`define TG_MCTRL_INDEX 63:48
`define TG_MCONF_AD 4'h0a
`define TG_MCONF_INDEX 79:64
`define TG_DEBUG_AD 4'h0f
`define TG_DEBUG_INDEX 95:80
`define TG_REG_BITS_W 95:0
`define TG_REG_W_NBITS 96
 
// R register definitions
`define TG_TQ_STAT_AD 4'h01
`define TG_TQ_STAT_INDEX 15:0
`define TG_MQ_STAT_AD 4'h09
`define TG_MQ_STAT_INDEX 31:16
`define TG_MQUEUE_AD 4'h0c
`define TG_MQUEUE_INDEX 47:32
`define TG_REG_BITS_R 47:0
`define TG_REG_R_NBITS 48
 
// control signal definitions
`define TG_TQUEUE_LD_INDEX 0
`define TG_MQUEUE_RD_INDEX 1
`define TG_REG_BITS_CTL 1:0
`define TG_REG_CTL_NBITS 2
 
// RW register definitions
`define DAT_I_DLY_INDEX 15:0
`define CONF_AD 6'h00
`define CONF_INDEX 31:16
`define TRIG_SRC_AD 6'h01
`define TRIG_SRC_INDEX 47:32
`define CTRL_AD 6'h02
`define CTRL_INDEX 63:48
`define IRQ_MASK_AD 6'h0a
`define IRQ_MASK_INDEX 79:64
`define IRQ_CLR_AD 6'h06
`define IRQ_CLR_INDEX 95:80
`define SYNC_AD 6'h07
`define SYNC_INDEX 111:96
`define FILTER_AD 6'h09
`define FILTER_INDEX 127:112
`define REG_BITS_W 127:0
`define REG_W_NBITS 128
 
// R register definitions
`define STAT_AD 6'h03
`define STAT_INDEX 15:0
`define IRQ_AD 6'h04
`define IRQ_INDEX 31:16
`define VERSION_AD 6'h3f
`define VERSION_INDEX 47:32
`define REG_BITS_R 47:0
`define REG_R_NBITS 48

Line No.	Rev	Author	Line
1	2	jclaytons	`// $Id: registers_def.v 912 2015-05-14 21:41:57Z nxp20190 $`
2			`//`
3			`// @brief Sango X7 Main SPI registers definition.`
4			`//`
5			`// @Author Roger Williams <roger.williams@nxp.com>`
6			`//`
7			`// (c) 2015 NXP Semiconductors. All rights reserved.`
8			`//`
9			`// PROPRIETARY INFORMATION`
10			`//`
11			`// The information contained in this file is the property of NXP Semiconductors.`
12			`// Except as specifically authorized in writing by NXP, the holder of this file:`
13			`// (1) shall keep all information contained herein confidential and shall protect`
14			`// same in whole or in part from disclosure and dissemination to all third parties`
15			`// and (2) shall use same for operation and maintenance purposes only.`
16			`// -----------------------------------------------------------------------------`
17			`// 0.03.1 2015-05-14 (RAW) Hard-code some parameters to get this working today`
18			`// 0.03.0 2015-05-13 (RAW) Adapted from XCtrl4 code for initial X7`
19			`//------------------------------------------------------------------------------`
20
21			`// RW register definitions`
22			`/* -----\/----- EXCLUDED -----\/-----`
23			`define TG_DAT_I_DLY_INDEX 15:0
24			`define TG_TCTRL_AD 4'h00
25			`define TG_TCTRL_INDEX 31:16
26			`define TG_TQUEUE_AD 4'h02
27			`define TG_TQUEUE_INDEX 63:32
28			`define TG_MCTRL_AD 4'h08
29			`define TG_MCTRL_INDEX 79:64
30			`define TG_MCONF_AD 4'h0a
31			`define TG_MCONF_INDEX 95:80
32			`define TG_DEBUG_AD 4'h0f
33			`define TG_DEBUG_INDEX 111:96
34			`define TG_REG_BITS_W 111:0
35			`define TG_REG_W_NBITS 112
36			`-----/\----- EXCLUDED -----/\----- */`
37			`define TG_DAT_I_DLY_INDEX 15:0
38			`define TG_TCTRL_AD 4'h00
39			`define TG_TCTRL_INDEX 31:16
40			`define TG_TQUEUE_AD 4'h02
41			`define TG_TQUEUE_INDEX 47:32
42			`define TG_MCTRL_AD 4'h08
43			`define TG_MCTRL_INDEX 63:48
44			`define TG_MCONF_AD 4'h0a
45			`define TG_MCONF_INDEX 79:64
46			`define TG_DEBUG_AD 4'h0f
47			`define TG_DEBUG_INDEX 95:80
48			`define TG_REG_BITS_W 95:0
49			`define TG_REG_W_NBITS 96
50
51			`// R register definitions`
52			`define TG_TQ_STAT_AD 4'h01
53			`define TG_TQ_STAT_INDEX 15:0
54			`define TG_MQ_STAT_AD 4'h09
55			`define TG_MQ_STAT_INDEX 31:16
56			`define TG_MQUEUE_AD 4'h0c
57			`define TG_MQUEUE_INDEX 47:32
58			`define TG_REG_BITS_R 47:0
59			`define TG_REG_R_NBITS 48
60
61			`// control signal definitions`
62			`define TG_TQUEUE_LD_INDEX 0
63			`define TG_MQUEUE_RD_INDEX 1
64			`define TG_REG_BITS_CTL 1:0
65			`define TG_REG_CTL_NBITS 2
66
67			`// RW register definitions`
68			`define DAT_I_DLY_INDEX 15:0
69			`define CONF_AD 6'h00
70			`define CONF_INDEX 31:16
71			`define TRIG_SRC_AD 6'h01
72			`define TRIG_SRC_INDEX 47:32
73			`define CTRL_AD 6'h02
74			`define CTRL_INDEX 63:48
75			`define IRQ_MASK_AD 6'h0a
76			`define IRQ_MASK_INDEX 79:64
77			`define IRQ_CLR_AD 6'h06
78			`define IRQ_CLR_INDEX 95:80
79			`define SYNC_AD 6'h07
80			`define SYNC_INDEX 111:96
81			`define FILTER_AD 6'h09
82			`define FILTER_INDEX 127:112
83			`define REG_BITS_W 127:0
84			`define REG_W_NBITS 128
85
86			`// R register definitions`
87			`define STAT_AD 6'h03
88			`define STAT_INDEX 15:0
89			`define IRQ_AD 6'h04
90			`define IRQ_INDEX 31:16
91			`define VERSION_AD 6'h3f
92			`define VERSION_INDEX 47:32
93			`define REG_BITS_R 47:0
94			`define REG_R_NBITS 48

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[/] [sd_mmc_emulator/] [trunk/] [rtl/] [registers_def.v] - Blame information for rev 2